1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
26 #include "replacements.h"
35 #include "algorithm.h"
36 #include "binarybuffer.h"
43 static int cfi_register_commands(struct command_context_s
*cmd_ctx
);
44 static int cfi_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
);
45 static int cfi_erase(struct flash_bank_s
*bank
, int first
, int last
);
46 static int cfi_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
);
47 static int cfi_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
);
48 static int cfi_probe(struct flash_bank_s
*bank
);
49 static int cfi_auto_probe(struct flash_bank_s
*bank
);
50 static int cfi_protect_check(struct flash_bank_s
*bank
);
51 static int cfi_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
);
53 //static int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
55 #define CFI_MAX_BUS_WIDTH 4
56 #define CFI_MAX_CHIP_WIDTH 4
58 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
59 #define CFI_MAX_INTEL_CODESIZE 256
61 flash_driver_t cfi_flash
=
64 .register_commands
= cfi_register_commands
,
65 .flash_bank_command
= cfi_flash_bank_command
,
67 .protect
= cfi_protect
,
70 .auto_probe
= cfi_auto_probe
,
71 .erase_check
= default_flash_blank_check
,
72 .protect_check
= cfi_protect_check
,
76 static cfi_unlock_addresses_t cfi_unlock_addresses
[] =
78 [CFI_UNLOCK_555_2AA
] = { .unlock1
= 0x555, .unlock2
= 0x2aa },
79 [CFI_UNLOCK_5555_2AAA
] = { .unlock1
= 0x5555, .unlock2
= 0x2aaa },
82 /* CFI fixups foward declarations */
83 static void cfi_fixup_0002_erase_regions(flash_bank_t
*flash
, void *param
);
84 static void cfi_fixup_0002_unlock_addresses(flash_bank_t
*flash
, void *param
);
85 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t
*flash
, void *param
);
87 /* fixup after reading cmdset 0002 primary query table */
88 static cfi_fixup_t cfi_0002_fixups
[] = {
89 {CFI_MFR_SST
, 0x00D4, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
90 {CFI_MFR_SST
, 0x00D5, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
91 {CFI_MFR_SST
, 0x00D6, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
92 {CFI_MFR_SST
, 0x00D7, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
93 {CFI_MFR_SST
, 0x2780, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
94 {CFI_MFR_ATMEL
, 0x00C8, cfi_fixup_atmel_reversed_erase_regions
, NULL
},
95 {CFI_MFR_FUJITSU
, 0x226b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
96 {CFI_MFR_AMIC
, 0xb31a, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
97 {CFI_MFR_MX
, 0x225b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
98 {CFI_MFR_AMD
, 0x225b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
99 {CFI_MFR_ANY
, CFI_ID_ANY
, cfi_fixup_0002_erase_regions
, NULL
},
103 /* fixup after reading cmdset 0001 primary query table */
104 static cfi_fixup_t cfi_0001_fixups
[] = {
108 static void cfi_fixup(flash_bank_t
*bank
, cfi_fixup_t
*fixups
)
110 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
113 for (f
= fixups
; f
->fixup
; f
++)
115 if (((f
->mfr
== CFI_MFR_ANY
) || (f
->mfr
== cfi_info
->manufacturer
)) &&
116 ((f
->id
== CFI_ID_ANY
) || (f
->id
== cfi_info
->device_id
)))
118 f
->fixup(bank
, f
->param
);
123 /* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
124 __inline__ u32
flash_address(flash_bank_t
*bank
, int sector
, u32 offset
)
126 /* while the sector list isn't built, only accesses to sector 0 work */
128 return bank
->base
+ offset
* bank
->bus_width
;
133 LOG_ERROR("BUG: sector list not yet built");
136 return bank
->base
+ bank
->sectors
[sector
].offset
+ offset
* bank
->bus_width
;
141 static void cfi_command(flash_bank_t
*bank
, u8 cmd
, u8
*cmd_buf
)
145 /* clear whole buffer, to ensure bits that exceed the bus_width
148 for (i
= 0; i
< CFI_MAX_BUS_WIDTH
; i
++)
151 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
153 for (i
= bank
->bus_width
; i
> 0; i
--)
155 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
160 for (i
= 1; i
<= bank
->bus_width
; i
++)
162 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
167 /* read unsigned 8-bit value from the bank
168 * flash banks are expected to be made of similar chips
169 * the query result should be the same for all
171 static u8
cfi_query_u8(flash_bank_t
*bank
, int sector
, u32 offset
)
173 target_t
*target
= bank
->target
;
174 u8 data
[CFI_MAX_BUS_WIDTH
];
176 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
178 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
181 return data
[bank
->bus_width
- 1];
184 /* read unsigned 8-bit value from the bank
185 * in case of a bank made of multiple chips,
186 * the individual values are ORed
188 static u8
cfi_get_u8(flash_bank_t
*bank
, int sector
, u32 offset
)
190 target_t
*target
= bank
->target
;
191 u8 data
[CFI_MAX_BUS_WIDTH
];
194 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
196 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
198 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
206 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
207 value
|= data
[bank
->bus_width
- 1 - i
];
213 static u16
cfi_query_u16(flash_bank_t
*bank
, int sector
, u32 offset
)
215 target_t
*target
= bank
->target
;
216 u8 data
[CFI_MAX_BUS_WIDTH
* 2];
218 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 2, data
);
220 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
221 return data
[0] | data
[bank
->bus_width
] << 8;
223 return data
[bank
->bus_width
- 1] | data
[(2 * bank
->bus_width
) - 1] << 8;
226 static u32
cfi_query_u32(flash_bank_t
*bank
, int sector
, u32 offset
)
228 target_t
*target
= bank
->target
;
229 u8 data
[CFI_MAX_BUS_WIDTH
* 4];
231 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 4, data
);
233 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
234 return data
[0] | data
[bank
->bus_width
] << 8 | data
[bank
->bus_width
* 2] << 16 | data
[bank
->bus_width
* 3] << 24;
236 return data
[bank
->bus_width
- 1] | data
[(2* bank
->bus_width
) - 1] << 8 |
237 data
[(3 * bank
->bus_width
) - 1] << 16 | data
[(4 * bank
->bus_width
) - 1] << 24;
240 static void cfi_intel_clear_status_register(flash_bank_t
*bank
)
242 target_t
*target
= bank
->target
;
245 if (target
->state
!= TARGET_HALTED
)
247 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
251 cfi_command(bank
, 0x50, command
);
252 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
255 u8
cfi_intel_wait_status_busy(flash_bank_t
*bank
, int timeout
)
259 while ((!((status
= cfi_get_u8(bank
, 0, 0x0)) & 0x80)) && (timeout
-- > 0))
261 LOG_DEBUG("status: 0x%x", status
);
265 /* mask out bit 0 (reserved) */
266 status
= status
& 0xfe;
268 LOG_DEBUG("status: 0x%x", status
);
270 if ((status
& 0x80) != 0x80)
272 LOG_ERROR("timeout while waiting for WSM to become ready");
274 else if (status
!= 0x80)
276 LOG_ERROR("status register: 0x%x", status
);
278 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
280 LOG_ERROR("Program suspended");
282 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
284 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
286 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
288 LOG_ERROR("Block Erase Suspended");
290 cfi_intel_clear_status_register(bank
);
296 int cfi_spansion_wait_status_busy(flash_bank_t
*bank
, int timeout
)
298 u8 status
, oldstatus
;
300 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
303 status
= cfi_get_u8(bank
, 0, 0x0);
304 if ((status
^ oldstatus
) & 0x40) {
306 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
307 status
= cfi_get_u8(bank
, 0, 0x0);
308 if ((status
^ oldstatus
) & 0x40) {
309 LOG_ERROR("dq5 timeout, status: 0x%x", status
);
310 return(ERROR_FLASH_OPERATION_FAILED
);
312 LOG_DEBUG("status: 0x%x", status
);
317 LOG_DEBUG("status: 0x%x", status
);
323 } while (timeout
-- > 0);
325 LOG_ERROR("timeout, status: 0x%x", status
);
327 return(ERROR_FLASH_BUSY
);
330 static int cfi_read_intel_pri_ext(flash_bank_t
*bank
)
333 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
334 cfi_intel_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_intel_pri_ext_t
));
335 target_t
*target
= bank
->target
;
338 cfi_info
->pri_ext
= pri_ext
;
340 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
341 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
342 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
344 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
346 cfi_command(bank
, 0xf0, command
);
347 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
351 cfi_command(bank
, 0xff, command
);
352 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
356 LOG_ERROR("Could not read bank flash bank information");
357 return ERROR_FLASH_BANK_INVALID
;
360 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
361 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
363 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
365 pri_ext
->feature_support
= cfi_query_u32(bank
, 0, cfi_info
->pri_addr
+ 5);
366 pri_ext
->suspend_cmd_support
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
367 pri_ext
->blk_status_reg_mask
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xa);
369 LOG_DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext
->feature_support
, pri_ext
->suspend_cmd_support
, pri_ext
->blk_status_reg_mask
);
371 pri_ext
->vcc_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xc);
372 pri_ext
->vpp_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xd);
374 LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
375 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
376 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
378 pri_ext
->num_protection_fields
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xe);
379 if (pri_ext
->num_protection_fields
!= 1)
381 LOG_WARNING("expected one protection register field, but found %i", pri_ext
->num_protection_fields
);
384 pri_ext
->prot_reg_addr
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xf);
385 pri_ext
->fact_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x11);
386 pri_ext
->user_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x12);
388 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
393 static int cfi_read_spansion_pri_ext(flash_bank_t
*bank
)
396 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
397 cfi_spansion_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_spansion_pri_ext_t
));
398 target_t
*target
= bank
->target
;
401 cfi_info
->pri_ext
= pri_ext
;
403 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
404 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
405 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
407 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
409 cfi_command(bank
, 0xf0, command
);
410 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
414 LOG_ERROR("Could not read spansion bank information");
415 return ERROR_FLASH_BANK_INVALID
;
418 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
419 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
421 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
423 pri_ext
->SiliconRevision
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
424 pri_ext
->EraseSuspend
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
425 pri_ext
->BlkProt
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
426 pri_ext
->TmpBlkUnprotect
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
427 pri_ext
->BlkProtUnprot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
428 pri_ext
->SimultaneousOps
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 10);
429 pri_ext
->BurstMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 11);
430 pri_ext
->PageMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 12);
431 pri_ext
->VppMin
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 13);
432 pri_ext
->VppMax
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 14);
433 pri_ext
->TopBottom
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 15);
435 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext
->SiliconRevision
,
436 pri_ext
->EraseSuspend
, pri_ext
->BlkProt
);
438 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext
->TmpBlkUnprotect
,
439 pri_ext
->BlkProtUnprot
, pri_ext
->SimultaneousOps
);
441 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext
->BurstMode
, pri_ext
->PageMode
);
444 LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
445 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
446 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
448 LOG_DEBUG("WP# protection 0x%x", pri_ext
->TopBottom
);
450 /* default values for implementation specific workarounds */
451 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
452 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
453 pri_ext
->_reversed_geometry
= 0;
458 static int cfi_read_atmel_pri_ext(flash_bank_t
*bank
)
461 cfi_atmel_pri_ext_t atmel_pri_ext
;
462 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
463 cfi_spansion_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_spansion_pri_ext_t
));
464 target_t
*target
= bank
->target
;
467 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
468 * but a different primary extended query table.
469 * We read the atmel table, and prepare a valid AMD/Spansion query table.
472 memset(pri_ext
, 0, sizeof(cfi_spansion_pri_ext_t
));
474 cfi_info
->pri_ext
= pri_ext
;
476 atmel_pri_ext
.pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
477 atmel_pri_ext
.pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
478 atmel_pri_ext
.pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
480 if ((atmel_pri_ext
.pri
[0] != 'P') || (atmel_pri_ext
.pri
[1] != 'R') || (atmel_pri_ext
.pri
[2] != 'I'))
482 cfi_command(bank
, 0xf0, command
);
483 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
487 LOG_ERROR("Could not read atmel bank information");
488 return ERROR_FLASH_BANK_INVALID
;
491 pri_ext
->pri
[0] = atmel_pri_ext
.pri
[0];
492 pri_ext
->pri
[1] = atmel_pri_ext
.pri
[1];
493 pri_ext
->pri
[2] = atmel_pri_ext
.pri
[2];
495 atmel_pri_ext
.major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
496 atmel_pri_ext
.minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
498 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext
.pri
[0], atmel_pri_ext
.pri
[1], atmel_pri_ext
.pri
[2], atmel_pri_ext
.major_version
, atmel_pri_ext
.minor_version
);
500 pri_ext
->major_version
= atmel_pri_ext
.major_version
;
501 pri_ext
->minor_version
= atmel_pri_ext
.minor_version
;
503 atmel_pri_ext
.features
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
504 atmel_pri_ext
.bottom_boot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
505 atmel_pri_ext
.burst_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
506 atmel_pri_ext
.page_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
508 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
509 atmel_pri_ext
.features
, atmel_pri_ext
.bottom_boot
, atmel_pri_ext
.burst_mode
, atmel_pri_ext
.page_mode
);
511 if (atmel_pri_ext
.features
& 0x02)
512 pri_ext
->EraseSuspend
= 2;
514 if (atmel_pri_ext
.bottom_boot
)
515 pri_ext
->TopBottom
= 2;
517 pri_ext
->TopBottom
= 3;
519 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
520 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
525 static int cfi_read_0002_pri_ext(flash_bank_t
*bank
)
527 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
529 if (cfi_info
->manufacturer
== CFI_MFR_ATMEL
)
531 return cfi_read_atmel_pri_ext(bank
);
535 return cfi_read_spansion_pri_ext(bank
);
539 static int cfi_spansion_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
542 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
543 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
545 printed
= snprintf(buf
, buf_size
, "\nSpansion primary algorithm extend information:\n");
549 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0],
550 pri_ext
->pri
[1], pri_ext
->pri
[2],
551 pri_ext
->major_version
, pri_ext
->minor_version
);
555 printed
= snprintf(buf
, buf_size
, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
556 (pri_ext
->SiliconRevision
) >> 2,
557 (pri_ext
->SiliconRevision
) & 0x03);
561 printed
= snprintf(buf
, buf_size
, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
562 pri_ext
->EraseSuspend
,
567 printed
= snprintf(buf
, buf_size
, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
568 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
569 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
574 static int cfi_intel_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
577 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
578 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
580 printed
= snprintf(buf
, buf_size
, "\nintel primary algorithm extend information:\n");
584 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
588 printed
= snprintf(buf
, buf_size
, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext
->feature_support
, pri_ext
->suspend_cmd_support
, pri_ext
->blk_status_reg_mask
);
592 printed
= snprintf(buf
, buf_size
, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
593 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
594 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
598 printed
= snprintf(buf
, buf_size
, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
603 static int cfi_register_commands(struct command_context_s
*cmd_ctx
)
605 /*command_t *cfi_cmd = */
606 register_command(cmd_ctx
, NULL
, "cfi", NULL
, COMMAND_ANY
, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
608 register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
609 "print part id of cfi flash bank <num>");
614 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
616 static int cfi_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
)
618 cfi_flash_bank_t
*cfi_info
;
625 LOG_WARNING("incomplete flash_bank cfi configuration");
626 return ERROR_FLASH_BANK_INVALID
;
629 if ((strtoul(args
[4], NULL
, 0) > CFI_MAX_CHIP_WIDTH
)
630 || (strtoul(args
[3], NULL
, 0) > CFI_MAX_BUS_WIDTH
))
632 LOG_ERROR("chip and bus width have to specified in bytes");
633 return ERROR_FLASH_BANK_INVALID
;
636 cfi_info
= malloc(sizeof(cfi_flash_bank_t
));
637 cfi_info
->probed
= 0;
638 bank
->driver_priv
= cfi_info
;
640 cfi_info
->write_algorithm
= NULL
;
642 cfi_info
->x16_as_x8
= 0;
643 cfi_info
->jedec_probe
= 0;
644 cfi_info
->not_cfi
= 0;
646 for (i
= 6; i
< argc
; i
++)
648 if (strcmp(args
[i
], "x16_as_x8") == 0)
650 cfi_info
->x16_as_x8
= 1;
652 else if (strcmp(args
[i
], "jedec_probe") == 0)
654 cfi_info
->jedec_probe
= 1;
658 cfi_info
->write_algorithm
= NULL
;
660 /* bank wasn't probed yet */
661 cfi_info
->qry
[0] = -1;
666 static int cfi_intel_erase(struct flash_bank_s
*bank
, int first
, int last
)
669 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
670 target_t
*target
= bank
->target
;
674 cfi_intel_clear_status_register(bank
);
676 for (i
= first
; i
<= last
; i
++)
678 cfi_command(bank
, 0x20, command
);
679 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
684 cfi_command(bank
, 0xd0, command
);
685 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
690 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == 0x80)
691 bank
->sectors
[i
].is_erased
= 1;
694 cfi_command(bank
, 0xff, command
);
695 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
700 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i
, bank
->base
);
701 return ERROR_FLASH_OPERATION_FAILED
;
705 cfi_command(bank
, 0xff, command
);
706 return target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
710 static int cfi_spansion_erase(struct flash_bank_s
*bank
, int first
, int last
)
713 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
714 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
715 target_t
*target
= bank
->target
;
719 for (i
= first
; i
<= last
; i
++)
721 cfi_command(bank
, 0xaa, command
);
722 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
727 cfi_command(bank
, 0x55, command
);
728 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
733 cfi_command(bank
, 0x80, command
);
734 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
739 cfi_command(bank
, 0xaa, command
);
740 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
745 cfi_command(bank
, 0x55, command
);
746 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
751 cfi_command(bank
, 0x30, command
);
752 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
757 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == ERROR_OK
)
758 bank
->sectors
[i
].is_erased
= 1;
761 cfi_command(bank
, 0xf0, command
);
762 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
767 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i
, bank
->base
);
768 return ERROR_FLASH_OPERATION_FAILED
;
772 cfi_command(bank
, 0xf0, command
);
773 return target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
776 static int cfi_erase(struct flash_bank_s
*bank
, int first
, int last
)
778 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
780 if (bank
->target
->state
!= TARGET_HALTED
)
782 LOG_ERROR("Target not halted");
783 return ERROR_TARGET_NOT_HALTED
;
786 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
788 return ERROR_FLASH_SECTOR_INVALID
;
791 if (cfi_info
->qry
[0] != 'Q')
792 return ERROR_FLASH_BANK_NOT_PROBED
;
794 switch(cfi_info
->pri_id
)
798 return cfi_intel_erase(bank
, first
, last
);
801 return cfi_spansion_erase(bank
, first
, last
);
804 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
811 static int cfi_intel_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
814 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
815 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
816 target_t
*target
= bank
->target
;
821 /* if the device supports neither legacy lock/unlock (bit 3) nor
822 * instant individual block locking (bit 5).
824 if (!(pri_ext
->feature_support
& 0x28))
825 return ERROR_FLASH_OPERATION_FAILED
;
827 cfi_intel_clear_status_register(bank
);
829 for (i
= first
; i
<= last
; i
++)
831 cfi_command(bank
, 0x60, command
);
832 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
833 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
839 cfi_command(bank
, 0x01, command
);
840 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
841 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
845 bank
->sectors
[i
].is_protected
= 1;
849 cfi_command(bank
, 0xd0, command
);
850 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
851 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
855 bank
->sectors
[i
].is_protected
= 0;
858 /* instant individual block locking doesn't require reading of the status register */
859 if (!(pri_ext
->feature_support
& 0x20))
861 /* Clear lock bits operation may take up to 1.4s */
862 cfi_intel_wait_status_busy(bank
, 1400);
867 /* read block lock bit, to verify status */
868 cfi_command(bank
, 0x90, command
);
869 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
)) != ERROR_OK
)
873 block_status
= cfi_get_u8(bank
, i
, 0x2);
875 if ((block_status
& 0x1) != set
)
877 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set
, block_status
);
878 cfi_command(bank
, 0x70, command
);
879 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
)) != ERROR_OK
)
883 cfi_intel_wait_status_busy(bank
, 10);
886 return ERROR_FLASH_OPERATION_FAILED
;
896 /* if the device doesn't support individual block lock bits set/clear,
897 * all blocks have been unlocked in parallel, so we set those that should be protected
899 if ((!set
) && (!(pri_ext
->feature_support
& 0x20)))
901 for (i
= 0; i
< bank
->num_sectors
; i
++)
903 if (bank
->sectors
[i
].is_protected
== 1)
905 cfi_intel_clear_status_register(bank
);
907 cfi_command(bank
, 0x60, command
);
908 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
913 cfi_command(bank
, 0x01, command
);
914 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
919 cfi_intel_wait_status_busy(bank
, 100);
924 cfi_command(bank
, 0xff, command
);
925 return target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
928 static int cfi_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
930 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
932 if (bank
->target
->state
!= TARGET_HALTED
)
934 LOG_ERROR("Target not halted");
935 return ERROR_TARGET_NOT_HALTED
;
938 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
940 return ERROR_FLASH_SECTOR_INVALID
;
943 if (cfi_info
->qry
[0] != 'Q')
944 return ERROR_FLASH_BANK_NOT_PROBED
;
946 switch(cfi_info
->pri_id
)
950 cfi_intel_protect(bank
, set
, first
, last
);
953 LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info
->pri_id
);
960 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
961 static void cfi_add_byte(struct flash_bank_s
*bank
, u8
*word
, u8 byte
)
963 /* target_t *target = bank->target; */
968 * The data to flash must not be changed in endian! We write a bytestrem in
969 * target byte order already. Only the control and status byte lane of the flash
970 * WSM is interpreted by the CPU in different ways, when read a u16 or u32
971 * word (data seems to be in the upper or lower byte lane for u16 accesses).
975 if (target
->endianness
== TARGET_LITTLE_ENDIAN
)
979 for (i
= 0; i
< bank
->bus_width
- 1; i
++)
980 word
[i
] = word
[i
+ 1];
981 word
[bank
->bus_width
- 1] = byte
;
987 for (i
= bank
->bus_width
- 1; i
> 0; i
--)
988 word
[i
] = word
[i
- 1];
994 /* Convert code image to target endian */
995 /* FIXME create general block conversion fcts in target.c?) */
996 static void cfi_fix_code_endian(target_t
*target
, u8
*dest
, const u32
*src
, u32 count
)
999 for (i
=0; i
< count
; i
++)
1001 target_buffer_set_u32(target
, dest
, *src
);
1007 static u32
cfi_command_val(flash_bank_t
*bank
, u8 cmd
)
1009 target_t
*target
= bank
->target
;
1011 u8 buf
[CFI_MAX_BUS_WIDTH
];
1012 cfi_command(bank
, cmd
, buf
);
1013 switch (bank
->bus_width
)
1019 return target_buffer_get_u16(target
, buf
);
1022 return target_buffer_get_u32(target
, buf
);
1025 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1030 static int cfi_intel_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 address
, u32 count
)
1032 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1033 target_t
*target
= bank
->target
;
1034 reg_param_t reg_params
[7];
1035 armv4_5_algorithm_t armv4_5_info
;
1036 working_area_t
*source
;
1037 u32 buffer_size
= 32768;
1038 u32 write_command_val
, busy_pattern_val
, error_pattern_val
;
1040 /* algorithm register usage:
1041 * r0: source address (in RAM)
1042 * r1: target address (in Flash)
1044 * r3: flash write command
1045 * r4: status byte (returned to host)
1046 * r5: busy test pattern
1047 * r6: error test pattern
1050 static const u32 word_32_code
[] = {
1051 0xe4904004, /* loop: ldr r4, [r0], #4 */
1052 0xe5813000, /* str r3, [r1] */
1053 0xe5814000, /* str r4, [r1] */
1054 0xe5914000, /* busy: ldr r4, [r1] */
1055 0xe0047005, /* and r7, r4, r5 */
1056 0xe1570005, /* cmp r7, r5 */
1057 0x1afffffb, /* bne busy */
1058 0xe1140006, /* tst r4, r6 */
1059 0x1a000003, /* bne done */
1060 0xe2522001, /* subs r2, r2, #1 */
1061 0x0a000001, /* beq done */
1062 0xe2811004, /* add r1, r1 #4 */
1063 0xeafffff2, /* b loop */
1064 0xeafffffe /* done: b -2 */
1067 static const u32 word_16_code
[] = {
1068 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1069 0xe1c130b0, /* strh r3, [r1] */
1070 0xe1c140b0, /* strh r4, [r1] */
1071 0xe1d140b0, /* busy ldrh r4, [r1] */
1072 0xe0047005, /* and r7, r4, r5 */
1073 0xe1570005, /* cmp r7, r5 */
1074 0x1afffffb, /* bne busy */
1075 0xe1140006, /* tst r4, r6 */
1076 0x1a000003, /* bne done */
1077 0xe2522001, /* subs r2, r2, #1 */
1078 0x0a000001, /* beq done */
1079 0xe2811002, /* add r1, r1 #2 */
1080 0xeafffff2, /* b loop */
1081 0xeafffffe /* done: b -2 */
1084 static const u32 word_8_code
[] = {
1085 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1086 0xe5c13000, /* strb r3, [r1] */
1087 0xe5c14000, /* strb r4, [r1] */
1088 0xe5d14000, /* busy ldrb r4, [r1] */
1089 0xe0047005, /* and r7, r4, r5 */
1090 0xe1570005, /* cmp r7, r5 */
1091 0x1afffffb, /* bne busy */
1092 0xe1140006, /* tst r4, r6 */
1093 0x1a000003, /* bne done */
1094 0xe2522001, /* subs r2, r2, #1 */
1095 0x0a000001, /* beq done */
1096 0xe2811001, /* add r1, r1 #1 */
1097 0xeafffff2, /* b loop */
1098 0xeafffffe /* done: b -2 */
1100 u8 target_code
[4*CFI_MAX_INTEL_CODESIZE
];
1101 const u32
*target_code_src
;
1102 u32 target_code_size
;
1103 int retval
= ERROR_OK
;
1106 cfi_intel_clear_status_register(bank
);
1108 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
1109 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
1110 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
1112 /* If we are setting up the write_algorith, we need target_code_src */
1113 /* if not we only need target_code_size. */
1115 /* However, we don't want to create multiple code paths, so we */
1116 /* do the unecessary evaluation of target_code_src, which the */
1117 /* compiler will probably nicely optimize away if not needed */
1119 /* prepare algorithm code for target endian */
1120 switch (bank
->bus_width
)
1123 target_code_src
= word_8_code
;
1124 target_code_size
= sizeof(word_8_code
);
1127 target_code_src
= word_16_code
;
1128 target_code_size
= sizeof(word_16_code
);
1131 target_code_src
= word_32_code
;
1132 target_code_size
= sizeof(word_32_code
);
1135 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1136 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1139 /* flash write code */
1140 if (!cfi_info
->write_algorithm
)
1142 if ( target_code_size
> sizeof(target_code
) )
1144 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1145 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1147 cfi_fix_code_endian(target
, target_code
, target_code_src
, target_code_size
/ 4);
1149 /* Get memory for block write handler */
1150 retval
= target_alloc_working_area(target
, target_code_size
, &cfi_info
->write_algorithm
);
1151 if (retval
!= ERROR_OK
)
1153 LOG_WARNING("No working area available, can't do block memory writes");
1154 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1157 /* write algorithm code to working area */
1158 retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
, target_code_size
, target_code
);
1159 if (retval
!= ERROR_OK
)
1161 LOG_ERROR("Unable to write block write code to target");
1166 /* Get a workspace buffer for the data to flash starting with 32k size.
1167 Half size until buffer would be smaller 256 Bytem then fail back */
1168 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1169 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
1172 if (buffer_size
<= 256)
1174 LOG_WARNING("no large enough working area available, can't do block memory writes");
1175 retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1180 /* setup algo registers */
1181 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1182 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1183 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1184 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1185 init_reg_param(®_params
[4], "r4", 32, PARAM_IN
);
1186 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
);
1187 init_reg_param(®_params
[6], "r6", 32, PARAM_OUT
);
1189 /* prepare command and status register patterns */
1190 write_command_val
= cfi_command_val(bank
, 0x40);
1191 busy_pattern_val
= cfi_command_val(bank
, 0x80);
1192 error_pattern_val
= cfi_command_val(bank
, 0x7e);
1194 LOG_INFO("Using target buffer at 0x%08x and of size 0x%04x", source
->address
, buffer_size
);
1196 /* Programming main loop */
1199 u32 thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1202 if((retval
= target_write_buffer(target
, source
->address
, thisrun_count
, buffer
)) != ERROR_OK
)
1207 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1208 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1209 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1211 buf_set_u32(reg_params
[3].value
, 0, 32, write_command_val
);
1212 buf_set_u32(reg_params
[5].value
, 0, 32, busy_pattern_val
);
1213 buf_set_u32(reg_params
[6].value
, 0, 32, error_pattern_val
);
1215 LOG_INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count
, address
);
1217 /* Execute algorithm, assume breakpoint for last instruction */
1218 retval
= target
->type
->run_algorithm(target
, 0, NULL
, 7, reg_params
,
1219 cfi_info
->write_algorithm
->address
,
1220 cfi_info
->write_algorithm
->address
+ target_code_size
- sizeof(u32
),
1221 10000, /* 10s should be enough for max. 32k of data */
1224 /* On failure try a fall back to direct word writes */
1225 if (retval
!= ERROR_OK
)
1227 cfi_intel_clear_status_register(bank
);
1228 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1229 retval
= ERROR_FLASH_OPERATION_FAILED
;
1230 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1231 /* FIXME To allow fall back or recovery, we must save the actual status
1232 somewhere, so that a higher level code can start recovery. */
1236 /* Check return value from algo code */
1237 wsm_error
= buf_get_u32(reg_params
[4].value
, 0, 32) & error_pattern_val
;
1240 /* read status register (outputs debug inforation) */
1241 cfi_intel_wait_status_busy(bank
, 100);
1242 cfi_intel_clear_status_register(bank
);
1243 retval
= ERROR_FLASH_OPERATION_FAILED
;
1247 buffer
+= thisrun_count
;
1248 address
+= thisrun_count
;
1249 count
-= thisrun_count
;
1252 /* free up resources */
1255 target_free_working_area(target
, source
);
1257 if (cfi_info
->write_algorithm
)
1259 target_free_working_area(target
, cfi_info
->write_algorithm
);
1260 cfi_info
->write_algorithm
= NULL
;
1263 destroy_reg_param(®_params
[0]);
1264 destroy_reg_param(®_params
[1]);
1265 destroy_reg_param(®_params
[2]);
1266 destroy_reg_param(®_params
[3]);
1267 destroy_reg_param(®_params
[4]);
1268 destroy_reg_param(®_params
[5]);
1269 destroy_reg_param(®_params
[6]);
1274 static int cfi_spansion_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 address
, u32 count
)
1276 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1277 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1278 target_t
*target
= bank
->target
;
1279 reg_param_t reg_params
[10];
1280 armv4_5_algorithm_t armv4_5_info
;
1281 working_area_t
*source
;
1282 u32 buffer_size
= 32768;
1284 int retval
, retvaltemp
;
1285 int exit_code
= ERROR_OK
;
1287 /* input parameters - */
1288 /* R0 = source address */
1289 /* R1 = destination address */
1290 /* R2 = number of writes */
1291 /* R3 = flash write command */
1292 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1293 /* output parameters - */
1294 /* R5 = 0x80 ok 0x00 bad */
1295 /* temp registers - */
1296 /* R6 = value read from flash to test status */
1297 /* R7 = holding register */
1298 /* unlock registers - */
1299 /* R8 = unlock1_addr */
1300 /* R9 = unlock1_cmd */
1301 /* R10 = unlock2_addr */
1302 /* R11 = unlock2_cmd */
1304 static const u32 word_32_code
[] = {
1305 /* 00008100 <sp_32_code>: */
1306 0xe4905004, /* ldr r5, [r0], #4 */
1307 0xe5889000, /* str r9, [r8] */
1308 0xe58ab000, /* str r11, [r10] */
1309 0xe5883000, /* str r3, [r8] */
1310 0xe5815000, /* str r5, [r1] */
1311 0xe1a00000, /* nop */
1313 /* 00008110 <sp_32_busy>: */
1314 0xe5916000, /* ldr r6, [r1] */
1315 0xe0257006, /* eor r7, r5, r6 */
1316 0xe0147007, /* ands r7, r4, r7 */
1317 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1318 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1319 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1320 0xe5916000, /* ldr r6, [r1] */
1321 0xe0257006, /* eor r7, r5, r6 */
1322 0xe0147007, /* ands r7, r4, r7 */
1323 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1324 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1325 0x1a000004, /* bne 8154 <sp_32_done> */
1327 /* 00008140 <sp_32_cont>: */
1328 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1329 0x03a05080, /* moveq r5, #128 ; 0x80 */
1330 0x0a000001, /* beq 8154 <sp_32_done> */
1331 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1332 0xeaffffe8, /* b 8100 <sp_32_code> */
1334 /* 00008154 <sp_32_done>: */
1335 0xeafffffe /* b 8154 <sp_32_done> */
1338 static const u32 word_16_code
[] = {
1339 /* 00008158 <sp_16_code>: */
1340 0xe0d050b2, /* ldrh r5, [r0], #2 */
1341 0xe1c890b0, /* strh r9, [r8] */
1342 0xe1cab0b0, /* strh r11, [r10] */
1343 0xe1c830b0, /* strh r3, [r8] */
1344 0xe1c150b0, /* strh r5, [r1] */
1345 0xe1a00000, /* nop (mov r0,r0) */
1347 /* 00008168 <sp_16_busy>: */
1348 0xe1d160b0, /* ldrh r6, [r1] */
1349 0xe0257006, /* eor r7, r5, r6 */
1350 0xe0147007, /* ands r7, r4, r7 */
1351 0x0a000007, /* beq 8198 <sp_16_cont> */
1352 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1353 0x0afffff9, /* beq 8168 <sp_16_busy> */
1354 0xe1d160b0, /* ldrh r6, [r1] */
1355 0xe0257006, /* eor r7, r5, r6 */
1356 0xe0147007, /* ands r7, r4, r7 */
1357 0x0a000001, /* beq 8198 <sp_16_cont> */
1358 0xe3a05000, /* mov r5, #0 ; 0x0 */
1359 0x1a000004, /* bne 81ac <sp_16_done> */
1361 /* 00008198 <sp_16_cont>: */
1362 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1363 0x03a05080, /* moveq r5, #128 ; 0x80 */
1364 0x0a000001, /* beq 81ac <sp_16_done> */
1365 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1366 0xeaffffe8, /* b 8158 <sp_16_code> */
1368 /* 000081ac <sp_16_done>: */
1369 0xeafffffe /* b 81ac <sp_16_done> */
1372 static const u32 word_8_code
[] = {
1373 /* 000081b0 <sp_16_code_end>: */
1374 0xe4d05001, /* ldrb r5, [r0], #1 */
1375 0xe5c89000, /* strb r9, [r8] */
1376 0xe5cab000, /* strb r11, [r10] */
1377 0xe5c83000, /* strb r3, [r8] */
1378 0xe5c15000, /* strb r5, [r1] */
1379 0xe1a00000, /* nop (mov r0,r0) */
1381 /* 000081c0 <sp_8_busy>: */
1382 0xe5d16000, /* ldrb r6, [r1] */
1383 0xe0257006, /* eor r7, r5, r6 */
1384 0xe0147007, /* ands r7, r4, r7 */
1385 0x0a000007, /* beq 81f0 <sp_8_cont> */
1386 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1387 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1388 0xe5d16000, /* ldrb r6, [r1] */
1389 0xe0257006, /* eor r7, r5, r6 */
1390 0xe0147007, /* ands r7, r4, r7 */
1391 0x0a000001, /* beq 81f0 <sp_8_cont> */
1392 0xe3a05000, /* mov r5, #0 ; 0x0 */
1393 0x1a000004, /* bne 8204 <sp_8_done> */
1395 /* 000081f0 <sp_8_cont>: */
1396 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1397 0x03a05080, /* moveq r5, #128 ; 0x80 */
1398 0x0a000001, /* beq 8204 <sp_8_done> */
1399 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1400 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1402 /* 00008204 <sp_8_done>: */
1403 0xeafffffe /* b 8204 <sp_8_done> */
1406 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
1407 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
1408 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
1410 /* flash write code */
1411 if (!cfi_info
->write_algorithm
)
1414 int target_code_size
;
1417 /* convert bus-width dependent algorithm code to correct endiannes */
1418 switch (bank
->bus_width
)
1422 target_code_size
= sizeof(word_8_code
);
1426 target_code_size
= sizeof(word_16_code
);
1430 target_code_size
= sizeof(word_32_code
);
1433 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1434 return ERROR_FLASH_OPERATION_FAILED
;
1436 target_code
= malloc(target_code_size
);
1437 cfi_fix_code_endian(target
, target_code
, src
, target_code_size
/ 4);
1439 /* allocate working area */
1440 retval
=target_alloc_working_area(target
, target_code_size
,
1441 &cfi_info
->write_algorithm
);
1442 if (retval
!= ERROR_OK
)
1448 /* write algorithm code to working area */
1449 if((retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
,
1450 target_code_size
, target_code
)) != ERROR_OK
)
1458 /* the following code still assumes target code is fixed 24*4 bytes */
1460 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
1463 if (buffer_size
<= 256)
1465 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1466 if (cfi_info
->write_algorithm
)
1467 target_free_working_area(target
, cfi_info
->write_algorithm
);
1469 LOG_WARNING("not enough working area available, can't do block memory writes");
1470 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1474 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1475 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1476 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1477 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1478 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
);
1479 init_reg_param(®_params
[5], "r5", 32, PARAM_IN
);
1480 init_reg_param(®_params
[6], "r8", 32, PARAM_OUT
);
1481 init_reg_param(®_params
[7], "r9", 32, PARAM_OUT
);
1482 init_reg_param(®_params
[8], "r10", 32, PARAM_OUT
);
1483 init_reg_param(®_params
[9], "r11", 32, PARAM_OUT
);
1487 u32 thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1489 retvaltemp
= target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1491 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1492 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1493 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1494 buf_set_u32(reg_params
[3].value
, 0, 32, cfi_command_val(bank
, 0xA0));
1495 buf_set_u32(reg_params
[4].value
, 0, 32, cfi_command_val(bank
, 0x80));
1496 buf_set_u32(reg_params
[6].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock1
));
1497 buf_set_u32(reg_params
[7].value
, 0, 32, 0xaaaaaaaa);
1498 buf_set_u32(reg_params
[8].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock2
));
1499 buf_set_u32(reg_params
[9].value
, 0, 32, 0x55555555);
1501 retval
= target
->type
->run_algorithm(target
, 0, NULL
, 10, reg_params
,
1502 cfi_info
->write_algorithm
->address
,
1503 cfi_info
->write_algorithm
->address
+ ((24 * 4) - 4),
1504 10000, &armv4_5_info
);
1506 status
= buf_get_u32(reg_params
[5].value
, 0, 32);
1508 if ((retval
!= ERROR_OK
) || (retvaltemp
!= ERROR_OK
) || status
!= 0x80)
1510 LOG_DEBUG("status: 0x%x", status
);
1511 exit_code
= ERROR_FLASH_OPERATION_FAILED
;
1515 buffer
+= thisrun_count
;
1516 address
+= thisrun_count
;
1517 count
-= thisrun_count
;
1520 target_free_working_area(target
, source
);
1522 destroy_reg_param(®_params
[0]);
1523 destroy_reg_param(®_params
[1]);
1524 destroy_reg_param(®_params
[2]);
1525 destroy_reg_param(®_params
[3]);
1526 destroy_reg_param(®_params
[4]);
1527 destroy_reg_param(®_params
[5]);
1528 destroy_reg_param(®_params
[6]);
1529 destroy_reg_param(®_params
[7]);
1530 destroy_reg_param(®_params
[8]);
1531 destroy_reg_param(®_params
[9]);
1536 static int cfi_intel_write_word(struct flash_bank_s
*bank
, u8
*word
, u32 address
)
1539 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1540 target_t
*target
= bank
->target
;
1543 cfi_intel_clear_status_register(bank
);
1544 cfi_command(bank
, 0x40, command
);
1545 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1550 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, word
)) != ERROR_OK
)
1555 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != 0x80)
1557 cfi_command(bank
, 0xff, command
);
1558 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1563 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank
->base
, address
);
1564 return ERROR_FLASH_OPERATION_FAILED
;
1570 static int cfi_intel_write_words(struct flash_bank_s
*bank
, u8
*word
, u32 wordcount
, u32 address
)
1573 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1574 target_t
*target
= bank
->target
;
1577 /* Calculate buffer size and boundary mask */
1578 u32 buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
1579 u32 buffermask
= buffersize
-1;
1582 /* Check for valid range */
1583 if (address
& buffermask
)
1585 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank
->base
, address
, cfi_info
->max_buf_write_size
);
1586 return ERROR_FLASH_OPERATION_FAILED
;
1588 switch(bank
->chip_width
)
1590 case 4 : bufferwsize
= buffersize
/ 4; break;
1591 case 2 : bufferwsize
= buffersize
/ 2; break;
1592 case 1 : bufferwsize
= buffersize
; break;
1594 LOG_ERROR("Unsupported chip width %d", bank
->chip_width
);
1595 return ERROR_FLASH_OPERATION_FAILED
;
1598 bufferwsize
/=(bank
->bus_width
/ bank
->chip_width
);
1601 /* Check for valid size */
1602 if (wordcount
> bufferwsize
)
1604 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount
, buffersize
);
1605 return ERROR_FLASH_OPERATION_FAILED
;
1608 /* Write to flash buffer */
1609 cfi_intel_clear_status_register(bank
);
1611 /* Initiate buffer operation _*/
1612 cfi_command(bank
, 0xE8, command
);
1613 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1617 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
)) != 0x80)
1619 cfi_command(bank
, 0xff, command
);
1620 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1625 LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank
->base
, address
);
1626 return ERROR_FLASH_OPERATION_FAILED
;
1629 /* Write buffer wordcount-1 and data words */
1630 cfi_command(bank
, bufferwsize
-1, command
);
1631 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1636 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, bufferwsize
, word
)) != ERROR_OK
)
1641 /* Commit write operation */
1642 cfi_command(bank
, 0xd0, command
);
1643 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1647 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
)) != 0x80)
1649 cfi_command(bank
, 0xff, command
);
1650 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1655 LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank
->base
, address
);
1656 return ERROR_FLASH_OPERATION_FAILED
;
1662 static int cfi_spansion_write_word(struct flash_bank_s
*bank
, u8
*word
, u32 address
)
1665 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1666 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1667 target_t
*target
= bank
->target
;
1670 cfi_command(bank
, 0xaa, command
);
1671 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1676 cfi_command(bank
, 0x55, command
);
1677 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1682 cfi_command(bank
, 0xa0, command
);
1683 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1688 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, word
)) != ERROR_OK
)
1693 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1695 cfi_command(bank
, 0xf0, command
);
1696 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1701 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank
->base
, address
);
1702 return ERROR_FLASH_OPERATION_FAILED
;
1708 static int cfi_spansion_write_words(struct flash_bank_s
*bank
, u8
*word
, u32 wordcount
, u32 address
)
1711 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1712 target_t
*target
= bank
->target
;
1714 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1716 /* Calculate buffer size and boundary mask */
1717 u32 buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
1718 u32 buffermask
= buffersize
-1;
1721 /* Check for valid range */
1722 if (address
& buffermask
)
1724 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank
->base
, address
, cfi_info
->max_buf_write_size
);
1725 return ERROR_FLASH_OPERATION_FAILED
;
1727 switch(bank
->chip_width
)
1729 case 4 : bufferwsize
= buffersize
/ 4; break;
1730 case 2 : bufferwsize
= buffersize
/ 2; break;
1731 case 1 : bufferwsize
= buffersize
; break;
1733 LOG_ERROR("Unsupported chip width %d", bank
->chip_width
);
1734 return ERROR_FLASH_OPERATION_FAILED
;
1737 bufferwsize
/=(bank
->bus_width
/ bank
->chip_width
);
1739 /* Check for valid size */
1740 if (wordcount
> bufferwsize
)
1742 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount
, buffersize
);
1743 return ERROR_FLASH_OPERATION_FAILED
;
1747 cfi_command(bank
, 0xaa, command
);
1748 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1753 cfi_command(bank
, 0x55, command
);
1754 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1759 // Buffer load command
1760 cfi_command(bank
, 0x25, command
);
1761 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1766 /* Write buffer wordcount-1 and data words */
1767 cfi_command(bank
, bufferwsize
-1, command
);
1768 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1773 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, bufferwsize
, word
)) != ERROR_OK
)
1778 /* Commit write operation */
1779 cfi_command(bank
, 0x29, command
);
1780 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1785 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1787 cfi_command(bank
, 0xf0, command
);
1788 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1793 LOG_ERROR("couldn't write block at base 0x%x, address %x, size %x", bank
->base
, address
, bufferwsize
);
1794 return ERROR_FLASH_OPERATION_FAILED
;
1800 static int cfi_write_word(struct flash_bank_s
*bank
, u8
*word
, u32 address
)
1802 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1804 switch(cfi_info
->pri_id
)
1808 return cfi_intel_write_word(bank
, word
, address
);
1811 return cfi_spansion_write_word(bank
, word
, address
);
1814 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1818 return ERROR_FLASH_OPERATION_FAILED
;
1821 static int cfi_write_words(struct flash_bank_s
*bank
, u8
*word
, u32 wordcount
, u32 address
)
1823 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1825 switch(cfi_info
->pri_id
)
1829 return cfi_intel_write_words(bank
, word
, wordcount
, address
);
1832 return cfi_spansion_write_words(bank
, word
, wordcount
, address
);
1835 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1839 return ERROR_FLASH_OPERATION_FAILED
;
1842 int cfi_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
1844 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1845 target_t
*target
= bank
->target
;
1846 u32 address
= bank
->base
+ offset
; /* address of first byte to be programmed */
1847 u32 write_p
, copy_p
;
1848 int align
; /* number of unaligned bytes */
1849 int blk_count
; /* number of bus_width bytes for block copy */
1850 u8 current_word
[CFI_MAX_BUS_WIDTH
* 4]; /* word (bus_width size) currently being programmed */
1854 if (bank
->target
->state
!= TARGET_HALTED
)
1856 LOG_ERROR("Target not halted");
1857 return ERROR_TARGET_NOT_HALTED
;
1860 if (offset
+ count
> bank
->size
)
1861 return ERROR_FLASH_DST_OUT_OF_BANK
;
1863 if (cfi_info
->qry
[0] != 'Q')
1864 return ERROR_FLASH_BANK_NOT_PROBED
;
1866 /* start at the first byte of the first word (bus_width size) */
1867 write_p
= address
& ~(bank
->bus_width
- 1);
1868 if ((align
= address
- write_p
) != 0)
1870 LOG_INFO("Fixup %d unaligned head bytes", align
);
1872 for (i
= 0; i
< bank
->bus_width
; i
++)
1873 current_word
[i
] = 0;
1876 /* copy bytes before the first write address */
1877 for (i
= 0; i
< align
; ++i
, ++copy_p
)
1880 if((retval
= target
->type
->read_memory(target
, copy_p
, 1, 1, &byte
)) != ERROR_OK
)
1884 cfi_add_byte(bank
, current_word
, byte
);
1887 /* add bytes from the buffer */
1888 for (; (i
< bank
->bus_width
) && (count
> 0); i
++)
1890 cfi_add_byte(bank
, current_word
, *buffer
++);
1895 /* if the buffer is already finished, copy bytes after the last write address */
1896 for (; (count
== 0) && (i
< bank
->bus_width
); ++i
, ++copy_p
)
1899 if((retval
= target
->type
->read_memory(target
, copy_p
, 1, 1, &byte
)) != ERROR_OK
)
1903 cfi_add_byte(bank
, current_word
, byte
);
1906 retval
= cfi_write_word(bank
, current_word
, write_p
);
1907 if (retval
!= ERROR_OK
)
1912 /* handle blocks of bus_size aligned bytes */
1913 blk_count
= count
& ~(bank
->bus_width
- 1); /* round down, leave tail bytes */
1914 switch(cfi_info
->pri_id
)
1916 /* try block writes (fails without working area) */
1919 retval
= cfi_intel_write_block(bank
, buffer
, write_p
, blk_count
);
1922 retval
= cfi_spansion_write_block(bank
, buffer
, write_p
, blk_count
);
1925 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1926 retval
= ERROR_FLASH_OPERATION_FAILED
;
1929 if (retval
== ERROR_OK
)
1931 /* Increment pointers and decrease count on succesful block write */
1932 buffer
+= blk_count
;
1933 write_p
+= blk_count
;
1938 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
1940 //adjust buffersize for chip width
1941 u32 buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
1942 u32 buffermask
= buffersize
-1;
1945 switch(bank
->chip_width
)
1947 case 4 : bufferwsize
= buffersize
/ 4; break;
1948 case 2 : bufferwsize
= buffersize
/ 2; break;
1949 case 1 : bufferwsize
= buffersize
; break;
1951 LOG_ERROR("Unsupported chip width %d", bank
->chip_width
);
1952 return ERROR_FLASH_OPERATION_FAILED
;
1955 bufferwsize
/=(bank
->bus_width
/ bank
->chip_width
);
1957 /* fall back to memory writes */
1958 while (count
>= (u32
)bank
->bus_width
)
1961 if ((write_p
& 0xff) == 0)
1963 LOG_INFO("Programming at %08x, count %08x bytes remaining", write_p
, count
);
1966 if ((bufferwsize
> 0) && (count
>= buffersize
) && !(write_p
& buffermask
))
1968 retval
= cfi_write_words(bank
, buffer
, bufferwsize
, write_p
);
1969 if (retval
== ERROR_OK
)
1971 buffer
+= buffersize
;
1972 write_p
+= buffersize
;
1973 count
-= buffersize
;
1977 /* try the slow way? */
1980 for (i
= 0; i
< bank
->bus_width
; i
++)
1981 current_word
[i
] = 0;
1983 for (i
= 0; i
< bank
->bus_width
; i
++)
1985 cfi_add_byte(bank
, current_word
, *buffer
++);
1988 retval
= cfi_write_word(bank
, current_word
, write_p
);
1989 if (retval
!= ERROR_OK
)
1992 write_p
+= bank
->bus_width
;
1993 count
-= bank
->bus_width
;
2001 /* return to read array mode, so we can read from flash again for padding */
2002 cfi_command(bank
, 0xf0, current_word
);
2003 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2007 cfi_command(bank
, 0xff, current_word
);
2008 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2013 /* handle unaligned tail bytes */
2016 LOG_INFO("Fixup %d unaligned tail bytes", count
);
2019 for (i
= 0; i
< bank
->bus_width
; i
++)
2020 current_word
[i
] = 0;
2022 for (i
= 0; (i
< bank
->bus_width
) && (count
> 0); ++i
, ++copy_p
)
2024 cfi_add_byte(bank
, current_word
, *buffer
++);
2027 for (; i
< bank
->bus_width
; ++i
, ++copy_p
)
2030 if((retval
= target
->type
->read_memory(target
, copy_p
, 1, 1, &byte
)) != ERROR_OK
)
2034 cfi_add_byte(bank
, current_word
, byte
);
2036 retval
= cfi_write_word(bank
, current_word
, write_p
);
2037 if (retval
!= ERROR_OK
)
2041 /* return to read array mode */
2042 cfi_command(bank
, 0xf0, current_word
);
2043 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2047 cfi_command(bank
, 0xff, current_word
);
2048 return target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
2051 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t
*bank
, void *param
)
2054 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2055 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2057 pri_ext
->_reversed_geometry
= 1;
2060 static void cfi_fixup_0002_erase_regions(flash_bank_t
*bank
, void *param
)
2063 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2064 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2067 if ((pri_ext
->_reversed_geometry
) || (pri_ext
->TopBottom
== 3))
2069 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2071 for (i
= 0; i
< cfi_info
->num_erase_regions
/ 2; i
++)
2073 int j
= (cfi_info
->num_erase_regions
- 1) - i
;
2076 swap
= cfi_info
->erase_region_info
[i
];
2077 cfi_info
->erase_region_info
[i
] = cfi_info
->erase_region_info
[j
];
2078 cfi_info
->erase_region_info
[j
] = swap
;
2083 static void cfi_fixup_0002_unlock_addresses(flash_bank_t
*bank
, void *param
)
2085 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2086 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2087 cfi_unlock_addresses_t
*unlock_addresses
= param
;
2089 pri_ext
->_unlock1
= unlock_addresses
->unlock1
;
2090 pri_ext
->_unlock2
= unlock_addresses
->unlock2
;
2093 static int cfi_probe(struct flash_bank_s
*bank
)
2095 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2096 target_t
*target
= bank
->target
;
2098 int num_sectors
= 0;
2101 u32 unlock1
= 0x555;
2102 u32 unlock2
= 0x2aa;
2105 if (bank
->target
->state
!= TARGET_HALTED
)
2107 LOG_ERROR("Target not halted");
2108 return ERROR_TARGET_NOT_HALTED
;
2111 cfi_info
->probed
= 0;
2113 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2114 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2116 if (cfi_info
->jedec_probe
)
2122 /* switch to read identifier codes mode ("AUTOSELECT") */
2123 cfi_command(bank
, 0xaa, command
);
2124 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2128 cfi_command(bank
, 0x55, command
);
2129 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2133 cfi_command(bank
, 0x90, command
);
2134 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2139 if (bank
->chip_width
== 1)
2141 u8 manufacturer
, device_id
;
2142 if((retval
= target_read_u8(target
, bank
->base
+ 0x0, &manufacturer
)) != ERROR_OK
)
2146 if((retval
= target_read_u8(target
, bank
->base
+ 0x1, &device_id
)) != ERROR_OK
)
2150 cfi_info
->manufacturer
= manufacturer
;
2151 cfi_info
->device_id
= device_id
;
2153 else if (bank
->chip_width
== 2)
2155 if((retval
= target_read_u16(target
, bank
->base
+ 0x0, &cfi_info
->manufacturer
)) != ERROR_OK
)
2159 if((retval
= target_read_u16(target
, bank
->base
+ 0x2, &cfi_info
->device_id
)) != ERROR_OK
)
2165 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info
->manufacturer
, cfi_info
->device_id
);
2166 /* switch back to read array mode */
2167 cfi_command(bank
, 0xf0, command
);
2168 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x00), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2172 cfi_command(bank
, 0xff, command
);
2173 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x00), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2178 /* check device/manufacturer ID for known non-CFI flashes. */
2179 cfi_fixup_non_cfi(bank
);
2181 /* query only if this is a CFI compatible flash,
2182 * otherwise the relevant info has already been filled in
2184 if (cfi_info
->not_cfi
== 0)
2186 /* enter CFI query mode
2187 * according to JEDEC Standard No. 68.01,
2188 * a single bus sequence with address = 0x55, data = 0x98 should put
2189 * the device into CFI query mode.
2191 * SST flashes clearly violate this, and we will consider them incompatbile for now
2193 cfi_command(bank
, 0x98, command
);
2194 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2199 cfi_info
->qry
[0] = cfi_query_u8(bank
, 0, 0x10);
2200 cfi_info
->qry
[1] = cfi_query_u8(bank
, 0, 0x11);
2201 cfi_info
->qry
[2] = cfi_query_u8(bank
, 0, 0x12);
2203 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2]);
2205 if ((cfi_info
->qry
[0] != 'Q') || (cfi_info
->qry
[1] != 'R') || (cfi_info
->qry
[2] != 'Y'))
2207 cfi_command(bank
, 0xf0, command
);
2208 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2212 cfi_command(bank
, 0xff, command
);
2213 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2217 LOG_ERROR("Could not probe bank: no QRY");
2218 return ERROR_FLASH_BANK_INVALID
;
2221 cfi_info
->pri_id
= cfi_query_u16(bank
, 0, 0x13);
2222 cfi_info
->pri_addr
= cfi_query_u16(bank
, 0, 0x15);
2223 cfi_info
->alt_id
= cfi_query_u16(bank
, 0, 0x17);
2224 cfi_info
->alt_addr
= cfi_query_u16(bank
, 0, 0x19);
2226 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2228 cfi_info
->vcc_min
= cfi_query_u8(bank
, 0, 0x1b);
2229 cfi_info
->vcc_max
= cfi_query_u8(bank
, 0, 0x1c);
2230 cfi_info
->vpp_min
= cfi_query_u8(bank
, 0, 0x1d);
2231 cfi_info
->vpp_max
= cfi_query_u8(bank
, 0, 0x1e);
2232 cfi_info
->word_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x1f);
2233 cfi_info
->buf_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x20);
2234 cfi_info
->block_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x21);
2235 cfi_info
->chip_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x22);
2236 cfi_info
->word_write_timeout_max
= cfi_query_u8(bank
, 0, 0x23);
2237 cfi_info
->buf_write_timeout_max
= cfi_query_u8(bank
, 0, 0x24);
2238 cfi_info
->block_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x25);
2239 cfi_info
->chip_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x26);
2241 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
2242 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2243 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2244 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2245 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2246 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info
->word_write_timeout_typ
, 1 << cfi_info
->buf_write_timeout_typ
,
2247 1 << cfi_info
->block_erase_timeout_typ
, 1 << cfi_info
->chip_erase_timeout_typ
);
2248 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2249 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2250 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2251 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2253 cfi_info
->dev_size
= 1<<cfi_query_u8(bank
, 0, 0x27);
2254 cfi_info
->interface_desc
= cfi_query_u16(bank
, 0, 0x28);
2255 cfi_info
->max_buf_write_size
= cfi_query_u16(bank
, 0, 0x2a);
2256 cfi_info
->num_erase_regions
= cfi_query_u8(bank
, 0, 0x2c);
2258 LOG_DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", cfi_info
->dev_size
, cfi_info
->interface_desc
, (1 << cfi_info
->max_buf_write_size
));
2260 if (cfi_info
->num_erase_regions
)
2262 cfi_info
->erase_region_info
= malloc(4 * cfi_info
->num_erase_regions
);
2263 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2265 cfi_info
->erase_region_info
[i
] = cfi_query_u32(bank
, 0, 0x2d + (4 * i
));
2266 LOG_DEBUG("erase region[%i]: %i blocks of size 0x%x", i
, (cfi_info
->erase_region_info
[i
] & 0xffff) + 1, (cfi_info
->erase_region_info
[i
] >> 16) * 256);
2271 cfi_info
->erase_region_info
= NULL
;
2274 /* We need to read the primary algorithm extended query table before calculating
2275 * the sector layout to be able to apply fixups
2277 switch(cfi_info
->pri_id
)
2279 /* Intel command set (standard and extended) */
2282 cfi_read_intel_pri_ext(bank
);
2284 /* AMD/Spansion, Atmel, ... command set */
2286 cfi_read_0002_pri_ext(bank
);
2289 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2293 /* return to read array mode
2294 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2296 cfi_command(bank
, 0xf0, command
);
2297 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2301 cfi_command(bank
, 0xff, command
);
2302 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2308 /* apply fixups depending on the primary command set */
2309 switch(cfi_info
->pri_id
)
2311 /* Intel command set (standard and extended) */
2314 cfi_fixup(bank
, cfi_0001_fixups
);
2316 /* AMD/Spansion, Atmel, ... command set */
2318 cfi_fixup(bank
, cfi_0002_fixups
);
2321 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2325 if ((cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
) != bank
->size
)
2327 LOG_WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank
->size
, cfi_info
->dev_size
);
2330 if (cfi_info
->num_erase_regions
== 0)
2332 /* a device might have only one erase block, spanning the whole device */
2333 bank
->num_sectors
= 1;
2334 bank
->sectors
= malloc(sizeof(flash_sector_t
));
2336 bank
->sectors
[sector
].offset
= 0x0;
2337 bank
->sectors
[sector
].size
= bank
->size
;
2338 bank
->sectors
[sector
].is_erased
= -1;
2339 bank
->sectors
[sector
].is_protected
= -1;
2345 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2347 num_sectors
+= (cfi_info
->erase_region_info
[i
] & 0xffff) + 1;
2350 bank
->num_sectors
= num_sectors
;
2351 bank
->sectors
= malloc(sizeof(flash_sector_t
) * num_sectors
);
2353 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2356 for (j
= 0; j
< (cfi_info
->erase_region_info
[i
] & 0xffff) + 1; j
++)
2358 bank
->sectors
[sector
].offset
= offset
;
2359 bank
->sectors
[sector
].size
= ((cfi_info
->erase_region_info
[i
] >> 16) * 256) * bank
->bus_width
/ bank
->chip_width
;
2360 offset
+= bank
->sectors
[sector
].size
;
2361 bank
->sectors
[sector
].is_erased
= -1;
2362 bank
->sectors
[sector
].is_protected
= -1;
2366 if (offset
!= cfi_info
->dev_size
)
2368 LOG_WARNING("CFI size is 0x%x, but total sector size is 0x%x", cfi_info
->dev_size
, offset
);
2372 cfi_info
->probed
= 1;
2377 static int cfi_auto_probe(struct flash_bank_s
*bank
)
2379 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2380 if (cfi_info
->probed
)
2382 return cfi_probe(bank
);
2386 static int cfi_intel_protect_check(struct flash_bank_s
*bank
)
2389 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2390 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2391 target_t
*target
= bank
->target
;
2392 u8 command
[CFI_MAX_BUS_WIDTH
];
2395 /* check if block lock bits are supported on this device */
2396 if (!(pri_ext
->blk_status_reg_mask
& 0x1))
2397 return ERROR_FLASH_OPERATION_FAILED
;
2399 cfi_command(bank
, 0x90, command
);
2400 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2405 for (i
= 0; i
< bank
->num_sectors
; i
++)
2407 u8 block_status
= cfi_get_u8(bank
, i
, 0x2);
2409 if (block_status
& 1)
2410 bank
->sectors
[i
].is_protected
= 1;
2412 bank
->sectors
[i
].is_protected
= 0;
2415 cfi_command(bank
, 0xff, command
);
2416 return target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2419 static int cfi_spansion_protect_check(struct flash_bank_s
*bank
)
2422 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2423 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2424 target_t
*target
= bank
->target
;
2428 cfi_command(bank
, 0xaa, command
);
2429 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2434 cfi_command(bank
, 0x55, command
);
2435 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2440 cfi_command(bank
, 0x90, command
);
2441 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2446 for (i
= 0; i
< bank
->num_sectors
; i
++)
2448 u8 block_status
= cfi_get_u8(bank
, i
, 0x2);
2450 if (block_status
& 1)
2451 bank
->sectors
[i
].is_protected
= 1;
2453 bank
->sectors
[i
].is_protected
= 0;
2456 cfi_command(bank
, 0xf0, command
);
2457 return target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2460 static int cfi_protect_check(struct flash_bank_s
*bank
)
2462 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2464 if (bank
->target
->state
!= TARGET_HALTED
)
2466 LOG_ERROR("Target not halted");
2467 return ERROR_TARGET_NOT_HALTED
;
2470 if (cfi_info
->qry
[0] != 'Q')
2471 return ERROR_FLASH_BANK_NOT_PROBED
;
2473 switch(cfi_info
->pri_id
)
2477 return cfi_intel_protect_check(bank
);
2480 return cfi_spansion_protect_check(bank
);
2483 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2490 static int cfi_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
2493 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2495 if (cfi_info
->qry
[0] == (char)-1)
2497 printed
= snprintf(buf
, buf_size
, "\ncfi flash bank not probed yet\n");
2501 if (cfi_info
->not_cfi
== 0)
2502 printed
= snprintf(buf
, buf_size
, "\ncfi information:\n");
2504 printed
= snprintf(buf
, buf_size
, "\nnon-cfi flash:\n");
2506 buf_size
-= printed
;
2508 printed
= snprintf(buf
, buf_size
, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2509 cfi_info
->manufacturer
, cfi_info
->device_id
);
2511 buf_size
-= printed
;
2513 if (cfi_info
->not_cfi
== 0)
2515 printed
= snprintf(buf
, buf_size
, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2517 buf_size
-= printed
;
2519 printed
= snprintf(buf
, buf_size
, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2520 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2521 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2522 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2523 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2525 buf_size
-= printed
;
2527 printed
= snprintf(buf
, buf_size
, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2528 1 << cfi_info
->word_write_timeout_typ
,
2529 1 << cfi_info
->buf_write_timeout_typ
,
2530 1 << cfi_info
->block_erase_timeout_typ
,
2531 1 << cfi_info
->chip_erase_timeout_typ
);
2533 buf_size
-= printed
;
2535 printed
= snprintf(buf
, buf_size
, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2536 (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2537 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2538 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2539 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2541 buf_size
-= printed
;
2543 printed
= snprintf(buf
, buf_size
, "size: 0x%x, interface desc: %i, max buffer write size: %x\n",
2545 cfi_info
->interface_desc
,
2546 1 << cfi_info
->max_buf_write_size
);
2548 buf_size
-= printed
;
2550 switch(cfi_info
->pri_id
)
2554 cfi_intel_info(bank
, buf
, buf_size
);
2557 cfi_spansion_info(bank
, buf
, buf_size
);
2560 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
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