1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
29 #include "binarybuffer.h"
32 #define CFI_MAX_BUS_WIDTH 4
33 #define CFI_MAX_CHIP_WIDTH 4
35 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
36 #define CFI_MAX_INTEL_CODESIZE 256
38 static cfi_unlock_addresses_t cfi_unlock_addresses
[] =
40 [CFI_UNLOCK_555_2AA
] = { .unlock1
= 0x555, .unlock2
= 0x2aa },
41 [CFI_UNLOCK_5555_2AAA
] = { .unlock1
= 0x5555, .unlock2
= 0x2aaa },
44 /* CFI fixups foward declarations */
45 static void cfi_fixup_0002_erase_regions(flash_bank_t
*flash
, void *param
);
46 static void cfi_fixup_0002_unlock_addresses(flash_bank_t
*flash
, void *param
);
47 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t
*flash
, void *param
);
49 /* fixup after reading cmdset 0002 primary query table */
50 static const cfi_fixup_t cfi_0002_fixups
[] = {
51 {CFI_MFR_SST
, 0x00D4, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
52 {CFI_MFR_SST
, 0x00D5, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
53 {CFI_MFR_SST
, 0x00D6, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
54 {CFI_MFR_SST
, 0x00D7, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
55 {CFI_MFR_SST
, 0x2780, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
56 {CFI_MFR_ATMEL
, 0x00C8, cfi_fixup_atmel_reversed_erase_regions
, NULL
},
57 {CFI_MFR_FUJITSU
, 0x226b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
58 {CFI_MFR_AMIC
, 0xb31a, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
59 {CFI_MFR_MX
, 0x225b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
60 {CFI_MFR_AMD
, 0x225b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
61 {CFI_MFR_ANY
, CFI_ID_ANY
, cfi_fixup_0002_erase_regions
, NULL
},
65 /* fixup after reading cmdset 0001 primary query table */
66 static const cfi_fixup_t cfi_0001_fixups
[] = {
70 static void cfi_fixup(flash_bank_t
*bank
, const cfi_fixup_t
*fixups
)
72 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
75 for (f
= fixups
; f
->fixup
; f
++)
77 if (((f
->mfr
== CFI_MFR_ANY
) || (f
->mfr
== cfi_info
->manufacturer
)) &&
78 ((f
->id
== CFI_ID_ANY
) || (f
->id
== cfi_info
->device_id
)))
80 f
->fixup(bank
, f
->param
);
85 /* inline uint32_t flash_address(flash_bank_t *bank, int sector, uint32_t offset) */
86 static __inline__
uint32_t flash_address(flash_bank_t
*bank
, int sector
, uint32_t offset
)
88 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
90 if (cfi_info
->x16_as_x8
) offset
*= 2;
92 /* while the sector list isn't built, only accesses to sector 0 work */
94 return bank
->base
+ offset
* bank
->bus_width
;
99 LOG_ERROR("BUG: sector list not yet built");
102 return bank
->base
+ bank
->sectors
[sector
].offset
+ offset
* bank
->bus_width
;
107 static void cfi_command(flash_bank_t
*bank
, uint8_t cmd
, uint8_t *cmd_buf
)
111 /* clear whole buffer, to ensure bits that exceed the bus_width
114 for (i
= 0; i
< CFI_MAX_BUS_WIDTH
; i
++)
117 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
119 for (i
= bank
->bus_width
; i
> 0; i
--)
121 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
126 for (i
= 1; i
<= bank
->bus_width
; i
++)
128 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
133 /* read unsigned 8-bit value from the bank
134 * flash banks are expected to be made of similar chips
135 * the query result should be the same for all
137 static uint8_t cfi_query_u8(flash_bank_t
*bank
, int sector
, uint32_t offset
)
139 target_t
*target
= bank
->target
;
140 uint8_t data
[CFI_MAX_BUS_WIDTH
];
142 target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
144 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
147 return data
[bank
->bus_width
- 1];
150 /* read unsigned 8-bit value from the bank
151 * in case of a bank made of multiple chips,
152 * the individual values are ORed
154 static uint8_t cfi_get_u8(flash_bank_t
*bank
, int sector
, uint32_t offset
)
156 target_t
*target
= bank
->target
;
157 uint8_t data
[CFI_MAX_BUS_WIDTH
];
160 target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
162 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
164 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
172 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
173 value
|= data
[bank
->bus_width
- 1 - i
];
179 static uint16_t cfi_query_u16(flash_bank_t
*bank
, int sector
, uint32_t offset
)
181 target_t
*target
= bank
->target
;
182 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
183 uint8_t data
[CFI_MAX_BUS_WIDTH
* 2];
185 if (cfi_info
->x16_as_x8
)
188 for (i
= 0;i
< 2;i
++)
189 target_read_memory(target
, flash_address(bank
, sector
, offset
+ i
), bank
->bus_width
, 1,
190 &data
[i
*bank
->bus_width
]);
193 target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 2, data
);
195 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
196 return data
[0] | data
[bank
->bus_width
] << 8;
198 return data
[bank
->bus_width
- 1] | data
[(2 * bank
->bus_width
) - 1] << 8;
201 static uint32_t cfi_query_u32(flash_bank_t
*bank
, int sector
, uint32_t offset
)
203 target_t
*target
= bank
->target
;
204 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
205 uint8_t data
[CFI_MAX_BUS_WIDTH
* 4];
207 if (cfi_info
->x16_as_x8
)
210 for (i
= 0;i
< 4;i
++)
211 target_read_memory(target
, flash_address(bank
, sector
, offset
+ i
), bank
->bus_width
, 1,
212 &data
[i
*bank
->bus_width
]);
215 target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 4, data
);
217 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
218 return data
[0] | data
[bank
->bus_width
] << 8 | data
[bank
->bus_width
* 2] << 16 | data
[bank
->bus_width
* 3] << 24;
220 return data
[bank
->bus_width
- 1] | data
[(2* bank
->bus_width
) - 1] << 8 |
221 data
[(3 * bank
->bus_width
) - 1] << 16 | data
[(4 * bank
->bus_width
) - 1] << 24;
224 static void cfi_intel_clear_status_register(flash_bank_t
*bank
)
226 target_t
*target
= bank
->target
;
229 if (target
->state
!= TARGET_HALTED
)
231 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
235 cfi_command(bank
, 0x50, command
);
236 target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
239 uint8_t cfi_intel_wait_status_busy(flash_bank_t
*bank
, int timeout
)
243 while ((!((status
= cfi_get_u8(bank
, 0, 0x0)) & 0x80)) && (timeout
-- > 0))
245 LOG_DEBUG("status: 0x%x", status
);
249 /* mask out bit 0 (reserved) */
250 status
= status
& 0xfe;
252 LOG_DEBUG("status: 0x%x", status
);
254 if ((status
& 0x80) != 0x80)
256 LOG_ERROR("timeout while waiting for WSM to become ready");
258 else if (status
!= 0x80)
260 LOG_ERROR("status register: 0x%x", status
);
262 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
264 LOG_ERROR("Program suspended");
266 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
268 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
270 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
272 LOG_ERROR("Block Erase Suspended");
274 cfi_intel_clear_status_register(bank
);
280 int cfi_spansion_wait_status_busy(flash_bank_t
*bank
, int timeout
)
282 uint8_t status
, oldstatus
;
283 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
285 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
288 status
= cfi_get_u8(bank
, 0, 0x0);
289 if ((status
^ oldstatus
) & 0x40) {
290 if (status
& cfi_info
->status_poll_mask
& 0x20) {
291 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
292 status
= cfi_get_u8(bank
, 0, 0x0);
293 if ((status
^ oldstatus
) & 0x40) {
294 LOG_ERROR("dq5 timeout, status: 0x%x", status
);
295 return(ERROR_FLASH_OPERATION_FAILED
);
297 LOG_DEBUG("status: 0x%x", status
);
301 } else { /* no toggle: finished, OK */
302 LOG_DEBUG("status: 0x%x", status
);
308 } while (timeout
-- > 0);
310 LOG_ERROR("timeout, status: 0x%x", status
);
312 return(ERROR_FLASH_BUSY
);
315 static int cfi_read_intel_pri_ext(flash_bank_t
*bank
)
318 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
319 cfi_intel_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_intel_pri_ext_t
));
320 target_t
*target
= bank
->target
;
323 cfi_info
->pri_ext
= pri_ext
;
325 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
326 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
327 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
329 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
331 cfi_command(bank
, 0xf0, command
);
332 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
336 cfi_command(bank
, 0xff, command
);
337 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
341 LOG_ERROR("Could not read bank flash bank information");
342 return ERROR_FLASH_BANK_INVALID
;
345 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
346 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
348 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
350 pri_ext
->feature_support
= cfi_query_u32(bank
, 0, cfi_info
->pri_addr
+ 5);
351 pri_ext
->suspend_cmd_support
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
352 pri_ext
->blk_status_reg_mask
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xa);
354 LOG_DEBUG("feature_support: 0x%" PRIx32
", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
355 pri_ext
->feature_support
,
356 pri_ext
->suspend_cmd_support
,
357 pri_ext
->blk_status_reg_mask
);
359 pri_ext
->vcc_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xc);
360 pri_ext
->vpp_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xd);
362 LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
363 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
364 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
366 pri_ext
->num_protection_fields
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xe);
367 if (pri_ext
->num_protection_fields
!= 1)
369 LOG_WARNING("expected one protection register field, but found %i", pri_ext
->num_protection_fields
);
372 pri_ext
->prot_reg_addr
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xf);
373 pri_ext
->fact_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x11);
374 pri_ext
->user_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x12);
376 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
381 static int cfi_read_spansion_pri_ext(flash_bank_t
*bank
)
384 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
385 cfi_spansion_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_spansion_pri_ext_t
));
386 target_t
*target
= bank
->target
;
389 cfi_info
->pri_ext
= pri_ext
;
391 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
392 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
393 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
395 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
397 cfi_command(bank
, 0xf0, command
);
398 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
402 LOG_ERROR("Could not read spansion bank information");
403 return ERROR_FLASH_BANK_INVALID
;
406 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
407 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
409 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
411 pri_ext
->SiliconRevision
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
412 pri_ext
->EraseSuspend
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
413 pri_ext
->BlkProt
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
414 pri_ext
->TmpBlkUnprotect
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
415 pri_ext
->BlkProtUnprot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
416 pri_ext
->SimultaneousOps
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 10);
417 pri_ext
->BurstMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 11);
418 pri_ext
->PageMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 12);
419 pri_ext
->VppMin
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 13);
420 pri_ext
->VppMax
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 14);
421 pri_ext
->TopBottom
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 15);
423 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext
->SiliconRevision
,
424 pri_ext
->EraseSuspend
, pri_ext
->BlkProt
);
426 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext
->TmpBlkUnprotect
,
427 pri_ext
->BlkProtUnprot
, pri_ext
->SimultaneousOps
);
429 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext
->BurstMode
, pri_ext
->PageMode
);
432 LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
433 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
434 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
436 LOG_DEBUG("WP# protection 0x%x", pri_ext
->TopBottom
);
438 /* default values for implementation specific workarounds */
439 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
440 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
441 pri_ext
->_reversed_geometry
= 0;
446 static int cfi_read_atmel_pri_ext(flash_bank_t
*bank
)
449 cfi_atmel_pri_ext_t atmel_pri_ext
;
450 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
451 cfi_spansion_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_spansion_pri_ext_t
));
452 target_t
*target
= bank
->target
;
455 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
456 * but a different primary extended query table.
457 * We read the atmel table, and prepare a valid AMD/Spansion query table.
460 memset(pri_ext
, 0, sizeof(cfi_spansion_pri_ext_t
));
462 cfi_info
->pri_ext
= pri_ext
;
464 atmel_pri_ext
.pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
465 atmel_pri_ext
.pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
466 atmel_pri_ext
.pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
468 if ((atmel_pri_ext
.pri
[0] != 'P') || (atmel_pri_ext
.pri
[1] != 'R') || (atmel_pri_ext
.pri
[2] != 'I'))
470 cfi_command(bank
, 0xf0, command
);
471 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
475 LOG_ERROR("Could not read atmel bank information");
476 return ERROR_FLASH_BANK_INVALID
;
479 pri_ext
->pri
[0] = atmel_pri_ext
.pri
[0];
480 pri_ext
->pri
[1] = atmel_pri_ext
.pri
[1];
481 pri_ext
->pri
[2] = atmel_pri_ext
.pri
[2];
483 atmel_pri_ext
.major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
484 atmel_pri_ext
.minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
486 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext
.pri
[0], atmel_pri_ext
.pri
[1], atmel_pri_ext
.pri
[2], atmel_pri_ext
.major_version
, atmel_pri_ext
.minor_version
);
488 pri_ext
->major_version
= atmel_pri_ext
.major_version
;
489 pri_ext
->minor_version
= atmel_pri_ext
.minor_version
;
491 atmel_pri_ext
.features
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
492 atmel_pri_ext
.bottom_boot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
493 atmel_pri_ext
.burst_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
494 atmel_pri_ext
.page_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
496 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
497 atmel_pri_ext
.features
, atmel_pri_ext
.bottom_boot
, atmel_pri_ext
.burst_mode
, atmel_pri_ext
.page_mode
);
499 if (atmel_pri_ext
.features
& 0x02)
500 pri_ext
->EraseSuspend
= 2;
502 if (atmel_pri_ext
.bottom_boot
)
503 pri_ext
->TopBottom
= 2;
505 pri_ext
->TopBottom
= 3;
507 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
508 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
513 static int cfi_read_0002_pri_ext(flash_bank_t
*bank
)
515 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
517 if (cfi_info
->manufacturer
== CFI_MFR_ATMEL
)
519 return cfi_read_atmel_pri_ext(bank
);
523 return cfi_read_spansion_pri_ext(bank
);
527 static int cfi_spansion_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
530 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
531 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
533 printed
= snprintf(buf
, buf_size
, "\nSpansion primary algorithm extend information:\n");
537 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0],
538 pri_ext
->pri
[1], pri_ext
->pri
[2],
539 pri_ext
->major_version
, pri_ext
->minor_version
);
543 printed
= snprintf(buf
, buf_size
, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
544 (pri_ext
->SiliconRevision
) >> 2,
545 (pri_ext
->SiliconRevision
) & 0x03);
549 printed
= snprintf(buf
, buf_size
, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
550 pri_ext
->EraseSuspend
,
555 printed
= snprintf(buf
, buf_size
, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
556 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
557 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
562 static int cfi_intel_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
565 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
566 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
568 printed
= snprintf(buf
, buf_size
, "\nintel primary algorithm extend information:\n");
572 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
576 printed
= snprintf(buf
, buf_size
, "feature_support: 0x%" PRIx32
", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext
->feature_support
, pri_ext
->suspend_cmd_support
, pri_ext
->blk_status_reg_mask
);
580 printed
= snprintf(buf
, buf_size
, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
581 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
582 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
586 printed
= snprintf(buf
, buf_size
, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
591 static int cfi_register_commands(struct command_context_s
*cmd_ctx
)
593 /*command_t *cfi_cmd = */
594 register_command(cmd_ctx
, NULL
, "cfi", NULL
, COMMAND_ANY
, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
596 register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
597 "print part id of cfi flash bank <num>");
602 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
604 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command
)
606 cfi_flash_bank_t
*cfi_info
;
613 LOG_WARNING("incomplete flash_bank cfi configuration");
614 return ERROR_FLASH_BANK_INVALID
;
617 uint16_t chip_width
, bus_width
;
618 COMMAND_PARSE_NUMBER(u16
, args
[3], bus_width
);
619 COMMAND_PARSE_NUMBER(u16
, args
[4], chip_width
);
621 if ((chip_width
> CFI_MAX_CHIP_WIDTH
)
622 || (bus_width
> CFI_MAX_BUS_WIDTH
))
624 LOG_ERROR("chip and bus width have to specified in bytes");
625 return ERROR_FLASH_BANK_INVALID
;
628 cfi_info
= malloc(sizeof(cfi_flash_bank_t
));
629 cfi_info
->probed
= 0;
630 bank
->driver_priv
= cfi_info
;
632 cfi_info
->write_algorithm
= NULL
;
634 cfi_info
->x16_as_x8
= 0;
635 cfi_info
->jedec_probe
= 0;
636 cfi_info
->not_cfi
= 0;
638 for (i
= 6; i
< argc
; i
++)
640 if (strcmp(args
[i
], "x16_as_x8") == 0)
642 cfi_info
->x16_as_x8
= 1;
644 else if (strcmp(args
[i
], "jedec_probe") == 0)
646 cfi_info
->jedec_probe
= 1;
650 cfi_info
->write_algorithm
= NULL
;
652 /* bank wasn't probed yet */
653 cfi_info
->qry
[0] = -1;
658 static int cfi_intel_erase(struct flash_bank_s
*bank
, int first
, int last
)
661 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
662 target_t
*target
= bank
->target
;
666 cfi_intel_clear_status_register(bank
);
668 for (i
= first
; i
<= last
; i
++)
670 cfi_command(bank
, 0x20, command
);
671 if ((retval
= target_write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
676 cfi_command(bank
, 0xd0, command
);
677 if ((retval
= target_write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
682 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == 0x80)
683 bank
->sectors
[i
].is_erased
= 1;
686 cfi_command(bank
, 0xff, command
);
687 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
692 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32
, i
, bank
->base
);
693 return ERROR_FLASH_OPERATION_FAILED
;
697 cfi_command(bank
, 0xff, command
);
698 return target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
702 static int cfi_spansion_erase(struct flash_bank_s
*bank
, int first
, int last
)
705 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
706 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
707 target_t
*target
= bank
->target
;
711 for (i
= first
; i
<= last
; i
++)
713 cfi_command(bank
, 0xaa, command
);
714 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
719 cfi_command(bank
, 0x55, command
);
720 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
725 cfi_command(bank
, 0x80, command
);
726 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
731 cfi_command(bank
, 0xaa, command
);
732 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
737 cfi_command(bank
, 0x55, command
);
738 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
743 cfi_command(bank
, 0x30, command
);
744 if ((retval
= target_write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
749 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == ERROR_OK
)
750 bank
->sectors
[i
].is_erased
= 1;
753 cfi_command(bank
, 0xf0, command
);
754 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
759 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32
, i
, bank
->base
);
760 return ERROR_FLASH_OPERATION_FAILED
;
764 cfi_command(bank
, 0xf0, command
);
765 return target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
768 static int cfi_erase(struct flash_bank_s
*bank
, int first
, int last
)
770 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
772 if (bank
->target
->state
!= TARGET_HALTED
)
774 LOG_ERROR("Target not halted");
775 return ERROR_TARGET_NOT_HALTED
;
778 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
780 return ERROR_FLASH_SECTOR_INVALID
;
783 if (cfi_info
->qry
[0] != 'Q')
784 return ERROR_FLASH_BANK_NOT_PROBED
;
786 switch (cfi_info
->pri_id
)
790 return cfi_intel_erase(bank
, first
, last
);
793 return cfi_spansion_erase(bank
, first
, last
);
796 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
803 static int cfi_intel_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
806 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
807 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
808 target_t
*target
= bank
->target
;
813 /* if the device supports neither legacy lock/unlock (bit 3) nor
814 * instant individual block locking (bit 5).
816 if (!(pri_ext
->feature_support
& 0x28))
817 return ERROR_FLASH_OPERATION_FAILED
;
819 cfi_intel_clear_status_register(bank
);
821 for (i
= first
; i
<= last
; i
++)
823 cfi_command(bank
, 0x60, command
);
824 LOG_DEBUG("address: 0x%4.4" PRIx32
", command: 0x%4.4" PRIx32
, flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
825 if ((retval
= target_write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
831 cfi_command(bank
, 0x01, command
);
832 LOG_DEBUG("address: 0x%4.4" PRIx32
", command: 0x%4.4" PRIx32
, flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
833 if ((retval
= target_write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
837 bank
->sectors
[i
].is_protected
= 1;
841 cfi_command(bank
, 0xd0, command
);
842 LOG_DEBUG("address: 0x%4.4" PRIx32
", command: 0x%4.4" PRIx32
, flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
843 if ((retval
= target_write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
847 bank
->sectors
[i
].is_protected
= 0;
850 /* instant individual block locking doesn't require reading of the status register */
851 if (!(pri_ext
->feature_support
& 0x20))
853 /* Clear lock bits operation may take up to 1.4s */
854 cfi_intel_wait_status_busy(bank
, 1400);
858 uint8_t block_status
;
859 /* read block lock bit, to verify status */
860 cfi_command(bank
, 0x90, command
);
861 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
)) != ERROR_OK
)
865 block_status
= cfi_get_u8(bank
, i
, 0x2);
867 if ((block_status
& 0x1) != set
)
869 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set
, block_status
);
870 cfi_command(bank
, 0x70, command
);
871 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
)) != ERROR_OK
)
875 cfi_intel_wait_status_busy(bank
, 10);
878 return ERROR_FLASH_OPERATION_FAILED
;
888 /* if the device doesn't support individual block lock bits set/clear,
889 * all blocks have been unlocked in parallel, so we set those that should be protected
891 if ((!set
) && (!(pri_ext
->feature_support
& 0x20)))
893 for (i
= 0; i
< bank
->num_sectors
; i
++)
895 if (bank
->sectors
[i
].is_protected
== 1)
897 cfi_intel_clear_status_register(bank
);
899 cfi_command(bank
, 0x60, command
);
900 if ((retval
= target_write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
905 cfi_command(bank
, 0x01, command
);
906 if ((retval
= target_write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
911 cfi_intel_wait_status_busy(bank
, 100);
916 cfi_command(bank
, 0xff, command
);
917 return target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
920 static int cfi_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
922 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
924 if (bank
->target
->state
!= TARGET_HALTED
)
926 LOG_ERROR("Target not halted");
927 return ERROR_TARGET_NOT_HALTED
;
930 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
932 return ERROR_FLASH_SECTOR_INVALID
;
935 if (cfi_info
->qry
[0] != 'Q')
936 return ERROR_FLASH_BANK_NOT_PROBED
;
938 switch (cfi_info
->pri_id
)
942 cfi_intel_protect(bank
, set
, first
, last
);
945 LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info
->pri_id
);
952 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
953 static void cfi_add_byte(struct flash_bank_s
*bank
, uint8_t *word
, uint8_t byte
)
955 /* target_t *target = bank->target; */
960 * The data to flash must not be changed in endian! We write a bytestrem in
961 * target byte order already. Only the control and status byte lane of the flash
962 * WSM is interpreted by the CPU in different ways, when read a uint16_t or uint32_t
963 * word (data seems to be in the upper or lower byte lane for uint16_t accesses).
967 if (target
->endianness
== TARGET_LITTLE_ENDIAN
)
971 for (i
= 0; i
< bank
->bus_width
- 1; i
++)
972 word
[i
] = word
[i
+ 1];
973 word
[bank
->bus_width
- 1] = byte
;
979 for (i
= bank
->bus_width
- 1; i
> 0; i
--)
980 word
[i
] = word
[i
- 1];
986 /* Convert code image to target endian */
987 /* FIXME create general block conversion fcts in target.c?) */
988 static void cfi_fix_code_endian(target_t
*target
, uint8_t *dest
, const uint32_t *src
, uint32_t count
)
991 for (i
= 0; i
< count
; i
++)
993 target_buffer_set_u32(target
, dest
, *src
);
999 static uint32_t cfi_command_val(flash_bank_t
*bank
, uint8_t cmd
)
1001 target_t
*target
= bank
->target
;
1003 uint8_t buf
[CFI_MAX_BUS_WIDTH
];
1004 cfi_command(bank
, cmd
, buf
);
1005 switch (bank
->bus_width
)
1011 return target_buffer_get_u16(target
, buf
);
1014 return target_buffer_get_u32(target
, buf
);
1017 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1022 static int cfi_intel_write_block(struct flash_bank_s
*bank
, uint8_t *buffer
, uint32_t address
, uint32_t count
)
1024 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1025 target_t
*target
= bank
->target
;
1026 reg_param_t reg_params
[7];
1027 armv4_5_algorithm_t armv4_5_info
;
1028 working_area_t
*source
;
1029 uint32_t buffer_size
= 32768;
1030 uint32_t write_command_val
, busy_pattern_val
, error_pattern_val
;
1032 /* algorithm register usage:
1033 * r0: source address (in RAM)
1034 * r1: target address (in Flash)
1036 * r3: flash write command
1037 * r4: status byte (returned to host)
1038 * r5: busy test pattern
1039 * r6: error test pattern
1042 static const uint32_t word_32_code
[] = {
1043 0xe4904004, /* loop: ldr r4, [r0], #4 */
1044 0xe5813000, /* str r3, [r1] */
1045 0xe5814000, /* str r4, [r1] */
1046 0xe5914000, /* busy: ldr r4, [r1] */
1047 0xe0047005, /* and r7, r4, r5 */
1048 0xe1570005, /* cmp r7, r5 */
1049 0x1afffffb, /* bne busy */
1050 0xe1140006, /* tst r4, r6 */
1051 0x1a000003, /* bne done */
1052 0xe2522001, /* subs r2, r2, #1 */
1053 0x0a000001, /* beq done */
1054 0xe2811004, /* add r1, r1 #4 */
1055 0xeafffff2, /* b loop */
1056 0xeafffffe /* done: b -2 */
1059 static const uint32_t word_16_code
[] = {
1060 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1061 0xe1c130b0, /* strh r3, [r1] */
1062 0xe1c140b0, /* strh r4, [r1] */
1063 0xe1d140b0, /* busy ldrh r4, [r1] */
1064 0xe0047005, /* and r7, r4, r5 */
1065 0xe1570005, /* cmp r7, r5 */
1066 0x1afffffb, /* bne busy */
1067 0xe1140006, /* tst r4, r6 */
1068 0x1a000003, /* bne done */
1069 0xe2522001, /* subs r2, r2, #1 */
1070 0x0a000001, /* beq done */
1071 0xe2811002, /* add r1, r1 #2 */
1072 0xeafffff2, /* b loop */
1073 0xeafffffe /* done: b -2 */
1076 static const uint32_t word_8_code
[] = {
1077 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1078 0xe5c13000, /* strb r3, [r1] */
1079 0xe5c14000, /* strb r4, [r1] */
1080 0xe5d14000, /* busy ldrb r4, [r1] */
1081 0xe0047005, /* and r7, r4, r5 */
1082 0xe1570005, /* cmp r7, r5 */
1083 0x1afffffb, /* bne busy */
1084 0xe1140006, /* tst r4, r6 */
1085 0x1a000003, /* bne done */
1086 0xe2522001, /* subs r2, r2, #1 */
1087 0x0a000001, /* beq done */
1088 0xe2811001, /* add r1, r1 #1 */
1089 0xeafffff2, /* b loop */
1090 0xeafffffe /* done: b -2 */
1092 uint8_t target_code
[4*CFI_MAX_INTEL_CODESIZE
];
1093 const uint32_t *target_code_src
;
1094 uint32_t target_code_size
;
1095 int retval
= ERROR_OK
;
1098 cfi_intel_clear_status_register(bank
);
1100 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
1101 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
1102 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
1104 /* If we are setting up the write_algorith, we need target_code_src */
1105 /* if not we only need target_code_size. */
1107 /* However, we don't want to create multiple code paths, so we */
1108 /* do the unecessary evaluation of target_code_src, which the */
1109 /* compiler will probably nicely optimize away if not needed */
1111 /* prepare algorithm code for target endian */
1112 switch (bank
->bus_width
)
1115 target_code_src
= word_8_code
;
1116 target_code_size
= sizeof(word_8_code
);
1119 target_code_src
= word_16_code
;
1120 target_code_size
= sizeof(word_16_code
);
1123 target_code_src
= word_32_code
;
1124 target_code_size
= sizeof(word_32_code
);
1127 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1128 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1131 /* flash write code */
1132 if (!cfi_info
->write_algorithm
)
1134 if (target_code_size
> sizeof(target_code
))
1136 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1137 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1139 cfi_fix_code_endian(target
, target_code
, target_code_src
, target_code_size
/ 4);
1141 /* Get memory for block write handler */
1142 retval
= target_alloc_working_area(target
, target_code_size
, &cfi_info
->write_algorithm
);
1143 if (retval
!= ERROR_OK
)
1145 LOG_WARNING("No working area available, can't do block memory writes");
1146 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1149 /* write algorithm code to working area */
1150 retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
, target_code_size
, target_code
);
1151 if (retval
!= ERROR_OK
)
1153 LOG_ERROR("Unable to write block write code to target");
1158 /* Get a workspace buffer for the data to flash starting with 32k size.
1159 Half size until buffer would be smaller 256 Bytem then fail back */
1160 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1161 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
1164 if (buffer_size
<= 256)
1166 LOG_WARNING("no large enough working area available, can't do block memory writes");
1167 retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1172 /* setup algo registers */
1173 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1174 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1175 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1176 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1177 init_reg_param(®_params
[4], "r4", 32, PARAM_IN
);
1178 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
);
1179 init_reg_param(®_params
[6], "r6", 32, PARAM_OUT
);
1181 /* prepare command and status register patterns */
1182 write_command_val
= cfi_command_val(bank
, 0x40);
1183 busy_pattern_val
= cfi_command_val(bank
, 0x80);
1184 error_pattern_val
= cfi_command_val(bank
, 0x7e);
1186 LOG_INFO("Using target buffer at 0x%08" PRIx32
" and of size 0x%04" PRIx32
, source
->address
, buffer_size
);
1188 /* Programming main loop */
1191 uint32_t thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1194 if ((retval
= target_write_buffer(target
, source
->address
, thisrun_count
, buffer
)) != ERROR_OK
)
1199 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1200 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1201 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1203 buf_set_u32(reg_params
[3].value
, 0, 32, write_command_val
);
1204 buf_set_u32(reg_params
[5].value
, 0, 32, busy_pattern_val
);
1205 buf_set_u32(reg_params
[6].value
, 0, 32, error_pattern_val
);
1207 LOG_INFO("Write 0x%04" PRIx32
" bytes to flash at 0x%08" PRIx32
, thisrun_count
, address
);
1209 /* Execute algorithm, assume breakpoint for last instruction */
1210 retval
= target_run_algorithm(target
, 0, NULL
, 7, reg_params
,
1211 cfi_info
->write_algorithm
->address
,
1212 cfi_info
->write_algorithm
->address
+ target_code_size
- sizeof(uint32_t),
1213 10000, /* 10s should be enough for max. 32k of data */
1216 /* On failure try a fall back to direct word writes */
1217 if (retval
!= ERROR_OK
)
1219 cfi_intel_clear_status_register(bank
);
1220 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1221 retval
= ERROR_FLASH_OPERATION_FAILED
;
1222 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1223 /* FIXME To allow fall back or recovery, we must save the actual status
1224 somewhere, so that a higher level code can start recovery. */
1228 /* Check return value from algo code */
1229 wsm_error
= buf_get_u32(reg_params
[4].value
, 0, 32) & error_pattern_val
;
1232 /* read status register (outputs debug inforation) */
1233 cfi_intel_wait_status_busy(bank
, 100);
1234 cfi_intel_clear_status_register(bank
);
1235 retval
= ERROR_FLASH_OPERATION_FAILED
;
1239 buffer
+= thisrun_count
;
1240 address
+= thisrun_count
;
1241 count
-= thisrun_count
;
1244 /* free up resources */
1247 target_free_working_area(target
, source
);
1249 if (cfi_info
->write_algorithm
)
1251 target_free_working_area(target
, cfi_info
->write_algorithm
);
1252 cfi_info
->write_algorithm
= NULL
;
1255 destroy_reg_param(®_params
[0]);
1256 destroy_reg_param(®_params
[1]);
1257 destroy_reg_param(®_params
[2]);
1258 destroy_reg_param(®_params
[3]);
1259 destroy_reg_param(®_params
[4]);
1260 destroy_reg_param(®_params
[5]);
1261 destroy_reg_param(®_params
[6]);
1266 static int cfi_spansion_write_block(struct flash_bank_s
*bank
, uint8_t *buffer
, uint32_t address
, uint32_t count
)
1268 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1269 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1270 target_t
*target
= bank
->target
;
1271 reg_param_t reg_params
[10];
1272 armv4_5_algorithm_t armv4_5_info
;
1273 working_area_t
*source
;
1274 uint32_t buffer_size
= 32768;
1276 int retval
, retvaltemp
;
1277 int exit_code
= ERROR_OK
;
1279 /* input parameters - */
1280 /* R0 = source address */
1281 /* R1 = destination address */
1282 /* R2 = number of writes */
1283 /* R3 = flash write command */
1284 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1285 /* output parameters - */
1286 /* R5 = 0x80 ok 0x00 bad */
1287 /* temp registers - */
1288 /* R6 = value read from flash to test status */
1289 /* R7 = holding register */
1290 /* unlock registers - */
1291 /* R8 = unlock1_addr */
1292 /* R9 = unlock1_cmd */
1293 /* R10 = unlock2_addr */
1294 /* R11 = unlock2_cmd */
1296 static const uint32_t word_32_code
[] = {
1297 /* 00008100 <sp_32_code>: */
1298 0xe4905004, /* ldr r5, [r0], #4 */
1299 0xe5889000, /* str r9, [r8] */
1300 0xe58ab000, /* str r11, [r10] */
1301 0xe5883000, /* str r3, [r8] */
1302 0xe5815000, /* str r5, [r1] */
1303 0xe1a00000, /* nop */
1305 /* 00008110 <sp_32_busy>: */
1306 0xe5916000, /* ldr r6, [r1] */
1307 0xe0257006, /* eor r7, r5, r6 */
1308 0xe0147007, /* ands r7, r4, r7 */
1309 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1310 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1311 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1312 0xe5916000, /* ldr r6, [r1] */
1313 0xe0257006, /* eor r7, r5, r6 */
1314 0xe0147007, /* ands r7, r4, r7 */
1315 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1316 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1317 0x1a000004, /* bne 8154 <sp_32_done> */
1319 /* 00008140 <sp_32_cont>: */
1320 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1321 0x03a05080, /* moveq r5, #128 ; 0x80 */
1322 0x0a000001, /* beq 8154 <sp_32_done> */
1323 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1324 0xeaffffe8, /* b 8100 <sp_32_code> */
1326 /* 00008154 <sp_32_done>: */
1327 0xeafffffe /* b 8154 <sp_32_done> */
1330 static const uint32_t word_16_code
[] = {
1331 /* 00008158 <sp_16_code>: */
1332 0xe0d050b2, /* ldrh r5, [r0], #2 */
1333 0xe1c890b0, /* strh r9, [r8] */
1334 0xe1cab0b0, /* strh r11, [r10] */
1335 0xe1c830b0, /* strh r3, [r8] */
1336 0xe1c150b0, /* strh r5, [r1] */
1337 0xe1a00000, /* nop (mov r0,r0) */
1339 /* 00008168 <sp_16_busy>: */
1340 0xe1d160b0, /* ldrh r6, [r1] */
1341 0xe0257006, /* eor r7, r5, r6 */
1342 0xe0147007, /* ands r7, r4, r7 */
1343 0x0a000007, /* beq 8198 <sp_16_cont> */
1344 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1345 0x0afffff9, /* beq 8168 <sp_16_busy> */
1346 0xe1d160b0, /* ldrh r6, [r1] */
1347 0xe0257006, /* eor r7, r5, r6 */
1348 0xe0147007, /* ands r7, r4, r7 */
1349 0x0a000001, /* beq 8198 <sp_16_cont> */
1350 0xe3a05000, /* mov r5, #0 ; 0x0 */
1351 0x1a000004, /* bne 81ac <sp_16_done> */
1353 /* 00008198 <sp_16_cont>: */
1354 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1355 0x03a05080, /* moveq r5, #128 ; 0x80 */
1356 0x0a000001, /* beq 81ac <sp_16_done> */
1357 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1358 0xeaffffe8, /* b 8158 <sp_16_code> */
1360 /* 000081ac <sp_16_done>: */
1361 0xeafffffe /* b 81ac <sp_16_done> */
1364 static const uint32_t word_16_code_dq7only
[] = {
1366 0xe0d050b2, /* ldrh r5, [r0], #2 */
1367 0xe1c890b0, /* strh r9, [r8] */
1368 0xe1cab0b0, /* strh r11, [r10] */
1369 0xe1c830b0, /* strh r3, [r8] */
1370 0xe1c150b0, /* strh r5, [r1] */
1371 0xe1a00000, /* nop (mov r0,r0) */
1374 0xe1d160b0, /* ldrh r6, [r1] */
1375 0xe0257006, /* eor r7, r5, r6 */
1376 0xe2177080, /* ands r7, #0x80 */
1377 0x1afffffb, /* bne 8168 <sp_16_busy> */
1379 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1380 0x03a05080, /* moveq r5, #128 ; 0x80 */
1381 0x0a000001, /* beq 81ac <sp_16_done> */
1382 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1383 0xeafffff0, /* b 8158 <sp_16_code> */
1385 /* 000081ac <sp_16_done>: */
1386 0xeafffffe /* b 81ac <sp_16_done> */
1389 static const uint32_t word_8_code
[] = {
1390 /* 000081b0 <sp_16_code_end>: */
1391 0xe4d05001, /* ldrb r5, [r0], #1 */
1392 0xe5c89000, /* strb r9, [r8] */
1393 0xe5cab000, /* strb r11, [r10] */
1394 0xe5c83000, /* strb r3, [r8] */
1395 0xe5c15000, /* strb r5, [r1] */
1396 0xe1a00000, /* nop (mov r0,r0) */
1398 /* 000081c0 <sp_8_busy>: */
1399 0xe5d16000, /* ldrb r6, [r1] */
1400 0xe0257006, /* eor r7, r5, r6 */
1401 0xe0147007, /* ands r7, r4, r7 */
1402 0x0a000007, /* beq 81f0 <sp_8_cont> */
1403 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1404 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1405 0xe5d16000, /* ldrb r6, [r1] */
1406 0xe0257006, /* eor r7, r5, r6 */
1407 0xe0147007, /* ands r7, r4, r7 */
1408 0x0a000001, /* beq 81f0 <sp_8_cont> */
1409 0xe3a05000, /* mov r5, #0 ; 0x0 */
1410 0x1a000004, /* bne 8204 <sp_8_done> */
1412 /* 000081f0 <sp_8_cont>: */
1413 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1414 0x03a05080, /* moveq r5, #128 ; 0x80 */
1415 0x0a000001, /* beq 8204 <sp_8_done> */
1416 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1417 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1419 /* 00008204 <sp_8_done>: */
1420 0xeafffffe /* b 8204 <sp_8_done> */
1423 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
1424 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
1425 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
1427 int target_code_size
;
1428 const uint32_t *target_code_src
;
1430 switch (bank
->bus_width
)
1433 target_code_src
= word_8_code
;
1434 target_code_size
= sizeof(word_8_code
);
1437 /* Check for DQ5 support */
1438 if( cfi_info
->status_poll_mask
& (1 << 5) )
1440 target_code_src
= word_16_code
;
1441 target_code_size
= sizeof(word_16_code
);
1445 /* No DQ5 support. Use DQ7 DATA# polling only. */
1446 target_code_src
= word_16_code_dq7only
;
1447 target_code_size
= sizeof(word_16_code_dq7only
);
1451 target_code_src
= word_32_code
;
1452 target_code_size
= sizeof(word_32_code
);
1455 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1456 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1459 /* flash write code */
1460 if (!cfi_info
->write_algorithm
)
1462 uint8_t *target_code
;
1464 /* convert bus-width dependent algorithm code to correct endiannes */
1465 target_code
= malloc(target_code_size
);
1466 cfi_fix_code_endian(target
, target_code
, target_code_src
, target_code_size
/ 4);
1468 /* allocate working area */
1469 retval
= target_alloc_working_area(target
, target_code_size
,
1470 &cfi_info
->write_algorithm
);
1471 if (retval
!= ERROR_OK
)
1477 /* write algorithm code to working area */
1478 if ((retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
,
1479 target_code_size
, target_code
)) != ERROR_OK
)
1487 /* the following code still assumes target code is fixed 24*4 bytes */
1489 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
1492 if (buffer_size
<= 256)
1494 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1495 if (cfi_info
->write_algorithm
)
1496 target_free_working_area(target
, cfi_info
->write_algorithm
);
1498 LOG_WARNING("not enough working area available, can't do block memory writes");
1499 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1503 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1504 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1505 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1506 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1507 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
);
1508 init_reg_param(®_params
[5], "r5", 32, PARAM_IN
);
1509 init_reg_param(®_params
[6], "r8", 32, PARAM_OUT
);
1510 init_reg_param(®_params
[7], "r9", 32, PARAM_OUT
);
1511 init_reg_param(®_params
[8], "r10", 32, PARAM_OUT
);
1512 init_reg_param(®_params
[9], "r11", 32, PARAM_OUT
);
1516 uint32_t thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1518 retvaltemp
= target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1520 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1521 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1522 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1523 buf_set_u32(reg_params
[3].value
, 0, 32, cfi_command_val(bank
, 0xA0));
1524 buf_set_u32(reg_params
[4].value
, 0, 32, cfi_command_val(bank
, 0x80));
1525 buf_set_u32(reg_params
[6].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock1
));
1526 buf_set_u32(reg_params
[7].value
, 0, 32, 0xaaaaaaaa);
1527 buf_set_u32(reg_params
[8].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock2
));
1528 buf_set_u32(reg_params
[9].value
, 0, 32, 0x55555555);
1530 retval
= target_run_algorithm(target
, 0, NULL
, 10, reg_params
,
1531 cfi_info
->write_algorithm
->address
,
1532 cfi_info
->write_algorithm
->address
+ ((target_code_size
) - 4),
1533 10000, &armv4_5_info
);
1535 status
= buf_get_u32(reg_params
[5].value
, 0, 32);
1537 if ((retval
!= ERROR_OK
) || (retvaltemp
!= ERROR_OK
) || status
!= 0x80)
1539 LOG_DEBUG("status: 0x%" PRIx32
, status
);
1540 exit_code
= ERROR_FLASH_OPERATION_FAILED
;
1544 buffer
+= thisrun_count
;
1545 address
+= thisrun_count
;
1546 count
-= thisrun_count
;
1549 target_free_all_working_areas(target
);
1551 destroy_reg_param(®_params
[0]);
1552 destroy_reg_param(®_params
[1]);
1553 destroy_reg_param(®_params
[2]);
1554 destroy_reg_param(®_params
[3]);
1555 destroy_reg_param(®_params
[4]);
1556 destroy_reg_param(®_params
[5]);
1557 destroy_reg_param(®_params
[6]);
1558 destroy_reg_param(®_params
[7]);
1559 destroy_reg_param(®_params
[8]);
1560 destroy_reg_param(®_params
[9]);
1565 static int cfi_intel_write_word(struct flash_bank_s
*bank
, uint8_t *word
, uint32_t address
)
1568 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1569 target_t
*target
= bank
->target
;
1572 cfi_intel_clear_status_register(bank
);
1573 cfi_command(bank
, 0x40, command
);
1574 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1579 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, word
)) != ERROR_OK
)
1584 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != 0x80)
1586 cfi_command(bank
, 0xff, command
);
1587 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1592 LOG_ERROR("couldn't write word at base 0x%" PRIx32
", address %" PRIx32
, bank
->base
, address
);
1593 return ERROR_FLASH_OPERATION_FAILED
;
1599 static int cfi_intel_write_words(struct flash_bank_s
*bank
, uint8_t *word
, uint32_t wordcount
, uint32_t address
)
1602 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1603 target_t
*target
= bank
->target
;
1606 /* Calculate buffer size and boundary mask */
1607 uint32_t buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
1608 uint32_t buffermask
= buffersize
-1;
1609 uint32_t bufferwsize
;
1611 /* Check for valid range */
1612 if (address
& buffermask
)
1614 LOG_ERROR("Write address at base 0x%" PRIx32
", address %" PRIx32
" not aligned to 2^%d boundary",
1615 bank
->base
, address
, cfi_info
->max_buf_write_size
);
1616 return ERROR_FLASH_OPERATION_FAILED
;
1618 switch (bank
->chip_width
)
1620 case 4 : bufferwsize
= buffersize
/ 4; break;
1621 case 2 : bufferwsize
= buffersize
/ 2; break;
1622 case 1 : bufferwsize
= buffersize
; break;
1624 LOG_ERROR("Unsupported chip width %d", bank
->chip_width
);
1625 return ERROR_FLASH_OPERATION_FAILED
;
1628 bufferwsize
/=(bank
->bus_width
/ bank
->chip_width
);
1631 /* Check for valid size */
1632 if (wordcount
> bufferwsize
)
1634 LOG_ERROR("Number of data words %" PRId32
" exceeds available buffersize %" PRId32
, wordcount
, buffersize
);
1635 return ERROR_FLASH_OPERATION_FAILED
;
1638 /* Write to flash buffer */
1639 cfi_intel_clear_status_register(bank
);
1641 /* Initiate buffer operation _*/
1642 cfi_command(bank
, 0xE8, command
);
1643 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1647 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
)) != 0x80)
1649 cfi_command(bank
, 0xff, command
);
1650 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1655 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32
", address %" PRIx32
, bank
->base
, address
);
1656 return ERROR_FLASH_OPERATION_FAILED
;
1659 /* Write buffer wordcount-1 and data words */
1660 cfi_command(bank
, bufferwsize
-1, command
);
1661 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1666 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, bufferwsize
, word
)) != ERROR_OK
)
1671 /* Commit write operation */
1672 cfi_command(bank
, 0xd0, command
);
1673 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1677 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
)) != 0x80)
1679 cfi_command(bank
, 0xff, command
);
1680 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1685 LOG_ERROR("Buffer write at base 0x%" PRIx32
", address %" PRIx32
" failed.", bank
->base
, address
);
1686 return ERROR_FLASH_OPERATION_FAILED
;
1692 static int cfi_spansion_write_word(struct flash_bank_s
*bank
, uint8_t *word
, uint32_t address
)
1695 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1696 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1697 target_t
*target
= bank
->target
;
1700 cfi_command(bank
, 0xaa, command
);
1701 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1706 cfi_command(bank
, 0x55, command
);
1707 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1712 cfi_command(bank
, 0xa0, command
);
1713 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1718 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, word
)) != ERROR_OK
)
1723 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1725 cfi_command(bank
, 0xf0, command
);
1726 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1731 LOG_ERROR("couldn't write word at base 0x%" PRIx32
", address %" PRIx32
, bank
->base
, address
);
1732 return ERROR_FLASH_OPERATION_FAILED
;
1738 static int cfi_spansion_write_words(struct flash_bank_s
*bank
, uint8_t *word
, uint32_t wordcount
, uint32_t address
)
1741 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1742 target_t
*target
= bank
->target
;
1744 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1746 /* Calculate buffer size and boundary mask */
1747 uint32_t buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
1748 uint32_t buffermask
= buffersize
-1;
1749 uint32_t bufferwsize
;
1751 /* Check for valid range */
1752 if (address
& buffermask
)
1754 LOG_ERROR("Write address at base 0x%" PRIx32
", address %" PRIx32
" not aligned to 2^%d boundary", bank
->base
, address
, cfi_info
->max_buf_write_size
);
1755 return ERROR_FLASH_OPERATION_FAILED
;
1757 switch (bank
->chip_width
)
1759 case 4 : bufferwsize
= buffersize
/ 4; break;
1760 case 2 : bufferwsize
= buffersize
/ 2; break;
1761 case 1 : bufferwsize
= buffersize
; break;
1763 LOG_ERROR("Unsupported chip width %d", bank
->chip_width
);
1764 return ERROR_FLASH_OPERATION_FAILED
;
1767 bufferwsize
/=(bank
->bus_width
/ bank
->chip_width
);
1769 /* Check for valid size */
1770 if (wordcount
> bufferwsize
)
1772 LOG_ERROR("Number of data words %" PRId32
" exceeds available buffersize %" PRId32
, wordcount
, buffersize
);
1773 return ERROR_FLASH_OPERATION_FAILED
;
1777 cfi_command(bank
, 0xaa, command
);
1778 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1783 cfi_command(bank
, 0x55, command
);
1784 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1789 // Buffer load command
1790 cfi_command(bank
, 0x25, command
);
1791 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1796 /* Write buffer wordcount-1 and data words */
1797 cfi_command(bank
, bufferwsize
-1, command
);
1798 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1803 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, bufferwsize
, word
)) != ERROR_OK
)
1808 /* Commit write operation */
1809 cfi_command(bank
, 0x29, command
);
1810 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1815 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1817 cfi_command(bank
, 0xf0, command
);
1818 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1823 LOG_ERROR("couldn't write block at base 0x%" PRIx32
", address %" PRIx32
", size %" PRIx32
, bank
->base
, address
, bufferwsize
);
1824 return ERROR_FLASH_OPERATION_FAILED
;
1830 static int cfi_write_word(struct flash_bank_s
*bank
, uint8_t *word
, uint32_t address
)
1832 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1834 switch (cfi_info
->pri_id
)
1838 return cfi_intel_write_word(bank
, word
, address
);
1841 return cfi_spansion_write_word(bank
, word
, address
);
1844 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1848 return ERROR_FLASH_OPERATION_FAILED
;
1851 static int cfi_write_words(struct flash_bank_s
*bank
, uint8_t *word
, uint32_t wordcount
, uint32_t address
)
1853 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1855 switch (cfi_info
->pri_id
)
1859 return cfi_intel_write_words(bank
, word
, wordcount
, address
);
1862 return cfi_spansion_write_words(bank
, word
, wordcount
, address
);
1865 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1869 return ERROR_FLASH_OPERATION_FAILED
;
1872 int cfi_write(struct flash_bank_s
*bank
, uint8_t *buffer
, uint32_t offset
, uint32_t count
)
1874 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1875 target_t
*target
= bank
->target
;
1876 uint32_t address
= bank
->base
+ offset
; /* address of first byte to be programmed */
1877 uint32_t write_p
, copy_p
;
1878 int align
; /* number of unaligned bytes */
1879 int blk_count
; /* number of bus_width bytes for block copy */
1880 uint8_t current_word
[CFI_MAX_BUS_WIDTH
* 4]; /* word (bus_width size) currently being programmed */
1884 if (bank
->target
->state
!= TARGET_HALTED
)
1886 LOG_ERROR("Target not halted");
1887 return ERROR_TARGET_NOT_HALTED
;
1890 if (offset
+ count
> bank
->size
)
1891 return ERROR_FLASH_DST_OUT_OF_BANK
;
1893 if (cfi_info
->qry
[0] != 'Q')
1894 return ERROR_FLASH_BANK_NOT_PROBED
;
1896 /* start at the first byte of the first word (bus_width size) */
1897 write_p
= address
& ~(bank
->bus_width
- 1);
1898 if ((align
= address
- write_p
) != 0)
1900 LOG_INFO("Fixup %d unaligned head bytes", align
);
1902 for (i
= 0; i
< bank
->bus_width
; i
++)
1903 current_word
[i
] = 0;
1906 /* copy bytes before the first write address */
1907 for (i
= 0; i
< align
; ++i
, ++copy_p
)
1910 if ((retval
= target_read_memory(target
, copy_p
, 1, 1, &byte
)) != ERROR_OK
)
1914 cfi_add_byte(bank
, current_word
, byte
);
1917 /* add bytes from the buffer */
1918 for (; (i
< bank
->bus_width
) && (count
> 0); i
++)
1920 cfi_add_byte(bank
, current_word
, *buffer
++);
1925 /* if the buffer is already finished, copy bytes after the last write address */
1926 for (; (count
== 0) && (i
< bank
->bus_width
); ++i
, ++copy_p
)
1929 if ((retval
= target_read_memory(target
, copy_p
, 1, 1, &byte
)) != ERROR_OK
)
1933 cfi_add_byte(bank
, current_word
, byte
);
1936 retval
= cfi_write_word(bank
, current_word
, write_p
);
1937 if (retval
!= ERROR_OK
)
1942 /* handle blocks of bus_size aligned bytes */
1943 blk_count
= count
& ~(bank
->bus_width
- 1); /* round down, leave tail bytes */
1944 switch (cfi_info
->pri_id
)
1946 /* try block writes (fails without working area) */
1949 retval
= cfi_intel_write_block(bank
, buffer
, write_p
, blk_count
);
1952 retval
= cfi_spansion_write_block(bank
, buffer
, write_p
, blk_count
);
1955 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1956 retval
= ERROR_FLASH_OPERATION_FAILED
;
1959 if (retval
== ERROR_OK
)
1961 /* Increment pointers and decrease count on succesful block write */
1962 buffer
+= blk_count
;
1963 write_p
+= blk_count
;
1968 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
1970 //adjust buffersize for chip width
1971 uint32_t buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
1972 uint32_t buffermask
= buffersize
-1;
1973 uint32_t bufferwsize
;
1975 switch (bank
->chip_width
)
1977 case 4 : bufferwsize
= buffersize
/ 4; break;
1978 case 2 : bufferwsize
= buffersize
/ 2; break;
1979 case 1 : bufferwsize
= buffersize
; break;
1981 LOG_ERROR("Unsupported chip width %d", bank
->chip_width
);
1982 return ERROR_FLASH_OPERATION_FAILED
;
1985 bufferwsize
/=(bank
->bus_width
/ bank
->chip_width
);
1987 /* fall back to memory writes */
1988 while (count
>= (uint32_t)bank
->bus_width
)
1991 if ((write_p
& 0xff) == 0)
1993 LOG_INFO("Programming at %08" PRIx32
", count %08" PRIx32
" bytes remaining", write_p
, count
);
1996 if ((bufferwsize
> 0) && (count
>= buffersize
) && !(write_p
& buffermask
))
1998 retval
= cfi_write_words(bank
, buffer
, bufferwsize
, write_p
);
1999 if (retval
== ERROR_OK
)
2001 buffer
+= buffersize
;
2002 write_p
+= buffersize
;
2003 count
-= buffersize
;
2007 /* try the slow way? */
2010 for (i
= 0; i
< bank
->bus_width
; i
++)
2011 current_word
[i
] = 0;
2013 for (i
= 0; i
< bank
->bus_width
; i
++)
2015 cfi_add_byte(bank
, current_word
, *buffer
++);
2018 retval
= cfi_write_word(bank
, current_word
, write_p
);
2019 if (retval
!= ERROR_OK
)
2022 write_p
+= bank
->bus_width
;
2023 count
-= bank
->bus_width
;
2031 /* return to read array mode, so we can read from flash again for padding */
2032 cfi_command(bank
, 0xf0, current_word
);
2033 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2037 cfi_command(bank
, 0xff, current_word
);
2038 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2043 /* handle unaligned tail bytes */
2046 LOG_INFO("Fixup %" PRId32
" unaligned tail bytes", count
);
2049 for (i
= 0; i
< bank
->bus_width
; i
++)
2050 current_word
[i
] = 0;
2052 for (i
= 0; (i
< bank
->bus_width
) && (count
> 0); ++i
, ++copy_p
)
2054 cfi_add_byte(bank
, current_word
, *buffer
++);
2057 for (; i
< bank
->bus_width
; ++i
, ++copy_p
)
2060 if ((retval
= target_read_memory(target
, copy_p
, 1, 1, &byte
)) != ERROR_OK
)
2064 cfi_add_byte(bank
, current_word
, byte
);
2066 retval
= cfi_write_word(bank
, current_word
, write_p
);
2067 if (retval
!= ERROR_OK
)
2071 /* return to read array mode */
2072 cfi_command(bank
, 0xf0, current_word
);
2073 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2077 cfi_command(bank
, 0xff, current_word
);
2078 return target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
2081 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t
*bank
, void *param
)
2084 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2085 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2087 pri_ext
->_reversed_geometry
= 1;
2090 static void cfi_fixup_0002_erase_regions(flash_bank_t
*bank
, void *param
)
2093 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2094 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2097 if ((pri_ext
->_reversed_geometry
) || (pri_ext
->TopBottom
== 3))
2099 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2101 for (i
= 0; i
< cfi_info
->num_erase_regions
/ 2; i
++)
2103 int j
= (cfi_info
->num_erase_regions
- 1) - i
;
2106 swap
= cfi_info
->erase_region_info
[i
];
2107 cfi_info
->erase_region_info
[i
] = cfi_info
->erase_region_info
[j
];
2108 cfi_info
->erase_region_info
[j
] = swap
;
2113 static void cfi_fixup_0002_unlock_addresses(flash_bank_t
*bank
, void *param
)
2115 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2116 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2117 cfi_unlock_addresses_t
*unlock_addresses
= param
;
2119 pri_ext
->_unlock1
= unlock_addresses
->unlock1
;
2120 pri_ext
->_unlock2
= unlock_addresses
->unlock2
;
2124 static int cfi_query_string(struct flash_bank_s
*bank
, int address
)
2126 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2127 target_t
*target
= bank
->target
;
2131 cfi_command(bank
, 0x98, command
);
2132 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, address
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2137 cfi_info
->qry
[0] = cfi_query_u8(bank
, 0, 0x10);
2138 cfi_info
->qry
[1] = cfi_query_u8(bank
, 0, 0x11);
2139 cfi_info
->qry
[2] = cfi_query_u8(bank
, 0, 0x12);
2141 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2]);
2143 if ((cfi_info
->qry
[0] != 'Q') || (cfi_info
->qry
[1] != 'R') || (cfi_info
->qry
[2] != 'Y'))
2145 cfi_command(bank
, 0xf0, command
);
2146 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2150 cfi_command(bank
, 0xff, command
);
2151 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2155 LOG_ERROR("Could not probe bank: no QRY");
2156 return ERROR_FLASH_BANK_INVALID
;
2162 static int cfi_probe(struct flash_bank_s
*bank
)
2164 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2165 target_t
*target
= bank
->target
;
2167 int num_sectors
= 0;
2170 uint32_t unlock1
= 0x555;
2171 uint32_t unlock2
= 0x2aa;
2174 if (bank
->target
->state
!= TARGET_HALTED
)
2176 LOG_ERROR("Target not halted");
2177 return ERROR_TARGET_NOT_HALTED
;
2180 cfi_info
->probed
= 0;
2182 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2183 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2185 if (cfi_info
->jedec_probe
)
2191 /* switch to read identifier codes mode ("AUTOSELECT") */
2192 cfi_command(bank
, 0xaa, command
);
2193 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2197 cfi_command(bank
, 0x55, command
);
2198 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2202 cfi_command(bank
, 0x90, command
);
2203 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2208 if (bank
->chip_width
== 1)
2210 uint8_t manufacturer
, device_id
;
2211 if ((retval
= target_read_u8(target
, flash_address(bank
, 0, 0x00), &manufacturer
)) != ERROR_OK
)
2215 if ((retval
= target_read_u8(target
, flash_address(bank
, 0, 0x01), &device_id
)) != ERROR_OK
)
2219 cfi_info
->manufacturer
= manufacturer
;
2220 cfi_info
->device_id
= device_id
;
2222 else if (bank
->chip_width
== 2)
2224 if ((retval
= target_read_u16(target
, flash_address(bank
, 0, 0x00), &cfi_info
->manufacturer
)) != ERROR_OK
)
2228 if ((retval
= target_read_u16(target
, flash_address(bank
, 0, 0x01), &cfi_info
->device_id
)) != ERROR_OK
)
2234 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info
->manufacturer
, cfi_info
->device_id
);
2235 /* switch back to read array mode */
2236 cfi_command(bank
, 0xf0, command
);
2237 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x00), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2241 cfi_command(bank
, 0xff, command
);
2242 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x00), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2247 /* check device/manufacturer ID for known non-CFI flashes. */
2248 cfi_fixup_non_cfi(bank
);
2250 /* query only if this is a CFI compatible flash,
2251 * otherwise the relevant info has already been filled in
2253 if (cfi_info
->not_cfi
== 0)
2257 /* enter CFI query mode
2258 * according to JEDEC Standard No. 68.01,
2259 * a single bus sequence with address = 0x55, data = 0x98 should put
2260 * the device into CFI query mode.
2262 * SST flashes clearly violate this, and we will consider them incompatbile for now
2265 retval
= cfi_query_string(bank
, 0x55);
2266 if (retval
!= ERROR_OK
)
2269 * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2270 * be harmless enough:
2272 * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2274 LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2275 retval
= cfi_query_string(bank
, 0x555);
2277 if (retval
!= ERROR_OK
)
2280 cfi_info
->pri_id
= cfi_query_u16(bank
, 0, 0x13);
2281 cfi_info
->pri_addr
= cfi_query_u16(bank
, 0, 0x15);
2282 cfi_info
->alt_id
= cfi_query_u16(bank
, 0, 0x17);
2283 cfi_info
->alt_addr
= cfi_query_u16(bank
, 0, 0x19);
2285 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2287 cfi_info
->vcc_min
= cfi_query_u8(bank
, 0, 0x1b);
2288 cfi_info
->vcc_max
= cfi_query_u8(bank
, 0, 0x1c);
2289 cfi_info
->vpp_min
= cfi_query_u8(bank
, 0, 0x1d);
2290 cfi_info
->vpp_max
= cfi_query_u8(bank
, 0, 0x1e);
2291 cfi_info
->word_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x1f);
2292 cfi_info
->buf_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x20);
2293 cfi_info
->block_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x21);
2294 cfi_info
->chip_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x22);
2295 cfi_info
->word_write_timeout_max
= cfi_query_u8(bank
, 0, 0x23);
2296 cfi_info
->buf_write_timeout_max
= cfi_query_u8(bank
, 0, 0x24);
2297 cfi_info
->block_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x25);
2298 cfi_info
->chip_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x26);
2300 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
2301 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2302 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2303 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2304 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2305 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info
->word_write_timeout_typ
, 1 << cfi_info
->buf_write_timeout_typ
,
2306 1 << cfi_info
->block_erase_timeout_typ
, 1 << cfi_info
->chip_erase_timeout_typ
);
2307 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2308 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2309 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2310 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2312 cfi_info
->dev_size
= 1 << cfi_query_u8(bank
, 0, 0x27);
2313 cfi_info
->interface_desc
= cfi_query_u16(bank
, 0, 0x28);
2314 cfi_info
->max_buf_write_size
= cfi_query_u16(bank
, 0, 0x2a);
2315 cfi_info
->num_erase_regions
= cfi_query_u8(bank
, 0, 0x2c);
2317 LOG_DEBUG("size: 0x%" PRIx32
", interface desc: %i, max buffer write size: %x", cfi_info
->dev_size
, cfi_info
->interface_desc
, (1 << cfi_info
->max_buf_write_size
));
2319 if (cfi_info
->num_erase_regions
)
2321 cfi_info
->erase_region_info
= malloc(4 * cfi_info
->num_erase_regions
);
2322 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2324 cfi_info
->erase_region_info
[i
] = cfi_query_u32(bank
, 0, 0x2d + (4 * i
));
2325 LOG_DEBUG("erase region[%i]: %" PRIu32
" blocks of size 0x%" PRIx32
"",
2327 (cfi_info
->erase_region_info
[i
] & 0xffff) + 1,
2328 (cfi_info
->erase_region_info
[i
] >> 16) * 256);
2333 cfi_info
->erase_region_info
= NULL
;
2336 /* We need to read the primary algorithm extended query table before calculating
2337 * the sector layout to be able to apply fixups
2339 switch (cfi_info
->pri_id
)
2341 /* Intel command set (standard and extended) */
2344 cfi_read_intel_pri_ext(bank
);
2346 /* AMD/Spansion, Atmel, ... command set */
2348 cfi_info
->status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
; /* default for all CFI flashs */
2349 cfi_read_0002_pri_ext(bank
);
2352 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2356 /* return to read array mode
2357 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2359 cfi_command(bank
, 0xf0, command
);
2360 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2364 cfi_command(bank
, 0xff, command
);
2365 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2369 } /* end CFI case */
2371 /* apply fixups depending on the primary command set */
2372 switch (cfi_info
->pri_id
)
2374 /* Intel command set (standard and extended) */
2377 cfi_fixup(bank
, cfi_0001_fixups
);
2379 /* AMD/Spansion, Atmel, ... command set */
2381 cfi_fixup(bank
, cfi_0002_fixups
);
2384 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2388 if ((cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
) != bank
->size
)
2390 LOG_WARNING("configuration specifies 0x%" PRIx32
" size, but a 0x%" PRIx32
" size flash was found", bank
->size
, cfi_info
->dev_size
);
2393 if (cfi_info
->num_erase_regions
== 0)
2395 /* a device might have only one erase block, spanning the whole device */
2396 bank
->num_sectors
= 1;
2397 bank
->sectors
= malloc(sizeof(flash_sector_t
));
2399 bank
->sectors
[sector
].offset
= 0x0;
2400 bank
->sectors
[sector
].size
= bank
->size
;
2401 bank
->sectors
[sector
].is_erased
= -1;
2402 bank
->sectors
[sector
].is_protected
= -1;
2406 uint32_t offset
= 0;
2408 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2410 num_sectors
+= (cfi_info
->erase_region_info
[i
] & 0xffff) + 1;
2413 bank
->num_sectors
= num_sectors
;
2414 bank
->sectors
= malloc(sizeof(flash_sector_t
) * num_sectors
);
2416 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2419 for (j
= 0; j
< (cfi_info
->erase_region_info
[i
] & 0xffff) + 1; j
++)
2421 bank
->sectors
[sector
].offset
= offset
;
2422 bank
->sectors
[sector
].size
= ((cfi_info
->erase_region_info
[i
] >> 16) * 256) * bank
->bus_width
/ bank
->chip_width
;
2423 offset
+= bank
->sectors
[sector
].size
;
2424 bank
->sectors
[sector
].is_erased
= -1;
2425 bank
->sectors
[sector
].is_protected
= -1;
2429 if (offset
!= (cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
))
2431 LOG_WARNING("CFI size is 0x%" PRIx32
", but total sector size is 0x%" PRIx32
"", \
2432 (cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
), offset
);
2436 cfi_info
->probed
= 1;
2441 static int cfi_auto_probe(struct flash_bank_s
*bank
)
2443 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2444 if (cfi_info
->probed
)
2446 return cfi_probe(bank
);
2450 static int cfi_intel_protect_check(struct flash_bank_s
*bank
)
2453 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2454 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2455 target_t
*target
= bank
->target
;
2456 uint8_t command
[CFI_MAX_BUS_WIDTH
];
2459 /* check if block lock bits are supported on this device */
2460 if (!(pri_ext
->blk_status_reg_mask
& 0x1))
2461 return ERROR_FLASH_OPERATION_FAILED
;
2463 cfi_command(bank
, 0x90, command
);
2464 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2469 for (i
= 0; i
< bank
->num_sectors
; i
++)
2471 uint8_t block_status
= cfi_get_u8(bank
, i
, 0x2);
2473 if (block_status
& 1)
2474 bank
->sectors
[i
].is_protected
= 1;
2476 bank
->sectors
[i
].is_protected
= 0;
2479 cfi_command(bank
, 0xff, command
);
2480 return target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2483 static int cfi_spansion_protect_check(struct flash_bank_s
*bank
)
2486 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2487 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2488 target_t
*target
= bank
->target
;
2492 cfi_command(bank
, 0xaa, command
);
2493 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2498 cfi_command(bank
, 0x55, command
);
2499 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2504 cfi_command(bank
, 0x90, command
);
2505 if ((retval
= target_write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2510 for (i
= 0; i
< bank
->num_sectors
; i
++)
2512 uint8_t block_status
= cfi_get_u8(bank
, i
, 0x2);
2514 if (block_status
& 1)
2515 bank
->sectors
[i
].is_protected
= 1;
2517 bank
->sectors
[i
].is_protected
= 0;
2520 cfi_command(bank
, 0xf0, command
);
2521 return target_write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2524 static int cfi_protect_check(struct flash_bank_s
*bank
)
2526 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2528 if (bank
->target
->state
!= TARGET_HALTED
)
2530 LOG_ERROR("Target not halted");
2531 return ERROR_TARGET_NOT_HALTED
;
2534 if (cfi_info
->qry
[0] != 'Q')
2535 return ERROR_FLASH_BANK_NOT_PROBED
;
2537 switch (cfi_info
->pri_id
)
2541 return cfi_intel_protect_check(bank
);
2544 return cfi_spansion_protect_check(bank
);
2547 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2554 static int cfi_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
2557 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2559 if (cfi_info
->qry
[0] == (char)-1)
2561 printed
= snprintf(buf
, buf_size
, "\ncfi flash bank not probed yet\n");
2565 if (cfi_info
->not_cfi
== 0)
2566 printed
= snprintf(buf
, buf_size
, "\ncfi information:\n");
2568 printed
= snprintf(buf
, buf_size
, "\nnon-cfi flash:\n");
2570 buf_size
-= printed
;
2572 printed
= snprintf(buf
, buf_size
, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2573 cfi_info
->manufacturer
, cfi_info
->device_id
);
2575 buf_size
-= printed
;
2577 if (cfi_info
->not_cfi
== 0)
2579 printed
= snprintf(buf
, buf_size
, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2581 buf_size
-= printed
;
2583 printed
= snprintf(buf
, buf_size
, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2584 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2585 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2586 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2587 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2589 buf_size
-= printed
;
2591 printed
= snprintf(buf
, buf_size
, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2592 1 << cfi_info
->word_write_timeout_typ
,
2593 1 << cfi_info
->buf_write_timeout_typ
,
2594 1 << cfi_info
->block_erase_timeout_typ
,
2595 1 << cfi_info
->chip_erase_timeout_typ
);
2597 buf_size
-= printed
;
2599 printed
= snprintf(buf
, buf_size
, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2600 (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2601 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2602 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2603 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2605 buf_size
-= printed
;
2607 printed
= snprintf(buf
, buf_size
, "size: 0x%" PRIx32
", interface desc: %i, max buffer write size: %x\n",
2609 cfi_info
->interface_desc
,
2610 1 << cfi_info
->max_buf_write_size
);
2612 buf_size
-= printed
;
2614 switch (cfi_info
->pri_id
)
2618 cfi_intel_info(bank
, buf
, buf_size
);
2621 cfi_spansion_info(bank
, buf
, buf_size
);
2624 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2632 flash_driver_t cfi_flash
= {
2634 .register_commands
= &cfi_register_commands
,
2635 .flash_bank_command
= &cfi_flash_bank_command
,
2636 .erase
= &cfi_erase
,
2637 .protect
= &cfi_protect
,
2638 .write
= &cfi_write
,
2639 .probe
= &cfi_probe
,
2640 .auto_probe
= &cfi_auto_probe
,
2641 .erase_check
= &default_flash_blank_check
,
2642 .protect_check
= &cfi_protect_check
,
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