1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
32 #include "algorithm.h"
33 #include "binarybuffer.h"
40 int cfi_register_commands(struct command_context_s
*cmd_ctx
);
41 int cfi_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
);
42 int cfi_erase(struct flash_bank_s
*bank
, int first
, int last
);
43 int cfi_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
);
44 int cfi_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
);
45 int cfi_probe(struct flash_bank_s
*bank
);
46 int cfi_erase_check(struct flash_bank_s
*bank
);
47 int cfi_protect_check(struct flash_bank_s
*bank
);
48 int cfi_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
);
50 int cfi_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
52 #define CFI_MAX_BUS_WIDTH 4
53 #define CFI_MAX_CHIP_WIDTH 4
55 flash_driver_t cfi_flash
=
58 .register_commands
= cfi_register_commands
,
59 .flash_bank_command
= cfi_flash_bank_command
,
61 .protect
= cfi_protect
,
64 .erase_check
= cfi_erase_check
,
65 .protect_check
= cfi_protect_check
,
69 cfi_unlock_addresses_t cfi_unlock_addresses
[] =
71 [CFI_UNLOCK_555_2AA
] = { .unlock1
= 0x555, .unlock2
= 0x2aa },
72 [CFI_UNLOCK_5555_2AAA
] = { .unlock1
= 0x5555, .unlock2
= 0x2aaa },
75 /* CFI fixups foward declarations */
76 void cfi_fixup_non_cfi(flash_bank_t
*flash
, void *param
);
77 void cfi_fixup_0002_erase_regions(flash_bank_t
*flash
, void *param
);
78 void cfi_fixup_0002_unlock_addresses(flash_bank_t
*flash
, void *param
);
79 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t
*flash
, void *param
);
81 /* fixup after identifying JEDEC manufactuer and ID */
82 cfi_fixup_t cfi_jedec_fixups
[] = {
83 {CFI_MFR_SST
, 0x00D4, cfi_fixup_non_cfi
, NULL
},
84 {CFI_MFR_SST
, 0x00D5, cfi_fixup_non_cfi
, NULL
},
85 {CFI_MFR_SST
, 0x00D6, cfi_fixup_non_cfi
, NULL
},
86 {CFI_MFR_SST
, 0x00D7, cfi_fixup_non_cfi
, NULL
},
87 {CFI_MFR_ST
, 0x00D5, cfi_fixup_non_cfi
, NULL
},
88 {CFI_MFR_ST
, 0x00D6, cfi_fixup_non_cfi
, NULL
},
89 {CFI_MFR_AMD
, 0x2223, cfi_fixup_non_cfi
, NULL
},
90 {CFI_MFR_AMD
, 0x22ab, cfi_fixup_non_cfi
, NULL
},
94 /* fixup after reading cmdset 0002 primary query table */
95 cfi_fixup_t cfi_0002_fixups
[] = {
96 {CFI_MFR_SST
, 0x00D4, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
97 {CFI_MFR_SST
, 0x00D5, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
98 {CFI_MFR_SST
, 0x00D6, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
99 {CFI_MFR_SST
, 0x00D7, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
100 {CFI_MFR_ATMEL
, 0x00C8, cfi_fixup_atmel_reversed_erase_regions
, NULL
},
101 {CFI_MFR_ANY
, CFI_ID_ANY
, cfi_fixup_0002_erase_regions
, NULL
},
105 /* fixup after reading cmdset 0001 primary query table */
106 cfi_fixup_t cfi_0001_fixups
[] = {
110 void cfi_fixup(flash_bank_t
*bank
, cfi_fixup_t
*fixups
)
112 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
115 for (f
= fixups
; f
->fixup
; f
++)
117 if (((f
->mfr
== CFI_MFR_ANY
) || (f
->mfr
== cfi_info
->manufacturer
)) &&
118 ((f
->id
== CFI_ID_ANY
) || (f
->id
== cfi_info
->device_id
)))
120 f
->fixup(bank
, f
->param
);
125 inline u32
flash_address(flash_bank_t
*bank
, int sector
, u32 offset
)
127 /* while the sector list isn't built, only accesses to sector 0 work */
129 return bank
->base
+ offset
* bank
->bus_width
;
134 ERROR("BUG: sector list not yet built");
137 return bank
->base
+ bank
->sectors
[sector
].offset
+ offset
* bank
->bus_width
;
142 void cfi_command(flash_bank_t
*bank
, u8 cmd
, u8
*cmd_buf
)
146 /* clear whole buffer, to ensure bits that exceed the bus_width
149 for (i
= 0; i
< CFI_MAX_BUS_WIDTH
; i
++)
152 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
154 for (i
= bank
->bus_width
; i
> 0; i
--)
156 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
161 for (i
= 1; i
<= bank
->bus_width
; i
++)
163 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
168 /* read unsigned 8-bit value from the bank
169 * flash banks are expected to be made of similar chips
170 * the query result should be the same for all
172 u8
cfi_query_u8(flash_bank_t
*bank
, int sector
, u32 offset
)
174 target_t
*target
= bank
->target
;
175 u8 data
[CFI_MAX_BUS_WIDTH
];
177 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
179 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
182 return data
[bank
->bus_width
- 1];
185 /* read unsigned 8-bit value from the bank
186 * in case of a bank made of multiple chips,
187 * the individual values are ORed
189 u8
cfi_get_u8(flash_bank_t
*bank
, int sector
, u32 offset
)
191 target_t
*target
= bank
->target
;
192 u8 data
[CFI_MAX_BUS_WIDTH
];
195 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
197 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
199 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
207 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
208 value
|= data
[bank
->bus_width
- 1 - i
];
214 u16
cfi_query_u16(flash_bank_t
*bank
, int sector
, u32 offset
)
216 target_t
*target
= bank
->target
;
217 u8 data
[CFI_MAX_BUS_WIDTH
* 2];
219 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 2, data
);
221 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
222 return data
[0] | data
[bank
->bus_width
] << 8;
224 return data
[bank
->bus_width
- 1] | data
[(2 * bank
->bus_width
) - 1] << 8;
227 u32
cfi_query_u32(flash_bank_t
*bank
, int sector
, u32 offset
)
229 target_t
*target
= bank
->target
;
230 u8 data
[CFI_MAX_BUS_WIDTH
* 4];
232 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 4, data
);
234 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
235 return data
[0] | data
[bank
->bus_width
] << 8 | data
[bank
->bus_width
* 2] << 16 | data
[bank
->bus_width
* 3] << 24;
237 return data
[bank
->bus_width
- 1] | data
[(2* bank
->bus_width
) - 1] << 8 |
238 data
[(3 * bank
->bus_width
) - 1] << 16 | data
[(4 * bank
->bus_width
) - 1] << 24;
241 void cfi_intel_clear_status_register(flash_bank_t
*bank
)
243 target_t
*target
= bank
->target
;
246 if (target
->state
!= TARGET_HALTED
)
248 ERROR("BUG: attempted to clear status register while target wasn't halted");
252 cfi_command(bank
, 0x50, command
);
253 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
256 u8
cfi_intel_wait_status_busy(flash_bank_t
*bank
, int timeout
)
260 while ((!((status
= cfi_get_u8(bank
, 0, 0x0)) & 0x80)) && (timeout
-- > 0))
262 DEBUG("status: 0x%x", status
);
266 /* mask out bit 0 (reserved) */
267 status
= status
& 0xfe;
269 DEBUG("status: 0x%x", status
);
271 if ((status
& 0x80) != 0x80)
273 ERROR("timeout while waiting for WSM to become ready");
275 else if (status
!= 0x80)
277 ERROR("status register: 0x%x", status
);
279 ERROR("Block Lock-Bit Detected, Operation Abort");
281 ERROR("Program suspended");
283 ERROR("Low Programming Voltage Detected, Operation Aborted");
285 ERROR("Program Error / Error in Setting Lock-Bit");
287 ERROR("Error in Block Erasure or Clear Lock-Bits");
289 ERROR("Block Erase Suspended");
291 cfi_intel_clear_status_register(bank
);
297 int cfi_spansion_wait_status_busy(flash_bank_t
*bank
, int timeout
)
299 u8 status
, oldstatus
;
301 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
304 status
= cfi_get_u8(bank
, 0, 0x0);
305 if ((status
^ oldstatus
) & 0x40) {
307 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
308 status
= cfi_get_u8(bank
, 0, 0x0);
309 if ((status
^ oldstatus
) & 0x40) {
310 ERROR("dq5 timeout, status: 0x%x", status
);
311 return(ERROR_FLASH_OPERATION_FAILED
);
313 DEBUG("status: 0x%x", status
);
318 DEBUG("status: 0x%x", status
);
324 } while (timeout
-- > 0);
326 ERROR("timeout, status: 0x%x", status
);
328 return(ERROR_FLASH_BUSY
);
331 int cfi_read_intel_pri_ext(flash_bank_t
*bank
)
333 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
334 cfi_intel_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_intel_pri_ext_t
));
335 target_t
*target
= bank
->target
;
338 cfi_info
->pri_ext
= pri_ext
;
340 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
341 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
342 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
344 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
346 cfi_command(bank
, 0xf0, command
);
347 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
348 cfi_command(bank
, 0xff, command
);
349 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
350 return ERROR_FLASH_BANK_INVALID
;
353 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
354 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
356 DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
358 pri_ext
->feature_support
= cfi_query_u32(bank
, 0, cfi_info
->pri_addr
+ 5);
359 pri_ext
->suspend_cmd_support
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
360 pri_ext
->blk_status_reg_mask
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xa);
362 DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext
->feature_support
, pri_ext
->suspend_cmd_support
, pri_ext
->blk_status_reg_mask
);
364 pri_ext
->vcc_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xc);
365 pri_ext
->vpp_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xd);
367 DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
368 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
369 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
371 pri_ext
->num_protection_fields
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xe);
372 if (pri_ext
->num_protection_fields
!= 1)
374 WARNING("expected one protection register field, but found %i", pri_ext
->num_protection_fields
);
377 pri_ext
->prot_reg_addr
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xf);
378 pri_ext
->fact_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x11);
379 pri_ext
->user_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x12);
381 DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
386 int cfi_read_spansion_pri_ext(flash_bank_t
*bank
)
388 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
389 cfi_spansion_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_spansion_pri_ext_t
));
390 target_t
*target
= bank
->target
;
393 cfi_info
->pri_ext
= pri_ext
;
395 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
396 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
397 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
399 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
401 cfi_command(bank
, 0xf0, command
);
402 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
403 return ERROR_FLASH_BANK_INVALID
;
406 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
407 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
409 DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
411 pri_ext
->SiliconRevision
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
412 pri_ext
->EraseSuspend
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
413 pri_ext
->BlkProt
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
414 pri_ext
->TmpBlkUnprotect
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
415 pri_ext
->BlkProtUnprot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
416 pri_ext
->SimultaneousOps
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 10);
417 pri_ext
->BurstMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 11);
418 pri_ext
->PageMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 12);
419 pri_ext
->VppMin
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 13);
420 pri_ext
->VppMax
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 14);
421 pri_ext
->TopBottom
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 15);
423 DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext
->SiliconRevision
,
424 pri_ext
->EraseSuspend
, pri_ext
->BlkProt
);
426 DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext
->TmpBlkUnprotect
,
427 pri_ext
->BlkProtUnprot
, pri_ext
->SimultaneousOps
);
429 DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext
->BurstMode
, pri_ext
->PageMode
);
432 DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
433 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
434 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
436 DEBUG("WP# protection 0x%x", pri_ext
->TopBottom
);
438 /* default values for implementation specific workarounds */
439 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
440 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
441 pri_ext
->_reversed_geometry
= 0;
446 int cfi_read_atmel_pri_ext(flash_bank_t
*bank
)
448 cfi_atmel_pri_ext_t atmel_pri_ext
;
449 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
450 cfi_spansion_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_spansion_pri_ext_t
));
451 target_t
*target
= bank
->target
;
454 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
455 * but a different primary extended query table.
456 * We read the atmel table, and prepare a valid AMD/Spansion query table.
459 memset(pri_ext
, 0, sizeof(cfi_spansion_pri_ext_t
));
461 cfi_info
->pri_ext
= pri_ext
;
463 atmel_pri_ext
.pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
464 atmel_pri_ext
.pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
465 atmel_pri_ext
.pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
467 if ((atmel_pri_ext
.pri
[0] != 'P') || (atmel_pri_ext
.pri
[1] != 'R') || (atmel_pri_ext
.pri
[2] != 'I'))
469 cfi_command(bank
, 0xf0, command
);
470 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
471 return ERROR_FLASH_BANK_INVALID
;
474 pri_ext
->pri
[0] = atmel_pri_ext
.pri
[0];
475 pri_ext
->pri
[1] = atmel_pri_ext
.pri
[1];
476 pri_ext
->pri
[2] = atmel_pri_ext
.pri
[2];
478 atmel_pri_ext
.major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
479 atmel_pri_ext
.minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
481 DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext
.pri
[0], atmel_pri_ext
.pri
[1], atmel_pri_ext
.pri
[2], atmel_pri_ext
.major_version
, atmel_pri_ext
.minor_version
);
483 pri_ext
->major_version
= atmel_pri_ext
.major_version
;
484 pri_ext
->minor_version
= atmel_pri_ext
.minor_version
;
486 atmel_pri_ext
.features
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
487 atmel_pri_ext
.bottom_boot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
488 atmel_pri_ext
.burst_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
489 atmel_pri_ext
.page_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
491 DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
492 atmel_pri_ext
.features
, atmel_pri_ext
.bottom_boot
, atmel_pri_ext
.burst_mode
, atmel_pri_ext
.page_mode
);
494 if (atmel_pri_ext
.features
& 0x02)
495 pri_ext
->EraseSuspend
= 2;
497 if (atmel_pri_ext
.bottom_boot
)
498 pri_ext
->TopBottom
= 2;
500 pri_ext
->TopBottom
= 3;
502 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
503 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
508 int cfi_read_0002_pri_ext(flash_bank_t
*bank
)
510 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
512 if (cfi_info
->manufacturer
== CFI_MFR_ATMEL
)
514 return cfi_read_atmel_pri_ext(bank
);
518 return cfi_read_spansion_pri_ext(bank
);
522 int cfi_spansion_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
525 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
526 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
528 printed
= snprintf(buf
, buf_size
, "\nSpansion primary algorithm extend information:\n");
532 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0],
533 pri_ext
->pri
[1], pri_ext
->pri
[2],
534 pri_ext
->major_version
, pri_ext
->minor_version
);
538 printed
= snprintf(buf
, buf_size
, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
539 (pri_ext
->SiliconRevision
) >> 2,
540 (pri_ext
->SiliconRevision
) & 0x03);
544 printed
= snprintf(buf
, buf_size
, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
545 pri_ext
->EraseSuspend
,
550 printed
= snprintf(buf
, buf_size
, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
551 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
552 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
557 int cfi_intel_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
560 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
561 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
563 printed
= snprintf(buf
, buf_size
, "\nintel primary algorithm extend information:\n");
567 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
571 printed
= snprintf(buf
, buf_size
, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext
->feature_support
, pri_ext
->suspend_cmd_support
, pri_ext
->blk_status_reg_mask
);
575 printed
= snprintf(buf
, buf_size
, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
576 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
577 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
581 printed
= snprintf(buf
, buf_size
, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
586 int cfi_register_commands(struct command_context_s
*cmd_ctx
)
588 /*command_t *cfi_cmd = */register_command(cmd_ctx
, NULL
, "cfi", NULL
, COMMAND_ANY
, NULL
);
590 register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
591 "print part id of cfi flash bank <num>");
596 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
598 int cfi_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
)
600 cfi_flash_bank_t
*cfi_info
;
605 WARNING("incomplete flash_bank cfi configuration");
606 return ERROR_FLASH_BANK_INVALID
;
609 if ((strtoul(args
[4], NULL
, 0) > CFI_MAX_CHIP_WIDTH
)
610 || (strtoul(args
[3], NULL
, 0) > CFI_MAX_BUS_WIDTH
))
612 ERROR("chip and bus width have to specified in byte");
613 return ERROR_FLASH_BANK_INVALID
;
616 cfi_info
= malloc(sizeof(cfi_flash_bank_t
));
617 bank
->driver_priv
= cfi_info
;
619 cfi_info
->write_algorithm
= NULL
;
620 cfi_info
->erase_check_algorithm
= NULL
;
622 cfi_info
->x16_as_x8
= 0;
623 cfi_info
->jedec_probe
= 0;
624 cfi_info
->not_cfi
= 0;
626 for (i
= 6; i
< argc
; i
++)
628 if (strcmp(args
[i
], "x16_as_x8") == 0)
630 cfi_info
->x16_as_x8
= 1;
632 else if (strcmp(args
[i
], "jedec_probe") == 0)
634 cfi_info
->jedec_probe
= 1;
638 cfi_info
->write_algorithm
= NULL
;
640 /* bank wasn't probed yet */
641 cfi_info
->qry
[0] = -1;
646 int cfi_intel_erase(struct flash_bank_s
*bank
, int first
, int last
)
648 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
649 target_t
*target
= bank
->target
;
653 cfi_intel_clear_status_register(bank
);
655 for (i
= first
; i
<= last
; i
++)
657 cfi_command(bank
, 0x20, command
);
658 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
660 cfi_command(bank
, 0xd0, command
);
661 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
663 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == 0x80)
664 bank
->sectors
[i
].is_erased
= 1;
667 cfi_command(bank
, 0xff, command
);
668 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
670 ERROR("couldn't erase block %i of flash bank at base 0x%x", i
, bank
->base
);
671 return ERROR_FLASH_OPERATION_FAILED
;
675 cfi_command(bank
, 0xff, command
);
676 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
681 int cfi_spansion_erase(struct flash_bank_s
*bank
, int first
, int last
)
683 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
684 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
685 target_t
*target
= bank
->target
;
689 for (i
= first
; i
<= last
; i
++)
691 cfi_command(bank
, 0xaa, command
);
692 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
694 cfi_command(bank
, 0x55, command
);
695 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
);
697 cfi_command(bank
, 0x80, command
);
698 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
700 cfi_command(bank
, 0xaa, command
);
701 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
703 cfi_command(bank
, 0x55, command
);
704 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
);
706 cfi_command(bank
, 0x30, command
);
707 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
709 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == ERROR_OK
)
710 bank
->sectors
[i
].is_erased
= 1;
713 cfi_command(bank
, 0xf0, command
);
714 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
716 ERROR("couldn't erase block %i of flash bank at base 0x%x", i
, bank
->base
);
717 return ERROR_FLASH_OPERATION_FAILED
;
721 cfi_command(bank
, 0xf0, command
);
722 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
727 int cfi_erase(struct flash_bank_s
*bank
, int first
, int last
)
729 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
731 if (bank
->target
->state
!= TARGET_HALTED
)
733 return ERROR_TARGET_NOT_HALTED
;
736 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
738 return ERROR_FLASH_SECTOR_INVALID
;
741 if (cfi_info
->qry
[0] != 'Q')
742 return ERROR_FLASH_BANK_NOT_PROBED
;
744 switch(cfi_info
->pri_id
)
748 return cfi_intel_erase(bank
, first
, last
);
751 return cfi_spansion_erase(bank
, first
, last
);
754 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
761 int cfi_intel_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
763 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
764 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
765 target_t
*target
= bank
->target
;
770 /* if the device supports neither legacy lock/unlock (bit 3) nor
771 * instant individual block locking (bit 5).
773 if (!(pri_ext
->feature_support
& 0x28))
774 return ERROR_FLASH_OPERATION_FAILED
;
776 cfi_intel_clear_status_register(bank
);
778 for (i
= first
; i
<= last
; i
++)
780 cfi_command(bank
, 0x60, command
);
781 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
782 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
785 cfi_command(bank
, 0x01, command
);
786 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
787 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
788 bank
->sectors
[i
].is_protected
= 1;
792 cfi_command(bank
, 0xd0, command
);
793 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
794 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
795 bank
->sectors
[i
].is_protected
= 0;
798 /* instant individual block locking doesn't require reading of the status register */
799 if (!(pri_ext
->feature_support
& 0x20))
801 /* Clear lock bits operation may take up to 1.4s */
802 cfi_intel_wait_status_busy(bank
, 1400);
807 /* read block lock bit, to verify status */
808 cfi_command(bank
, 0x90, command
);
809 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
);
810 block_status
= cfi_get_u8(bank
, i
, 0x2);
812 if ((block_status
& 0x1) != set
)
814 ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set
, block_status
);
815 cfi_command(bank
, 0x70, command
);
816 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
);
817 cfi_intel_wait_status_busy(bank
, 10);
820 return ERROR_FLASH_OPERATION_FAILED
;
830 /* if the device doesn't support individual block lock bits set/clear,
831 * all blocks have been unlocked in parallel, so we set those that should be protected
833 if ((!set
) && (!(pri_ext
->feature_support
& 0x20)))
835 for (i
= 0; i
< bank
->num_sectors
; i
++)
837 cfi_intel_clear_status_register(bank
);
838 cfi_command(bank
, 0x60, command
);
839 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
840 if (bank
->sectors
[i
].is_protected
== 1)
842 cfi_command(bank
, 0x01, command
);
843 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
846 cfi_intel_wait_status_busy(bank
, 100);
850 cfi_command(bank
, 0xff, command
);
851 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
856 int cfi_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
858 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
860 if (bank
->target
->state
!= TARGET_HALTED
)
862 return ERROR_TARGET_NOT_HALTED
;
865 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
867 return ERROR_FLASH_SECTOR_INVALID
;
870 if (cfi_info
->qry
[0] != 'Q')
871 return ERROR_FLASH_BANK_NOT_PROBED
;
873 switch(cfi_info
->pri_id
)
877 cfi_intel_protect(bank
, set
, first
, last
);
880 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
887 void cfi_add_byte(struct flash_bank_s
*bank
, u8
*word
, u8 byte
)
889 target_t
*target
= bank
->target
;
893 if (target
->endianness
== TARGET_LITTLE_ENDIAN
)
896 for (i
= 0; i
< bank
->bus_width
- 1; i
++)
897 word
[i
] = word
[i
+ 1];
898 word
[bank
->bus_width
- 1] = byte
;
903 for (i
= bank
->bus_width
- 1; i
> 0; i
--)
904 word
[i
] = word
[i
- 1];
909 int cfi_intel_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 address
, u32 count
)
911 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
912 target_t
*target
= bank
->target
;
913 reg_param_t reg_params
[7];
914 armv4_5_algorithm_t armv4_5_info
;
915 working_area_t
*source
;
916 u32 buffer_size
= 32768;
917 u8 write_command_buf
[CFI_MAX_BUS_WIDTH
];
918 u8 busy_pattern_buf
[CFI_MAX_BUS_WIDTH
];
919 u8 error_pattern_buf
[CFI_MAX_BUS_WIDTH
];
920 u32 write_command_val
, busy_pattern_val
, error_pattern_val
;
923 /* algorithm register usage:
924 * r0: source address (in RAM)
925 * r1: target address (in Flash)
927 * r3: flash write command
928 * r4: status byte (returned to host)
929 * r5: busy test pattern
930 * r6: error test pattern
933 static const u32 word_32_code
[] = {
934 0xe4904004, /* loop: ldr r4, [r0], #4 */
935 0xe5813000, /* str r3, [r1] */
936 0xe5814000, /* str r4, [r1] */
937 0xe5914000, /* busy: ldr r4, [r1] */
938 0xe0047005, /* and r7, r4, r5 */
939 0xe1570005, /* cmp r7, r5 */
940 0x1afffffb, /* bne busy */
941 0xe1140006, /* tst r4, r6 */
942 0x1a000003, /* bne done */
943 0xe2522001, /* subs r2, r2, #1 */
944 0x0a000001, /* beq done */
945 0xe2811004, /* add r1, r1 #4 */
946 0xeafffff2, /* b loop */
947 0xeafffffe, /* done: b -2 */
950 static const u32 word_16_code
[] = {
951 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
952 0xe1c130b0, /* strh r3, [r1] */
953 0xe1c140b0, /* strh r4, [r1] */
954 0xe1d140b0, /* busy ldrh r4, [r1] */
955 0xe0047005, /* and r7, r4, r5 */
956 0xe1570005, /* cmp r7, r5 */
957 0x1afffffb, /* bne busy */
958 0xe1140006, /* tst r4, r6 */
959 0x1a000003, /* bne done */
960 0xe2522001, /* subs r2, r2, #1 */
961 0x0a000001, /* beq done */
962 0xe2811002, /* add r1, r1 #2 */
963 0xeafffff2, /* b loop */
964 0xeafffffe, /* done: b -2 */
967 static const u32 word_8_code
[] = {
968 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
969 0xe5c13000, /* strb r3, [r1] */
970 0xe5c14000, /* strb r4, [r1] */
971 0xe5d14000, /* busy ldrb r4, [r1] */
972 0xe0047005, /* and r7, r4, r5 */
973 0xe1570005, /* cmp r7, r5 */
974 0x1afffffb, /* bne busy */
975 0xe1140006, /* tst r4, r6 */
976 0x1a000003, /* bne done */
977 0xe2522001, /* subs r2, r2, #1 */
978 0x0a000001, /* beq done */
979 0xe2811001, /* add r1, r1 #1 */
980 0xeafffff2, /* b loop */
981 0xeafffffe, /* done: b -2 */
984 cfi_intel_clear_status_register(bank
);
986 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
987 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
988 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
990 /* flash write code */
991 if (!cfi_info
->write_algorithm
)
993 u8 write_code_buf
[14 * 4];
996 if (target_alloc_working_area(target
, 4 * 14, &cfi_info
->write_algorithm
) != ERROR_OK
)
998 WARNING("no working area available, can't do block memory writes");
999 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1002 /* write algorithm code to working area */
1003 if (bank
->bus_width
== 1)
1005 for (i
= 0; i
< 14; i
++)
1006 target_buffer_set_u32(target
, write_code_buf
+ (i
*4), word_8_code
[i
]);
1008 else if (bank
->bus_width
== 2)
1010 for (i
= 0; i
< 14; i
++)
1011 target_buffer_set_u32(target
, write_code_buf
+ (i
*4), word_16_code
[i
]);
1013 else if (bank
->bus_width
== 4)
1015 for (i
= 0; i
< 14; i
++)
1016 target_buffer_set_u32(target
, write_code_buf
+ (i
*4), word_32_code
[i
]);
1020 return ERROR_FLASH_OPERATION_FAILED
;
1023 target_write_buffer(target
, cfi_info
->write_algorithm
->address
, 14 * 4, write_code_buf
);
1026 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
1029 if (buffer_size
<= 256)
1031 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1032 if (cfi_info
->write_algorithm
)
1033 target_free_working_area(target
, cfi_info
->write_algorithm
);
1035 WARNING("no large enough working area available, can't do block memory writes");
1036 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1040 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1041 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1042 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1043 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1044 init_reg_param(®_params
[4], "r4", 32, PARAM_IN
);
1045 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
);
1046 init_reg_param(®_params
[6], "r6", 32, PARAM_OUT
);
1048 /* prepare command and status register patterns */
1049 cfi_command(bank
, 0x40, write_command_buf
);
1050 cfi_command(bank
, 0x80, busy_pattern_buf
);
1051 cfi_command(bank
, 0x7e, error_pattern_buf
);
1053 if (bank
->bus_width
== 1)
1055 write_command_val
= write_command_buf
[0];
1056 busy_pattern_val
= busy_pattern_buf
[0];
1057 error_pattern_val
= error_pattern_buf
[0];
1059 else if (bank
->bus_width
== 2)
1061 write_command_val
= target_buffer_get_u16(target
, write_command_buf
);
1062 busy_pattern_val
= target_buffer_get_u16(target
, busy_pattern_buf
);
1063 error_pattern_val
= target_buffer_get_u16(target
, error_pattern_buf
);
1065 else if (bank
->bus_width
== 4)
1067 write_command_val
= target_buffer_get_u32(target
, write_command_buf
);
1068 busy_pattern_val
= target_buffer_get_u32(target
, busy_pattern_buf
);
1069 error_pattern_val
= target_buffer_get_u32(target
, error_pattern_buf
);
1074 u32 thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1076 target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1078 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1079 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1080 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1081 buf_set_u32(reg_params
[3].value
, 0, 32, write_command_val
);
1082 buf_set_u32(reg_params
[5].value
, 0, 32, busy_pattern_val
);
1083 buf_set_u32(reg_params
[6].value
, 0, 32, error_pattern_val
);
1085 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 7, reg_params
, cfi_info
->write_algorithm
->address
, cfi_info
->write_algorithm
->address
+ (13 * 4), 10000, &armv4_5_info
)) != ERROR_OK
)
1087 cfi_intel_clear_status_register(bank
);
1088 return ERROR_FLASH_OPERATION_FAILED
;
1091 if (buf_get_u32(reg_params
[4].value
, 0, 32) & error_pattern_val
)
1093 /* read status register (outputs debug inforation) */
1094 cfi_intel_wait_status_busy(bank
, 100);
1095 cfi_intel_clear_status_register(bank
);
1096 return ERROR_FLASH_OPERATION_FAILED
;
1099 buffer
+= thisrun_count
;
1100 address
+= thisrun_count
;
1101 count
-= thisrun_count
;
1104 target_free_working_area(target
, source
);
1106 destroy_reg_param(®_params
[0]);
1107 destroy_reg_param(®_params
[1]);
1108 destroy_reg_param(®_params
[2]);
1109 destroy_reg_param(®_params
[3]);
1110 destroy_reg_param(®_params
[4]);
1111 destroy_reg_param(®_params
[5]);
1112 destroy_reg_param(®_params
[6]);
1117 int cfi_spansion_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 address
, u32 count
)
1119 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1120 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1121 target_t
*target
= bank
->target
;
1122 reg_param_t reg_params
[10];
1123 armv4_5_algorithm_t armv4_5_info
;
1124 working_area_t
*source
;
1125 u32 buffer_size
= 32768;
1126 u8 write_command
[CFI_MAX_BUS_WIDTH
];
1130 int exit_code
= ERROR_OK
;
1132 /* input parameters - */
1133 /* R0 = source address */
1134 /* R1 = destination address */
1135 /* R2 = number of writes */
1136 /* R3 = flash write command */
1137 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1138 /* output parameters - */
1139 /* R5 = 0x80 ok 0x00 bad */
1140 /* temp registers - */
1141 /* R6 = value read from flash to test status */
1142 /* R7 = holding register */
1143 /* unlock registers - */
1144 /* R8 = unlock1_addr */
1145 /* R9 = unlock1_cmd */
1146 /* R10 = unlock2_addr */
1147 /* R11 = unlock2_cmd */
1149 u32 word_32_code
[] = {
1150 /* 00008100 <sp_32_code>: */
1151 0xe4905004, /* ldr r5, [r0], #4 */
1152 0xe5889000, /* str r9, [r8] */
1153 0xe58ab000, /* str r11, [r10] */
1154 0xe5883000, /* str r3, [r8] */
1155 0xe5815000, /* str r5, [r1] */
1156 0xe1a00000, /* nop */
1158 /* 00008110 <sp_32_busy>: */
1159 0xe5916000, /* ldr r6, [r1] */
1160 0xe0257006, /* eor r7, r5, r6 */
1161 0xe0147007, /* ands r7, r4, r7 */
1162 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1163 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1164 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1165 0xe5916000, /* ldr r6, [r1] */
1166 0xe0257006, /* eor r7, r5, r6 */
1167 0xe0147007, /* ands r7, r4, r7 */
1168 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1169 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1170 0x1a000004, /* bne 8154 <sp_32_done> */
1172 /* 00008140 <sp_32_cont>: */
1173 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1174 0x03a05080, /* moveq r5, #128 ; 0x80 */
1175 0x0a000001, /* beq 8154 <sp_32_done> */
1176 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1177 0xeaffffe8, /* b 8100 <sp_32_code> */
1179 /* 00008154 <sp_32_done>: */
1180 0xeafffffe /* b 8154 <sp_32_done> */
1183 u32 word_16_code
[] = {
1184 /* 00008158 <sp_16_code>: */
1185 0xe0d050b2, /* ldrh r5, [r0], #2 */
1186 0xe1c890b0, /* strh r9, [r8] */
1187 0xe1cab0b0, /* strh r11, [r10] */
1188 0xe1c830b0, /* strh r3, [r8] */
1189 0xe1c150b0, /* strh r5, [r1] */
1190 0xe1a00000, /* nop (mov r0,r0) */
1192 /* 00008168 <sp_16_busy>: */
1193 0xe1d160b0, /* ldrh r6, [r1] */
1194 0xe0257006, /* eor r7, r5, r6 */
1195 0xe0147007, /* ands r7, r4, r7 */
1196 0x0a000007, /* beq 8198 <sp_16_cont> */
1197 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1198 0x0afffff9, /* beq 8168 <sp_16_busy> */
1199 0xe1d160b0, /* ldrh r6, [r1] */
1200 0xe0257006, /* eor r7, r5, r6 */
1201 0xe0147007, /* ands r7, r4, r7 */
1202 0x0a000001, /* beq 8198 <sp_16_cont> */
1203 0xe3a05000, /* mov r5, #0 ; 0x0 */
1204 0x1a000004, /* bne 81ac <sp_16_done> */
1206 /* 00008198 <sp_16_cont>: */
1207 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1208 0x03a05080, /* moveq r5, #128 ; 0x80 */
1209 0x0a000001, /* beq 81ac <sp_16_done> */
1210 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1211 0xeaffffe8, /* b 8158 <sp_16_code> */
1213 /* 000081ac <sp_16_done>: */
1214 0xeafffffe /* b 81ac <sp_16_done> */
1217 u32 word_8_code
[] = {
1218 /* 000081b0 <sp_16_code_end>: */
1219 0xe4d05001, /* ldrb r5, [r0], #1 */
1220 0xe5c89000, /* strb r9, [r8] */
1221 0xe5cab000, /* strb r11, [r10] */
1222 0xe5c83000, /* strb r3, [r8] */
1223 0xe5c15000, /* strb r5, [r1] */
1224 0xe1a00000, /* nop (mov r0,r0) */
1226 /* 000081c0 <sp_8_busy>: */
1227 0xe5d16000, /* ldrb r6, [r1] */
1228 0xe0257006, /* eor r7, r5, r6 */
1229 0xe0147007, /* ands r7, r4, r7 */
1230 0x0a000007, /* beq 81f0 <sp_8_cont> */
1231 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1232 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1233 0xe5d16000, /* ldrb r6, [r1] */
1234 0xe0257006, /* eor r7, r5, r6 */
1235 0xe0147007, /* ands r7, r4, r7 */
1236 0x0a000001, /* beq 81f0 <sp_8_cont> */
1237 0xe3a05000, /* mov r5, #0 ; 0x0 */
1238 0x1a000004, /* bne 8204 <sp_8_done> */
1240 /* 000081f0 <sp_8_cont>: */
1241 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1242 0x03a05080, /* moveq r5, #128 ; 0x80 */
1243 0x0a000001, /* beq 8204 <sp_8_done> */
1244 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1245 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1247 /* 00008204 <sp_8_done>: */
1248 0xeafffffe /* b 8204 <sp_8_done> */
1251 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
1252 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
1253 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
1255 /* flash write code */
1256 if (!cfi_info
->write_algorithm
)
1260 /* convert bus-width dependent algorithm code to correct endiannes */
1261 if (bank
->bus_width
== 1)
1263 code_p
= malloc(24 * 4);
1265 for (i
= 0; i
< 24; i
++)
1266 target_buffer_set_u32(target
, code_p
+ (i
*4), word_8_code
[i
]);
1268 else if (bank
->bus_width
== 2)
1270 code_p
= malloc(24 * 4);
1272 for (i
= 0; i
< 24; i
++)
1273 target_buffer_set_u32(target
, code_p
+ (i
*4), word_16_code
[i
]);
1275 else if (bank
->bus_width
== 4)
1277 code_p
= malloc(24 * 4);
1279 for (i
= 0; i
< 24; i
++)
1280 target_buffer_set_u32(target
, code_p
+ (i
*4), word_32_code
[i
]);
1284 return ERROR_FLASH_OPERATION_FAILED
;
1287 /* allocate working area */
1288 if (target_alloc_working_area(target
, 24 * 4,
1289 &cfi_info
->write_algorithm
) != ERROR_OK
)
1291 WARNING("no working area available, can't do block memory writes");
1292 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1295 /* write algorithm code to working area */
1296 target_write_buffer(target
, cfi_info
->write_algorithm
->address
, 24 * 4, code_p
);
1301 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
1304 if (buffer_size
<= 256)
1306 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1307 if (cfi_info
->write_algorithm
)
1308 target_free_working_area(target
, cfi_info
->write_algorithm
);
1310 WARNING("not enough working area available, can't do block memory writes");
1311 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1315 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1316 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1317 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1318 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1319 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
);
1320 init_reg_param(®_params
[5], "r5", 32, PARAM_IN
);
1321 init_reg_param(®_params
[6], "r8", 32, PARAM_OUT
);
1322 init_reg_param(®_params
[7], "r9", 32, PARAM_OUT
);
1323 init_reg_param(®_params
[8], "r10", 32, PARAM_OUT
);
1324 init_reg_param(®_params
[9], "r11", 32, PARAM_OUT
);
1328 u32 thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1330 target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1332 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1333 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1334 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1335 cfi_command(bank
, 0xA0, write_command
);
1336 buf_set_u32(reg_params
[3].value
, 0, 32, buf_get_u32(write_command
, 0, 32));
1337 cfi_command(bank
, 0x80, write_command
);
1338 buf_set_u32(reg_params
[4].value
, 0, 32, buf_get_u32(write_command
, 0, 32));
1339 buf_set_u32(reg_params
[6].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock1
));
1340 buf_set_u32(reg_params
[7].value
, 0, 32, 0xaa);
1341 buf_set_u32(reg_params
[8].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock2
));
1342 buf_set_u32(reg_params
[9].value
, 0, 32, 0x55);
1344 retval
= target
->type
->run_algorithm(target
, 0, NULL
, 10, reg_params
,
1345 cfi_info
->write_algorithm
->address
,
1346 cfi_info
->write_algorithm
->address
+ ((24 * 4) - 4),
1347 10000, &armv4_5_info
);
1349 status
= buf_get_u32(reg_params
[5].value
, 0, 32);
1351 if ((retval
!= ERROR_OK
) || status
!= 0x80)
1353 DEBUG("status: 0x%x", status
);
1354 exit_code
= ERROR_FLASH_OPERATION_FAILED
;
1358 buffer
+= thisrun_count
;
1359 address
+= thisrun_count
;
1360 count
-= thisrun_count
;
1363 target_free_working_area(target
, source
);
1365 destroy_reg_param(®_params
[0]);
1366 destroy_reg_param(®_params
[1]);
1367 destroy_reg_param(®_params
[2]);
1368 destroy_reg_param(®_params
[3]);
1369 destroy_reg_param(®_params
[4]);
1370 destroy_reg_param(®_params
[5]);
1371 destroy_reg_param(®_params
[6]);
1372 destroy_reg_param(®_params
[7]);
1373 destroy_reg_param(®_params
[8]);
1374 destroy_reg_param(®_params
[9]);
1379 int cfi_intel_write_word(struct flash_bank_s
*bank
, u8
*word
, u32 address
)
1381 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1382 target_t
*target
= bank
->target
;
1385 cfi_intel_clear_status_register(bank
);
1386 cfi_command(bank
, 0x40, command
);
1387 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
);
1389 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, word
);
1391 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != 0x80)
1393 cfi_command(bank
, 0xff, command
);
1394 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1396 ERROR("couldn't write word at base 0x%x, address %x", bank
->base
, address
);
1397 return ERROR_FLASH_OPERATION_FAILED
;
1403 int cfi_spansion_write_word(struct flash_bank_s
*bank
, u8
*word
, u32 address
)
1405 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1406 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1407 target_t
*target
= bank
->target
;
1410 cfi_command(bank
, 0xaa, command
);
1411 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
1413 cfi_command(bank
, 0x55, command
);
1414 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
);
1416 cfi_command(bank
, 0xa0, command
);
1417 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
1419 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, word
);
1421 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1423 cfi_command(bank
, 0xf0, command
);
1424 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1426 ERROR("couldn't write word at base 0x%x, address %x", bank
->base
, address
);
1427 return ERROR_FLASH_OPERATION_FAILED
;
1433 int cfi_write_word(struct flash_bank_s
*bank
, u8
*word
, u32 address
)
1435 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1437 switch(cfi_info
->pri_id
)
1441 return cfi_intel_write_word(bank
, word
, address
);
1444 return cfi_spansion_write_word(bank
, word
, address
);
1447 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1451 return ERROR_FLASH_OPERATION_FAILED
;
1454 int cfi_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
1456 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1457 target_t
*target
= bank
->target
;
1458 u32 address
= bank
->base
+ offset
; /* address of first byte to be programmed */
1459 u32 write_p
, copy_p
;
1460 int align
; /* number of unaligned bytes */
1461 u8 current_word
[CFI_MAX_BUS_WIDTH
* 4]; /* word (bus_width size) currently being programmed */
1465 if (bank
->target
->state
!= TARGET_HALTED
)
1467 return ERROR_TARGET_NOT_HALTED
;
1470 if (offset
+ count
> bank
->size
)
1471 return ERROR_FLASH_DST_OUT_OF_BANK
;
1473 if (cfi_info
->qry
[0] != 'Q')
1474 return ERROR_FLASH_BANK_NOT_PROBED
;
1476 /* start at the first byte of the first word (bus_width size) */
1477 write_p
= address
& ~(bank
->bus_width
- 1);
1478 if ((align
= address
- write_p
) != 0)
1480 for (i
= 0; i
< bank
->bus_width
; i
++)
1481 current_word
[i
] = 0;
1484 /* copy bytes before the first write address */
1485 for (i
= 0; i
< align
; ++i
, ++copy_p
)
1488 target
->type
->read_memory(target
, copy_p
, 1, 1, &byte
);
1489 cfi_add_byte(bank
, current_word
, byte
);
1492 /* add bytes from the buffer */
1493 for (; (i
< bank
->bus_width
) && (count
> 0); i
++)
1495 cfi_add_byte(bank
, current_word
, *buffer
++);
1500 /* if the buffer is already finished, copy bytes after the last write address */
1501 for (; (count
== 0) && (i
< bank
->bus_width
); ++i
, ++copy_p
)
1504 target
->type
->read_memory(target
, copy_p
, 1, 1, &byte
);
1505 cfi_add_byte(bank
, current_word
, byte
);
1508 retval
= cfi_write_word(bank
, current_word
, write_p
);
1509 if (retval
!= ERROR_OK
)
1514 /* handle blocks of bus_size aligned bytes */
1515 switch(cfi_info
->pri_id
)
1517 /* try block writes (fails without working area) */
1520 retval
= cfi_intel_write_block(bank
, buffer
, write_p
, count
);
1523 retval
= cfi_spansion_write_block(bank
, buffer
, write_p
, count
);
1526 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1527 retval
= ERROR_FLASH_OPERATION_FAILED
;
1530 if (retval
!= ERROR_OK
)
1532 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
1534 /* fall back to memory writes */
1535 while (count
> bank
->bus_width
)
1537 for (i
= 0; i
< bank
->bus_width
; i
++)
1538 current_word
[i
] = 0;
1540 for (i
= 0; i
< bank
->bus_width
; i
++)
1542 cfi_add_byte(bank
, current_word
, *buffer
++);
1545 retval
= cfi_write_word(bank
, current_word
, write_p
);
1546 if (retval
!= ERROR_OK
)
1548 write_p
+= bank
->bus_width
;
1549 count
-= bank
->bus_width
;
1556 /* handle unaligned tail bytes */
1560 for (i
= 0; i
< bank
->bus_width
; i
++)
1561 current_word
[i
] = 0;
1563 for (i
= 0; (i
< bank
->bus_width
) && (count
> 0); ++i
, ++copy_p
)
1565 cfi_add_byte(bank
, current_word
, *buffer
++);
1568 for (; i
< bank
->bus_width
; ++i
, ++copy_p
)
1571 target
->type
->read_memory(target
, copy_p
, 1, 1, &byte
);
1572 cfi_add_byte(bank
, current_word
, byte
);
1574 retval
= cfi_write_word(bank
, current_word
, write_p
);
1575 if (retval
!= ERROR_OK
)
1579 /* return to read array mode */
1580 cfi_command(bank
, 0xf0, current_word
);
1581 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
1582 cfi_command(bank
, 0xff, current_word
);
1583 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
1588 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t
*bank
, void *param
)
1590 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1591 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1593 pri_ext
->_reversed_geometry
= 1;
1596 void cfi_fixup_0002_erase_regions(flash_bank_t
*bank
, void *param
)
1599 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1600 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1602 if ((pri_ext
->_reversed_geometry
) || (pri_ext
->TopBottom
== 3))
1604 DEBUG("swapping reversed erase region information on cmdset 0002 device");
1606 for (i
= 0; i
< cfi_info
->num_erase_regions
/ 2; i
++)
1608 int j
= (cfi_info
->num_erase_regions
- 1) - i
;
1611 swap
= cfi_info
->erase_region_info
[i
];
1612 cfi_info
->erase_region_info
[i
] = cfi_info
->erase_region_info
[j
];
1613 cfi_info
->erase_region_info
[j
] = swap
;
1618 void cfi_fixup_0002_unlock_addresses(flash_bank_t
*bank
, void *param
)
1620 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1621 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1622 cfi_unlock_addresses_t
*unlock_addresses
= param
;
1624 pri_ext
->_unlock1
= unlock_addresses
->unlock1
;
1625 pri_ext
->_unlock2
= unlock_addresses
->unlock2
;
1628 int cfi_probe(struct flash_bank_s
*bank
)
1630 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1631 target_t
*target
= bank
->target
;
1633 int num_sectors
= 0;
1637 u32 unlock1
= 0x555;
1638 u32 unlock2
= 0x2aa;
1640 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
1641 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
1643 if (cfi_info
->jedec_probe
)
1649 /* switch to read identifier codes mode ("AUTOSELECT") */
1650 cfi_command(bank
, 0xaa, command
);
1651 target
->type
->write_memory(target
, flash_address(bank
, 0, unlock1
), bank
->bus_width
, 1, command
);
1652 cfi_command(bank
, 0x55, command
);
1653 target
->type
->write_memory(target
, flash_address(bank
, 0, unlock2
), bank
->bus_width
, 1, command
);
1654 cfi_command(bank
, 0x90, command
);
1655 target
->type
->write_memory(target
, flash_address(bank
, 0, unlock1
), bank
->bus_width
, 1, command
);
1657 if (bank
->chip_width
== 1)
1659 u8 manufacturer
, device_id
;
1660 target_read_u8(target
, bank
->base
+ 0x0, &manufacturer
);
1661 target_read_u8(target
, bank
->base
+ 0x1, &device_id
);
1662 cfi_info
->manufacturer
= manufacturer
;
1663 cfi_info
->device_id
= device_id
;
1665 else if (bank
->chip_width
== 2)
1667 target_read_u16(target
, bank
->base
+ 0x0, &cfi_info
->manufacturer
);
1668 target_read_u16(target
, bank
->base
+ 0x2, &cfi_info
->device_id
);
1671 /* switch back to read array mode */
1672 cfi_command(bank
, 0xf0, command
);
1673 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x00), bank
->bus_width
, 1, command
);
1674 cfi_command(bank
, 0xff, command
);
1675 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x00), bank
->bus_width
, 1, command
);
1677 cfi_fixup(bank
, cfi_jedec_fixups
);
1679 /* query only if this is a CFI compatible flash,
1680 * otherwise the relevant info has already been filled in
1682 if (cfi_info
->not_cfi
== 0)
1684 /* enter CFI query mode
1685 * according to JEDEC Standard No. 68.01,
1686 * a single bus sequence with address = 0x55, data = 0x98 should put
1687 * the device into CFI query mode.
1689 * SST flashes clearly violate this, and we will consider them incompatbile for now
1691 cfi_command(bank
, 0x98, command
);
1692 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
);
1694 cfi_info
->qry
[0] = cfi_query_u8(bank
, 0, 0x10);
1695 cfi_info
->qry
[1] = cfi_query_u8(bank
, 0, 0x11);
1696 cfi_info
->qry
[2] = cfi_query_u8(bank
, 0, 0x12);
1698 DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2]);
1700 if ((cfi_info
->qry
[0] != 'Q') || (cfi_info
->qry
[1] != 'R') || (cfi_info
->qry
[2] != 'Y'))
1702 cfi_command(bank
, 0xf0, command
);
1703 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1704 cfi_command(bank
, 0xff, command
);
1705 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1706 return ERROR_FLASH_BANK_INVALID
;
1709 cfi_info
->pri_id
= cfi_query_u16(bank
, 0, 0x13);
1710 cfi_info
->pri_addr
= cfi_query_u16(bank
, 0, 0x15);
1711 cfi_info
->alt_id
= cfi_query_u16(bank
, 0, 0x17);
1712 cfi_info
->alt_addr
= cfi_query_u16(bank
, 0, 0x19);
1714 DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
1716 cfi_info
->vcc_min
= cfi_query_u8(bank
, 0, 0x1b);
1717 cfi_info
->vcc_max
= cfi_query_u8(bank
, 0, 0x1c);
1718 cfi_info
->vpp_min
= cfi_query_u8(bank
, 0, 0x1d);
1719 cfi_info
->vpp_max
= cfi_query_u8(bank
, 0, 0x1e);
1720 cfi_info
->word_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x1f);
1721 cfi_info
->buf_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x20);
1722 cfi_info
->block_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x21);
1723 cfi_info
->chip_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x22);
1724 cfi_info
->word_write_timeout_max
= cfi_query_u8(bank
, 0, 0x23);
1725 cfi_info
->buf_write_timeout_max
= cfi_query_u8(bank
, 0, 0x24);
1726 cfi_info
->block_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x25);
1727 cfi_info
->chip_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x26);
1729 DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
1730 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
1731 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
1732 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
1733 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
1734 DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info
->word_write_timeout_typ
, 1 << cfi_info
->buf_write_timeout_typ
,
1735 1 << cfi_info
->block_erase_timeout_typ
, 1 << cfi_info
->chip_erase_timeout_typ
);
1736 DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
1737 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
1738 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
1739 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
1741 cfi_info
->dev_size
= cfi_query_u8(bank
, 0, 0x27);
1742 cfi_info
->interface_desc
= cfi_query_u16(bank
, 0, 0x28);
1743 cfi_info
->max_buf_write_size
= cfi_query_u16(bank
, 0, 0x2a);
1744 cfi_info
->num_erase_regions
= cfi_query_u8(bank
, 0, 0x2c);
1746 DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info
->dev_size
, cfi_info
->interface_desc
, (1 << cfi_info
->max_buf_write_size
));
1748 if (((1 << cfi_info
->dev_size
) * bank
->bus_width
/ bank
->chip_width
) != bank
->size
)
1750 WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank
->size
, 1 << cfi_info
->dev_size
);
1753 if (cfi_info
->num_erase_regions
)
1755 cfi_info
->erase_region_info
= malloc(4 * cfi_info
->num_erase_regions
);
1756 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
1758 cfi_info
->erase_region_info
[i
] = cfi_query_u32(bank
, 0, 0x2d + (4 * i
));
1759 DEBUG("erase region[%i]: %i blocks of size 0x%x", i
, (cfi_info
->erase_region_info
[i
] & 0xffff) + 1, (cfi_info
->erase_region_info
[i
] >> 16) * 256);
1764 cfi_info
->erase_region_info
= NULL
;
1767 /* We need to read the primary algorithm extended query table before calculating
1768 * the sector layout to be able to apply fixups
1770 switch(cfi_info
->pri_id
)
1772 /* Intel command set (standard and extended) */
1775 cfi_read_intel_pri_ext(bank
);
1777 /* AMD/Spansion, Atmel, ... command set */
1779 cfi_read_0002_pri_ext(bank
);
1782 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1786 /* return to read array mode
1787 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
1789 cfi_command(bank
, 0xf0, command
);
1790 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1791 cfi_command(bank
, 0xff, command
);
1792 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1795 /* apply fixups depending on the primary command set */
1796 switch(cfi_info
->pri_id
)
1798 /* Intel command set (standard and extended) */
1801 cfi_fixup(bank
, cfi_0001_fixups
);
1803 /* AMD/Spansion, Atmel, ... command set */
1805 cfi_fixup(bank
, cfi_0002_fixups
);
1808 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1812 if (cfi_info
->num_erase_regions
== 0)
1814 /* a device might have only one erase block, spanning the whole device */
1815 bank
->num_sectors
= 1;
1816 bank
->sectors
= malloc(sizeof(flash_sector_t
));
1818 bank
->sectors
[sector
].offset
= 0x0;
1819 bank
->sectors
[sector
].size
= bank
->size
;
1820 bank
->sectors
[sector
].is_erased
= -1;
1821 bank
->sectors
[sector
].is_protected
= -1;
1825 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
1827 num_sectors
+= (cfi_info
->erase_region_info
[i
] & 0xffff) + 1;
1830 bank
->num_sectors
= num_sectors
;
1831 bank
->sectors
= malloc(sizeof(flash_sector_t
) * num_sectors
);
1833 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
1836 for (j
= 0; j
< (cfi_info
->erase_region_info
[i
] & 0xffff) + 1; j
++)
1838 bank
->sectors
[sector
].offset
= offset
;
1839 bank
->sectors
[sector
].size
= ((cfi_info
->erase_region_info
[i
] >> 16) * 256) * bank
->bus_width
/ bank
->chip_width
;
1840 offset
+= bank
->sectors
[sector
].size
;
1841 bank
->sectors
[sector
].is_erased
= -1;
1842 bank
->sectors
[sector
].is_protected
= -1;
1851 int cfi_erase_check(struct flash_bank_s
*bank
)
1853 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1854 target_t
*target
= bank
->target
;
1858 if (!cfi_info
->erase_check_algorithm
)
1860 u32 erase_check_code
[] =
1862 0xe4d03001, /* ldrb r3, [r0], #1 */
1863 0xe0022003, /* and r2, r2, r3 */
1864 0xe2511001, /* subs r1, r1, #1 */
1865 0x1afffffb, /* b -4 */
1866 0xeafffffe /* b 0 */
1869 /* make sure we have a working area */
1870 if (target_alloc_working_area(target
, 20, &cfi_info
->erase_check_algorithm
) != ERROR_OK
)
1872 WARNING("no working area available, falling back to slow memory reads");
1876 u8 erase_check_code_buf
[5 * 4];
1878 for (i
= 0; i
< 5; i
++)
1879 target_buffer_set_u32(target
, erase_check_code_buf
+ (i
*4), erase_check_code
[i
]);
1881 /* write algorithm code to working area */
1882 target
->type
->write_memory(target
, cfi_info
->erase_check_algorithm
->address
, 4, 5, erase_check_code_buf
);
1886 if (!cfi_info
->erase_check_algorithm
)
1888 u32
*buffer
= malloc(4096);
1890 for (i
= 0; i
< bank
->num_sectors
; i
++)
1892 u32 address
= bank
->base
+ bank
->sectors
[i
].offset
;
1893 u32 size
= bank
->sectors
[i
].size
;
1894 u32 check
= 0xffffffffU
;
1899 u32 thisrun_size
= (size
> 4096) ? 4096 : size
;
1902 target
->type
->read_memory(target
, address
, 4, thisrun_size
/ 4, (u8
*)buffer
);
1904 for (j
= 0; j
< thisrun_size
/ 4; j
++)
1907 if (check
!= 0xffffffff)
1913 size
-= thisrun_size
;
1914 address
+= thisrun_size
;
1917 bank
->sectors
[i
].is_erased
= erased
;
1924 for (i
= 0; i
< bank
->num_sectors
; i
++)
1926 u32 address
= bank
->base
+ bank
->sectors
[i
].offset
;
1927 u32 size
= bank
->sectors
[i
].size
;
1929 reg_param_t reg_params
[3];
1930 armv4_5_algorithm_t armv4_5_info
;
1932 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
1933 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
1934 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
1936 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1937 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
1939 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1940 buf_set_u32(reg_params
[1].value
, 0, 32, size
);
1942 init_reg_param(®_params
[2], "r2", 32, PARAM_IN_OUT
);
1943 buf_set_u32(reg_params
[2].value
, 0, 32, 0xff);
1945 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 3, reg_params
, cfi_info
->erase_check_algorithm
->address
, cfi_info
->erase_check_algorithm
->address
+ 0x10, 10000, &armv4_5_info
)) != ERROR_OK
)
1946 return ERROR_FLASH_OPERATION_FAILED
;
1948 if (buf_get_u32(reg_params
[2].value
, 0, 32) == 0xff)
1949 bank
->sectors
[i
].is_erased
= 1;
1951 bank
->sectors
[i
].is_erased
= 0;
1953 destroy_reg_param(®_params
[0]);
1954 destroy_reg_param(®_params
[1]);
1955 destroy_reg_param(®_params
[2]);
1962 int cfi_intel_protect_check(struct flash_bank_s
*bank
)
1964 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1965 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1966 target_t
*target
= bank
->target
;
1967 u8 command
[CFI_MAX_BUS_WIDTH
];
1970 /* check if block lock bits are supported on this device */
1971 if (!(pri_ext
->blk_status_reg_mask
& 0x1))
1972 return ERROR_FLASH_OPERATION_FAILED
;
1974 cfi_command(bank
, 0x90, command
);
1975 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
);
1977 for (i
= 0; i
< bank
->num_sectors
; i
++)
1979 u8 block_status
= cfi_get_u8(bank
, i
, 0x2);
1981 if (block_status
& 1)
1982 bank
->sectors
[i
].is_protected
= 1;
1984 bank
->sectors
[i
].is_protected
= 0;
1987 cfi_command(bank
, 0xff, command
);
1988 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1993 int cfi_spansion_protect_check(struct flash_bank_s
*bank
)
1995 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1996 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1997 target_t
*target
= bank
->target
;
2001 cfi_command(bank
, 0xaa, command
);
2002 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
2004 cfi_command(bank
, 0x55, command
);
2005 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
);
2007 cfi_command(bank
, 0x90, command
);
2008 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
2010 for (i
= 0; i
< bank
->num_sectors
; i
++)
2012 u8 block_status
= cfi_get_u8(bank
, i
, 0x2);
2014 if (block_status
& 1)
2015 bank
->sectors
[i
].is_protected
= 1;
2017 bank
->sectors
[i
].is_protected
= 0;
2020 cfi_command(bank
, 0xf0, command
);
2021 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2026 int cfi_protect_check(struct flash_bank_s
*bank
)
2028 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2030 if (cfi_info
->qry
[0] != 'Q')
2031 return ERROR_FLASH_BANK_NOT_PROBED
;
2033 switch(cfi_info
->pri_id
)
2037 return cfi_intel_protect_check(bank
);
2040 return cfi_spansion_protect_check(bank
);
2043 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2050 int cfi_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
2053 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2055 if (cfi_info
->qry
[0] == (char)-1)
2057 printed
= snprintf(buf
, buf_size
, "\ncfi flash bank not probed yet\n");
2061 printed
= snprintf(buf
, buf_size
, "\ncfi information:\n");
2063 buf_size
-= printed
;
2065 printed
= snprintf(buf
, buf_size
, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2066 cfi_info
->manufacturer
, cfi_info
->device_id
);
2068 buf_size
-= printed
;
2070 printed
= snprintf(buf
, buf_size
, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2072 buf_size
-= printed
;
2074 printed
= snprintf(buf
, buf_size
, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n", (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2075 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2076 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2077 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2079 buf_size
-= printed
;
2081 printed
= snprintf(buf
, buf_size
, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n", 1 << cfi_info
->word_write_timeout_typ
, 1 << cfi_info
->buf_write_timeout_typ
,
2082 1 << cfi_info
->block_erase_timeout_typ
, 1 << cfi_info
->chip_erase_timeout_typ
);
2084 buf_size
-= printed
;
2086 printed
= snprintf(buf
, buf_size
, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n", (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2087 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2088 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2089 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2091 buf_size
-= printed
;
2093 printed
= snprintf(buf
, buf_size
, "size: 0x%x, interface desc: %i, max buffer write size: %x\n", 1 << cfi_info
->dev_size
, cfi_info
->interface_desc
, cfi_info
->max_buf_write_size
);
2095 buf_size
-= printed
;
2097 switch(cfi_info
->pri_id
)
2101 cfi_intel_info(bank
, buf
, buf_size
);
2104 cfi_spansion_info(bank
, buf
, buf_size
);
2107 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
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