1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
32 #include "algorithm.h"
33 #include "binarybuffer.h"
40 int cfi_register_commands(struct command_context_s
*cmd_ctx
);
41 int cfi_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
);
42 int cfi_erase(struct flash_bank_s
*bank
, int first
, int last
);
43 int cfi_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
);
44 int cfi_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
);
45 int cfi_probe(struct flash_bank_s
*bank
);
46 int cfi_erase_check(struct flash_bank_s
*bank
);
47 int cfi_protect_check(struct flash_bank_s
*bank
);
48 int cfi_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
);
50 int cfi_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
52 #define CFI_MAX_BUS_WIDTH 4
53 #define CFI_MAX_CHIP_WIDTH 4
55 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
56 #define CFI_MAX_INTEL_CODESIZE 256
58 flash_driver_t cfi_flash
=
61 .register_commands
= cfi_register_commands
,
62 .flash_bank_command
= cfi_flash_bank_command
,
64 .protect
= cfi_protect
,
67 .erase_check
= cfi_erase_check
,
68 .protect_check
= cfi_protect_check
,
72 cfi_unlock_addresses_t cfi_unlock_addresses
[] =
74 [CFI_UNLOCK_555_2AA
] = { .unlock1
= 0x555, .unlock2
= 0x2aa },
75 [CFI_UNLOCK_5555_2AAA
] = { .unlock1
= 0x5555, .unlock2
= 0x2aaa },
78 /* CFI fixups foward declarations */
79 void cfi_fixup_non_cfi(flash_bank_t
*flash
, void *param
);
80 void cfi_fixup_0002_erase_regions(flash_bank_t
*flash
, void *param
);
81 void cfi_fixup_0002_unlock_addresses(flash_bank_t
*flash
, void *param
);
82 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t
*flash
, void *param
);
84 /* fixup after identifying JEDEC manufactuer and ID */
85 cfi_fixup_t cfi_jedec_fixups
[] = {
86 {CFI_MFR_SST
, 0x00D4, cfi_fixup_non_cfi
, NULL
},
87 {CFI_MFR_SST
, 0x00D5, cfi_fixup_non_cfi
, NULL
},
88 {CFI_MFR_SST
, 0x00D6, cfi_fixup_non_cfi
, NULL
},
89 {CFI_MFR_SST
, 0x00D7, cfi_fixup_non_cfi
, NULL
},
90 {CFI_MFR_ST
, 0x00D5, cfi_fixup_non_cfi
, NULL
},
91 {CFI_MFR_ST
, 0x00D6, cfi_fixup_non_cfi
, NULL
},
92 {CFI_MFR_AMD
, 0x2223, cfi_fixup_non_cfi
, NULL
},
93 {CFI_MFR_AMD
, 0x22ab, cfi_fixup_non_cfi
, NULL
},
97 /* fixup after reading cmdset 0002 primary query table */
98 cfi_fixup_t cfi_0002_fixups
[] = {
99 {CFI_MFR_SST
, 0x00D4, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
100 {CFI_MFR_SST
, 0x00D5, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
101 {CFI_MFR_SST
, 0x00D6, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
102 {CFI_MFR_SST
, 0x00D7, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
103 {CFI_MFR_ATMEL
, 0x00C8, cfi_fixup_atmel_reversed_erase_regions
, NULL
},
104 {CFI_MFR_ANY
, CFI_ID_ANY
, cfi_fixup_0002_erase_regions
, NULL
},
108 /* fixup after reading cmdset 0001 primary query table */
109 cfi_fixup_t cfi_0001_fixups
[] = {
113 void cfi_fixup(flash_bank_t
*bank
, cfi_fixup_t
*fixups
)
115 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
118 for (f
= fixups
; f
->fixup
; f
++)
120 if (((f
->mfr
== CFI_MFR_ANY
) || (f
->mfr
== cfi_info
->manufacturer
)) &&
121 ((f
->id
== CFI_ID_ANY
) || (f
->id
== cfi_info
->device_id
)))
123 f
->fixup(bank
, f
->param
);
128 inline u32
flash_address(flash_bank_t
*bank
, int sector
, u32 offset
)
130 /* while the sector list isn't built, only accesses to sector 0 work */
132 return bank
->base
+ offset
* bank
->bus_width
;
137 ERROR("BUG: sector list not yet built");
140 return bank
->base
+ bank
->sectors
[sector
].offset
+ offset
* bank
->bus_width
;
145 void cfi_command(flash_bank_t
*bank
, u8 cmd
, u8
*cmd_buf
)
149 /* clear whole buffer, to ensure bits that exceed the bus_width
152 for (i
= 0; i
< CFI_MAX_BUS_WIDTH
; i
++)
155 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
157 for (i
= bank
->bus_width
; i
> 0; i
--)
159 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
164 for (i
= 1; i
<= bank
->bus_width
; i
++)
166 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
171 /* read unsigned 8-bit value from the bank
172 * flash banks are expected to be made of similar chips
173 * the query result should be the same for all
175 u8
cfi_query_u8(flash_bank_t
*bank
, int sector
, u32 offset
)
177 target_t
*target
= bank
->target
;
178 u8 data
[CFI_MAX_BUS_WIDTH
];
180 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
182 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
185 return data
[bank
->bus_width
- 1];
188 /* read unsigned 8-bit value from the bank
189 * in case of a bank made of multiple chips,
190 * the individual values are ORed
192 u8
cfi_get_u8(flash_bank_t
*bank
, int sector
, u32 offset
)
194 target_t
*target
= bank
->target
;
195 u8 data
[CFI_MAX_BUS_WIDTH
];
198 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
200 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
202 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
210 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
211 value
|= data
[bank
->bus_width
- 1 - i
];
217 u16
cfi_query_u16(flash_bank_t
*bank
, int sector
, u32 offset
)
219 target_t
*target
= bank
->target
;
220 u8 data
[CFI_MAX_BUS_WIDTH
* 2];
222 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 2, data
);
224 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
225 return data
[0] | data
[bank
->bus_width
] << 8;
227 return data
[bank
->bus_width
- 1] | data
[(2 * bank
->bus_width
) - 1] << 8;
230 u32
cfi_query_u32(flash_bank_t
*bank
, int sector
, u32 offset
)
232 target_t
*target
= bank
->target
;
233 u8 data
[CFI_MAX_BUS_WIDTH
* 4];
235 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 4, data
);
237 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
238 return data
[0] | data
[bank
->bus_width
] << 8 | data
[bank
->bus_width
* 2] << 16 | data
[bank
->bus_width
* 3] << 24;
240 return data
[bank
->bus_width
- 1] | data
[(2* bank
->bus_width
) - 1] << 8 |
241 data
[(3 * bank
->bus_width
) - 1] << 16 | data
[(4 * bank
->bus_width
) - 1] << 24;
244 void cfi_intel_clear_status_register(flash_bank_t
*bank
)
246 target_t
*target
= bank
->target
;
249 if (target
->state
!= TARGET_HALTED
)
251 ERROR("BUG: attempted to clear status register while target wasn't halted");
255 cfi_command(bank
, 0x50, command
);
256 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
259 u8
cfi_intel_wait_status_busy(flash_bank_t
*bank
, int timeout
)
263 while ((!((status
= cfi_get_u8(bank
, 0, 0x0)) & 0x80)) && (timeout
-- > 0))
265 DEBUG("status: 0x%x", status
);
269 /* mask out bit 0 (reserved) */
270 status
= status
& 0xfe;
272 DEBUG("status: 0x%x", status
);
274 if ((status
& 0x80) != 0x80)
276 ERROR("timeout while waiting for WSM to become ready");
278 else if (status
!= 0x80)
280 ERROR("status register: 0x%x", status
);
282 ERROR("Block Lock-Bit Detected, Operation Abort");
284 ERROR("Program suspended");
286 ERROR("Low Programming Voltage Detected, Operation Aborted");
288 ERROR("Program Error / Error in Setting Lock-Bit");
290 ERROR("Error in Block Erasure or Clear Lock-Bits");
292 ERROR("Block Erase Suspended");
294 cfi_intel_clear_status_register(bank
);
300 int cfi_spansion_wait_status_busy(flash_bank_t
*bank
, int timeout
)
302 u8 status
, oldstatus
;
304 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
307 status
= cfi_get_u8(bank
, 0, 0x0);
308 if ((status
^ oldstatus
) & 0x40) {
310 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
311 status
= cfi_get_u8(bank
, 0, 0x0);
312 if ((status
^ oldstatus
) & 0x40) {
313 ERROR("dq5 timeout, status: 0x%x", status
);
314 return(ERROR_FLASH_OPERATION_FAILED
);
316 DEBUG("status: 0x%x", status
);
321 DEBUG("status: 0x%x", status
);
327 } while (timeout
-- > 0);
329 ERROR("timeout, status: 0x%x", status
);
331 return(ERROR_FLASH_BUSY
);
334 int cfi_read_intel_pri_ext(flash_bank_t
*bank
)
336 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
337 cfi_intel_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_intel_pri_ext_t
));
338 target_t
*target
= bank
->target
;
341 cfi_info
->pri_ext
= pri_ext
;
343 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
344 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
345 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
347 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
349 cfi_command(bank
, 0xf0, command
);
350 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
351 cfi_command(bank
, 0xff, command
);
352 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
353 return ERROR_FLASH_BANK_INVALID
;
356 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
357 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
359 DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
361 pri_ext
->feature_support
= cfi_query_u32(bank
, 0, cfi_info
->pri_addr
+ 5);
362 pri_ext
->suspend_cmd_support
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
363 pri_ext
->blk_status_reg_mask
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xa);
365 DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext
->feature_support
, pri_ext
->suspend_cmd_support
, pri_ext
->blk_status_reg_mask
);
367 pri_ext
->vcc_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xc);
368 pri_ext
->vpp_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xd);
370 DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
371 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
372 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
374 pri_ext
->num_protection_fields
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xe);
375 if (pri_ext
->num_protection_fields
!= 1)
377 WARNING("expected one protection register field, but found %i", pri_ext
->num_protection_fields
);
380 pri_ext
->prot_reg_addr
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xf);
381 pri_ext
->fact_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x11);
382 pri_ext
->user_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x12);
384 DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
389 int cfi_read_spansion_pri_ext(flash_bank_t
*bank
)
391 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
392 cfi_spansion_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_spansion_pri_ext_t
));
393 target_t
*target
= bank
->target
;
396 cfi_info
->pri_ext
= pri_ext
;
398 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
399 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
400 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
402 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
404 cfi_command(bank
, 0xf0, command
);
405 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
406 return ERROR_FLASH_BANK_INVALID
;
409 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
410 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
412 DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
414 pri_ext
->SiliconRevision
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
415 pri_ext
->EraseSuspend
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
416 pri_ext
->BlkProt
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
417 pri_ext
->TmpBlkUnprotect
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
418 pri_ext
->BlkProtUnprot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
419 pri_ext
->SimultaneousOps
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 10);
420 pri_ext
->BurstMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 11);
421 pri_ext
->PageMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 12);
422 pri_ext
->VppMin
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 13);
423 pri_ext
->VppMax
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 14);
424 pri_ext
->TopBottom
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 15);
426 DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext
->SiliconRevision
,
427 pri_ext
->EraseSuspend
, pri_ext
->BlkProt
);
429 DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext
->TmpBlkUnprotect
,
430 pri_ext
->BlkProtUnprot
, pri_ext
->SimultaneousOps
);
432 DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext
->BurstMode
, pri_ext
->PageMode
);
435 DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
436 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
437 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
439 DEBUG("WP# protection 0x%x", pri_ext
->TopBottom
);
441 /* default values for implementation specific workarounds */
442 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
443 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
444 pri_ext
->_reversed_geometry
= 0;
449 int cfi_read_atmel_pri_ext(flash_bank_t
*bank
)
451 cfi_atmel_pri_ext_t atmel_pri_ext
;
452 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
453 cfi_spansion_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_spansion_pri_ext_t
));
454 target_t
*target
= bank
->target
;
457 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
458 * but a different primary extended query table.
459 * We read the atmel table, and prepare a valid AMD/Spansion query table.
462 memset(pri_ext
, 0, sizeof(cfi_spansion_pri_ext_t
));
464 cfi_info
->pri_ext
= pri_ext
;
466 atmel_pri_ext
.pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
467 atmel_pri_ext
.pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
468 atmel_pri_ext
.pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
470 if ((atmel_pri_ext
.pri
[0] != 'P') || (atmel_pri_ext
.pri
[1] != 'R') || (atmel_pri_ext
.pri
[2] != 'I'))
472 cfi_command(bank
, 0xf0, command
);
473 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
474 return ERROR_FLASH_BANK_INVALID
;
477 pri_ext
->pri
[0] = atmel_pri_ext
.pri
[0];
478 pri_ext
->pri
[1] = atmel_pri_ext
.pri
[1];
479 pri_ext
->pri
[2] = atmel_pri_ext
.pri
[2];
481 atmel_pri_ext
.major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
482 atmel_pri_ext
.minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
484 DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext
.pri
[0], atmel_pri_ext
.pri
[1], atmel_pri_ext
.pri
[2], atmel_pri_ext
.major_version
, atmel_pri_ext
.minor_version
);
486 pri_ext
->major_version
= atmel_pri_ext
.major_version
;
487 pri_ext
->minor_version
= atmel_pri_ext
.minor_version
;
489 atmel_pri_ext
.features
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
490 atmel_pri_ext
.bottom_boot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
491 atmel_pri_ext
.burst_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
492 atmel_pri_ext
.page_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
494 DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
495 atmel_pri_ext
.features
, atmel_pri_ext
.bottom_boot
, atmel_pri_ext
.burst_mode
, atmel_pri_ext
.page_mode
);
497 if (atmel_pri_ext
.features
& 0x02)
498 pri_ext
->EraseSuspend
= 2;
500 if (atmel_pri_ext
.bottom_boot
)
501 pri_ext
->TopBottom
= 2;
503 pri_ext
->TopBottom
= 3;
505 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
506 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
511 int cfi_read_0002_pri_ext(flash_bank_t
*bank
)
513 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
515 if (cfi_info
->manufacturer
== CFI_MFR_ATMEL
)
517 return cfi_read_atmel_pri_ext(bank
);
521 return cfi_read_spansion_pri_ext(bank
);
525 int cfi_spansion_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
528 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
529 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
531 printed
= snprintf(buf
, buf_size
, "\nSpansion primary algorithm extend information:\n");
535 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0],
536 pri_ext
->pri
[1], pri_ext
->pri
[2],
537 pri_ext
->major_version
, pri_ext
->minor_version
);
541 printed
= snprintf(buf
, buf_size
, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
542 (pri_ext
->SiliconRevision
) >> 2,
543 (pri_ext
->SiliconRevision
) & 0x03);
547 printed
= snprintf(buf
, buf_size
, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
548 pri_ext
->EraseSuspend
,
553 printed
= snprintf(buf
, buf_size
, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
554 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
555 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
560 int cfi_intel_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
563 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
564 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
566 printed
= snprintf(buf
, buf_size
, "\nintel primary algorithm extend information:\n");
570 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
574 printed
= snprintf(buf
, buf_size
, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext
->feature_support
, pri_ext
->suspend_cmd_support
, pri_ext
->blk_status_reg_mask
);
578 printed
= snprintf(buf
, buf_size
, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
579 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
580 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
584 printed
= snprintf(buf
, buf_size
, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
589 int cfi_register_commands(struct command_context_s
*cmd_ctx
)
591 /*command_t *cfi_cmd = */register_command(cmd_ctx
, NULL
, "cfi", NULL
, COMMAND_ANY
, NULL
);
593 register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
594 "print part id of cfi flash bank <num>");
599 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
601 int cfi_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
)
603 cfi_flash_bank_t
*cfi_info
;
608 WARNING("incomplete flash_bank cfi configuration");
609 return ERROR_FLASH_BANK_INVALID
;
612 if ((strtoul(args
[4], NULL
, 0) > CFI_MAX_CHIP_WIDTH
)
613 || (strtoul(args
[3], NULL
, 0) > CFI_MAX_BUS_WIDTH
))
615 ERROR("chip and bus width have to specified in byte");
616 return ERROR_FLASH_BANK_INVALID
;
619 cfi_info
= malloc(sizeof(cfi_flash_bank_t
));
620 bank
->driver_priv
= cfi_info
;
622 cfi_info
->write_algorithm
= NULL
;
623 cfi_info
->erase_check_algorithm
= NULL
;
625 cfi_info
->x16_as_x8
= 0;
626 cfi_info
->jedec_probe
= 0;
627 cfi_info
->not_cfi
= 0;
629 for (i
= 6; i
< argc
; i
++)
631 if (strcmp(args
[i
], "x16_as_x8") == 0)
633 cfi_info
->x16_as_x8
= 1;
635 else if (strcmp(args
[i
], "jedec_probe") == 0)
637 cfi_info
->jedec_probe
= 1;
641 cfi_info
->write_algorithm
= NULL
;
643 /* bank wasn't probed yet */
644 cfi_info
->qry
[0] = -1;
649 int cfi_intel_erase(struct flash_bank_s
*bank
, int first
, int last
)
651 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
652 target_t
*target
= bank
->target
;
656 cfi_intel_clear_status_register(bank
);
658 for (i
= first
; i
<= last
; i
++)
660 cfi_command(bank
, 0x20, command
);
661 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
663 cfi_command(bank
, 0xd0, command
);
664 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
666 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == 0x80)
667 bank
->sectors
[i
].is_erased
= 1;
670 cfi_command(bank
, 0xff, command
);
671 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
673 ERROR("couldn't erase block %i of flash bank at base 0x%x", i
, bank
->base
);
674 return ERROR_FLASH_OPERATION_FAILED
;
678 cfi_command(bank
, 0xff, command
);
679 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
684 int cfi_spansion_erase(struct flash_bank_s
*bank
, int first
, int last
)
686 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
687 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
688 target_t
*target
= bank
->target
;
692 for (i
= first
; i
<= last
; i
++)
694 cfi_command(bank
, 0xaa, command
);
695 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
697 cfi_command(bank
, 0x55, command
);
698 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
);
700 cfi_command(bank
, 0x80, command
);
701 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
703 cfi_command(bank
, 0xaa, command
);
704 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
706 cfi_command(bank
, 0x55, command
);
707 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
);
709 cfi_command(bank
, 0x30, command
);
710 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
712 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == ERROR_OK
)
713 bank
->sectors
[i
].is_erased
= 1;
716 cfi_command(bank
, 0xf0, command
);
717 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
719 ERROR("couldn't erase block %i of flash bank at base 0x%x", i
, bank
->base
);
720 return ERROR_FLASH_OPERATION_FAILED
;
724 cfi_command(bank
, 0xf0, command
);
725 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
730 int cfi_erase(struct flash_bank_s
*bank
, int first
, int last
)
732 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
734 if (bank
->target
->state
!= TARGET_HALTED
)
736 return ERROR_TARGET_NOT_HALTED
;
739 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
741 return ERROR_FLASH_SECTOR_INVALID
;
744 if (cfi_info
->qry
[0] != 'Q')
745 return ERROR_FLASH_BANK_NOT_PROBED
;
747 switch(cfi_info
->pri_id
)
751 return cfi_intel_erase(bank
, first
, last
);
754 return cfi_spansion_erase(bank
, first
, last
);
757 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
764 int cfi_intel_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
766 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
767 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
768 target_t
*target
= bank
->target
;
773 /* if the device supports neither legacy lock/unlock (bit 3) nor
774 * instant individual block locking (bit 5).
776 if (!(pri_ext
->feature_support
& 0x28))
777 return ERROR_FLASH_OPERATION_FAILED
;
779 cfi_intel_clear_status_register(bank
);
781 for (i
= first
; i
<= last
; i
++)
783 cfi_command(bank
, 0x60, command
);
784 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
785 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
788 cfi_command(bank
, 0x01, command
);
789 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
790 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
791 bank
->sectors
[i
].is_protected
= 1;
795 cfi_command(bank
, 0xd0, command
);
796 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
797 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
798 bank
->sectors
[i
].is_protected
= 0;
801 /* instant individual block locking doesn't require reading of the status register */
802 if (!(pri_ext
->feature_support
& 0x20))
804 /* Clear lock bits operation may take up to 1.4s */
805 cfi_intel_wait_status_busy(bank
, 1400);
810 /* read block lock bit, to verify status */
811 cfi_command(bank
, 0x90, command
);
812 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
);
813 block_status
= cfi_get_u8(bank
, i
, 0x2);
815 if ((block_status
& 0x1) != set
)
817 ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set
, block_status
);
818 cfi_command(bank
, 0x70, command
);
819 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
);
820 cfi_intel_wait_status_busy(bank
, 10);
823 return ERROR_FLASH_OPERATION_FAILED
;
833 /* if the device doesn't support individual block lock bits set/clear,
834 * all blocks have been unlocked in parallel, so we set those that should be protected
836 if ((!set
) && (!(pri_ext
->feature_support
& 0x20)))
838 for (i
= 0; i
< bank
->num_sectors
; i
++)
840 if (bank
->sectors
[i
].is_protected
== 1)
842 cfi_intel_clear_status_register(bank
);
844 cfi_command(bank
, 0x60, command
);
845 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
847 cfi_command(bank
, 0x01, command
);
848 target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
);
850 cfi_intel_wait_status_busy(bank
, 100);
855 cfi_command(bank
, 0xff, command
);
856 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
861 int cfi_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
863 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
865 if (bank
->target
->state
!= TARGET_HALTED
)
867 return ERROR_TARGET_NOT_HALTED
;
870 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
872 return ERROR_FLASH_SECTOR_INVALID
;
875 if (cfi_info
->qry
[0] != 'Q')
876 return ERROR_FLASH_BANK_NOT_PROBED
;
878 switch(cfi_info
->pri_id
)
882 cfi_intel_protect(bank
, set
, first
, last
);
885 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
892 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
893 static void cfi_add_byte(struct flash_bank_s
*bank
, u8
*word
, u8 byte
)
895 target_t
*target
= bank
->target
;
900 // The data to flash must not be changed in endian! We write a bytestrem in
901 // target byte order already. Only the control and status byte lane of the flash
902 // WSM is interpreted by the CPU in different ways, when read a u16 or u32
903 // word (data seems to be in the upper or lower byte lane for u16 accesses).
905 //if (target->endianness == TARGET_LITTLE_ENDIAN)
908 for (i
= 0; i
< bank
->bus_width
- 1; i
++)
909 word
[i
] = word
[i
+ 1];
910 word
[bank
->bus_width
- 1] = byte
;
915 // for (i = bank->bus_width - 1; i > 0; i--)
916 // word[i] = word[i - 1];
921 /* Convert code image to target endian */
922 /* FIXME create general block conversion fcts in target.c?) */ static
923 void cfi_fix_code_endian(target_t
*target
, u32
*dest
, const u32
*src
, u32 count
)
926 for (i
=0; i
< count
; i
++)
928 target_buffer_set_u32(target
, (u8
*)dest
, *src
);
934 int cfi_intel_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 address
, u32 count
)
936 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
937 target_t
*target
= bank
->target
;
938 reg_param_t reg_params
[7];
939 armv4_5_algorithm_t armv4_5_info
;
940 working_area_t
*source
;
941 u32 buffer_size
= 32768;
942 u8 write_command_buf
[CFI_MAX_BUS_WIDTH
];
943 u8 busy_pattern_buf
[CFI_MAX_BUS_WIDTH
];
944 u8 error_pattern_buf
[CFI_MAX_BUS_WIDTH
];
945 u32 write_command_val
, busy_pattern_val
, error_pattern_val
;
947 /* algorithm register usage:
948 * r0: source address (in RAM)
949 * r1: target address (in Flash)
951 * r3: flash write command
952 * r4: status byte (returned to host)
953 * r5: busy test pattern
954 * r6: error test pattern
957 static const u32 word_32_code
[] = {
958 0xe4904004, /* loop: ldr r4, [r0], #4 */
959 0xe5813000, /* str r3, [r1] */
960 0xe5814000, /* str r4, [r1] */
961 0xe5914000, /* busy: ldr r4, [r1] */
962 0xe0047005, /* and r7, r4, r5 */
963 0xe1570005, /* cmp r7, r5 */
964 0x1afffffb, /* bne busy */
965 0xe1140006, /* tst r4, r6 */
966 0x1a000003, /* bne done */
967 0xe2522001, /* subs r2, r2, #1 */
968 0x0a000001, /* beq done */
969 0xe2811004, /* add r1, r1 #4 */
970 0xeafffff2, /* b loop */
971 0xeafffffe /* done: b -2 */
974 static const u32 word_16_code
[] = {
975 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
976 0xe1c130b0, /* strh r3, [r1] */
977 0xe1c140b0, /* strh r4, [r1] */
978 0xe1d140b0, /* busy ldrh r4, [r1] */
979 0xe0047005, /* and r7, r4, r5 */
980 0xe1570005, /* cmp r7, r5 */
981 0x1afffffb, /* bne busy */
982 0xe1140006, /* tst r4, r6 */
983 0x1a000003, /* bne done */
984 0xe2522001, /* subs r2, r2, #1 */
985 0x0a000001, /* beq done */
986 0xe2811002, /* add r1, r1 #2 */
987 0xeafffff2, /* b loop */
988 0xeafffffe /* done: b -2 */
991 static const u32 word_8_code
[] = {
992 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
993 0xe5c13000, /* strb r3, [r1] */
994 0xe5c14000, /* strb r4, [r1] */
995 0xe5d14000, /* busy ldrb r4, [r1] */
996 0xe0047005, /* and r7, r4, r5 */
997 0xe1570005, /* cmp r7, r5 */
998 0x1afffffb, /* bne busy */
999 0xe1140006, /* tst r4, r6 */
1000 0x1a000003, /* bne done */
1001 0xe2522001, /* subs r2, r2, #1 */
1002 0x0a000001, /* beq done */
1003 0xe2811001, /* add r1, r1 #1 */
1004 0xeafffff2, /* b loop */
1005 0xeafffffe /* done: b -2 */
1007 u32 target_code
[CFI_MAX_INTEL_CODESIZE
];
1008 const u32
*target_code_src
;
1009 int target_code_size
;
1010 int retval
= ERROR_OK
;
1013 cfi_intel_clear_status_register(bank
);
1015 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
1016 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
1017 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
1019 /* flash write code */
1020 if (!cfi_info
->write_algorithm
)
1022 /* prepare algorithm code for target endian */
1023 switch (bank
->bus_width
)
1026 target_code_src
= word_8_code
;
1027 target_code_size
= sizeof(word_8_code
);
1030 target_code_src
= word_16_code
;
1031 target_code_size
= sizeof(word_16_code
);
1034 target_code_src
= word_32_code
;
1035 target_code_size
= sizeof(word_32_code
);
1038 ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1039 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1041 if ( target_code_size
> sizeof(target_code
) )
1043 WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1044 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1046 cfi_fix_code_endian(target
, target_code
, target_code_src
, target_code_size
);
1048 /* Get memory for block write handler */
1049 retval
= target_alloc_working_area(target
, target_code_size
, &cfi_info
->write_algorithm
);
1050 if (retval
!= ERROR_OK
)
1052 WARNING("No working area available, can't do block memory writes");
1053 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1056 /* write algorithm code to working area */
1057 retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
, target_code_size
, (u8
*)target_code
);
1058 if (retval
!= ERROR_OK
)
1060 ERROR("Unable to write block write code to target");
1065 /* Get a workspace buffer for the data to flash starting with 32k size.
1066 Half size until buffer would be smaller 256 Bytem then fail back */
1067 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1068 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
1071 if (buffer_size
<= 256)
1073 WARNING("no large enough working area available, can't do block memory writes");
1074 retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1079 /* setup algo registers */
1080 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1081 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1082 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1083 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1084 init_reg_param(®_params
[4], "r4", 32, PARAM_IN
);
1085 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
);
1086 init_reg_param(®_params
[6], "r6", 32, PARAM_OUT
);
1088 /* prepare command and status register patterns */
1089 cfi_command(bank
, 0x40, write_command_buf
);
1090 cfi_command(bank
, 0x80, busy_pattern_buf
);
1091 cfi_command(bank
, 0x7e, error_pattern_buf
);
1093 switch (bank
->bus_width
)
1096 write_command_val
= write_command_buf
[0];
1097 busy_pattern_val
= busy_pattern_buf
[0];
1098 error_pattern_val
= error_pattern_buf
[0];
1101 write_command_val
= target_buffer_get_u16(target
, write_command_buf
);
1102 busy_pattern_val
= target_buffer_get_u16(target
, busy_pattern_buf
);
1103 error_pattern_val
= target_buffer_get_u16(target
, error_pattern_buf
);
1106 write_command_val
= target_buffer_get_u32(target
, write_command_buf
);
1107 busy_pattern_val
= target_buffer_get_u32(target
, busy_pattern_buf
);
1108 error_pattern_val
= target_buffer_get_u32(target
, error_pattern_buf
);
1111 ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1112 retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1116 INFO("Using target buffer at 0x%08x and of size 0x%04x", source
->address
, buffer_size
);
1118 /* Programming main loop */
1121 u32 thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1124 target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1126 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1127 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1128 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1130 buf_set_u32(reg_params
[3].value
, 0, 32, write_command_val
);
1131 buf_set_u32(reg_params
[5].value
, 0, 32, busy_pattern_val
);
1132 buf_set_u32(reg_params
[6].value
, 0, 32, error_pattern_val
);
1134 INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count
, address
);
1136 /* Execute algorithm, assume breakpoint for last instruction */
1137 retval
= target
->type
->run_algorithm(target
, 0, NULL
, 7, reg_params
,
1138 cfi_info
->write_algorithm
->address
,
1139 cfi_info
->write_algorithm
->address
+ target_code_size
- sizeof(u32
),
1140 10000, /* 10s should be enough for max. 32k of data */
1143 /* On failure try a fall back to direct word writes */
1144 if (retval
!= ERROR_OK
)
1146 cfi_intel_clear_status_register(bank
);
1147 ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1148 retval
= ERROR_FLASH_OPERATION_FAILED
;
1149 //retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1150 // FIXME To allow fall back or recovery, we must save the actual status
1151 // somewhere, so that a higher level code can start recovery.
1155 /* Check return value from algo code */
1156 wsm_error
= buf_get_u32(reg_params
[4].value
, 0, 32) & error_pattern_val
;
1159 /* read status register (outputs debug inforation) */
1160 cfi_intel_wait_status_busy(bank
, 100);
1161 cfi_intel_clear_status_register(bank
);
1162 retval
= ERROR_FLASH_OPERATION_FAILED
;
1166 buffer
+= thisrun_count
;
1167 address
+= thisrun_count
;
1168 count
-= thisrun_count
;
1171 /* free up resources */
1174 target_free_working_area(target
, source
);
1176 if (cfi_info
->write_algorithm
)
1178 target_free_working_area(target
, cfi_info
->write_algorithm
);
1179 cfi_info
->write_algorithm
= NULL
;
1182 destroy_reg_param(®_params
[0]);
1183 destroy_reg_param(®_params
[1]);
1184 destroy_reg_param(®_params
[2]);
1185 destroy_reg_param(®_params
[3]);
1186 destroy_reg_param(®_params
[4]);
1187 destroy_reg_param(®_params
[5]);
1188 destroy_reg_param(®_params
[6]);
1193 int cfi_spansion_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 address
, u32 count
)
1195 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1196 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1197 target_t
*target
= bank
->target
;
1198 reg_param_t reg_params
[10];
1199 armv4_5_algorithm_t armv4_5_info
;
1200 working_area_t
*source
;
1201 u32 buffer_size
= 32768;
1202 u8 write_command
[CFI_MAX_BUS_WIDTH
];
1206 int exit_code
= ERROR_OK
;
1208 /* input parameters - */
1209 /* R0 = source address */
1210 /* R1 = destination address */
1211 /* R2 = number of writes */
1212 /* R3 = flash write command */
1213 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1214 /* output parameters - */
1215 /* R5 = 0x80 ok 0x00 bad */
1216 /* temp registers - */
1217 /* R6 = value read from flash to test status */
1218 /* R7 = holding register */
1219 /* unlock registers - */
1220 /* R8 = unlock1_addr */
1221 /* R9 = unlock1_cmd */
1222 /* R10 = unlock2_addr */
1223 /* R11 = unlock2_cmd */
1225 u32 word_32_code
[] = {
1226 /* 00008100 <sp_32_code>: */
1227 0xe4905004, /* ldr r5, [r0], #4 */
1228 0xe5889000, /* str r9, [r8] */
1229 0xe58ab000, /* str r11, [r10] */
1230 0xe5883000, /* str r3, [r8] */
1231 0xe5815000, /* str r5, [r1] */
1232 0xe1a00000, /* nop */
1234 /* 00008110 <sp_32_busy>: */
1235 0xe5916000, /* ldr r6, [r1] */
1236 0xe0257006, /* eor r7, r5, r6 */
1237 0xe0147007, /* ands r7, r4, r7 */
1238 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1239 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1240 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1241 0xe5916000, /* ldr r6, [r1] */
1242 0xe0257006, /* eor r7, r5, r6 */
1243 0xe0147007, /* ands r7, r4, r7 */
1244 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1245 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1246 0x1a000004, /* bne 8154 <sp_32_done> */
1248 /* 00008140 <sp_32_cont>: */
1249 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1250 0x03a05080, /* moveq r5, #128 ; 0x80 */
1251 0x0a000001, /* beq 8154 <sp_32_done> */
1252 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1253 0xeaffffe8, /* b 8100 <sp_32_code> */
1255 /* 00008154 <sp_32_done>: */
1256 0xeafffffe /* b 8154 <sp_32_done> */
1259 u32 word_16_code
[] = {
1260 /* 00008158 <sp_16_code>: */
1261 0xe0d050b2, /* ldrh r5, [r0], #2 */
1262 0xe1c890b0, /* strh r9, [r8] */
1263 0xe1cab0b0, /* strh r11, [r10] */
1264 0xe1c830b0, /* strh r3, [r8] */
1265 0xe1c150b0, /* strh r5, [r1] */
1266 0xe1a00000, /* nop (mov r0,r0) */
1268 /* 00008168 <sp_16_busy>: */
1269 0xe1d160b0, /* ldrh r6, [r1] */
1270 0xe0257006, /* eor r7, r5, r6 */
1271 0xe0147007, /* ands r7, r4, r7 */
1272 0x0a000007, /* beq 8198 <sp_16_cont> */
1273 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1274 0x0afffff9, /* beq 8168 <sp_16_busy> */
1275 0xe1d160b0, /* ldrh r6, [r1] */
1276 0xe0257006, /* eor r7, r5, r6 */
1277 0xe0147007, /* ands r7, r4, r7 */
1278 0x0a000001, /* beq 8198 <sp_16_cont> */
1279 0xe3a05000, /* mov r5, #0 ; 0x0 */
1280 0x1a000004, /* bne 81ac <sp_16_done> */
1282 /* 00008198 <sp_16_cont>: */
1283 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1284 0x03a05080, /* moveq r5, #128 ; 0x80 */
1285 0x0a000001, /* beq 81ac <sp_16_done> */
1286 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1287 0xeaffffe8, /* b 8158 <sp_16_code> */
1289 /* 000081ac <sp_16_done>: */
1290 0xeafffffe /* b 81ac <sp_16_done> */
1293 u32 word_8_code
[] = {
1294 /* 000081b0 <sp_16_code_end>: */
1295 0xe4d05001, /* ldrb r5, [r0], #1 */
1296 0xe5c89000, /* strb r9, [r8] */
1297 0xe5cab000, /* strb r11, [r10] */
1298 0xe5c83000, /* strb r3, [r8] */
1299 0xe5c15000, /* strb r5, [r1] */
1300 0xe1a00000, /* nop (mov r0,r0) */
1302 /* 000081c0 <sp_8_busy>: */
1303 0xe5d16000, /* ldrb r6, [r1] */
1304 0xe0257006, /* eor r7, r5, r6 */
1305 0xe0147007, /* ands r7, r4, r7 */
1306 0x0a000007, /* beq 81f0 <sp_8_cont> */
1307 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1308 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1309 0xe5d16000, /* ldrb r6, [r1] */
1310 0xe0257006, /* eor r7, r5, r6 */
1311 0xe0147007, /* ands r7, r4, r7 */
1312 0x0a000001, /* beq 81f0 <sp_8_cont> */
1313 0xe3a05000, /* mov r5, #0 ; 0x0 */
1314 0x1a000004, /* bne 8204 <sp_8_done> */
1316 /* 000081f0 <sp_8_cont>: */
1317 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1318 0x03a05080, /* moveq r5, #128 ; 0x80 */
1319 0x0a000001, /* beq 8204 <sp_8_done> */
1320 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1321 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1323 /* 00008204 <sp_8_done>: */
1324 0xeafffffe /* b 8204 <sp_8_done> */
1327 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
1328 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
1329 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
1331 /* flash write code */
1332 if (!cfi_info
->write_algorithm
)
1336 /* convert bus-width dependent algorithm code to correct endiannes */
1337 if (bank
->bus_width
== 1)
1339 code_p
= malloc(24 * 4);
1341 for (i
= 0; i
< 24; i
++)
1342 target_buffer_set_u32(target
, code_p
+ (i
*4), word_8_code
[i
]);
1344 else if (bank
->bus_width
== 2)
1346 code_p
= malloc(24 * 4);
1348 for (i
= 0; i
< 24; i
++)
1349 target_buffer_set_u32(target
, code_p
+ (i
*4), word_16_code
[i
]);
1351 else if (bank
->bus_width
== 4)
1353 code_p
= malloc(24 * 4);
1355 for (i
= 0; i
< 24; i
++)
1356 target_buffer_set_u32(target
, code_p
+ (i
*4), word_32_code
[i
]);
1360 return ERROR_FLASH_OPERATION_FAILED
;
1363 /* allocate working area */
1364 if (target_alloc_working_area(target
, 24 * 4,
1365 &cfi_info
->write_algorithm
) != ERROR_OK
)
1367 WARNING("no working area available, can't do block memory writes");
1368 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1371 /* write algorithm code to working area */
1372 target_write_buffer(target
, cfi_info
->write_algorithm
->address
, 24 * 4, code_p
);
1377 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
1380 if (buffer_size
<= 256)
1382 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1383 if (cfi_info
->write_algorithm
)
1384 target_free_working_area(target
, cfi_info
->write_algorithm
);
1386 WARNING("not enough working area available, can't do block memory writes");
1387 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1391 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1392 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1393 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1394 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1395 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
);
1396 init_reg_param(®_params
[5], "r5", 32, PARAM_IN
);
1397 init_reg_param(®_params
[6], "r8", 32, PARAM_OUT
);
1398 init_reg_param(®_params
[7], "r9", 32, PARAM_OUT
);
1399 init_reg_param(®_params
[8], "r10", 32, PARAM_OUT
);
1400 init_reg_param(®_params
[9], "r11", 32, PARAM_OUT
);
1404 u32 thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1406 target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1408 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1409 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1410 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1411 cfi_command(bank
, 0xA0, write_command
);
1412 buf_set_u32(reg_params
[3].value
, 0, 32, buf_get_u32(write_command
, 0, 32));
1413 cfi_command(bank
, 0x80, write_command
);
1414 buf_set_u32(reg_params
[4].value
, 0, 32, buf_get_u32(write_command
, 0, 32));
1415 buf_set_u32(reg_params
[6].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock1
));
1416 buf_set_u32(reg_params
[7].value
, 0, 32, 0xaa);
1417 buf_set_u32(reg_params
[8].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock2
));
1418 buf_set_u32(reg_params
[9].value
, 0, 32, 0x55);
1420 retval
= target
->type
->run_algorithm(target
, 0, NULL
, 10, reg_params
,
1421 cfi_info
->write_algorithm
->address
,
1422 cfi_info
->write_algorithm
->address
+ ((24 * 4) - 4),
1423 10000, &armv4_5_info
);
1425 status
= buf_get_u32(reg_params
[5].value
, 0, 32);
1427 if ((retval
!= ERROR_OK
) || status
!= 0x80)
1429 DEBUG("status: 0x%x", status
);
1430 exit_code
= ERROR_FLASH_OPERATION_FAILED
;
1434 buffer
+= thisrun_count
;
1435 address
+= thisrun_count
;
1436 count
-= thisrun_count
;
1439 target_free_working_area(target
, source
);
1441 destroy_reg_param(®_params
[0]);
1442 destroy_reg_param(®_params
[1]);
1443 destroy_reg_param(®_params
[2]);
1444 destroy_reg_param(®_params
[3]);
1445 destroy_reg_param(®_params
[4]);
1446 destroy_reg_param(®_params
[5]);
1447 destroy_reg_param(®_params
[6]);
1448 destroy_reg_param(®_params
[7]);
1449 destroy_reg_param(®_params
[8]);
1450 destroy_reg_param(®_params
[9]);
1455 int cfi_intel_write_word(struct flash_bank_s
*bank
, u8
*word
, u32 address
)
1457 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1458 target_t
*target
= bank
->target
;
1461 cfi_intel_clear_status_register(bank
);
1462 cfi_command(bank
, 0x40, command
);
1463 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
);
1465 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, word
);
1467 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != 0x80)
1469 cfi_command(bank
, 0xff, command
);
1470 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1472 ERROR("couldn't write word at base 0x%x, address %x", bank
->base
, address
);
1473 return ERROR_FLASH_OPERATION_FAILED
;
1479 int cfi_intel_write_words(struct flash_bank_s
*bank
, u8
*word
, u32 wordcount
, u32 address
)
1481 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1482 target_t
*target
= bank
->target
;
1486 /* Calculate buffer size and boundary mask */
1487 u32 buffersize
= 1UL << cfi_info
->max_buf_write_size
;
1488 u32 buffermask
= buffersize
-1;
1491 /* Check for valid range */
1492 if (address
& buffermask
)
1494 ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank
->base
, address
, cfi_info
->max_buf_write_size
);
1495 return ERROR_FLASH_OPERATION_FAILED
;
1497 switch(bank
->chip_width
)
1499 case 4 : bufferwsize
= buffersize
/ 4; break;
1500 case 2 : bufferwsize
= buffersize
/ 2; break;
1501 case 1 : bufferwsize
= buffersize
; break;
1503 ERROR("Unsupported chip width %d", bank
->chip_width
);
1504 return ERROR_FLASH_OPERATION_FAILED
;
1507 /* Check for valid size */
1508 if (wordcount
> bufferwsize
)
1510 ERROR("Number of data words %d exceeds available buffersize %d", wordcount
, buffersize
);
1511 return ERROR_FLASH_OPERATION_FAILED
;
1514 /* Write to flash buffer */
1515 cfi_intel_clear_status_register(bank
);
1517 /* Initiate buffer operation _*/
1518 cfi_command(bank
, 0xE8, command
);
1519 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
);
1520 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
)) != 0x80)
1522 cfi_command(bank
, 0xff, command
);
1523 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1525 ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank
->base
, address
);
1526 return ERROR_FLASH_OPERATION_FAILED
;
1529 /* Write buffer wordcount-1 and data words */
1530 cfi_command(bank
, bufferwsize
-1, command
);
1531 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
);
1533 target
->type
->write_memory(target
, address
, bank
->bus_width
, bufferwsize
, word
);
1535 /* Commit write operation */
1536 cfi_command(bank
, 0xd0, command
);
1537 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
);
1538 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
)) != 0x80)
1540 cfi_command(bank
, 0xff, command
);
1541 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1543 ERROR("Buffer write at base 0x%x, address %x failed.", bank
->base
, address
);
1544 return ERROR_FLASH_OPERATION_FAILED
;
1550 int cfi_spansion_write_word(struct flash_bank_s
*bank
, u8
*word
, u32 address
)
1552 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1553 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1554 target_t
*target
= bank
->target
;
1557 cfi_command(bank
, 0xaa, command
);
1558 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
1560 cfi_command(bank
, 0x55, command
);
1561 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
);
1563 cfi_command(bank
, 0xa0, command
);
1564 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
1566 target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, word
);
1568 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1570 cfi_command(bank
, 0xf0, command
);
1571 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1573 ERROR("couldn't write word at base 0x%x, address %x", bank
->base
, address
);
1574 return ERROR_FLASH_OPERATION_FAILED
;
1580 int cfi_write_word(struct flash_bank_s
*bank
, u8
*word
, u32 address
)
1582 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1584 switch(cfi_info
->pri_id
)
1588 return cfi_intel_write_word(bank
, word
, address
);
1591 return cfi_spansion_write_word(bank
, word
, address
);
1594 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1598 return ERROR_FLASH_OPERATION_FAILED
;
1601 int cfi_write_words(struct flash_bank_s
*bank
, u8
*word
, u32 wordcount
, u32 address
)
1603 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1605 switch(cfi_info
->pri_id
)
1609 return cfi_intel_write_words(bank
, word
, wordcount
, address
);
1612 //return cfi_spansion_write_words(bank, word, address);
1613 ERROR("cfi primary command set %i unimplemented - FIXME", cfi_info
->pri_id
);
1616 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1620 return ERROR_FLASH_OPERATION_FAILED
;
1623 int cfi_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
1625 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1626 target_t
*target
= bank
->target
;
1627 u32 address
= bank
->base
+ offset
; /* address of first byte to be programmed */
1628 u32 write_p
, copy_p
;
1629 int align
; /* number of unaligned bytes */
1630 int blk_count
; /* number of bus_width bytes for block copy */
1631 u8 current_word
[CFI_MAX_BUS_WIDTH
* 4]; /* word (bus_width size) currently being programmed */
1635 if (bank
->target
->state
!= TARGET_HALTED
)
1637 return ERROR_TARGET_NOT_HALTED
;
1640 if (offset
+ count
> bank
->size
)
1641 return ERROR_FLASH_DST_OUT_OF_BANK
;
1643 if (cfi_info
->qry
[0] != 'Q')
1644 return ERROR_FLASH_BANK_NOT_PROBED
;
1646 /* start at the first byte of the first word (bus_width size) */
1647 write_p
= address
& ~(bank
->bus_width
- 1);
1648 if ((align
= address
- write_p
) != 0)
1650 INFO("Fixup %d unaligned head bytes", align
);
1652 for (i
= 0; i
< bank
->bus_width
; i
++)
1653 current_word
[i
] = 0;
1656 /* copy bytes before the first write address */
1657 for (i
= 0; i
< align
; ++i
, ++copy_p
)
1660 target
->type
->read_memory(target
, copy_p
, 1, 1, &byte
);
1661 cfi_add_byte(bank
, current_word
, byte
);
1664 /* add bytes from the buffer */
1665 for (; (i
< bank
->bus_width
) && (count
> 0); i
++)
1667 cfi_add_byte(bank
, current_word
, *buffer
++);
1672 /* if the buffer is already finished, copy bytes after the last write address */
1673 for (; (count
== 0) && (i
< bank
->bus_width
); ++i
, ++copy_p
)
1676 target
->type
->read_memory(target
, copy_p
, 1, 1, &byte
);
1677 cfi_add_byte(bank
, current_word
, byte
);
1680 retval
= cfi_write_word(bank
, current_word
, write_p
);
1681 if (retval
!= ERROR_OK
)
1686 /* handle blocks of bus_size aligned bytes */
1687 blk_count
= count
& ~(bank
->bus_width
- 1); /* round down, leave tail bytes */
1688 switch(cfi_info
->pri_id
)
1690 /* try block writes (fails without working area) */
1693 retval
= cfi_intel_write_block(bank
, buffer
, write_p
, blk_count
);
1696 retval
= cfi_spansion_write_block(bank
, buffer
, write_p
, blk_count
);
1699 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1700 retval
= ERROR_FLASH_OPERATION_FAILED
;
1703 if (retval
== ERROR_OK
)
1705 /* Increment pointers and decrease count on succesful block write */
1706 buffer
+= blk_count
;
1707 write_p
+= blk_count
;
1712 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
1714 u32 buffersize
= 1UL << cfi_info
->max_buf_write_size
;
1715 u32 buffermask
= buffersize
-1;
1718 switch(bank
->chip_width
)
1720 case 4 : bufferwsize
= buffersize
/ 4; break;
1721 case 2 : bufferwsize
= buffersize
/ 2; break;
1722 case 1 : bufferwsize
= buffersize
; break;
1724 ERROR("Unsupported chip width %d", bank
->chip_width
);
1725 return ERROR_FLASH_OPERATION_FAILED
;
1728 /* fall back to memory writes */
1729 while (count
> bank
->bus_width
)
1731 if ((write_p
& 0xff) == 0)
1733 INFO("Programming at %08x, count %08x bytes remaining", write_p
, count
);
1735 if ((count
> bufferwsize
) && !(write_p
& buffermask
))
1737 retval
= cfi_write_words(bank
, buffer
, bufferwsize
, write_p
);
1738 if (retval
!= ERROR_OK
)
1741 buffer
+= buffersize
;
1742 write_p
+= buffersize
;
1743 count
-= buffersize
;
1747 for (i
= 0; i
< bank
->bus_width
; i
++)
1748 current_word
[i
] = 0;
1750 for (i
= 0; i
< bank
->bus_width
; i
++)
1752 cfi_add_byte(bank
, current_word
, *buffer
++);
1755 retval
= cfi_write_word(bank
, current_word
, write_p
);
1756 if (retval
!= ERROR_OK
)
1759 write_p
+= bank
->bus_width
;
1760 count
-= bank
->bus_width
;
1768 /* return to read array mode, so we can read from flash again for padding */
1769 cfi_command(bank
, 0xf0, current_word
);
1770 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
1771 cfi_command(bank
, 0xff, current_word
);
1772 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
1774 /* handle unaligned tail bytes */
1777 INFO("Fixup %d unaligned tail bytes", count
);
1780 for (i
= 0; i
< bank
->bus_width
; i
++)
1781 current_word
[i
] = 0;
1783 for (i
= 0; (i
< bank
->bus_width
) && (count
> 0); ++i
, ++copy_p
)
1785 cfi_add_byte(bank
, current_word
, *buffer
++);
1788 for (; i
< bank
->bus_width
; ++i
, ++copy_p
)
1791 target
->type
->read_memory(target
, copy_p
, 1, 1, &byte
);
1792 cfi_add_byte(bank
, current_word
, byte
);
1794 retval
= cfi_write_word(bank
, current_word
, write_p
);
1795 if (retval
!= ERROR_OK
)
1799 /* return to read array mode */
1800 cfi_command(bank
, 0xf0, current_word
);
1801 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
1802 cfi_command(bank
, 0xff, current_word
);
1803 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
1808 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t
*bank
, void *param
)
1810 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1811 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1813 pri_ext
->_reversed_geometry
= 1;
1816 void cfi_fixup_0002_erase_regions(flash_bank_t
*bank
, void *param
)
1819 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1820 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1822 if ((pri_ext
->_reversed_geometry
) || (pri_ext
->TopBottom
== 3))
1824 DEBUG("swapping reversed erase region information on cmdset 0002 device");
1826 for (i
= 0; i
< cfi_info
->num_erase_regions
/ 2; i
++)
1828 int j
= (cfi_info
->num_erase_regions
- 1) - i
;
1831 swap
= cfi_info
->erase_region_info
[i
];
1832 cfi_info
->erase_region_info
[i
] = cfi_info
->erase_region_info
[j
];
1833 cfi_info
->erase_region_info
[j
] = swap
;
1838 void cfi_fixup_0002_unlock_addresses(flash_bank_t
*bank
, void *param
)
1840 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1841 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1842 cfi_unlock_addresses_t
*unlock_addresses
= param
;
1844 pri_ext
->_unlock1
= unlock_addresses
->unlock1
;
1845 pri_ext
->_unlock2
= unlock_addresses
->unlock2
;
1848 int cfi_probe(struct flash_bank_s
*bank
)
1850 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1851 target_t
*target
= bank
->target
;
1853 int num_sectors
= 0;
1857 u32 unlock1
= 0x555;
1858 u32 unlock2
= 0x2aa;
1860 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
1861 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
1863 if (cfi_info
->jedec_probe
)
1869 /* switch to read identifier codes mode ("AUTOSELECT") */
1870 cfi_command(bank
, 0xaa, command
);
1871 target
->type
->write_memory(target
, flash_address(bank
, 0, unlock1
), bank
->bus_width
, 1, command
);
1872 cfi_command(bank
, 0x55, command
);
1873 target
->type
->write_memory(target
, flash_address(bank
, 0, unlock2
), bank
->bus_width
, 1, command
);
1874 cfi_command(bank
, 0x90, command
);
1875 target
->type
->write_memory(target
, flash_address(bank
, 0, unlock1
), bank
->bus_width
, 1, command
);
1877 if (bank
->chip_width
== 1)
1879 u8 manufacturer
, device_id
;
1880 target_read_u8(target
, bank
->base
+ 0x0, &manufacturer
);
1881 target_read_u8(target
, bank
->base
+ 0x1, &device_id
);
1882 cfi_info
->manufacturer
= manufacturer
;
1883 cfi_info
->device_id
= device_id
;
1885 else if (bank
->chip_width
== 2)
1887 target_read_u16(target
, bank
->base
+ 0x0, &cfi_info
->manufacturer
);
1888 target_read_u16(target
, bank
->base
+ 0x2, &cfi_info
->device_id
);
1891 /* switch back to read array mode */
1892 cfi_command(bank
, 0xf0, command
);
1893 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x00), bank
->bus_width
, 1, command
);
1894 cfi_command(bank
, 0xff, command
);
1895 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x00), bank
->bus_width
, 1, command
);
1897 cfi_fixup(bank
, cfi_jedec_fixups
);
1899 /* query only if this is a CFI compatible flash,
1900 * otherwise the relevant info has already been filled in
1902 if (cfi_info
->not_cfi
== 0)
1904 /* enter CFI query mode
1905 * according to JEDEC Standard No. 68.01,
1906 * a single bus sequence with address = 0x55, data = 0x98 should put
1907 * the device into CFI query mode.
1909 * SST flashes clearly violate this, and we will consider them incompatbile for now
1911 cfi_command(bank
, 0x98, command
);
1912 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
);
1914 cfi_info
->qry
[0] = cfi_query_u8(bank
, 0, 0x10);
1915 cfi_info
->qry
[1] = cfi_query_u8(bank
, 0, 0x11);
1916 cfi_info
->qry
[2] = cfi_query_u8(bank
, 0, 0x12);
1918 DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2]);
1920 if ((cfi_info
->qry
[0] != 'Q') || (cfi_info
->qry
[1] != 'R') || (cfi_info
->qry
[2] != 'Y'))
1922 cfi_command(bank
, 0xf0, command
);
1923 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1924 cfi_command(bank
, 0xff, command
);
1925 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
1926 return ERROR_FLASH_BANK_INVALID
;
1929 cfi_info
->pri_id
= cfi_query_u16(bank
, 0, 0x13);
1930 cfi_info
->pri_addr
= cfi_query_u16(bank
, 0, 0x15);
1931 cfi_info
->alt_id
= cfi_query_u16(bank
, 0, 0x17);
1932 cfi_info
->alt_addr
= cfi_query_u16(bank
, 0, 0x19);
1934 DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
1936 cfi_info
->vcc_min
= cfi_query_u8(bank
, 0, 0x1b);
1937 cfi_info
->vcc_max
= cfi_query_u8(bank
, 0, 0x1c);
1938 cfi_info
->vpp_min
= cfi_query_u8(bank
, 0, 0x1d);
1939 cfi_info
->vpp_max
= cfi_query_u8(bank
, 0, 0x1e);
1940 cfi_info
->word_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x1f);
1941 cfi_info
->buf_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x20);
1942 cfi_info
->block_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x21);
1943 cfi_info
->chip_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x22);
1944 cfi_info
->word_write_timeout_max
= cfi_query_u8(bank
, 0, 0x23);
1945 cfi_info
->buf_write_timeout_max
= cfi_query_u8(bank
, 0, 0x24);
1946 cfi_info
->block_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x25);
1947 cfi_info
->chip_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x26);
1949 DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
1950 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
1951 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
1952 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
1953 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
1954 DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info
->word_write_timeout_typ
, 1 << cfi_info
->buf_write_timeout_typ
,
1955 1 << cfi_info
->block_erase_timeout_typ
, 1 << cfi_info
->chip_erase_timeout_typ
);
1956 DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
1957 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
1958 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
1959 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
1961 cfi_info
->dev_size
= cfi_query_u8(bank
, 0, 0x27);
1962 cfi_info
->interface_desc
= cfi_query_u16(bank
, 0, 0x28);
1963 cfi_info
->max_buf_write_size
= cfi_query_u16(bank
, 0, 0x2a);
1964 cfi_info
->num_erase_regions
= cfi_query_u8(bank
, 0, 0x2c);
1966 DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info
->dev_size
, cfi_info
->interface_desc
, (1 << cfi_info
->max_buf_write_size
));
1968 if (((1 << cfi_info
->dev_size
) * bank
->bus_width
/ bank
->chip_width
) != bank
->size
)
1970 WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank
->size
, 1 << cfi_info
->dev_size
);
1973 if (cfi_info
->num_erase_regions
)
1975 cfi_info
->erase_region_info
= malloc(4 * cfi_info
->num_erase_regions
);
1976 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
1978 cfi_info
->erase_region_info
[i
] = cfi_query_u32(bank
, 0, 0x2d + (4 * i
));
1979 DEBUG("erase region[%i]: %i blocks of size 0x%x", i
, (cfi_info
->erase_region_info
[i
] & 0xffff) + 1, (cfi_info
->erase_region_info
[i
] >> 16) * 256);
1984 cfi_info
->erase_region_info
= NULL
;
1987 /* We need to read the primary algorithm extended query table before calculating
1988 * the sector layout to be able to apply fixups
1990 switch(cfi_info
->pri_id
)
1992 /* Intel command set (standard and extended) */
1995 cfi_read_intel_pri_ext(bank
);
1997 /* AMD/Spansion, Atmel, ... command set */
1999 cfi_read_0002_pri_ext(bank
);
2002 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2006 /* return to read array mode
2007 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2009 cfi_command(bank
, 0xf0, command
);
2010 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2011 cfi_command(bank
, 0xff, command
);
2012 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2015 /* apply fixups depending on the primary command set */
2016 switch(cfi_info
->pri_id
)
2018 /* Intel command set (standard and extended) */
2021 cfi_fixup(bank
, cfi_0001_fixups
);
2023 /* AMD/Spansion, Atmel, ... command set */
2025 cfi_fixup(bank
, cfi_0002_fixups
);
2028 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2032 if (cfi_info
->num_erase_regions
== 0)
2034 /* a device might have only one erase block, spanning the whole device */
2035 bank
->num_sectors
= 1;
2036 bank
->sectors
= malloc(sizeof(flash_sector_t
));
2038 bank
->sectors
[sector
].offset
= 0x0;
2039 bank
->sectors
[sector
].size
= bank
->size
;
2040 bank
->sectors
[sector
].is_erased
= -1;
2041 bank
->sectors
[sector
].is_protected
= -1;
2045 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2047 num_sectors
+= (cfi_info
->erase_region_info
[i
] & 0xffff) + 1;
2050 bank
->num_sectors
= num_sectors
;
2051 bank
->sectors
= malloc(sizeof(flash_sector_t
) * num_sectors
);
2053 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2056 for (j
= 0; j
< (cfi_info
->erase_region_info
[i
] & 0xffff) + 1; j
++)
2058 bank
->sectors
[sector
].offset
= offset
;
2059 bank
->sectors
[sector
].size
= ((cfi_info
->erase_region_info
[i
] >> 16) * 256) * bank
->bus_width
/ bank
->chip_width
;
2060 offset
+= bank
->sectors
[sector
].size
;
2061 bank
->sectors
[sector
].is_erased
= -1;
2062 bank
->sectors
[sector
].is_protected
= -1;
2071 int cfi_erase_check(struct flash_bank_s
*bank
)
2073 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2074 target_t
*target
= bank
->target
;
2078 if (!cfi_info
->erase_check_algorithm
)
2080 u32 erase_check_code
[] =
2082 0xe4d03001, /* ldrb r3, [r0], #1 */
2083 0xe0022003, /* and r2, r2, r3 */
2084 0xe2511001, /* subs r1, r1, #1 */
2085 0x1afffffb, /* b -4 */
2086 0xeafffffe /* b 0 */
2089 /* make sure we have a working area */
2090 if (target_alloc_working_area(target
, 20, &cfi_info
->erase_check_algorithm
) != ERROR_OK
)
2092 WARNING("no working area available, falling back to slow memory reads");
2096 u8 erase_check_code_buf
[5 * 4];
2098 for (i
= 0; i
< 5; i
++)
2099 target_buffer_set_u32(target
, erase_check_code_buf
+ (i
*4), erase_check_code
[i
]);
2101 /* write algorithm code to working area */
2102 target
->type
->write_memory(target
, cfi_info
->erase_check_algorithm
->address
, 4, 5, erase_check_code_buf
);
2106 if (!cfi_info
->erase_check_algorithm
)
2108 u32
*buffer
= malloc(4096);
2110 for (i
= 0; i
< bank
->num_sectors
; i
++)
2112 u32 address
= bank
->base
+ bank
->sectors
[i
].offset
;
2113 u32 size
= bank
->sectors
[i
].size
;
2114 u32 check
= 0xffffffffU
;
2119 u32 thisrun_size
= (size
> 4096) ? 4096 : size
;
2122 target
->type
->read_memory(target
, address
, 4, thisrun_size
/ 4, (u8
*)buffer
);
2124 for (j
= 0; j
< thisrun_size
/ 4; j
++)
2127 if (check
!= 0xffffffff)
2133 size
-= thisrun_size
;
2134 address
+= thisrun_size
;
2137 bank
->sectors
[i
].is_erased
= erased
;
2144 for (i
= 0; i
< bank
->num_sectors
; i
++)
2146 u32 address
= bank
->base
+ bank
->sectors
[i
].offset
;
2147 u32 size
= bank
->sectors
[i
].size
;
2149 reg_param_t reg_params
[3];
2150 armv4_5_algorithm_t armv4_5_info
;
2152 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
2153 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
2154 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
2156 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
2157 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
2159 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
2160 buf_set_u32(reg_params
[1].value
, 0, 32, size
);
2162 init_reg_param(®_params
[2], "r2", 32, PARAM_IN_OUT
);
2163 buf_set_u32(reg_params
[2].value
, 0, 32, 0xff);
2165 if ((retval
= target
->type
->run_algorithm(target
, 0, NULL
, 3, reg_params
, cfi_info
->erase_check_algorithm
->address
, cfi_info
->erase_check_algorithm
->address
+ 0x10, 10000, &armv4_5_info
)) != ERROR_OK
)
2166 return ERROR_FLASH_OPERATION_FAILED
;
2168 if (buf_get_u32(reg_params
[2].value
, 0, 32) == 0xff)
2169 bank
->sectors
[i
].is_erased
= 1;
2171 bank
->sectors
[i
].is_erased
= 0;
2173 destroy_reg_param(®_params
[0]);
2174 destroy_reg_param(®_params
[1]);
2175 destroy_reg_param(®_params
[2]);
2182 int cfi_intel_protect_check(struct flash_bank_s
*bank
)
2184 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2185 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2186 target_t
*target
= bank
->target
;
2187 u8 command
[CFI_MAX_BUS_WIDTH
];
2190 /* check if block lock bits are supported on this device */
2191 if (!(pri_ext
->blk_status_reg_mask
& 0x1))
2192 return ERROR_FLASH_OPERATION_FAILED
;
2194 cfi_command(bank
, 0x90, command
);
2195 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
);
2197 for (i
= 0; i
< bank
->num_sectors
; i
++)
2199 u8 block_status
= cfi_get_u8(bank
, i
, 0x2);
2201 if (block_status
& 1)
2202 bank
->sectors
[i
].is_protected
= 1;
2204 bank
->sectors
[i
].is_protected
= 0;
2207 cfi_command(bank
, 0xff, command
);
2208 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2213 int cfi_spansion_protect_check(struct flash_bank_s
*bank
)
2215 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2216 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2217 target_t
*target
= bank
->target
;
2221 cfi_command(bank
, 0xaa, command
);
2222 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
2224 cfi_command(bank
, 0x55, command
);
2225 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
);
2227 cfi_command(bank
, 0x90, command
);
2228 target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
);
2230 for (i
= 0; i
< bank
->num_sectors
; i
++)
2232 u8 block_status
= cfi_get_u8(bank
, i
, 0x2);
2234 if (block_status
& 1)
2235 bank
->sectors
[i
].is_protected
= 1;
2237 bank
->sectors
[i
].is_protected
= 0;
2240 cfi_command(bank
, 0xf0, command
);
2241 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2246 int cfi_protect_check(struct flash_bank_s
*bank
)
2248 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2250 if (cfi_info
->qry
[0] != 'Q')
2251 return ERROR_FLASH_BANK_NOT_PROBED
;
2253 switch(cfi_info
->pri_id
)
2257 return cfi_intel_protect_check(bank
);
2260 return cfi_spansion_protect_check(bank
);
2263 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2270 int cfi_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
2273 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2275 if (cfi_info
->qry
[0] == (char)-1)
2277 printed
= snprintf(buf
, buf_size
, "\ncfi flash bank not probed yet\n");
2281 printed
= snprintf(buf
, buf_size
, "\ncfi information:\n");
2283 buf_size
-= printed
;
2285 printed
= snprintf(buf
, buf_size
, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2286 cfi_info
->manufacturer
, cfi_info
->device_id
);
2288 buf_size
-= printed
;
2290 printed
= snprintf(buf
, buf_size
, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2292 buf_size
-= printed
;
2294 printed
= snprintf(buf
, buf_size
, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n", (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2295 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2296 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2297 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2299 buf_size
-= printed
;
2301 printed
= snprintf(buf
, buf_size
, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n", 1 << cfi_info
->word_write_timeout_typ
, 1 << cfi_info
->buf_write_timeout_typ
,
2302 1 << cfi_info
->block_erase_timeout_typ
, 1 << cfi_info
->chip_erase_timeout_typ
);
2304 buf_size
-= printed
;
2306 printed
= snprintf(buf
, buf_size
, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n", (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2307 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2308 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2309 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2311 buf_size
-= printed
;
2313 printed
= snprintf(buf
, buf_size
, "size: 0x%x, interface desc: %i, max buffer write size: %x\n", 1 << cfi_info
->dev_size
, cfi_info
->interface_desc
, cfi_info
->max_buf_write_size
);
2315 buf_size
-= printed
;
2317 switch(cfi_info
->pri_id
)
2321 cfi_intel_info(bank
, buf
, buf_size
);
2324 cfi_spansion_info(bank
, buf
, buf_size
);
2327 ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
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