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- added the patch CFI-BE-Fixes-Blockwrite-Support.diff
[openocd.git] / src / flash / cfi.c
1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "cfi.h"
27
28 #include "flash.h"
29 #include "target.h"
30 #include "log.h"
31 #include "armv4_5.h"
32 #include "algorithm.h"
33 #include "binarybuffer.h"
34 #include "types.h"
35
36 #include <stdlib.h>
37 #include <string.h>
38 #include <unistd.h>
39
40 int cfi_register_commands(struct command_context_s *cmd_ctx);
41 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
42 int cfi_erase(struct flash_bank_s *bank, int first, int last);
43 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
44 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
45 int cfi_probe(struct flash_bank_s *bank);
46 int cfi_erase_check(struct flash_bank_s *bank);
47 int cfi_protect_check(struct flash_bank_s *bank);
48 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
49
50 int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
51
52 #define CFI_MAX_BUS_WIDTH 4
53 #define CFI_MAX_CHIP_WIDTH 4
54
55 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
56 #define CFI_MAX_INTEL_CODESIZE 256
57
58 flash_driver_t cfi_flash =
59 {
60 .name = "cfi",
61 .register_commands = cfi_register_commands,
62 .flash_bank_command = cfi_flash_bank_command,
63 .erase = cfi_erase,
64 .protect = cfi_protect,
65 .write = cfi_write,
66 .probe = cfi_probe,
67 .erase_check = cfi_erase_check,
68 .protect_check = cfi_protect_check,
69 .info = cfi_info
70 };
71
72 cfi_unlock_addresses_t cfi_unlock_addresses[] =
73 {
74 [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
75 [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
76 };
77
78 /* CFI fixups foward declarations */
79 void cfi_fixup_non_cfi(flash_bank_t *flash, void *param);
80 void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
81 void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
82 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
83
84 /* fixup after identifying JEDEC manufactuer and ID */
85 cfi_fixup_t cfi_jedec_fixups[] = {
86 {CFI_MFR_SST, 0x00D4, cfi_fixup_non_cfi, NULL},
87 {CFI_MFR_SST, 0x00D5, cfi_fixup_non_cfi, NULL},
88 {CFI_MFR_SST, 0x00D6, cfi_fixup_non_cfi, NULL},
89 {CFI_MFR_SST, 0x00D7, cfi_fixup_non_cfi, NULL},
90 {CFI_MFR_ST, 0x00D5, cfi_fixup_non_cfi, NULL},
91 {CFI_MFR_ST, 0x00D6, cfi_fixup_non_cfi, NULL},
92 {CFI_MFR_AMD, 0x2223, cfi_fixup_non_cfi, NULL},
93 {CFI_MFR_AMD, 0x22ab, cfi_fixup_non_cfi, NULL},
94 {0, 0, NULL, NULL}
95 };
96
97 /* fixup after reading cmdset 0002 primary query table */
98 cfi_fixup_t cfi_0002_fixups[] = {
99 {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
100 {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
101 {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
102 {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
103 {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
104 {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
105 {0, 0, NULL, NULL}
106 };
107
108 /* fixup after reading cmdset 0001 primary query table */
109 cfi_fixup_t cfi_0001_fixups[] = {
110 {0, 0, NULL, NULL}
111 };
112
113 void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
114 {
115 cfi_flash_bank_t *cfi_info = bank->driver_priv;
116 cfi_fixup_t *f;
117
118 for (f = fixups; f->fixup; f++)
119 {
120 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
121 ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
122 {
123 f->fixup(bank, f->param);
124 }
125 }
126 }
127
128 inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
129 {
130 /* while the sector list isn't built, only accesses to sector 0 work */
131 if (sector == 0)
132 return bank->base + offset * bank->bus_width;
133 else
134 {
135 if (!bank->sectors)
136 {
137 ERROR("BUG: sector list not yet built");
138 exit(-1);
139 }
140 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
141 }
142
143 }
144
145 void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
146 {
147 int i;
148
149 /* clear whole buffer, to ensure bits that exceed the bus_width
150 * are set to zero
151 */
152 for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
153 cmd_buf[i] = 0;
154
155 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
156 {
157 for (i = bank->bus_width; i > 0; i--)
158 {
159 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
160 }
161 }
162 else
163 {
164 for (i = 1; i <= bank->bus_width; i++)
165 {
166 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
167 }
168 }
169 }
170
171 /* read unsigned 8-bit value from the bank
172 * flash banks are expected to be made of similar chips
173 * the query result should be the same for all
174 */
175 u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
176 {
177 target_t *target = bank->target;
178 u8 data[CFI_MAX_BUS_WIDTH];
179
180 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
181
182 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
183 return data[0];
184 else
185 return data[bank->bus_width - 1];
186 }
187
188 /* read unsigned 8-bit value from the bank
189 * in case of a bank made of multiple chips,
190 * the individual values are ORed
191 */
192 u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
193 {
194 target_t *target = bank->target;
195 u8 data[CFI_MAX_BUS_WIDTH];
196 int i;
197
198 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
199
200 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
201 {
202 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
203 data[0] |= data[i];
204
205 return data[0];
206 }
207 else
208 {
209 u8 value = 0;
210 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
211 value |= data[bank->bus_width - 1 - i];
212
213 return value;
214 }
215 }
216
217 u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
218 {
219 target_t *target = bank->target;
220 u8 data[CFI_MAX_BUS_WIDTH * 2];
221
222 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
223
224 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
225 return data[0] | data[bank->bus_width] << 8;
226 else
227 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
228 }
229
230 u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
231 {
232 target_t *target = bank->target;
233 u8 data[CFI_MAX_BUS_WIDTH * 4];
234
235 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
236
237 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
238 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
239 else
240 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
241 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
242 }
243
244 void cfi_intel_clear_status_register(flash_bank_t *bank)
245 {
246 target_t *target = bank->target;
247 u8 command[8];
248
249 if (target->state != TARGET_HALTED)
250 {
251 ERROR("BUG: attempted to clear status register while target wasn't halted");
252 exit(-1);
253 }
254
255 cfi_command(bank, 0x50, command);
256 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
257 }
258
259 u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
260 {
261 u8 status;
262
263 while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
264 {
265 DEBUG("status: 0x%x", status);
266 usleep(1000);
267 }
268
269 /* mask out bit 0 (reserved) */
270 status = status & 0xfe;
271
272 DEBUG("status: 0x%x", status);
273
274 if ((status & 0x80) != 0x80)
275 {
276 ERROR("timeout while waiting for WSM to become ready");
277 }
278 else if (status != 0x80)
279 {
280 ERROR("status register: 0x%x", status);
281 if (status & 0x2)
282 ERROR("Block Lock-Bit Detected, Operation Abort");
283 if (status & 0x4)
284 ERROR("Program suspended");
285 if (status & 0x8)
286 ERROR("Low Programming Voltage Detected, Operation Aborted");
287 if (status & 0x10)
288 ERROR("Program Error / Error in Setting Lock-Bit");
289 if (status & 0x20)
290 ERROR("Error in Block Erasure or Clear Lock-Bits");
291 if (status & 0x40)
292 ERROR("Block Erase Suspended");
293
294 cfi_intel_clear_status_register(bank);
295 }
296
297 return status;
298 }
299
300 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
301 {
302 u8 status, oldstatus;
303
304 oldstatus = cfi_get_u8(bank, 0, 0x0);
305
306 do {
307 status = cfi_get_u8(bank, 0, 0x0);
308 if ((status ^ oldstatus) & 0x40) {
309 if (status & 0x20) {
310 oldstatus = cfi_get_u8(bank, 0, 0x0);
311 status = cfi_get_u8(bank, 0, 0x0);
312 if ((status ^ oldstatus) & 0x40) {
313 ERROR("dq5 timeout, status: 0x%x", status);
314 return(ERROR_FLASH_OPERATION_FAILED);
315 } else {
316 DEBUG("status: 0x%x", status);
317 return(ERROR_OK);
318 }
319 }
320 } else {
321 DEBUG("status: 0x%x", status);
322 return(ERROR_OK);
323 }
324
325 oldstatus = status;
326 usleep(1000);
327 } while (timeout-- > 0);
328
329 ERROR("timeout, status: 0x%x", status);
330
331 return(ERROR_FLASH_BUSY);
332 }
333
334 int cfi_read_intel_pri_ext(flash_bank_t *bank)
335 {
336 cfi_flash_bank_t *cfi_info = bank->driver_priv;
337 cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
338 target_t *target = bank->target;
339 u8 command[8];
340
341 cfi_info->pri_ext = pri_ext;
342
343 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
344 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
345 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
346
347 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
348 {
349 cfi_command(bank, 0xf0, command);
350 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
351 cfi_command(bank, 0xff, command);
352 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
353 return ERROR_FLASH_BANK_INVALID;
354 }
355
356 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
357 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
358
359 DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
360
361 pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
362 pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
363 pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
364
365 DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
366
367 pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
368 pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
369
370 DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
371 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
372 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
373
374 pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
375 if (pri_ext->num_protection_fields != 1)
376 {
377 WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
378 }
379
380 pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
381 pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
382 pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
383
384 DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
385
386 return ERROR_OK;
387 }
388
389 int cfi_read_spansion_pri_ext(flash_bank_t *bank)
390 {
391 cfi_flash_bank_t *cfi_info = bank->driver_priv;
392 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
393 target_t *target = bank->target;
394 u8 command[8];
395
396 cfi_info->pri_ext = pri_ext;
397
398 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
399 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
400 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
401
402 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
403 {
404 cfi_command(bank, 0xf0, command);
405 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
406 return ERROR_FLASH_BANK_INVALID;
407 }
408
409 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
410 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
411
412 DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
413
414 pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
415 pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
416 pri_ext->BlkProt = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
417 pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
418 pri_ext->BlkProtUnprot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
419 pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
420 pri_ext->BurstMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
421 pri_ext->PageMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
422 pri_ext->VppMin = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
423 pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
424 pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
425
426 DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
427 pri_ext->EraseSuspend, pri_ext->BlkProt);
428
429 DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
430 pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
431
432 DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
433
434
435 DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
436 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
437 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
438
439 DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
440
441 /* default values for implementation specific workarounds */
442 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
443 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
444 pri_ext->_reversed_geometry = 0;
445
446 return ERROR_OK;
447 }
448
449 int cfi_read_atmel_pri_ext(flash_bank_t *bank)
450 {
451 cfi_atmel_pri_ext_t atmel_pri_ext;
452 cfi_flash_bank_t *cfi_info = bank->driver_priv;
453 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
454 target_t *target = bank->target;
455 u8 command[8];
456
457 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
458 * but a different primary extended query table.
459 * We read the atmel table, and prepare a valid AMD/Spansion query table.
460 */
461
462 memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));
463
464 cfi_info->pri_ext = pri_ext;
465
466 atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
467 atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
468 atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
469
470 if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
471 {
472 cfi_command(bank, 0xf0, command);
473 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
474 return ERROR_FLASH_BANK_INVALID;
475 }
476
477 pri_ext->pri[0] = atmel_pri_ext.pri[0];
478 pri_ext->pri[1] = atmel_pri_ext.pri[1];
479 pri_ext->pri[2] = atmel_pri_ext.pri[2];
480
481 atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
482 atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
483
484 DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
485
486 pri_ext->major_version = atmel_pri_ext.major_version;
487 pri_ext->minor_version = atmel_pri_ext.minor_version;
488
489 atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
490 atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
491 atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
492 atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
493
494 DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
495 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
496
497 if (atmel_pri_ext.features & 0x02)
498 pri_ext->EraseSuspend = 2;
499
500 if (atmel_pri_ext.bottom_boot)
501 pri_ext->TopBottom = 2;
502 else
503 pri_ext->TopBottom = 3;
504
505 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
506 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
507
508 return ERROR_OK;
509 }
510
511 int cfi_read_0002_pri_ext(flash_bank_t *bank)
512 {
513 cfi_flash_bank_t *cfi_info = bank->driver_priv;
514
515 if (cfi_info->manufacturer == CFI_MFR_ATMEL)
516 {
517 return cfi_read_atmel_pri_ext(bank);
518 }
519 else
520 {
521 return cfi_read_spansion_pri_ext(bank);
522 }
523 }
524
525 int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
526 {
527 int printed;
528 cfi_flash_bank_t *cfi_info = bank->driver_priv;
529 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
530
531 printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
532 buf += printed;
533 buf_size -= printed;
534
535 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
536 pri_ext->pri[1], pri_ext->pri[2],
537 pri_ext->major_version, pri_ext->minor_version);
538 buf += printed;
539 buf_size -= printed;
540
541 printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
542 (pri_ext->SiliconRevision) >> 2,
543 (pri_ext->SiliconRevision) & 0x03);
544 buf += printed;
545 buf_size -= printed;
546
547 printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
548 pri_ext->EraseSuspend,
549 pri_ext->BlkProt);
550 buf += printed;
551 buf_size -= printed;
552
553 printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
554 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
555 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
556
557 return ERROR_OK;
558 }
559
560 int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
561 {
562 int printed;
563 cfi_flash_bank_t *cfi_info = bank->driver_priv;
564 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
565
566 printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
567 buf += printed;
568 buf_size -= printed;
569
570 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
571 buf += printed;
572 buf_size -= printed;
573
574 printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
575 buf += printed;
576 buf_size -= printed;
577
578 printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
579 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
580 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
581 buf += printed;
582 buf_size -= printed;
583
584 printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
585
586 return ERROR_OK;
587 }
588
589 int cfi_register_commands(struct command_context_s *cmd_ctx)
590 {
591 /*command_t *cfi_cmd = */register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, NULL);
592 /*
593 register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
594 "print part id of cfi flash bank <num>");
595 */
596 return ERROR_OK;
597 }
598
599 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
600 */
601 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
602 {
603 cfi_flash_bank_t *cfi_info;
604 int i;
605
606 if (argc < 6)
607 {
608 WARNING("incomplete flash_bank cfi configuration");
609 return ERROR_FLASH_BANK_INVALID;
610 }
611
612 if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
613 || (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
614 {
615 ERROR("chip and bus width have to specified in byte");
616 return ERROR_FLASH_BANK_INVALID;
617 }
618
619 cfi_info = malloc(sizeof(cfi_flash_bank_t));
620 bank->driver_priv = cfi_info;
621
622 cfi_info->write_algorithm = NULL;
623 cfi_info->erase_check_algorithm = NULL;
624
625 cfi_info->x16_as_x8 = 0;
626 cfi_info->jedec_probe = 0;
627 cfi_info->not_cfi = 0;
628
629 for (i = 6; i < argc; i++)
630 {
631 if (strcmp(args[i], "x16_as_x8") == 0)
632 {
633 cfi_info->x16_as_x8 = 1;
634 }
635 else if (strcmp(args[i], "jedec_probe") == 0)
636 {
637 cfi_info->jedec_probe = 1;
638 }
639 }
640
641 cfi_info->write_algorithm = NULL;
642
643 /* bank wasn't probed yet */
644 cfi_info->qry[0] = -1;
645
646 return ERROR_OK;
647 }
648
649 int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
650 {
651 cfi_flash_bank_t *cfi_info = bank->driver_priv;
652 target_t *target = bank->target;
653 u8 command[8];
654 int i;
655
656 cfi_intel_clear_status_register(bank);
657
658 for (i = first; i <= last; i++)
659 {
660 cfi_command(bank, 0x20, command);
661 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
662
663 cfi_command(bank, 0xd0, command);
664 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
665
666 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
667 bank->sectors[i].is_erased = 1;
668 else
669 {
670 cfi_command(bank, 0xff, command);
671 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
672
673 ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
674 return ERROR_FLASH_OPERATION_FAILED;
675 }
676 }
677
678 cfi_command(bank, 0xff, command);
679 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
680
681 return ERROR_OK;
682 }
683
684 int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
685 {
686 cfi_flash_bank_t *cfi_info = bank->driver_priv;
687 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
688 target_t *target = bank->target;
689 u8 command[8];
690 int i;
691
692 for (i = first; i <= last; i++)
693 {
694 cfi_command(bank, 0xaa, command);
695 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
696
697 cfi_command(bank, 0x55, command);
698 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
699
700 cfi_command(bank, 0x80, command);
701 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
702
703 cfi_command(bank, 0xaa, command);
704 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
705
706 cfi_command(bank, 0x55, command);
707 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
708
709 cfi_command(bank, 0x30, command);
710 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
711
712 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
713 bank->sectors[i].is_erased = 1;
714 else
715 {
716 cfi_command(bank, 0xf0, command);
717 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
718
719 ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
720 return ERROR_FLASH_OPERATION_FAILED;
721 }
722 }
723
724 cfi_command(bank, 0xf0, command);
725 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
726
727 return ERROR_OK;
728 }
729
730 int cfi_erase(struct flash_bank_s *bank, int first, int last)
731 {
732 cfi_flash_bank_t *cfi_info = bank->driver_priv;
733
734 if (bank->target->state != TARGET_HALTED)
735 {
736 return ERROR_TARGET_NOT_HALTED;
737 }
738
739 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
740 {
741 return ERROR_FLASH_SECTOR_INVALID;
742 }
743
744 if (cfi_info->qry[0] != 'Q')
745 return ERROR_FLASH_BANK_NOT_PROBED;
746
747 switch(cfi_info->pri_id)
748 {
749 case 1:
750 case 3:
751 return cfi_intel_erase(bank, first, last);
752 break;
753 case 2:
754 return cfi_spansion_erase(bank, first, last);
755 break;
756 default:
757 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
758 break;
759 }
760
761 return ERROR_OK;
762 }
763
764 int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
765 {
766 cfi_flash_bank_t *cfi_info = bank->driver_priv;
767 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
768 target_t *target = bank->target;
769 u8 command[8];
770 int retry = 0;
771 int i;
772
773 /* if the device supports neither legacy lock/unlock (bit 3) nor
774 * instant individual block locking (bit 5).
775 */
776 if (!(pri_ext->feature_support & 0x28))
777 return ERROR_FLASH_OPERATION_FAILED;
778
779 cfi_intel_clear_status_register(bank);
780
781 for (i = first; i <= last; i++)
782 {
783 cfi_command(bank, 0x60, command);
784 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
785 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
786 if (set)
787 {
788 cfi_command(bank, 0x01, command);
789 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
790 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
791 bank->sectors[i].is_protected = 1;
792 }
793 else
794 {
795 cfi_command(bank, 0xd0, command);
796 DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
797 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
798 bank->sectors[i].is_protected = 0;
799 }
800
801 /* instant individual block locking doesn't require reading of the status register */
802 if (!(pri_ext->feature_support & 0x20))
803 {
804 /* Clear lock bits operation may take up to 1.4s */
805 cfi_intel_wait_status_busy(bank, 1400);
806 }
807 else
808 {
809 u8 block_status;
810 /* read block lock bit, to verify status */
811 cfi_command(bank, 0x90, command);
812 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
813 block_status = cfi_get_u8(bank, i, 0x2);
814
815 if ((block_status & 0x1) != set)
816 {
817 ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
818 cfi_command(bank, 0x70, command);
819 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
820 cfi_intel_wait_status_busy(bank, 10);
821
822 if (retry > 10)
823 return ERROR_FLASH_OPERATION_FAILED;
824 else
825 {
826 i--;
827 retry++;
828 }
829 }
830 }
831 }
832
833 /* if the device doesn't support individual block lock bits set/clear,
834 * all blocks have been unlocked in parallel, so we set those that should be protected
835 */
836 if ((!set) && (!(pri_ext->feature_support & 0x20)))
837 {
838 for (i = 0; i < bank->num_sectors; i++)
839 {
840 if (bank->sectors[i].is_protected == 1)
841 {
842 cfi_intel_clear_status_register(bank);
843
844 cfi_command(bank, 0x60, command);
845 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
846
847 cfi_command(bank, 0x01, command);
848 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
849
850 cfi_intel_wait_status_busy(bank, 100);
851 }
852 }
853 }
854
855 cfi_command(bank, 0xff, command);
856 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
857
858 return ERROR_OK;
859 }
860
861 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
862 {
863 cfi_flash_bank_t *cfi_info = bank->driver_priv;
864
865 if (bank->target->state != TARGET_HALTED)
866 {
867 return ERROR_TARGET_NOT_HALTED;
868 }
869
870 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
871 {
872 return ERROR_FLASH_SECTOR_INVALID;
873 }
874
875 if (cfi_info->qry[0] != 'Q')
876 return ERROR_FLASH_BANK_NOT_PROBED;
877
878 switch(cfi_info->pri_id)
879 {
880 case 1:
881 case 3:
882 cfi_intel_protect(bank, set, first, last);
883 break;
884 default:
885 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
886 break;
887 }
888
889 return ERROR_OK;
890 }
891
892 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
893 static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
894 {
895 target_t *target = bank->target;
896
897 int i;
898
899 // NOTE:
900 // The data to flash must not be changed in endian! We write a bytestrem in
901 // target byte order already. Only the control and status byte lane of the flash
902 // WSM is interpreted by the CPU in different ways, when read a u16 or u32
903 // word (data seems to be in the upper or lower byte lane for u16 accesses).
904
905 //if (target->endianness == TARGET_LITTLE_ENDIAN)
906 //{
907 /* shift bytes */
908 for (i = 0; i < bank->bus_width - 1; i++)
909 word[i] = word[i + 1];
910 word[bank->bus_width - 1] = byte;
911 //}
912 //else
913 //{
914 // /* shift bytes */
915 // for (i = bank->bus_width - 1; i > 0; i--)
916 // word[i] = word[i - 1];
917 // word[0] = byte;
918 //}
919 }
920
921 /* Convert code image to target endian */
922 /* FIXME create general block conversion fcts in target.c?) */ static
923 void cfi_fix_code_endian(target_t *target, u32 *dest, const u32 *src, u32 count)
924 {
925 u32 i;
926 for (i=0; i< count; i++)
927 {
928 target_buffer_set_u32(target, (u8*)dest, *src);
929 dest++;
930 src++;
931 }
932 }
933
934 int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
935 {
936 cfi_flash_bank_t *cfi_info = bank->driver_priv;
937 target_t *target = bank->target;
938 reg_param_t reg_params[7];
939 armv4_5_algorithm_t armv4_5_info;
940 working_area_t *source;
941 u32 buffer_size = 32768;
942 u8 write_command_buf[CFI_MAX_BUS_WIDTH];
943 u8 busy_pattern_buf[CFI_MAX_BUS_WIDTH];
944 u8 error_pattern_buf[CFI_MAX_BUS_WIDTH];
945 u32 write_command_val, busy_pattern_val, error_pattern_val;
946
947 /* algorithm register usage:
948 * r0: source address (in RAM)
949 * r1: target address (in Flash)
950 * r2: count
951 * r3: flash write command
952 * r4: status byte (returned to host)
953 * r5: busy test pattern
954 * r6: error test pattern
955 */
956
957 static const u32 word_32_code[] = {
958 0xe4904004, /* loop: ldr r4, [r0], #4 */
959 0xe5813000, /* str r3, [r1] */
960 0xe5814000, /* str r4, [r1] */
961 0xe5914000, /* busy: ldr r4, [r1] */
962 0xe0047005, /* and r7, r4, r5 */
963 0xe1570005, /* cmp r7, r5 */
964 0x1afffffb, /* bne busy */
965 0xe1140006, /* tst r4, r6 */
966 0x1a000003, /* bne done */
967 0xe2522001, /* subs r2, r2, #1 */
968 0x0a000001, /* beq done */
969 0xe2811004, /* add r1, r1 #4 */
970 0xeafffff2, /* b loop */
971 0xeafffffe /* done: b -2 */
972 };
973
974 static const u32 word_16_code[] = {
975 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
976 0xe1c130b0, /* strh r3, [r1] */
977 0xe1c140b0, /* strh r4, [r1] */
978 0xe1d140b0, /* busy ldrh r4, [r1] */
979 0xe0047005, /* and r7, r4, r5 */
980 0xe1570005, /* cmp r7, r5 */
981 0x1afffffb, /* bne busy */
982 0xe1140006, /* tst r4, r6 */
983 0x1a000003, /* bne done */
984 0xe2522001, /* subs r2, r2, #1 */
985 0x0a000001, /* beq done */
986 0xe2811002, /* add r1, r1 #2 */
987 0xeafffff2, /* b loop */
988 0xeafffffe /* done: b -2 */
989 };
990
991 static const u32 word_8_code[] = {
992 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
993 0xe5c13000, /* strb r3, [r1] */
994 0xe5c14000, /* strb r4, [r1] */
995 0xe5d14000, /* busy ldrb r4, [r1] */
996 0xe0047005, /* and r7, r4, r5 */
997 0xe1570005, /* cmp r7, r5 */
998 0x1afffffb, /* bne busy */
999 0xe1140006, /* tst r4, r6 */
1000 0x1a000003, /* bne done */
1001 0xe2522001, /* subs r2, r2, #1 */
1002 0x0a000001, /* beq done */
1003 0xe2811001, /* add r1, r1 #1 */
1004 0xeafffff2, /* b loop */
1005 0xeafffffe /* done: b -2 */
1006 };
1007 u32 target_code[CFI_MAX_INTEL_CODESIZE];
1008 const u32 *target_code_src;
1009 int target_code_size;
1010 int retval = ERROR_OK;
1011
1012
1013 cfi_intel_clear_status_register(bank);
1014
1015 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1016 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1017 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1018
1019 /* flash write code */
1020 if (!cfi_info->write_algorithm)
1021 {
1022 /* prepare algorithm code for target endian */
1023 switch (bank->bus_width)
1024 {
1025 case 1 :
1026 target_code_src = word_8_code;
1027 target_code_size = sizeof(word_8_code);
1028 break;
1029 case 2 :
1030 target_code_src = word_16_code;
1031 target_code_size = sizeof(word_16_code);
1032 break;
1033 case 4 :
1034 target_code_src = word_32_code;
1035 target_code_size = sizeof(word_32_code);
1036 break;
1037 default:
1038 ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1039 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1040 }
1041 if ( target_code_size > sizeof(target_code) )
1042 {
1043 WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1044 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1045 }
1046 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size);
1047
1048 /* Get memory for block write handler */
1049 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1050 if (retval != ERROR_OK)
1051 {
1052 WARNING("No working area available, can't do block memory writes");
1053 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1054 };
1055
1056 /* write algorithm code to working area */
1057 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, (u8*)target_code);
1058 if (retval != ERROR_OK)
1059 {
1060 ERROR("Unable to write block write code to target");
1061 goto cleanup;
1062 }
1063 }
1064
1065 /* Get a workspace buffer for the data to flash starting with 32k size.
1066 Half size until buffer would be smaller 256 Bytem then fail back */
1067 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1068 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1069 {
1070 buffer_size /= 2;
1071 if (buffer_size <= 256)
1072 {
1073 WARNING("no large enough working area available, can't do block memory writes");
1074 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1075 goto cleanup;
1076 }
1077 };
1078
1079 /* setup algo registers */
1080 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1081 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1082 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1083 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1084 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1085 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1086 init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1087
1088 /* prepare command and status register patterns */
1089 cfi_command(bank, 0x40, write_command_buf);
1090 cfi_command(bank, 0x80, busy_pattern_buf);
1091 cfi_command(bank, 0x7e, error_pattern_buf);
1092
1093 switch (bank->bus_width)
1094 {
1095 case 1 :
1096 write_command_val = write_command_buf[0];
1097 busy_pattern_val = busy_pattern_buf[0];
1098 error_pattern_val = error_pattern_buf[0];
1099 break;
1100 case 2 :
1101 write_command_val = target_buffer_get_u16(target, write_command_buf);
1102 busy_pattern_val = target_buffer_get_u16(target, busy_pattern_buf);
1103 error_pattern_val = target_buffer_get_u16(target, error_pattern_buf);
1104 break;
1105 case 4 :
1106 write_command_val = target_buffer_get_u32(target, write_command_buf);
1107 busy_pattern_val = target_buffer_get_u32(target, busy_pattern_buf);
1108 error_pattern_val = target_buffer_get_u32(target, error_pattern_buf);
1109 break;
1110 default :
1111 ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1112 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1113 goto cleanup;
1114 }
1115
1116 INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );
1117
1118 /* Programming main loop */
1119 while (count > 0)
1120 {
1121 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1122 u32 wsm_error;
1123
1124 target_write_buffer(target, source->address, thisrun_count, buffer);
1125
1126 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1127 buf_set_u32(reg_params[1].value, 0, 32, address);
1128 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1129
1130 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1131 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1132 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1133
1134 INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );
1135
1136 /* Execute algorithm, assume breakpoint for last instruction */
1137 retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params,
1138 cfi_info->write_algorithm->address,
1139 cfi_info->write_algorithm->address + target_code_size - sizeof(u32),
1140 10000, /* 10s should be enough for max. 32k of data */
1141 &armv4_5_info);
1142
1143 /* On failure try a fall back to direct word writes */
1144 if (retval != ERROR_OK)
1145 {
1146 cfi_intel_clear_status_register(bank);
1147 ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1148 retval = ERROR_FLASH_OPERATION_FAILED;
1149 //retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1150 // FIXME To allow fall back or recovery, we must save the actual status
1151 // somewhere, so that a higher level code can start recovery.
1152 goto cleanup;
1153 }
1154
1155 /* Check return value from algo code */
1156 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1157 if (wsm_error)
1158 {
1159 /* read status register (outputs debug inforation) */
1160 cfi_intel_wait_status_busy(bank, 100);
1161 cfi_intel_clear_status_register(bank);
1162 retval = ERROR_FLASH_OPERATION_FAILED;
1163 goto cleanup;
1164 }
1165
1166 buffer += thisrun_count;
1167 address += thisrun_count;
1168 count -= thisrun_count;
1169 }
1170
1171 /* free up resources */
1172 cleanup:
1173 if (source)
1174 target_free_working_area(target, source);
1175
1176 if (cfi_info->write_algorithm)
1177 {
1178 target_free_working_area(target, cfi_info->write_algorithm);
1179 cfi_info->write_algorithm = NULL;
1180 }
1181
1182 destroy_reg_param(&reg_params[0]);
1183 destroy_reg_param(&reg_params[1]);
1184 destroy_reg_param(&reg_params[2]);
1185 destroy_reg_param(&reg_params[3]);
1186 destroy_reg_param(&reg_params[4]);
1187 destroy_reg_param(&reg_params[5]);
1188 destroy_reg_param(&reg_params[6]);
1189
1190 return retval;
1191 }
1192
1193 int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1194 {
1195 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1196 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1197 target_t *target = bank->target;
1198 reg_param_t reg_params[10];
1199 armv4_5_algorithm_t armv4_5_info;
1200 working_area_t *source;
1201 u32 buffer_size = 32768;
1202 u8 write_command[CFI_MAX_BUS_WIDTH];
1203 u32 status;
1204 int i;
1205 int retval;
1206 int exit_code = ERROR_OK;
1207
1208 /* input parameters - */
1209 /* R0 = source address */
1210 /* R1 = destination address */
1211 /* R2 = number of writes */
1212 /* R3 = flash write command */
1213 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1214 /* output parameters - */
1215 /* R5 = 0x80 ok 0x00 bad */
1216 /* temp registers - */
1217 /* R6 = value read from flash to test status */
1218 /* R7 = holding register */
1219 /* unlock registers - */
1220 /* R8 = unlock1_addr */
1221 /* R9 = unlock1_cmd */
1222 /* R10 = unlock2_addr */
1223 /* R11 = unlock2_cmd */
1224
1225 u32 word_32_code[] = {
1226 /* 00008100 <sp_32_code>: */
1227 0xe4905004, /* ldr r5, [r0], #4 */
1228 0xe5889000, /* str r9, [r8] */
1229 0xe58ab000, /* str r11, [r10] */
1230 0xe5883000, /* str r3, [r8] */
1231 0xe5815000, /* str r5, [r1] */
1232 0xe1a00000, /* nop */
1233 /* */
1234 /* 00008110 <sp_32_busy>: */
1235 0xe5916000, /* ldr r6, [r1] */
1236 0xe0257006, /* eor r7, r5, r6 */
1237 0xe0147007, /* ands r7, r4, r7 */
1238 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1239 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1240 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1241 0xe5916000, /* ldr r6, [r1] */
1242 0xe0257006, /* eor r7, r5, r6 */
1243 0xe0147007, /* ands r7, r4, r7 */
1244 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1245 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1246 0x1a000004, /* bne 8154 <sp_32_done> */
1247 /* */
1248 /* 00008140 <sp_32_cont>: */
1249 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1250 0x03a05080, /* moveq r5, #128 ; 0x80 */
1251 0x0a000001, /* beq 8154 <sp_32_done> */
1252 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1253 0xeaffffe8, /* b 8100 <sp_32_code> */
1254 /* */
1255 /* 00008154 <sp_32_done>: */
1256 0xeafffffe /* b 8154 <sp_32_done> */
1257 };
1258
1259 u32 word_16_code[] = {
1260 /* 00008158 <sp_16_code>: */
1261 0xe0d050b2, /* ldrh r5, [r0], #2 */
1262 0xe1c890b0, /* strh r9, [r8] */
1263 0xe1cab0b0, /* strh r11, [r10] */
1264 0xe1c830b0, /* strh r3, [r8] */
1265 0xe1c150b0, /* strh r5, [r1] */
1266 0xe1a00000, /* nop (mov r0,r0) */
1267 /* */
1268 /* 00008168 <sp_16_busy>: */
1269 0xe1d160b0, /* ldrh r6, [r1] */
1270 0xe0257006, /* eor r7, r5, r6 */
1271 0xe0147007, /* ands r7, r4, r7 */
1272 0x0a000007, /* beq 8198 <sp_16_cont> */
1273 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1274 0x0afffff9, /* beq 8168 <sp_16_busy> */
1275 0xe1d160b0, /* ldrh r6, [r1] */
1276 0xe0257006, /* eor r7, r5, r6 */
1277 0xe0147007, /* ands r7, r4, r7 */
1278 0x0a000001, /* beq 8198 <sp_16_cont> */
1279 0xe3a05000, /* mov r5, #0 ; 0x0 */
1280 0x1a000004, /* bne 81ac <sp_16_done> */
1281 /* */
1282 /* 00008198 <sp_16_cont>: */
1283 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1284 0x03a05080, /* moveq r5, #128 ; 0x80 */
1285 0x0a000001, /* beq 81ac <sp_16_done> */
1286 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1287 0xeaffffe8, /* b 8158 <sp_16_code> */
1288 /* */
1289 /* 000081ac <sp_16_done>: */
1290 0xeafffffe /* b 81ac <sp_16_done> */
1291 };
1292
1293 u32 word_8_code[] = {
1294 /* 000081b0 <sp_16_code_end>: */
1295 0xe4d05001, /* ldrb r5, [r0], #1 */
1296 0xe5c89000, /* strb r9, [r8] */
1297 0xe5cab000, /* strb r11, [r10] */
1298 0xe5c83000, /* strb r3, [r8] */
1299 0xe5c15000, /* strb r5, [r1] */
1300 0xe1a00000, /* nop (mov r0,r0) */
1301 /* */
1302 /* 000081c0 <sp_8_busy>: */
1303 0xe5d16000, /* ldrb r6, [r1] */
1304 0xe0257006, /* eor r7, r5, r6 */
1305 0xe0147007, /* ands r7, r4, r7 */
1306 0x0a000007, /* beq 81f0 <sp_8_cont> */
1307 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1308 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1309 0xe5d16000, /* ldrb r6, [r1] */
1310 0xe0257006, /* eor r7, r5, r6 */
1311 0xe0147007, /* ands r7, r4, r7 */
1312 0x0a000001, /* beq 81f0 <sp_8_cont> */
1313 0xe3a05000, /* mov r5, #0 ; 0x0 */
1314 0x1a000004, /* bne 8204 <sp_8_done> */
1315 /* */
1316 /* 000081f0 <sp_8_cont>: */
1317 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1318 0x03a05080, /* moveq r5, #128 ; 0x80 */
1319 0x0a000001, /* beq 8204 <sp_8_done> */
1320 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1321 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1322 /* */
1323 /* 00008204 <sp_8_done>: */
1324 0xeafffffe /* b 8204 <sp_8_done> */
1325 };
1326
1327 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1328 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1329 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1330
1331 /* flash write code */
1332 if (!cfi_info->write_algorithm)
1333 {
1334 u8 *code_p;
1335
1336 /* convert bus-width dependent algorithm code to correct endiannes */
1337 if (bank->bus_width == 1)
1338 {
1339 code_p = malloc(24 * 4);
1340
1341 for (i = 0; i < 24; i++)
1342 target_buffer_set_u32(target, code_p + (i*4), word_8_code[i]);
1343 }
1344 else if (bank->bus_width == 2)
1345 {
1346 code_p = malloc(24 * 4);
1347
1348 for (i = 0; i < 24; i++)
1349 target_buffer_set_u32(target, code_p + (i*4), word_16_code[i]);
1350 }
1351 else if (bank->bus_width == 4)
1352 {
1353 code_p = malloc(24 * 4);
1354
1355 for (i = 0; i < 24; i++)
1356 target_buffer_set_u32(target, code_p + (i*4), word_32_code[i]);
1357 }
1358 else
1359 {
1360 return ERROR_FLASH_OPERATION_FAILED;
1361 }
1362
1363 /* allocate working area */
1364 if (target_alloc_working_area(target, 24 * 4,
1365 &cfi_info->write_algorithm) != ERROR_OK)
1366 {
1367 WARNING("no working area available, can't do block memory writes");
1368 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1369 }
1370
1371 /* write algorithm code to working area */
1372 target_write_buffer(target, cfi_info->write_algorithm->address, 24 * 4, code_p);
1373
1374 free(code_p);
1375 }
1376
1377 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1378 {
1379 buffer_size /= 2;
1380 if (buffer_size <= 256)
1381 {
1382 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1383 if (cfi_info->write_algorithm)
1384 target_free_working_area(target, cfi_info->write_algorithm);
1385
1386 WARNING("not enough working area available, can't do block memory writes");
1387 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1388 }
1389 };
1390
1391 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1392 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1393 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1394 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1395 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1396 init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1397 init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1398 init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1399 init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1400 init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1401
1402 while (count > 0)
1403 {
1404 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1405
1406 target_write_buffer(target, source->address, thisrun_count, buffer);
1407
1408 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1409 buf_set_u32(reg_params[1].value, 0, 32, address);
1410 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1411 cfi_command(bank, 0xA0, write_command);
1412 buf_set_u32(reg_params[3].value, 0, 32, buf_get_u32(write_command, 0, 32));
1413 cfi_command(bank, 0x80, write_command);
1414 buf_set_u32(reg_params[4].value, 0, 32, buf_get_u32(write_command, 0, 32));
1415 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1416 buf_set_u32(reg_params[7].value, 0, 32, 0xaa);
1417 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1418 buf_set_u32(reg_params[9].value, 0, 32, 0x55);
1419
1420 retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params,
1421 cfi_info->write_algorithm->address,
1422 cfi_info->write_algorithm->address + ((24 * 4) - 4),
1423 10000, &armv4_5_info);
1424
1425 status = buf_get_u32(reg_params[5].value, 0, 32);
1426
1427 if ((retval != ERROR_OK) || status != 0x80)
1428 {
1429 DEBUG("status: 0x%x", status);
1430 exit_code = ERROR_FLASH_OPERATION_FAILED;
1431 break;
1432 }
1433
1434 buffer += thisrun_count;
1435 address += thisrun_count;
1436 count -= thisrun_count;
1437 }
1438
1439 target_free_working_area(target, source);
1440
1441 destroy_reg_param(&reg_params[0]);
1442 destroy_reg_param(&reg_params[1]);
1443 destroy_reg_param(&reg_params[2]);
1444 destroy_reg_param(&reg_params[3]);
1445 destroy_reg_param(&reg_params[4]);
1446 destroy_reg_param(&reg_params[5]);
1447 destroy_reg_param(&reg_params[6]);
1448 destroy_reg_param(&reg_params[7]);
1449 destroy_reg_param(&reg_params[8]);
1450 destroy_reg_param(&reg_params[9]);
1451
1452 return exit_code;
1453 }
1454
1455 int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1456 {
1457 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1458 target_t *target = bank->target;
1459 u8 command[8];
1460
1461 cfi_intel_clear_status_register(bank);
1462 cfi_command(bank, 0x40, command);
1463 target->type->write_memory(target, address, bank->bus_width, 1, command);
1464
1465 target->type->write_memory(target, address, bank->bus_width, 1, word);
1466
1467 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1468 {
1469 cfi_command(bank, 0xff, command);
1470 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1471
1472 ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1473 return ERROR_FLASH_OPERATION_FAILED;
1474 }
1475
1476 return ERROR_OK;
1477 }
1478
1479 int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1480 {
1481 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1482 target_t *target = bank->target;
1483 u8 command[8];
1484 int i;
1485
1486 /* Calculate buffer size and boundary mask */
1487 u32 buffersize = 1UL << cfi_info->max_buf_write_size;
1488 u32 buffermask = buffersize-1;
1489 u32 bufferwsize;
1490
1491 /* Check for valid range */
1492 if (address & buffermask)
1493 {
1494 ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1495 return ERROR_FLASH_OPERATION_FAILED;
1496 }
1497 switch(bank->chip_width)
1498 {
1499 case 4 : bufferwsize = buffersize / 4; break;
1500 case 2 : bufferwsize = buffersize / 2; break;
1501 case 1 : bufferwsize = buffersize; break;
1502 default:
1503 ERROR("Unsupported chip width %d", bank->chip_width);
1504 return ERROR_FLASH_OPERATION_FAILED;
1505 }
1506
1507 /* Check for valid size */
1508 if (wordcount > bufferwsize)
1509 {
1510 ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1511 return ERROR_FLASH_OPERATION_FAILED;
1512 }
1513
1514 /* Write to flash buffer */
1515 cfi_intel_clear_status_register(bank);
1516
1517 /* Initiate buffer operation _*/
1518 cfi_command(bank, 0xE8, command);
1519 target->type->write_memory(target, address, bank->bus_width, 1, command);
1520 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1521 {
1522 cfi_command(bank, 0xff, command);
1523 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1524
1525 ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
1526 return ERROR_FLASH_OPERATION_FAILED;
1527 }
1528
1529 /* Write buffer wordcount-1 and data words */
1530 cfi_command(bank, bufferwsize-1, command);
1531 target->type->write_memory(target, address, bank->bus_width, 1, command);
1532
1533 target->type->write_memory(target, address, bank->bus_width, bufferwsize, word);
1534
1535 /* Commit write operation */
1536 cfi_command(bank, 0xd0, command);
1537 target->type->write_memory(target, address, bank->bus_width, 1, command);
1538 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1539 {
1540 cfi_command(bank, 0xff, command);
1541 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1542
1543 ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
1544 return ERROR_FLASH_OPERATION_FAILED;
1545 }
1546
1547 return ERROR_OK;
1548 }
1549
1550 int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1551 {
1552 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1553 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1554 target_t *target = bank->target;
1555 u8 command[8];
1556
1557 cfi_command(bank, 0xaa, command);
1558 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1559
1560 cfi_command(bank, 0x55, command);
1561 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
1562
1563 cfi_command(bank, 0xa0, command);
1564 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1565
1566 target->type->write_memory(target, address, bank->bus_width, 1, word);
1567
1568 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1569 {
1570 cfi_command(bank, 0xf0, command);
1571 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1572
1573 ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1574 return ERROR_FLASH_OPERATION_FAILED;
1575 }
1576
1577 return ERROR_OK;
1578 }
1579
1580 int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1581 {
1582 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1583
1584 switch(cfi_info->pri_id)
1585 {
1586 case 1:
1587 case 3:
1588 return cfi_intel_write_word(bank, word, address);
1589 break;
1590 case 2:
1591 return cfi_spansion_write_word(bank, word, address);
1592 break;
1593 default:
1594 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1595 break;
1596 }
1597
1598 return ERROR_FLASH_OPERATION_FAILED;
1599 }
1600
1601 int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1602 {
1603 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1604
1605 switch(cfi_info->pri_id)
1606 {
1607 case 1:
1608 case 3:
1609 return cfi_intel_write_words(bank, word, wordcount, address);
1610 break;
1611 case 2:
1612 //return cfi_spansion_write_words(bank, word, address);
1613 ERROR("cfi primary command set %i unimplemented - FIXME", cfi_info->pri_id);
1614 break;
1615 default:
1616 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1617 break;
1618 }
1619
1620 return ERROR_FLASH_OPERATION_FAILED;
1621 }
1622
1623 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
1624 {
1625 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1626 target_t *target = bank->target;
1627 u32 address = bank->base + offset; /* address of first byte to be programmed */
1628 u32 write_p, copy_p;
1629 int align; /* number of unaligned bytes */
1630 int blk_count; /* number of bus_width bytes for block copy */
1631 u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1632 int i;
1633 int retval;
1634
1635 if (bank->target->state != TARGET_HALTED)
1636 {
1637 return ERROR_TARGET_NOT_HALTED;
1638 }
1639
1640 if (offset + count > bank->size)
1641 return ERROR_FLASH_DST_OUT_OF_BANK;
1642
1643 if (cfi_info->qry[0] != 'Q')
1644 return ERROR_FLASH_BANK_NOT_PROBED;
1645
1646 /* start at the first byte of the first word (bus_width size) */
1647 write_p = address & ~(bank->bus_width - 1);
1648 if ((align = address - write_p) != 0)
1649 {
1650 INFO("Fixup %d unaligned head bytes", align );
1651
1652 for (i = 0; i < bank->bus_width; i++)
1653 current_word[i] = 0;
1654 copy_p = write_p;
1655
1656 /* copy bytes before the first write address */
1657 for (i = 0; i < align; ++i, ++copy_p)
1658 {
1659 u8 byte;
1660 target->type->read_memory(target, copy_p, 1, 1, &byte);
1661 cfi_add_byte(bank, current_word, byte);
1662 }
1663
1664 /* add bytes from the buffer */
1665 for (; (i < bank->bus_width) && (count > 0); i++)
1666 {
1667 cfi_add_byte(bank, current_word, *buffer++);
1668 count--;
1669 copy_p++;
1670 }
1671
1672 /* if the buffer is already finished, copy bytes after the last write address */
1673 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1674 {
1675 u8 byte;
1676 target->type->read_memory(target, copy_p, 1, 1, &byte);
1677 cfi_add_byte(bank, current_word, byte);
1678 }
1679
1680 retval = cfi_write_word(bank, current_word, write_p);
1681 if (retval != ERROR_OK)
1682 return retval;
1683 write_p = copy_p;
1684 }
1685
1686 /* handle blocks of bus_size aligned bytes */
1687 blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1688 switch(cfi_info->pri_id)
1689 {
1690 /* try block writes (fails without working area) */
1691 case 1:
1692 case 3:
1693 retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1694 break;
1695 case 2:
1696 retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1697 break;
1698 default:
1699 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1700 retval = ERROR_FLASH_OPERATION_FAILED;
1701 break;
1702 }
1703 if (retval == ERROR_OK)
1704 {
1705 /* Increment pointers and decrease count on succesful block write */
1706 buffer += blk_count;
1707 write_p += blk_count;
1708 count -= blk_count;
1709 }
1710 else
1711 {
1712 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1713 {
1714 u32 buffersize = 1UL << cfi_info->max_buf_write_size;
1715 u32 buffermask = buffersize-1;
1716 u32 bufferwsize;
1717
1718 switch(bank->chip_width)
1719 {
1720 case 4 : bufferwsize = buffersize / 4; break;
1721 case 2 : bufferwsize = buffersize / 2; break;
1722 case 1 : bufferwsize = buffersize; break;
1723 default:
1724 ERROR("Unsupported chip width %d", bank->chip_width);
1725 return ERROR_FLASH_OPERATION_FAILED;
1726 }
1727
1728 /* fall back to memory writes */
1729 while (count > bank->bus_width)
1730 {
1731 if ((write_p & 0xff) == 0)
1732 {
1733 INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
1734 }
1735 if ((count > bufferwsize) && !(write_p & buffermask))
1736 {
1737 retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1738 if (retval != ERROR_OK)
1739 return retval;
1740
1741 buffer += buffersize;
1742 write_p += buffersize;
1743 count -= buffersize;
1744 }
1745 else
1746 {
1747 for (i = 0; i < bank->bus_width; i++)
1748 current_word[i] = 0;
1749
1750 for (i = 0; i < bank->bus_width; i++)
1751 {
1752 cfi_add_byte(bank, current_word, *buffer++);
1753 }
1754
1755 retval = cfi_write_word(bank, current_word, write_p);
1756 if (retval != ERROR_OK)
1757 return retval;
1758
1759 write_p += bank->bus_width;
1760 count -= bank->bus_width;
1761 }
1762 }
1763 }
1764 else
1765 return retval;
1766 }
1767
1768 /* return to read array mode, so we can read from flash again for padding */
1769 cfi_command(bank, 0xf0, current_word);
1770 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1771 cfi_command(bank, 0xff, current_word);
1772 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1773
1774 /* handle unaligned tail bytes */
1775 if (count > 0)
1776 {
1777 INFO("Fixup %d unaligned tail bytes", count );
1778
1779 copy_p = write_p;
1780 for (i = 0; i < bank->bus_width; i++)
1781 current_word[i] = 0;
1782
1783 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
1784 {
1785 cfi_add_byte(bank, current_word, *buffer++);
1786 count--;
1787 }
1788 for (; i < bank->bus_width; ++i, ++copy_p)
1789 {
1790 u8 byte;
1791 target->type->read_memory(target, copy_p, 1, 1, &byte);
1792 cfi_add_byte(bank, current_word, byte);
1793 }
1794 retval = cfi_write_word(bank, current_word, write_p);
1795 if (retval != ERROR_OK)
1796 return retval;
1797 }
1798
1799 /* return to read array mode */
1800 cfi_command(bank, 0xf0, current_word);
1801 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1802 cfi_command(bank, 0xff, current_word);
1803 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1804
1805 return ERROR_OK;
1806 }
1807
1808 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
1809 {
1810 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1811 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1812
1813 pri_ext->_reversed_geometry = 1;
1814 }
1815
1816 void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
1817 {
1818 int i;
1819 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1820 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1821
1822 if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
1823 {
1824 DEBUG("swapping reversed erase region information on cmdset 0002 device");
1825
1826 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
1827 {
1828 int j = (cfi_info->num_erase_regions - 1) - i;
1829 u32 swap;
1830
1831 swap = cfi_info->erase_region_info[i];
1832 cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
1833 cfi_info->erase_region_info[j] = swap;
1834 }
1835 }
1836 }
1837
1838 void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
1839 {
1840 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1841 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1842 cfi_unlock_addresses_t *unlock_addresses = param;
1843
1844 pri_ext->_unlock1 = unlock_addresses->unlock1;
1845 pri_ext->_unlock2 = unlock_addresses->unlock2;
1846 }
1847
1848 int cfi_probe(struct flash_bank_s *bank)
1849 {
1850 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1851 target_t *target = bank->target;
1852 u8 command[8];
1853 int num_sectors = 0;
1854 int i;
1855 int sector = 0;
1856 u32 offset = 0;
1857 u32 unlock1 = 0x555;
1858 u32 unlock2 = 0x2aa;
1859
1860 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
1861 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
1862 */
1863 if (cfi_info->jedec_probe)
1864 {
1865 unlock1 = 0x5555;
1866 unlock2 = 0x2aaa;
1867 }
1868
1869 /* switch to read identifier codes mode ("AUTOSELECT") */
1870 cfi_command(bank, 0xaa, command);
1871 target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1872 cfi_command(bank, 0x55, command);
1873 target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command);
1874 cfi_command(bank, 0x90, command);
1875 target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1876
1877 if (bank->chip_width == 1)
1878 {
1879 u8 manufacturer, device_id;
1880 target_read_u8(target, bank->base + 0x0, &manufacturer);
1881 target_read_u8(target, bank->base + 0x1, &device_id);
1882 cfi_info->manufacturer = manufacturer;
1883 cfi_info->device_id = device_id;
1884 }
1885 else if (bank->chip_width == 2)
1886 {
1887 target_read_u16(target, bank->base + 0x0, &cfi_info->manufacturer);
1888 target_read_u16(target, bank->base + 0x2, &cfi_info->device_id);
1889 }
1890
1891 /* switch back to read array mode */
1892 cfi_command(bank, 0xf0, command);
1893 target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
1894 cfi_command(bank, 0xff, command);
1895 target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
1896
1897 cfi_fixup(bank, cfi_jedec_fixups);
1898
1899 /* query only if this is a CFI compatible flash,
1900 * otherwise the relevant info has already been filled in
1901 */
1902 if (cfi_info->not_cfi == 0)
1903 {
1904 /* enter CFI query mode
1905 * according to JEDEC Standard No. 68.01,
1906 * a single bus sequence with address = 0x55, data = 0x98 should put
1907 * the device into CFI query mode.
1908 *
1909 * SST flashes clearly violate this, and we will consider them incompatbile for now
1910 */
1911 cfi_command(bank, 0x98, command);
1912 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
1913
1914 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
1915 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
1916 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
1917
1918 DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
1919
1920 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
1921 {
1922 cfi_command(bank, 0xf0, command);
1923 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1924 cfi_command(bank, 0xff, command);
1925 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1926 return ERROR_FLASH_BANK_INVALID;
1927 }
1928
1929 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
1930 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
1931 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
1932 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
1933
1934 DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
1935
1936 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
1937 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
1938 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
1939 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
1940 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
1941 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
1942 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
1943 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
1944 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
1945 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
1946 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
1947 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
1948
1949 DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
1950 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
1951 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
1952 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
1953 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
1954 DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
1955 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
1956 DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
1957 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
1958 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
1959 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
1960
1961 cfi_info->dev_size = cfi_query_u8(bank, 0, 0x27);
1962 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
1963 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
1964 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
1965
1966 DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
1967
1968 if (((1 << cfi_info->dev_size) * bank->bus_width / bank->chip_width) != bank->size)
1969 {
1970 WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, 1 << cfi_info->dev_size);
1971 }
1972
1973 if (cfi_info->num_erase_regions)
1974 {
1975 cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
1976 for (i = 0; i < cfi_info->num_erase_regions; i++)
1977 {
1978 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
1979 DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
1980 }
1981 }
1982 else
1983 {
1984 cfi_info->erase_region_info = NULL;
1985 }
1986
1987 /* We need to read the primary algorithm extended query table before calculating
1988 * the sector layout to be able to apply fixups
1989 */
1990 switch(cfi_info->pri_id)
1991 {
1992 /* Intel command set (standard and extended) */
1993 case 0x0001:
1994 case 0x0003:
1995 cfi_read_intel_pri_ext(bank);
1996 break;
1997 /* AMD/Spansion, Atmel, ... command set */
1998 case 0x0002:
1999 cfi_read_0002_pri_ext(bank);
2000 break;
2001 default:
2002 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2003 break;
2004 }
2005
2006 /* return to read array mode
2007 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2008 */
2009 cfi_command(bank, 0xf0, command);
2010 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2011 cfi_command(bank, 0xff, command);
2012 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2013 }
2014
2015 /* apply fixups depending on the primary command set */
2016 switch(cfi_info->pri_id)
2017 {
2018 /* Intel command set (standard and extended) */
2019 case 0x0001:
2020 case 0x0003:
2021 cfi_fixup(bank, cfi_0001_fixups);
2022 break;
2023 /* AMD/Spansion, Atmel, ... command set */
2024 case 0x0002:
2025 cfi_fixup(bank, cfi_0002_fixups);
2026 break;
2027 default:
2028 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2029 break;
2030 }
2031
2032 if (cfi_info->num_erase_regions == 0)
2033 {
2034 /* a device might have only one erase block, spanning the whole device */
2035 bank->num_sectors = 1;
2036 bank->sectors = malloc(sizeof(flash_sector_t));
2037
2038 bank->sectors[sector].offset = 0x0;
2039 bank->sectors[sector].size = bank->size;
2040 bank->sectors[sector].is_erased = -1;
2041 bank->sectors[sector].is_protected = -1;
2042 }
2043 else
2044 {
2045 for (i = 0; i < cfi_info->num_erase_regions; i++)
2046 {
2047 num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2048 }
2049
2050 bank->num_sectors = num_sectors;
2051 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
2052
2053 for (i = 0; i < cfi_info->num_erase_regions; i++)
2054 {
2055 int j;
2056 for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2057 {
2058 bank->sectors[sector].offset = offset;
2059 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2060 offset += bank->sectors[sector].size;
2061 bank->sectors[sector].is_erased = -1;
2062 bank->sectors[sector].is_protected = -1;
2063 sector++;
2064 }
2065 }
2066 }
2067
2068 return ERROR_OK;
2069 }
2070
2071 int cfi_erase_check(struct flash_bank_s *bank)
2072 {
2073 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2074 target_t *target = bank->target;
2075 int i;
2076 int retval;
2077
2078 if (!cfi_info->erase_check_algorithm)
2079 {
2080 u32 erase_check_code[] =
2081 {
2082 0xe4d03001, /* ldrb r3, [r0], #1 */
2083 0xe0022003, /* and r2, r2, r3 */
2084 0xe2511001, /* subs r1, r1, #1 */
2085 0x1afffffb, /* b -4 */
2086 0xeafffffe /* b 0 */
2087 };
2088
2089 /* make sure we have a working area */
2090 if (target_alloc_working_area(target, 20, &cfi_info->erase_check_algorithm) != ERROR_OK)
2091 {
2092 WARNING("no working area available, falling back to slow memory reads");
2093 }
2094 else
2095 {
2096 u8 erase_check_code_buf[5 * 4];
2097
2098 for (i = 0; i < 5; i++)
2099 target_buffer_set_u32(target, erase_check_code_buf + (i*4), erase_check_code[i]);
2100
2101 /* write algorithm code to working area */
2102 target->type->write_memory(target, cfi_info->erase_check_algorithm->address, 4, 5, erase_check_code_buf);
2103 }
2104 }
2105
2106 if (!cfi_info->erase_check_algorithm)
2107 {
2108 u32 *buffer = malloc(4096);
2109
2110 for (i = 0; i < bank->num_sectors; i++)
2111 {
2112 u32 address = bank->base + bank->sectors[i].offset;
2113 u32 size = bank->sectors[i].size;
2114 u32 check = 0xffffffffU;
2115 int erased = 1;
2116
2117 while (size > 0)
2118 {
2119 u32 thisrun_size = (size > 4096) ? 4096 : size;
2120 int j;
2121
2122 target->type->read_memory(target, address, 4, thisrun_size / 4, (u8*)buffer);
2123
2124 for (j = 0; j < thisrun_size / 4; j++)
2125 check &= buffer[j];
2126
2127 if (check != 0xffffffff)
2128 {
2129 erased = 0;
2130 break;
2131 }
2132
2133 size -= thisrun_size;
2134 address += thisrun_size;
2135 }
2136
2137 bank->sectors[i].is_erased = erased;
2138 }
2139
2140 free(buffer);
2141 }
2142 else
2143 {
2144 for (i = 0; i < bank->num_sectors; i++)
2145 {
2146 u32 address = bank->base + bank->sectors[i].offset;
2147 u32 size = bank->sectors[i].size;
2148
2149 reg_param_t reg_params[3];
2150 armv4_5_algorithm_t armv4_5_info;
2151
2152 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
2153 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
2154 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
2155
2156 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
2157 buf_set_u32(reg_params[0].value, 0, 32, address);
2158
2159 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
2160 buf_set_u32(reg_params[1].value, 0, 32, size);
2161
2162 init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
2163 buf_set_u32(reg_params[2].value, 0, 32, 0xff);
2164
2165 if ((retval = target->type->run_algorithm(target, 0, NULL, 3, reg_params, cfi_info->erase_check_algorithm->address, cfi_info->erase_check_algorithm->address + 0x10, 10000, &armv4_5_info)) != ERROR_OK)
2166 return ERROR_FLASH_OPERATION_FAILED;
2167
2168 if (buf_get_u32(reg_params[2].value, 0, 32) == 0xff)
2169 bank->sectors[i].is_erased = 1;
2170 else
2171 bank->sectors[i].is_erased = 0;
2172
2173 destroy_reg_param(&reg_params[0]);
2174 destroy_reg_param(&reg_params[1]);
2175 destroy_reg_param(&reg_params[2]);
2176 }
2177 }
2178
2179 return ERROR_OK;
2180 }
2181
2182 int cfi_intel_protect_check(struct flash_bank_s *bank)
2183 {
2184 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2185 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
2186 target_t *target = bank->target;
2187 u8 command[CFI_MAX_BUS_WIDTH];
2188 int i;
2189
2190 /* check if block lock bits are supported on this device */
2191 if (!(pri_ext->blk_status_reg_mask & 0x1))
2192 return ERROR_FLASH_OPERATION_FAILED;
2193
2194 cfi_command(bank, 0x90, command);
2195 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
2196
2197 for (i = 0; i < bank->num_sectors; i++)
2198 {
2199 u8 block_status = cfi_get_u8(bank, i, 0x2);
2200
2201 if (block_status & 1)
2202 bank->sectors[i].is_protected = 1;
2203 else
2204 bank->sectors[i].is_protected = 0;
2205 }
2206
2207 cfi_command(bank, 0xff, command);
2208 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2209
2210 return ERROR_OK;
2211 }
2212
2213 int cfi_spansion_protect_check(struct flash_bank_s *bank)
2214 {
2215 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2216 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2217 target_t *target = bank->target;
2218 u8 command[8];
2219 int i;
2220
2221 cfi_command(bank, 0xaa, command);
2222 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2223
2224 cfi_command(bank, 0x55, command);
2225 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
2226
2227 cfi_command(bank, 0x90, command);
2228 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2229
2230 for (i = 0; i < bank->num_sectors; i++)
2231 {
2232 u8 block_status = cfi_get_u8(bank, i, 0x2);
2233
2234 if (block_status & 1)
2235 bank->sectors[i].is_protected = 1;
2236 else
2237 bank->sectors[i].is_protected = 0;
2238 }
2239
2240 cfi_command(bank, 0xf0, command);
2241 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2242
2243 return ERROR_OK;
2244 }
2245
2246 int cfi_protect_check(struct flash_bank_s *bank)
2247 {
2248 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2249
2250 if (cfi_info->qry[0] != 'Q')
2251 return ERROR_FLASH_BANK_NOT_PROBED;
2252
2253 switch(cfi_info->pri_id)
2254 {
2255 case 1:
2256 case 3:
2257 return cfi_intel_protect_check(bank);
2258 break;
2259 case 2:
2260 return cfi_spansion_protect_check(bank);
2261 break;
2262 default:
2263 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2264 break;
2265 }
2266
2267 return ERROR_OK;
2268 }
2269
2270 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2271 {
2272 int printed;
2273 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2274
2275 if (cfi_info->qry[0] == (char)-1)
2276 {
2277 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2278 return ERROR_OK;
2279 }
2280
2281 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2282 buf += printed;
2283 buf_size -= printed;
2284
2285 printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2286 cfi_info->manufacturer, cfi_info->device_id);
2287 buf += printed;
2288 buf_size -= printed;
2289
2290 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2291 buf += printed;
2292 buf_size -= printed;
2293
2294 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n", (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2295 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2296 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2297 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2298 buf += printed;
2299 buf_size -= printed;
2300
2301 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2302 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2303 buf += printed;
2304 buf_size -= printed;
2305
2306 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2307 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2308 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2309 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2310 buf += printed;
2311 buf_size -= printed;
2312
2313 printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n", 1 << cfi_info->dev_size, cfi_info->interface_desc, cfi_info->max_buf_write_size);
2314 buf += printed;
2315 buf_size -= printed;
2316
2317 switch(cfi_info->pri_id)
2318 {
2319 case 1:
2320 case 3:
2321 cfi_intel_info(bank, buf, buf_size);
2322 break;
2323 case 2:
2324 cfi_spansion_info(bank, buf, buf_size);
2325 break;
2326 default:
2327 ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2328 break;
2329 }
2330
2331 return ERROR_OK;
2332 }
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