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added a couple of LOG_ERROR() messages to improve logfile.
[openocd.git] / src / flash / cfi.c
1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20 #ifdef HAVE_CONFIG_H
21 #include "config.h"
22 #endif
23
24 #include "replacements.h"
25
26 #include "cfi.h"
27 #include "non_cfi.h"
28
29 #include "flash.h"
30 #include "target.h"
31 #include "log.h"
32 #include "armv4_5.h"
33 #include "algorithm.h"
34 #include "binarybuffer.h"
35 #include "types.h"
36
37 #include <stdlib.h>
38 #include <string.h>
39 #include <unistd.h>
40
41 int cfi_register_commands(struct command_context_s *cmd_ctx);
42 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
43 int cfi_erase(struct flash_bank_s *bank, int first, int last);
44 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
45 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
46 int cfi_probe(struct flash_bank_s *bank);
47 int cfi_auto_probe(struct flash_bank_s *bank);
48 int cfi_protect_check(struct flash_bank_s *bank);
49 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
50
51 int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52
53 #define CFI_MAX_BUS_WIDTH 4
54 #define CFI_MAX_CHIP_WIDTH 4
55
56 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
57 #define CFI_MAX_INTEL_CODESIZE 256
58
59 flash_driver_t cfi_flash =
60 {
61 .name = "cfi",
62 .register_commands = cfi_register_commands,
63 .flash_bank_command = cfi_flash_bank_command,
64 .erase = cfi_erase,
65 .protect = cfi_protect,
66 .write = cfi_write,
67 .probe = cfi_probe,
68 .auto_probe = cfi_auto_probe,
69 .erase_check = default_flash_blank_check,
70 .protect_check = cfi_protect_check,
71 .info = cfi_info
72 };
73
74 cfi_unlock_addresses_t cfi_unlock_addresses[] =
75 {
76 [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
77 [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
78 };
79
80 /* CFI fixups foward declarations */
81 void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
82 void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
83 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
84
85 /* fixup after identifying JEDEC manufactuer and ID */
86 cfi_fixup_t cfi_jedec_fixups[] = {
87 {CFI_MFR_SST, 0x00D4, cfi_fixup_non_cfi, NULL},
88 {CFI_MFR_SST, 0x00D5, cfi_fixup_non_cfi, NULL},
89 {CFI_MFR_SST, 0x00D6, cfi_fixup_non_cfi, NULL},
90 {CFI_MFR_SST, 0x00D7, cfi_fixup_non_cfi, NULL},
91 {CFI_MFR_SST, 0x2780, cfi_fixup_non_cfi, NULL},
92 {CFI_MFR_ST, 0x00D5, cfi_fixup_non_cfi, NULL},
93 {CFI_MFR_ST, 0x00D6, cfi_fixup_non_cfi, NULL},
94 {CFI_MFR_AMD, 0x2223, cfi_fixup_non_cfi, NULL},
95 {CFI_MFR_AMD, 0x22ab, cfi_fixup_non_cfi, NULL},
96 {0, 0, NULL, NULL}
97 };
98
99 /* fixup after reading cmdset 0002 primary query table */
100 cfi_fixup_t cfi_0002_fixups[] = {
101 {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
102 {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
103 {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
104 {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
105 {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
106 {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
107 {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
108 {0, 0, NULL, NULL}
109 };
110
111 /* fixup after reading cmdset 0001 primary query table */
112 cfi_fixup_t cfi_0001_fixups[] = {
113 {0, 0, NULL, NULL}
114 };
115
116 void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
117 {
118 cfi_flash_bank_t *cfi_info = bank->driver_priv;
119 cfi_fixup_t *f;
120
121 for (f = fixups; f->fixup; f++)
122 {
123 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
124 ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
125 {
126 f->fixup(bank, f->param);
127 }
128 }
129 }
130
131 /* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
132 __inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
133 {
134 /* while the sector list isn't built, only accesses to sector 0 work */
135 if (sector == 0)
136 return bank->base + offset * bank->bus_width;
137 else
138 {
139 if (!bank->sectors)
140 {
141 LOG_ERROR("BUG: sector list not yet built");
142 exit(-1);
143 }
144 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
145 }
146
147 }
148
149 void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
150 {
151 int i;
152
153 /* clear whole buffer, to ensure bits that exceed the bus_width
154 * are set to zero
155 */
156 for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
157 cmd_buf[i] = 0;
158
159 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
160 {
161 for (i = bank->bus_width; i > 0; i--)
162 {
163 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
164 }
165 }
166 else
167 {
168 for (i = 1; i <= bank->bus_width; i++)
169 {
170 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
171 }
172 }
173 }
174
175 /* read unsigned 8-bit value from the bank
176 * flash banks are expected to be made of similar chips
177 * the query result should be the same for all
178 */
179 u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
180 {
181 target_t *target = bank->target;
182 u8 data[CFI_MAX_BUS_WIDTH];
183
184 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
185
186 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
187 return data[0];
188 else
189 return data[bank->bus_width - 1];
190 }
191
192 /* read unsigned 8-bit value from the bank
193 * in case of a bank made of multiple chips,
194 * the individual values are ORed
195 */
196 u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
197 {
198 target_t *target = bank->target;
199 u8 data[CFI_MAX_BUS_WIDTH];
200 int i;
201
202 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
203
204 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
205 {
206 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
207 data[0] |= data[i];
208
209 return data[0];
210 }
211 else
212 {
213 u8 value = 0;
214 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
215 value |= data[bank->bus_width - 1 - i];
216
217 return value;
218 }
219 }
220
221 u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
222 {
223 target_t *target = bank->target;
224 u8 data[CFI_MAX_BUS_WIDTH * 2];
225
226 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
227
228 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
229 return data[0] | data[bank->bus_width] << 8;
230 else
231 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
232 }
233
234 u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
235 {
236 target_t *target = bank->target;
237 u8 data[CFI_MAX_BUS_WIDTH * 4];
238
239 target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
240
241 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
242 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
243 else
244 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
245 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
246 }
247
248 void cfi_intel_clear_status_register(flash_bank_t *bank)
249 {
250 target_t *target = bank->target;
251 u8 command[8];
252
253 if (target->state != TARGET_HALTED)
254 {
255 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
256 exit(-1);
257 }
258
259 cfi_command(bank, 0x50, command);
260 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
261 }
262
263 u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
264 {
265 u8 status;
266
267 while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
268 {
269 LOG_DEBUG("status: 0x%x", status);
270 usleep(1000);
271 }
272
273 /* mask out bit 0 (reserved) */
274 status = status & 0xfe;
275
276 LOG_DEBUG("status: 0x%x", status);
277
278 if ((status & 0x80) != 0x80)
279 {
280 LOG_ERROR("timeout while waiting for WSM to become ready");
281 }
282 else if (status != 0x80)
283 {
284 LOG_ERROR("status register: 0x%x", status);
285 if (status & 0x2)
286 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
287 if (status & 0x4)
288 LOG_ERROR("Program suspended");
289 if (status & 0x8)
290 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
291 if (status & 0x10)
292 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
293 if (status & 0x20)
294 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
295 if (status & 0x40)
296 LOG_ERROR("Block Erase Suspended");
297
298 cfi_intel_clear_status_register(bank);
299 }
300
301 return status;
302 }
303
304 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
305 {
306 u8 status, oldstatus;
307
308 oldstatus = cfi_get_u8(bank, 0, 0x0);
309
310 do {
311 status = cfi_get_u8(bank, 0, 0x0);
312 if ((status ^ oldstatus) & 0x40) {
313 if (status & 0x20) {
314 oldstatus = cfi_get_u8(bank, 0, 0x0);
315 status = cfi_get_u8(bank, 0, 0x0);
316 if ((status ^ oldstatus) & 0x40) {
317 LOG_ERROR("dq5 timeout, status: 0x%x", status);
318 return(ERROR_FLASH_OPERATION_FAILED);
319 } else {
320 LOG_DEBUG("status: 0x%x", status);
321 return(ERROR_OK);
322 }
323 }
324 } else {
325 LOG_DEBUG("status: 0x%x", status);
326 return(ERROR_OK);
327 }
328
329 oldstatus = status;
330 usleep(1000);
331 } while (timeout-- > 0);
332
333 LOG_ERROR("timeout, status: 0x%x", status);
334
335 return(ERROR_FLASH_BUSY);
336 }
337
338 int cfi_read_intel_pri_ext(flash_bank_t *bank)
339 {
340 cfi_flash_bank_t *cfi_info = bank->driver_priv;
341 cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
342 target_t *target = bank->target;
343 u8 command[8];
344
345 cfi_info->pri_ext = pri_ext;
346
347 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
348 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
349 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
350
351 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
352 {
353 cfi_command(bank, 0xf0, command);
354 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
355 cfi_command(bank, 0xff, command);
356 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
357 LOG_ERROR("Could not read bank flash bank information");
358 return ERROR_FLASH_BANK_INVALID;
359 }
360
361 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
362 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
363
364 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
365
366 pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
367 pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
368 pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
369
370 LOG_DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
371
372 pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
373 pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
374
375 LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
376 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
377 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
378
379 pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
380 if (pri_ext->num_protection_fields != 1)
381 {
382 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
383 }
384
385 pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
386 pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
387 pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
388
389 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
390
391 return ERROR_OK;
392 }
393
394 int cfi_read_spansion_pri_ext(flash_bank_t *bank)
395 {
396 cfi_flash_bank_t *cfi_info = bank->driver_priv;
397 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
398 target_t *target = bank->target;
399 u8 command[8];
400
401 cfi_info->pri_ext = pri_ext;
402
403 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
404 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
405 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
406
407 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
408 {
409 cfi_command(bank, 0xf0, command);
410 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
411 LOG_ERROR("Could not read spansion bank information");
412 return ERROR_FLASH_BANK_INVALID;
413 }
414
415 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
416 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
417
418 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
419
420 pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
421 pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
422 pri_ext->BlkProt = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
423 pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
424 pri_ext->BlkProtUnprot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
425 pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
426 pri_ext->BurstMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
427 pri_ext->PageMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
428 pri_ext->VppMin = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
429 pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
430 pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
431
432 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
433 pri_ext->EraseSuspend, pri_ext->BlkProt);
434
435 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
436 pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
437
438 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
439
440
441 LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
442 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
443 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
444
445 LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
446
447 /* default values for implementation specific workarounds */
448 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
449 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
450 pri_ext->_reversed_geometry = 0;
451
452 return ERROR_OK;
453 }
454
455 int cfi_read_atmel_pri_ext(flash_bank_t *bank)
456 {
457 cfi_atmel_pri_ext_t atmel_pri_ext;
458 cfi_flash_bank_t *cfi_info = bank->driver_priv;
459 cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
460 target_t *target = bank->target;
461 u8 command[8];
462
463 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
464 * but a different primary extended query table.
465 * We read the atmel table, and prepare a valid AMD/Spansion query table.
466 */
467
468 memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));
469
470 cfi_info->pri_ext = pri_ext;
471
472 atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
473 atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
474 atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
475
476 if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
477 {
478 cfi_command(bank, 0xf0, command);
479 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
480 LOG_ERROR("Could not read atmel bank information");
481 return ERROR_FLASH_BANK_INVALID;
482 }
483
484 pri_ext->pri[0] = atmel_pri_ext.pri[0];
485 pri_ext->pri[1] = atmel_pri_ext.pri[1];
486 pri_ext->pri[2] = atmel_pri_ext.pri[2];
487
488 atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
489 atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
490
491 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
492
493 pri_ext->major_version = atmel_pri_ext.major_version;
494 pri_ext->minor_version = atmel_pri_ext.minor_version;
495
496 atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
497 atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
498 atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
499 atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
500
501 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
502 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
503
504 if (atmel_pri_ext.features & 0x02)
505 pri_ext->EraseSuspend = 2;
506
507 if (atmel_pri_ext.bottom_boot)
508 pri_ext->TopBottom = 2;
509 else
510 pri_ext->TopBottom = 3;
511
512 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
513 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
514
515 return ERROR_OK;
516 }
517
518 int cfi_read_0002_pri_ext(flash_bank_t *bank)
519 {
520 cfi_flash_bank_t *cfi_info = bank->driver_priv;
521
522 if (cfi_info->manufacturer == CFI_MFR_ATMEL)
523 {
524 return cfi_read_atmel_pri_ext(bank);
525 }
526 else
527 {
528 return cfi_read_spansion_pri_ext(bank);
529 }
530 }
531
532 int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
533 {
534 int printed;
535 cfi_flash_bank_t *cfi_info = bank->driver_priv;
536 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
537
538 printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
539 buf += printed;
540 buf_size -= printed;
541
542 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
543 pri_ext->pri[1], pri_ext->pri[2],
544 pri_ext->major_version, pri_ext->minor_version);
545 buf += printed;
546 buf_size -= printed;
547
548 printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
549 (pri_ext->SiliconRevision) >> 2,
550 (pri_ext->SiliconRevision) & 0x03);
551 buf += printed;
552 buf_size -= printed;
553
554 printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
555 pri_ext->EraseSuspend,
556 pri_ext->BlkProt);
557 buf += printed;
558 buf_size -= printed;
559
560 printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
561 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
562 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
563
564 return ERROR_OK;
565 }
566
567 int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
568 {
569 int printed;
570 cfi_flash_bank_t *cfi_info = bank->driver_priv;
571 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
572
573 printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
574 buf += printed;
575 buf_size -= printed;
576
577 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
578 buf += printed;
579 buf_size -= printed;
580
581 printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
582 buf += printed;
583 buf_size -= printed;
584
585 printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
586 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
587 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
588 buf += printed;
589 buf_size -= printed;
590
591 printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
592
593 return ERROR_OK;
594 }
595
596 int cfi_register_commands(struct command_context_s *cmd_ctx)
597 {
598 /*command_t *cfi_cmd = */
599 register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
600 /*
601 register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
602 "print part id of cfi flash bank <num>");
603 */
604 return ERROR_OK;
605 }
606
607 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
608 */
609 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
610 {
611 cfi_flash_bank_t *cfi_info;
612 int i;
613
614 if (argc < 6)
615 {
616 LOG_WARNING("incomplete flash_bank cfi configuration");
617 return ERROR_FLASH_BANK_INVALID;
618 }
619
620 if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
621 || (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
622 {
623 LOG_ERROR("chip and bus width have to specified in bytes");
624 return ERROR_FLASH_BANK_INVALID;
625 }
626
627 cfi_info = malloc(sizeof(cfi_flash_bank_t));
628 cfi_info->probed = 0;
629 bank->driver_priv = cfi_info;
630
631 cfi_info->write_algorithm = NULL;
632
633 cfi_info->x16_as_x8 = 0;
634 cfi_info->jedec_probe = 0;
635 cfi_info->not_cfi = 0;
636
637 for (i = 6; i < argc; i++)
638 {
639 if (strcmp(args[i], "x16_as_x8") == 0)
640 {
641 cfi_info->x16_as_x8 = 1;
642 }
643 else if (strcmp(args[i], "jedec_probe") == 0)
644 {
645 cfi_info->jedec_probe = 1;
646 }
647 }
648
649 cfi_info->write_algorithm = NULL;
650
651 /* bank wasn't probed yet */
652 cfi_info->qry[0] = -1;
653
654 return ERROR_OK;
655 }
656
657 int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
658 {
659 cfi_flash_bank_t *cfi_info = bank->driver_priv;
660 target_t *target = bank->target;
661 u8 command[8];
662 int i;
663
664 cfi_intel_clear_status_register(bank);
665
666 for (i = first; i <= last; i++)
667 {
668 cfi_command(bank, 0x20, command);
669 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
670
671 cfi_command(bank, 0xd0, command);
672 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
673
674 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
675 bank->sectors[i].is_erased = 1;
676 else
677 {
678 cfi_command(bank, 0xff, command);
679 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
680
681 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
682 return ERROR_FLASH_OPERATION_FAILED;
683 }
684 }
685
686 cfi_command(bank, 0xff, command);
687 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
688
689 return ERROR_OK;
690 }
691
692 int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
693 {
694 cfi_flash_bank_t *cfi_info = bank->driver_priv;
695 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
696 target_t *target = bank->target;
697 u8 command[8];
698 int i;
699
700 for (i = first; i <= last; i++)
701 {
702 cfi_command(bank, 0xaa, command);
703 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
704
705 cfi_command(bank, 0x55, command);
706 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
707
708 cfi_command(bank, 0x80, command);
709 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
710
711 cfi_command(bank, 0xaa, command);
712 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
713
714 cfi_command(bank, 0x55, command);
715 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
716
717 cfi_command(bank, 0x30, command);
718 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
719
720 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
721 bank->sectors[i].is_erased = 1;
722 else
723 {
724 cfi_command(bank, 0xf0, command);
725 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
726
727 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
728 return ERROR_FLASH_OPERATION_FAILED;
729 }
730 }
731
732 cfi_command(bank, 0xf0, command);
733 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
734
735 return ERROR_OK;
736 }
737
738 int cfi_erase(struct flash_bank_s *bank, int first, int last)
739 {
740 cfi_flash_bank_t *cfi_info = bank->driver_priv;
741
742 if (bank->target->state != TARGET_HALTED)
743 {
744 return ERROR_TARGET_NOT_HALTED;
745 }
746
747 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
748 {
749 return ERROR_FLASH_SECTOR_INVALID;
750 }
751
752 if (cfi_info->qry[0] != 'Q')
753 return ERROR_FLASH_BANK_NOT_PROBED;
754
755 switch(cfi_info->pri_id)
756 {
757 case 1:
758 case 3:
759 return cfi_intel_erase(bank, first, last);
760 break;
761 case 2:
762 return cfi_spansion_erase(bank, first, last);
763 break;
764 default:
765 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
766 break;
767 }
768
769 return ERROR_OK;
770 }
771
772 int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
773 {
774 cfi_flash_bank_t *cfi_info = bank->driver_priv;
775 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
776 target_t *target = bank->target;
777 u8 command[8];
778 int retry = 0;
779 int i;
780
781 /* if the device supports neither legacy lock/unlock (bit 3) nor
782 * instant individual block locking (bit 5).
783 */
784 if (!(pri_ext->feature_support & 0x28))
785 return ERROR_FLASH_OPERATION_FAILED;
786
787 cfi_intel_clear_status_register(bank);
788
789 for (i = first; i <= last; i++)
790 {
791 cfi_command(bank, 0x60, command);
792 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
793 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
794 if (set)
795 {
796 cfi_command(bank, 0x01, command);
797 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
798 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
799 bank->sectors[i].is_protected = 1;
800 }
801 else
802 {
803 cfi_command(bank, 0xd0, command);
804 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
805 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
806 bank->sectors[i].is_protected = 0;
807 }
808
809 /* instant individual block locking doesn't require reading of the status register */
810 if (!(pri_ext->feature_support & 0x20))
811 {
812 /* Clear lock bits operation may take up to 1.4s */
813 cfi_intel_wait_status_busy(bank, 1400);
814 }
815 else
816 {
817 u8 block_status;
818 /* read block lock bit, to verify status */
819 cfi_command(bank, 0x90, command);
820 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
821 block_status = cfi_get_u8(bank, i, 0x2);
822
823 if ((block_status & 0x1) != set)
824 {
825 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
826 cfi_command(bank, 0x70, command);
827 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
828 cfi_intel_wait_status_busy(bank, 10);
829
830 if (retry > 10)
831 return ERROR_FLASH_OPERATION_FAILED;
832 else
833 {
834 i--;
835 retry++;
836 }
837 }
838 }
839 }
840
841 /* if the device doesn't support individual block lock bits set/clear,
842 * all blocks have been unlocked in parallel, so we set those that should be protected
843 */
844 if ((!set) && (!(pri_ext->feature_support & 0x20)))
845 {
846 for (i = 0; i < bank->num_sectors; i++)
847 {
848 if (bank->sectors[i].is_protected == 1)
849 {
850 cfi_intel_clear_status_register(bank);
851
852 cfi_command(bank, 0x60, command);
853 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
854
855 cfi_command(bank, 0x01, command);
856 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
857
858 cfi_intel_wait_status_busy(bank, 100);
859 }
860 }
861 }
862
863 cfi_command(bank, 0xff, command);
864 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
865
866 return ERROR_OK;
867 }
868
869 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
870 {
871 cfi_flash_bank_t *cfi_info = bank->driver_priv;
872
873 if (bank->target->state != TARGET_HALTED)
874 {
875 return ERROR_TARGET_NOT_HALTED;
876 }
877
878 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
879 {
880 return ERROR_FLASH_SECTOR_INVALID;
881 }
882
883 if (cfi_info->qry[0] != 'Q')
884 return ERROR_FLASH_BANK_NOT_PROBED;
885
886 switch(cfi_info->pri_id)
887 {
888 case 1:
889 case 3:
890 cfi_intel_protect(bank, set, first, last);
891 break;
892 default:
893 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
894 break;
895 }
896
897 return ERROR_OK;
898 }
899
900 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
901 static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
902 {
903 /* target_t *target = bank->target; */
904
905 int i;
906
907 /* NOTE:
908 * The data to flash must not be changed in endian! We write a bytestrem in
909 * target byte order already. Only the control and status byte lane of the flash
910 * WSM is interpreted by the CPU in different ways, when read a u16 or u32
911 * word (data seems to be in the upper or lower byte lane for u16 accesses).
912 */
913
914 #if 0
915 if (target->endianness == TARGET_LITTLE_ENDIAN)
916 {
917 #endif
918 /* shift bytes */
919 for (i = 0; i < bank->bus_width - 1; i++)
920 word[i] = word[i + 1];
921 word[bank->bus_width - 1] = byte;
922 #if 0
923 }
924 else
925 {
926 /* shift bytes */
927 for (i = bank->bus_width - 1; i > 0; i--)
928 word[i] = word[i - 1];
929 word[0] = byte;
930 }
931 #endif
932 }
933
934 /* Convert code image to target endian */
935 /* FIXME create general block conversion fcts in target.c?) */
936 static void cfi_fix_code_endian(target_t *target, u8 *dest, const u32 *src, u32 count)
937 {
938 u32 i;
939 for (i=0; i< count; i++)
940 {
941 target_buffer_set_u32(target, dest, *src);
942 dest+=4;
943 src++;
944 }
945 }
946
947 u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
948 {
949 target_t *target = bank->target;
950
951 u8 buf[CFI_MAX_BUS_WIDTH];
952 cfi_command(bank, cmd, buf);
953 switch (bank->bus_width)
954 {
955 case 1 :
956 return buf[0];
957 break;
958 case 2 :
959 return target_buffer_get_u16(target, buf);
960 break;
961 case 4 :
962 return target_buffer_get_u32(target, buf);
963 break;
964 default :
965 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
966 return 0;
967 }
968 }
969
970 int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
971 {
972 cfi_flash_bank_t *cfi_info = bank->driver_priv;
973 target_t *target = bank->target;
974 reg_param_t reg_params[7];
975 armv4_5_algorithm_t armv4_5_info;
976 working_area_t *source;
977 u32 buffer_size = 32768;
978 u32 write_command_val, busy_pattern_val, error_pattern_val;
979
980 /* algorithm register usage:
981 * r0: source address (in RAM)
982 * r1: target address (in Flash)
983 * r2: count
984 * r3: flash write command
985 * r4: status byte (returned to host)
986 * r5: busy test pattern
987 * r6: error test pattern
988 */
989
990 static const u32 word_32_code[] = {
991 0xe4904004, /* loop: ldr r4, [r0], #4 */
992 0xe5813000, /* str r3, [r1] */
993 0xe5814000, /* str r4, [r1] */
994 0xe5914000, /* busy: ldr r4, [r1] */
995 0xe0047005, /* and r7, r4, r5 */
996 0xe1570005, /* cmp r7, r5 */
997 0x1afffffb, /* bne busy */
998 0xe1140006, /* tst r4, r6 */
999 0x1a000003, /* bne done */
1000 0xe2522001, /* subs r2, r2, #1 */
1001 0x0a000001, /* beq done */
1002 0xe2811004, /* add r1, r1 #4 */
1003 0xeafffff2, /* b loop */
1004 0xeafffffe /* done: b -2 */
1005 };
1006
1007 static const u32 word_16_code[] = {
1008 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1009 0xe1c130b0, /* strh r3, [r1] */
1010 0xe1c140b0, /* strh r4, [r1] */
1011 0xe1d140b0, /* busy ldrh r4, [r1] */
1012 0xe0047005, /* and r7, r4, r5 */
1013 0xe1570005, /* cmp r7, r5 */
1014 0x1afffffb, /* bne busy */
1015 0xe1140006, /* tst r4, r6 */
1016 0x1a000003, /* bne done */
1017 0xe2522001, /* subs r2, r2, #1 */
1018 0x0a000001, /* beq done */
1019 0xe2811002, /* add r1, r1 #2 */
1020 0xeafffff2, /* b loop */
1021 0xeafffffe /* done: b -2 */
1022 };
1023
1024 static const u32 word_8_code[] = {
1025 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1026 0xe5c13000, /* strb r3, [r1] */
1027 0xe5c14000, /* strb r4, [r1] */
1028 0xe5d14000, /* busy ldrb r4, [r1] */
1029 0xe0047005, /* and r7, r4, r5 */
1030 0xe1570005, /* cmp r7, r5 */
1031 0x1afffffb, /* bne busy */
1032 0xe1140006, /* tst r4, r6 */
1033 0x1a000003, /* bne done */
1034 0xe2522001, /* subs r2, r2, #1 */
1035 0x0a000001, /* beq done */
1036 0xe2811001, /* add r1, r1 #1 */
1037 0xeafffff2, /* b loop */
1038 0xeafffffe /* done: b -2 */
1039 };
1040 u8 target_code[4*CFI_MAX_INTEL_CODESIZE];
1041 const u32 *target_code_src;
1042 int target_code_size;
1043 int retval = ERROR_OK;
1044
1045
1046 cfi_intel_clear_status_register(bank);
1047
1048 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1049 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1050 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1051
1052 /* If we are setting up the write_algorith, we need target_code_src */
1053 /* if not we only need target_code_size. */
1054 /* */
1055 /* However, we don't want to create multiple code paths, so we */
1056 /* do the unecessary evaluation of target_code_src, which the */
1057 /* compiler will probably nicely optimize away if not needed */
1058
1059 /* prepare algorithm code for target endian */
1060 switch (bank->bus_width)
1061 {
1062 case 1 :
1063 target_code_src = word_8_code;
1064 target_code_size = sizeof(word_8_code);
1065 break;
1066 case 2 :
1067 target_code_src = word_16_code;
1068 target_code_size = sizeof(word_16_code);
1069 break;
1070 case 4 :
1071 target_code_src = word_32_code;
1072 target_code_size = sizeof(word_32_code);
1073 break;
1074 default:
1075 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1076 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1077 }
1078
1079 /* flash write code */
1080 if (!cfi_info->write_algorithm)
1081 {
1082 if ( target_code_size > sizeof(target_code) )
1083 {
1084 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1085 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1086 }
1087 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1088
1089 /* Get memory for block write handler */
1090 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1091 if (retval != ERROR_OK)
1092 {
1093 LOG_WARNING("No working area available, can't do block memory writes");
1094 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1095 };
1096
1097 /* write algorithm code to working area */
1098 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1099 if (retval != ERROR_OK)
1100 {
1101 LOG_ERROR("Unable to write block write code to target");
1102 goto cleanup;
1103 }
1104 }
1105
1106 /* Get a workspace buffer for the data to flash starting with 32k size.
1107 Half size until buffer would be smaller 256 Bytem then fail back */
1108 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1109 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1110 {
1111 buffer_size /= 2;
1112 if (buffer_size <= 256)
1113 {
1114 LOG_WARNING("no large enough working area available, can't do block memory writes");
1115 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1116 goto cleanup;
1117 }
1118 };
1119
1120 /* setup algo registers */
1121 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1122 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1123 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1124 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1125 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1126 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1127 init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1128
1129 /* prepare command and status register patterns */
1130 write_command_val = cfi_command_val(bank, 0x40);
1131 busy_pattern_val = cfi_command_val(bank, 0x80);
1132 error_pattern_val = cfi_command_val(bank, 0x7e);
1133
1134 LOG_INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );
1135
1136 /* Programming main loop */
1137 while (count > 0)
1138 {
1139 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1140 u32 wsm_error;
1141
1142 target_write_buffer(target, source->address, thisrun_count, buffer);
1143
1144 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1145 buf_set_u32(reg_params[1].value, 0, 32, address);
1146 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1147
1148 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1149 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1150 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1151
1152 LOG_INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );
1153
1154 /* Execute algorithm, assume breakpoint for last instruction */
1155 retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params,
1156 cfi_info->write_algorithm->address,
1157 cfi_info->write_algorithm->address + target_code_size - sizeof(u32),
1158 10000, /* 10s should be enough for max. 32k of data */
1159 &armv4_5_info);
1160
1161 /* On failure try a fall back to direct word writes */
1162 if (retval != ERROR_OK)
1163 {
1164 cfi_intel_clear_status_register(bank);
1165 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1166 retval = ERROR_FLASH_OPERATION_FAILED;
1167 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1168 /* FIXME To allow fall back or recovery, we must save the actual status
1169 somewhere, so that a higher level code can start recovery. */
1170 goto cleanup;
1171 }
1172
1173 /* Check return value from algo code */
1174 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1175 if (wsm_error)
1176 {
1177 /* read status register (outputs debug inforation) */
1178 cfi_intel_wait_status_busy(bank, 100);
1179 cfi_intel_clear_status_register(bank);
1180 retval = ERROR_FLASH_OPERATION_FAILED;
1181 goto cleanup;
1182 }
1183
1184 buffer += thisrun_count;
1185 address += thisrun_count;
1186 count -= thisrun_count;
1187 }
1188
1189 /* free up resources */
1190 cleanup:
1191 if (source)
1192 target_free_working_area(target, source);
1193
1194 if (cfi_info->write_algorithm)
1195 {
1196 target_free_working_area(target, cfi_info->write_algorithm);
1197 cfi_info->write_algorithm = NULL;
1198 }
1199
1200 destroy_reg_param(&reg_params[0]);
1201 destroy_reg_param(&reg_params[1]);
1202 destroy_reg_param(&reg_params[2]);
1203 destroy_reg_param(&reg_params[3]);
1204 destroy_reg_param(&reg_params[4]);
1205 destroy_reg_param(&reg_params[5]);
1206 destroy_reg_param(&reg_params[6]);
1207
1208 return retval;
1209 }
1210
1211 int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1212 {
1213 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1214 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1215 target_t *target = bank->target;
1216 reg_param_t reg_params[10];
1217 armv4_5_algorithm_t armv4_5_info;
1218 working_area_t *source;
1219 u32 buffer_size = 32768;
1220 u32 status;
1221 int retval;
1222 int exit_code = ERROR_OK;
1223
1224 /* input parameters - */
1225 /* R0 = source address */
1226 /* R1 = destination address */
1227 /* R2 = number of writes */
1228 /* R3 = flash write command */
1229 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1230 /* output parameters - */
1231 /* R5 = 0x80 ok 0x00 bad */
1232 /* temp registers - */
1233 /* R6 = value read from flash to test status */
1234 /* R7 = holding register */
1235 /* unlock registers - */
1236 /* R8 = unlock1_addr */
1237 /* R9 = unlock1_cmd */
1238 /* R10 = unlock2_addr */
1239 /* R11 = unlock2_cmd */
1240
1241 static const u32 word_32_code[] = {
1242 /* 00008100 <sp_32_code>: */
1243 0xe4905004, /* ldr r5, [r0], #4 */
1244 0xe5889000, /* str r9, [r8] */
1245 0xe58ab000, /* str r11, [r10] */
1246 0xe5883000, /* str r3, [r8] */
1247 0xe5815000, /* str r5, [r1] */
1248 0xe1a00000, /* nop */
1249 /* */
1250 /* 00008110 <sp_32_busy>: */
1251 0xe5916000, /* ldr r6, [r1] */
1252 0xe0257006, /* eor r7, r5, r6 */
1253 0xe0147007, /* ands r7, r4, r7 */
1254 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1255 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1256 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1257 0xe5916000, /* ldr r6, [r1] */
1258 0xe0257006, /* eor r7, r5, r6 */
1259 0xe0147007, /* ands r7, r4, r7 */
1260 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1261 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1262 0x1a000004, /* bne 8154 <sp_32_done> */
1263 /* */
1264 /* 00008140 <sp_32_cont>: */
1265 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1266 0x03a05080, /* moveq r5, #128 ; 0x80 */
1267 0x0a000001, /* beq 8154 <sp_32_done> */
1268 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1269 0xeaffffe8, /* b 8100 <sp_32_code> */
1270 /* */
1271 /* 00008154 <sp_32_done>: */
1272 0xeafffffe /* b 8154 <sp_32_done> */
1273 };
1274
1275 static const u32 word_16_code[] = {
1276 /* 00008158 <sp_16_code>: */
1277 0xe0d050b2, /* ldrh r5, [r0], #2 */
1278 0xe1c890b0, /* strh r9, [r8] */
1279 0xe1cab0b0, /* strh r11, [r10] */
1280 0xe1c830b0, /* strh r3, [r8] */
1281 0xe1c150b0, /* strh r5, [r1] */
1282 0xe1a00000, /* nop (mov r0,r0) */
1283 /* */
1284 /* 00008168 <sp_16_busy>: */
1285 0xe1d160b0, /* ldrh r6, [r1] */
1286 0xe0257006, /* eor r7, r5, r6 */
1287 0xe0147007, /* ands r7, r4, r7 */
1288 0x0a000007, /* beq 8198 <sp_16_cont> */
1289 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1290 0x0afffff9, /* beq 8168 <sp_16_busy> */
1291 0xe1d160b0, /* ldrh r6, [r1] */
1292 0xe0257006, /* eor r7, r5, r6 */
1293 0xe0147007, /* ands r7, r4, r7 */
1294 0x0a000001, /* beq 8198 <sp_16_cont> */
1295 0xe3a05000, /* mov r5, #0 ; 0x0 */
1296 0x1a000004, /* bne 81ac <sp_16_done> */
1297 /* */
1298 /* 00008198 <sp_16_cont>: */
1299 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1300 0x03a05080, /* moveq r5, #128 ; 0x80 */
1301 0x0a000001, /* beq 81ac <sp_16_done> */
1302 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1303 0xeaffffe8, /* b 8158 <sp_16_code> */
1304 /* */
1305 /* 000081ac <sp_16_done>: */
1306 0xeafffffe /* b 81ac <sp_16_done> */
1307 };
1308
1309 static const u32 word_8_code[] = {
1310 /* 000081b0 <sp_16_code_end>: */
1311 0xe4d05001, /* ldrb r5, [r0], #1 */
1312 0xe5c89000, /* strb r9, [r8] */
1313 0xe5cab000, /* strb r11, [r10] */
1314 0xe5c83000, /* strb r3, [r8] */
1315 0xe5c15000, /* strb r5, [r1] */
1316 0xe1a00000, /* nop (mov r0,r0) */
1317 /* */
1318 /* 000081c0 <sp_8_busy>: */
1319 0xe5d16000, /* ldrb r6, [r1] */
1320 0xe0257006, /* eor r7, r5, r6 */
1321 0xe0147007, /* ands r7, r4, r7 */
1322 0x0a000007, /* beq 81f0 <sp_8_cont> */
1323 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1324 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1325 0xe5d16000, /* ldrb r6, [r1] */
1326 0xe0257006, /* eor r7, r5, r6 */
1327 0xe0147007, /* ands r7, r4, r7 */
1328 0x0a000001, /* beq 81f0 <sp_8_cont> */
1329 0xe3a05000, /* mov r5, #0 ; 0x0 */
1330 0x1a000004, /* bne 8204 <sp_8_done> */
1331 /* */
1332 /* 000081f0 <sp_8_cont>: */
1333 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1334 0x03a05080, /* moveq r5, #128 ; 0x80 */
1335 0x0a000001, /* beq 8204 <sp_8_done> */
1336 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1337 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1338 /* */
1339 /* 00008204 <sp_8_done>: */
1340 0xeafffffe /* b 8204 <sp_8_done> */
1341 };
1342
1343 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1344 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1345 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1346
1347 /* flash write code */
1348 if (!cfi_info->write_algorithm)
1349 {
1350 u8 *target_code;
1351 int target_code_size;
1352 const u32 *src;
1353
1354 /* convert bus-width dependent algorithm code to correct endiannes */
1355 switch (bank->bus_width)
1356 {
1357 case 1:
1358 src = word_8_code;
1359 target_code_size = sizeof(word_8_code);
1360 break;
1361 case 2:
1362 src = word_16_code;
1363 target_code_size = sizeof(word_16_code);
1364 break;
1365 case 4:
1366 src = word_32_code;
1367 target_code_size = sizeof(word_32_code);
1368 break;
1369 default:
1370 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1371 return ERROR_FLASH_OPERATION_FAILED;
1372 }
1373 target_code = malloc(target_code_size);
1374 cfi_fix_code_endian(target, target_code, src, target_code_size / 4);
1375
1376 /* allocate working area */
1377 retval=target_alloc_working_area(target, target_code_size,
1378 &cfi_info->write_algorithm);
1379 if (retval != ERROR_OK)
1380 return retval;
1381
1382 /* write algorithm code to working area */
1383 target_write_buffer(target, cfi_info->write_algorithm->address,
1384 target_code_size, target_code);
1385
1386 free(target_code);
1387 }
1388 /* the following code still assumes target code is fixed 24*4 bytes */
1389
1390 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1391 {
1392 buffer_size /= 2;
1393 if (buffer_size <= 256)
1394 {
1395 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1396 if (cfi_info->write_algorithm)
1397 target_free_working_area(target, cfi_info->write_algorithm);
1398
1399 LOG_WARNING("not enough working area available, can't do block memory writes");
1400 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1401 }
1402 };
1403
1404 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1405 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1406 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1407 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1408 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1409 init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1410 init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1411 init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1412 init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1413 init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1414
1415 while (count > 0)
1416 {
1417 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1418
1419 target_write_buffer(target, source->address, thisrun_count, buffer);
1420
1421 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1422 buf_set_u32(reg_params[1].value, 0, 32, address);
1423 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1424 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1425 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1426 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1427 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1428 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1429 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1430
1431 retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params,
1432 cfi_info->write_algorithm->address,
1433 cfi_info->write_algorithm->address + ((24 * 4) - 4),
1434 10000, &armv4_5_info);
1435
1436 status = buf_get_u32(reg_params[5].value, 0, 32);
1437
1438 if ((retval != ERROR_OK) || status != 0x80)
1439 {
1440 LOG_DEBUG("status: 0x%x", status);
1441 exit_code = ERROR_FLASH_OPERATION_FAILED;
1442 break;
1443 }
1444
1445 buffer += thisrun_count;
1446 address += thisrun_count;
1447 count -= thisrun_count;
1448 }
1449
1450 target_free_working_area(target, source);
1451
1452 destroy_reg_param(&reg_params[0]);
1453 destroy_reg_param(&reg_params[1]);
1454 destroy_reg_param(&reg_params[2]);
1455 destroy_reg_param(&reg_params[3]);
1456 destroy_reg_param(&reg_params[4]);
1457 destroy_reg_param(&reg_params[5]);
1458 destroy_reg_param(&reg_params[6]);
1459 destroy_reg_param(&reg_params[7]);
1460 destroy_reg_param(&reg_params[8]);
1461 destroy_reg_param(&reg_params[9]);
1462
1463 return exit_code;
1464 }
1465
1466 int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1467 {
1468 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1469 target_t *target = bank->target;
1470 u8 command[8];
1471
1472 cfi_intel_clear_status_register(bank);
1473 cfi_command(bank, 0x40, command);
1474 target->type->write_memory(target, address, bank->bus_width, 1, command);
1475
1476 target->type->write_memory(target, address, bank->bus_width, 1, word);
1477
1478 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1479 {
1480 cfi_command(bank, 0xff, command);
1481 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1482
1483 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1484 return ERROR_FLASH_OPERATION_FAILED;
1485 }
1486
1487 return ERROR_OK;
1488 }
1489
1490 int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1491 {
1492 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1493 target_t *target = bank->target;
1494 u8 command[8];
1495
1496 /* Calculate buffer size and boundary mask */
1497 u32 buffersize = 1UL << cfi_info->max_buf_write_size;
1498 u32 buffermask = buffersize-1;
1499 u32 bufferwsize;
1500
1501 /* Check for valid range */
1502 if (address & buffermask)
1503 {
1504 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1505 return ERROR_FLASH_OPERATION_FAILED;
1506 }
1507 switch(bank->chip_width)
1508 {
1509 case 4 : bufferwsize = buffersize / 4; break;
1510 case 2 : bufferwsize = buffersize / 2; break;
1511 case 1 : bufferwsize = buffersize; break;
1512 default:
1513 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1514 return ERROR_FLASH_OPERATION_FAILED;
1515 }
1516
1517 /* Check for valid size */
1518 if (wordcount > bufferwsize)
1519 {
1520 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1521 return ERROR_FLASH_OPERATION_FAILED;
1522 }
1523
1524 /* Write to flash buffer */
1525 cfi_intel_clear_status_register(bank);
1526
1527 /* Initiate buffer operation _*/
1528 cfi_command(bank, 0xE8, command);
1529 target->type->write_memory(target, address, bank->bus_width, 1, command);
1530 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1531 {
1532 cfi_command(bank, 0xff, command);
1533 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1534
1535 LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
1536 return ERROR_FLASH_OPERATION_FAILED;
1537 }
1538
1539 /* Write buffer wordcount-1 and data words */
1540 cfi_command(bank, bufferwsize-1, command);
1541 target->type->write_memory(target, address, bank->bus_width, 1, command);
1542
1543 target->type->write_memory(target, address, bank->bus_width, bufferwsize, word);
1544
1545 /* Commit write operation */
1546 cfi_command(bank, 0xd0, command);
1547 target->type->write_memory(target, address, bank->bus_width, 1, command);
1548 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1549 {
1550 cfi_command(bank, 0xff, command);
1551 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1552
1553 LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
1554 return ERROR_FLASH_OPERATION_FAILED;
1555 }
1556
1557 return ERROR_OK;
1558 }
1559
1560 int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1561 {
1562 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1563 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1564 target_t *target = bank->target;
1565 u8 command[8];
1566
1567 cfi_command(bank, 0xaa, command);
1568 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1569
1570 cfi_command(bank, 0x55, command);
1571 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
1572
1573 cfi_command(bank, 0xa0, command);
1574 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1575
1576 target->type->write_memory(target, address, bank->bus_width, 1, word);
1577
1578 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1579 {
1580 cfi_command(bank, 0xf0, command);
1581 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1582
1583 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1584 return ERROR_FLASH_OPERATION_FAILED;
1585 }
1586
1587 return ERROR_OK;
1588 }
1589
1590 int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1591 {
1592 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1593
1594 switch(cfi_info->pri_id)
1595 {
1596 case 1:
1597 case 3:
1598 return cfi_intel_write_word(bank, word, address);
1599 break;
1600 case 2:
1601 return cfi_spansion_write_word(bank, word, address);
1602 break;
1603 default:
1604 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1605 break;
1606 }
1607
1608 return ERROR_FLASH_OPERATION_FAILED;
1609 }
1610
1611 int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1612 {
1613 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1614
1615 switch(cfi_info->pri_id)
1616 {
1617 case 1:
1618 case 3:
1619 return cfi_intel_write_words(bank, word, wordcount, address);
1620 break;
1621 case 2:
1622 /* return cfi_spansion_write_words(bank, word, address); */
1623 LOG_ERROR("cfi primary command set %i unimplemented - FIXME", cfi_info->pri_id);
1624 break;
1625 default:
1626 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1627 break;
1628 }
1629
1630 return ERROR_FLASH_OPERATION_FAILED;
1631 }
1632
1633 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
1634 {
1635 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1636 target_t *target = bank->target;
1637 u32 address = bank->base + offset; /* address of first byte to be programmed */
1638 u32 write_p, copy_p;
1639 int align; /* number of unaligned bytes */
1640 int blk_count; /* number of bus_width bytes for block copy */
1641 u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1642 int i;
1643 int retval;
1644
1645 if (bank->target->state != TARGET_HALTED)
1646 return ERROR_TARGET_NOT_HALTED;
1647
1648 if (offset + count > bank->size)
1649 return ERROR_FLASH_DST_OUT_OF_BANK;
1650
1651 if (cfi_info->qry[0] != 'Q')
1652 return ERROR_FLASH_BANK_NOT_PROBED;
1653
1654 /* start at the first byte of the first word (bus_width size) */
1655 write_p = address & ~(bank->bus_width - 1);
1656 if ((align = address - write_p) != 0)
1657 {
1658 LOG_INFO("Fixup %d unaligned head bytes", align );
1659
1660 for (i = 0; i < bank->bus_width; i++)
1661 current_word[i] = 0;
1662 copy_p = write_p;
1663
1664 /* copy bytes before the first write address */
1665 for (i = 0; i < align; ++i, ++copy_p)
1666 {
1667 u8 byte;
1668 target->type->read_memory(target, copy_p, 1, 1, &byte);
1669 cfi_add_byte(bank, current_word, byte);
1670 }
1671
1672 /* add bytes from the buffer */
1673 for (; (i < bank->bus_width) && (count > 0); i++)
1674 {
1675 cfi_add_byte(bank, current_word, *buffer++);
1676 count--;
1677 copy_p++;
1678 }
1679
1680 /* if the buffer is already finished, copy bytes after the last write address */
1681 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1682 {
1683 u8 byte;
1684 target->type->read_memory(target, copy_p, 1, 1, &byte);
1685 cfi_add_byte(bank, current_word, byte);
1686 }
1687
1688 retval = cfi_write_word(bank, current_word, write_p);
1689 if (retval != ERROR_OK)
1690 return retval;
1691 write_p = copy_p;
1692 }
1693
1694 /* handle blocks of bus_size aligned bytes */
1695 blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1696 switch(cfi_info->pri_id)
1697 {
1698 /* try block writes (fails without working area) */
1699 case 1:
1700 case 3:
1701 retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1702 break;
1703 case 2:
1704 retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1705 break;
1706 default:
1707 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1708 retval = ERROR_FLASH_OPERATION_FAILED;
1709 break;
1710 }
1711 if (retval == ERROR_OK)
1712 {
1713 /* Increment pointers and decrease count on succesful block write */
1714 buffer += blk_count;
1715 write_p += blk_count;
1716 count -= blk_count;
1717 }
1718 else
1719 {
1720 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1721 {
1722 u32 buffersize = 1UL << cfi_info->max_buf_write_size;
1723 u32 buffermask = buffersize-1;
1724 u32 bufferwsize;
1725
1726 switch(bank->chip_width)
1727 {
1728 case 4 : bufferwsize = buffersize / 4; break;
1729 case 2 : bufferwsize = buffersize / 2; break;
1730 case 1 : bufferwsize = buffersize; break;
1731 default:
1732 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1733 return ERROR_FLASH_OPERATION_FAILED;
1734 }
1735
1736 /* fall back to memory writes */
1737 while (count >= bank->bus_width)
1738 {
1739 if ((write_p & 0xff) == 0)
1740 {
1741 LOG_INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
1742 }
1743 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1744 {
1745 retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1746 if (retval != ERROR_OK)
1747 return retval;
1748
1749 buffer += buffersize;
1750 write_p += buffersize;
1751 count -= buffersize;
1752 }
1753 else
1754 {
1755 for (i = 0; i < bank->bus_width; i++)
1756 current_word[i] = 0;
1757
1758 for (i = 0; i < bank->bus_width; i++)
1759 {
1760 cfi_add_byte(bank, current_word, *buffer++);
1761 }
1762
1763 retval = cfi_write_word(bank, current_word, write_p);
1764 if (retval != ERROR_OK)
1765 return retval;
1766
1767 write_p += bank->bus_width;
1768 count -= bank->bus_width;
1769 }
1770 }
1771 }
1772 else
1773 return retval;
1774 }
1775
1776 /* return to read array mode, so we can read from flash again for padding */
1777 cfi_command(bank, 0xf0, current_word);
1778 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1779 cfi_command(bank, 0xff, current_word);
1780 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1781
1782 /* handle unaligned tail bytes */
1783 if (count > 0)
1784 {
1785 LOG_INFO("Fixup %d unaligned tail bytes", count );
1786
1787 copy_p = write_p;
1788 for (i = 0; i < bank->bus_width; i++)
1789 current_word[i] = 0;
1790
1791 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
1792 {
1793 cfi_add_byte(bank, current_word, *buffer++);
1794 count--;
1795 }
1796 for (; i < bank->bus_width; ++i, ++copy_p)
1797 {
1798 u8 byte;
1799 target->type->read_memory(target, copy_p, 1, 1, &byte);
1800 cfi_add_byte(bank, current_word, byte);
1801 }
1802 retval = cfi_write_word(bank, current_word, write_p);
1803 if (retval != ERROR_OK)
1804 return retval;
1805 }
1806
1807 /* return to read array mode */
1808 cfi_command(bank, 0xf0, current_word);
1809 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1810 cfi_command(bank, 0xff, current_word);
1811 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1812
1813 return ERROR_OK;
1814 }
1815
1816 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
1817 {
1818 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1819 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1820
1821 pri_ext->_reversed_geometry = 1;
1822 }
1823
1824 void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
1825 {
1826 int i;
1827 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1828 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1829
1830 if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
1831 {
1832 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
1833
1834 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
1835 {
1836 int j = (cfi_info->num_erase_regions - 1) - i;
1837 u32 swap;
1838
1839 swap = cfi_info->erase_region_info[i];
1840 cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
1841 cfi_info->erase_region_info[j] = swap;
1842 }
1843 }
1844 }
1845
1846 void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
1847 {
1848 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1849 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1850 cfi_unlock_addresses_t *unlock_addresses = param;
1851
1852 pri_ext->_unlock1 = unlock_addresses->unlock1;
1853 pri_ext->_unlock2 = unlock_addresses->unlock2;
1854 }
1855
1856 int cfi_probe(struct flash_bank_s *bank)
1857 {
1858 cfi_flash_bank_t *cfi_info = bank->driver_priv;
1859 target_t *target = bank->target;
1860 u8 command[8];
1861 int num_sectors = 0;
1862 int i;
1863 int sector = 0;
1864 u32 offset = 0;
1865 u32 unlock1 = 0x555;
1866 u32 unlock2 = 0x2aa;
1867
1868 if (bank->target->state != TARGET_HALTED)
1869 {
1870 return ERROR_TARGET_NOT_HALTED;
1871 }
1872
1873 cfi_info->probed = 0;
1874
1875 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
1876 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
1877 */
1878 if (cfi_info->jedec_probe)
1879 {
1880 unlock1 = 0x5555;
1881 unlock2 = 0x2aaa;
1882 }
1883
1884 /* switch to read identifier codes mode ("AUTOSELECT") */
1885 cfi_command(bank, 0xaa, command);
1886 target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1887 cfi_command(bank, 0x55, command);
1888 target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command);
1889 cfi_command(bank, 0x90, command);
1890 target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1891
1892 if (bank->chip_width == 1)
1893 {
1894 u8 manufacturer, device_id;
1895 target_read_u8(target, bank->base + 0x0, &manufacturer);
1896 target_read_u8(target, bank->base + 0x1, &device_id);
1897 cfi_info->manufacturer = manufacturer;
1898 cfi_info->device_id = device_id;
1899 }
1900 else if (bank->chip_width == 2)
1901 {
1902 target_read_u16(target, bank->base + 0x0, &cfi_info->manufacturer);
1903 target_read_u16(target, bank->base + 0x2, &cfi_info->device_id);
1904 }
1905
1906 /* switch back to read array mode */
1907 cfi_command(bank, 0xf0, command);
1908 target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
1909 cfi_command(bank, 0xff, command);
1910 target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
1911
1912 cfi_fixup(bank, cfi_jedec_fixups);
1913
1914 /* query only if this is a CFI compatible flash,
1915 * otherwise the relevant info has already been filled in
1916 */
1917 if (cfi_info->not_cfi == 0)
1918 {
1919 /* enter CFI query mode
1920 * according to JEDEC Standard No. 68.01,
1921 * a single bus sequence with address = 0x55, data = 0x98 should put
1922 * the device into CFI query mode.
1923 *
1924 * SST flashes clearly violate this, and we will consider them incompatbile for now
1925 */
1926 cfi_command(bank, 0x98, command);
1927 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
1928
1929 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
1930 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
1931 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
1932
1933 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
1934
1935 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
1936 {
1937 cfi_command(bank, 0xf0, command);
1938 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1939 cfi_command(bank, 0xff, command);
1940 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1941 LOG_ERROR("Could not probe bank");
1942 return ERROR_FLASH_BANK_INVALID;
1943 }
1944
1945 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
1946 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
1947 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
1948 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
1949
1950 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
1951
1952 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
1953 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
1954 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
1955 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
1956 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
1957 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
1958 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
1959 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
1960 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
1961 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
1962 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
1963 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
1964
1965 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
1966 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
1967 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
1968 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
1969 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
1970 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
1971 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
1972 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
1973 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
1974 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
1975 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
1976
1977 cfi_info->dev_size = cfi_query_u8(bank, 0, 0x27);
1978 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
1979 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
1980 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
1981
1982 LOG_DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
1983
1984 if (((1 << cfi_info->dev_size) * bank->bus_width / bank->chip_width) != bank->size)
1985 {
1986 LOG_WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, 1 << cfi_info->dev_size);
1987 }
1988
1989 if (cfi_info->num_erase_regions)
1990 {
1991 cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
1992 for (i = 0; i < cfi_info->num_erase_regions; i++)
1993 {
1994 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
1995 LOG_DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
1996 }
1997 }
1998 else
1999 {
2000 cfi_info->erase_region_info = NULL;
2001 }
2002
2003 /* We need to read the primary algorithm extended query table before calculating
2004 * the sector layout to be able to apply fixups
2005 */
2006 switch(cfi_info->pri_id)
2007 {
2008 /* Intel command set (standard and extended) */
2009 case 0x0001:
2010 case 0x0003:
2011 cfi_read_intel_pri_ext(bank);
2012 break;
2013 /* AMD/Spansion, Atmel, ... command set */
2014 case 0x0002:
2015 cfi_read_0002_pri_ext(bank);
2016 break;
2017 default:
2018 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2019 break;
2020 }
2021
2022 /* return to read array mode
2023 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2024 */
2025 cfi_command(bank, 0xf0, command);
2026 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2027 cfi_command(bank, 0xff, command);
2028 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2029 }
2030
2031 /* apply fixups depending on the primary command set */
2032 switch(cfi_info->pri_id)
2033 {
2034 /* Intel command set (standard and extended) */
2035 case 0x0001:
2036 case 0x0003:
2037 cfi_fixup(bank, cfi_0001_fixups);
2038 break;
2039 /* AMD/Spansion, Atmel, ... command set */
2040 case 0x0002:
2041 cfi_fixup(bank, cfi_0002_fixups);
2042 break;
2043 default:
2044 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2045 break;
2046 }
2047
2048 if (cfi_info->num_erase_regions == 0)
2049 {
2050 /* a device might have only one erase block, spanning the whole device */
2051 bank->num_sectors = 1;
2052 bank->sectors = malloc(sizeof(flash_sector_t));
2053
2054 bank->sectors[sector].offset = 0x0;
2055 bank->sectors[sector].size = bank->size;
2056 bank->sectors[sector].is_erased = -1;
2057 bank->sectors[sector].is_protected = -1;
2058 }
2059 else
2060 {
2061 for (i = 0; i < cfi_info->num_erase_regions; i++)
2062 {
2063 num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2064 }
2065
2066 bank->num_sectors = num_sectors;
2067 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
2068
2069 for (i = 0; i < cfi_info->num_erase_regions; i++)
2070 {
2071 int j;
2072 for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2073 {
2074 bank->sectors[sector].offset = offset;
2075 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2076 offset += bank->sectors[sector].size;
2077 bank->sectors[sector].is_erased = -1;
2078 bank->sectors[sector].is_protected = -1;
2079 sector++;
2080 }
2081 }
2082 }
2083
2084 cfi_info->probed = 1;
2085
2086 return ERROR_OK;
2087 }
2088
2089 int cfi_auto_probe(struct flash_bank_s *bank)
2090 {
2091 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2092 if (cfi_info->probed)
2093 return ERROR_OK;
2094 return cfi_probe(bank);
2095 }
2096
2097
2098 int cfi_intel_protect_check(struct flash_bank_s *bank)
2099 {
2100 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2101 cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
2102 target_t *target = bank->target;
2103 u8 command[CFI_MAX_BUS_WIDTH];
2104 int i;
2105
2106 /* check if block lock bits are supported on this device */
2107 if (!(pri_ext->blk_status_reg_mask & 0x1))
2108 return ERROR_FLASH_OPERATION_FAILED;
2109
2110 cfi_command(bank, 0x90, command);
2111 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
2112
2113 for (i = 0; i < bank->num_sectors; i++)
2114 {
2115 u8 block_status = cfi_get_u8(bank, i, 0x2);
2116
2117 if (block_status & 1)
2118 bank->sectors[i].is_protected = 1;
2119 else
2120 bank->sectors[i].is_protected = 0;
2121 }
2122
2123 cfi_command(bank, 0xff, command);
2124 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2125
2126 return ERROR_OK;
2127 }
2128
2129 int cfi_spansion_protect_check(struct flash_bank_s *bank)
2130 {
2131 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2132 cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2133 target_t *target = bank->target;
2134 u8 command[8];
2135 int i;
2136
2137 cfi_command(bank, 0xaa, command);
2138 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2139
2140 cfi_command(bank, 0x55, command);
2141 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
2142
2143 cfi_command(bank, 0x90, command);
2144 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2145
2146 for (i = 0; i < bank->num_sectors; i++)
2147 {
2148 u8 block_status = cfi_get_u8(bank, i, 0x2);
2149
2150 if (block_status & 1)
2151 bank->sectors[i].is_protected = 1;
2152 else
2153 bank->sectors[i].is_protected = 0;
2154 }
2155
2156 cfi_command(bank, 0xf0, command);
2157 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2158
2159 return ERROR_OK;
2160 }
2161
2162 int cfi_protect_check(struct flash_bank_s *bank)
2163 {
2164 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2165
2166 if (bank->target->state != TARGET_HALTED)
2167 {
2168 return ERROR_TARGET_NOT_HALTED;
2169 }
2170
2171 if (cfi_info->qry[0] != 'Q')
2172 return ERROR_FLASH_BANK_NOT_PROBED;
2173
2174 switch(cfi_info->pri_id)
2175 {
2176 case 1:
2177 case 3:
2178 return cfi_intel_protect_check(bank);
2179 break;
2180 case 2:
2181 return cfi_spansion_protect_check(bank);
2182 break;
2183 default:
2184 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2185 break;
2186 }
2187
2188 return ERROR_OK;
2189 }
2190
2191 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2192 {
2193 int printed;
2194 cfi_flash_bank_t *cfi_info = bank->driver_priv;
2195
2196 if (cfi_info->qry[0] == (char)-1)
2197 {
2198 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2199 return ERROR_OK;
2200 }
2201
2202 if (cfi_info->not_cfi == 0)
2203 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2204 else
2205 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2206 buf += printed;
2207 buf_size -= printed;
2208
2209 printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2210 cfi_info->manufacturer, cfi_info->device_id);
2211 buf += printed;
2212 buf_size -= printed;
2213
2214 if (cfi_info->not_cfi == 0)
2215 {
2216 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2217 buf += printed;
2218 buf_size -= printed;
2219
2220 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2221 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2222 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2223 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2224 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2225 buf += printed;
2226 buf_size -= printed;
2227
2228 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2229 1 << cfi_info->word_write_timeout_typ,
2230 1 << cfi_info->buf_write_timeout_typ,
2231 1 << cfi_info->block_erase_timeout_typ,
2232 1 << cfi_info->chip_erase_timeout_typ);
2233 buf += printed;
2234 buf_size -= printed;
2235
2236 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2237 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2238 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2239 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2240 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2241 buf += printed;
2242 buf_size -= printed;
2243
2244 printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n",
2245 1 << cfi_info->dev_size,
2246 cfi_info->interface_desc,
2247 cfi_info->max_buf_write_size);
2248 buf += printed;
2249 buf_size -= printed;
2250
2251 switch(cfi_info->pri_id)
2252 {
2253 case 1:
2254 case 3:
2255 cfi_intel_info(bank, buf, buf_size);
2256 break;
2257 case 2:
2258 cfi_spansion_info(bank, buf, buf_size);
2259 break;
2260 default:
2261 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2262 break;
2263 }
2264 }
2265
2266 return ERROR_OK;
2267 }
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