use COMMAND_HANDLER macro to define all commands
[openocd.git] / src / flash / lpc2900.c
1 /***************************************************************************
2 * Copyright (C) 2009 by *
3 * Rolf Meeser <rolfm_9dq@yahoo.de> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20
21 #ifdef HAVE_CONFIG_H
22 #include "config.h"
23 #endif
24
25
26 #include "image.h"
27
28 #include "lpc2900.h"
29 #include "binarybuffer.h"
30 #include "armv4_5.h"
31
32
33 /* 1024 bytes */
34 #define KiB 1024
35
36 /* Some flash constants */
37 #define FLASH_PAGE_SIZE 512 /* bytes */
38 #define FLASH_ERASE_TIME 100000 /* microseconds */
39 #define FLASH_PROGRAM_TIME 1000 /* microseconds */
40
41 /* Chip ID / Feature Registers */
42 #define CHIPID 0xE0000000 /* Chip ID */
43 #define FEAT0 0xE0000100 /* Chip feature 0 */
44 #define FEAT1 0xE0000104 /* Chip feature 1 */
45 #define FEAT2 0xE0000108 /* Chip feature 2 (contains flash size indicator) */
46 #define FEAT3 0xE000010C /* Chip feature 3 */
47
48 #define EXPECTED_CHIPID 0x209CE02B /* Chip ID of all LPC2900 devices */
49
50 /* Flash/EEPROM Control Registers */
51 #define FCTR 0x20200000 /* Flash control */
52 #define FPTR 0x20200008 /* Flash program-time */
53 #define FTCTR 0x2020000C /* Flash test control */
54 #define FBWST 0x20200010 /* Flash bridge wait-state */
55 #define FCRA 0x2020001C /* Flash clock divider */
56 #define FMSSTART 0x20200020 /* Flash Built-In Selft Test start address */
57 #define FMSSTOP 0x20200024 /* Flash Built-In Selft Test stop address */
58 #define FMS16 0x20200028 /* Flash 16-bit signature */
59 #define FMSW0 0x2020002C /* Flash 128-bit signature Word 0 */
60 #define FMSW1 0x20200030 /* Flash 128-bit signature Word 1 */
61 #define FMSW2 0x20200034 /* Flash 128-bit signature Word 2 */
62 #define FMSW3 0x20200038 /* Flash 128-bit signature Word 3 */
63
64 #define EECMD 0x20200080 /* EEPROM command */
65 #define EEADDR 0x20200084 /* EEPROM address */
66 #define EEWDATA 0x20200088 /* EEPROM write data */
67 #define EERDATA 0x2020008C /* EEPROM read data */
68 #define EEWSTATE 0x20200090 /* EEPROM wait state */
69 #define EECLKDIV 0x20200094 /* EEPROM clock divider */
70 #define EEPWRDWN 0x20200098 /* EEPROM power-down/start */
71 #define EEMSSTART 0x2020009C /* EEPROM BIST start address */
72 #define EEMSSTOP 0x202000A0 /* EEPROM BIST stop address */
73 #define EEMSSIG 0x202000A4 /* EEPROM 24-bit BIST signature */
74
75 #define INT_CLR_ENABLE 0x20200FD8 /* Flash/EEPROM interrupt clear enable */
76 #define INT_SET_ENABLE 0x20200FDC /* Flash/EEPROM interrupt set enable */
77 #define INT_STATUS 0x20200FE0 /* Flash/EEPROM interrupt status */
78 #define INT_ENABLE 0x20200FE4 /* Flash/EEPROM interrupt enable */
79 #define INT_CLR_STATUS 0x20200FE8 /* Flash/EEPROM interrupt clear status */
80 #define INT_SET_STATUS 0x20200FEC /* Flash/EEPROM interrupt set status */
81
82 /* Interrupt sources */
83 #define INTSRC_END_OF_PROG (1 << 28)
84 #define INTSRC_END_OF_BIST (1 << 27)
85 #define INTSRC_END_OF_RDWR (1 << 26)
86 #define INTSRC_END_OF_MISR (1 << 2)
87 #define INTSRC_END_OF_BURN (1 << 1)
88 #define INTSRC_END_OF_ERASE (1 << 0)
89
90
91 /* FCTR bits */
92 #define FCTR_FS_LOADREQ (1 << 15)
93 #define FCTR_FS_CACHECLR (1 << 14)
94 #define FCTR_FS_CACHEBYP (1 << 13)
95 #define FCTR_FS_PROGREQ (1 << 12)
96 #define FCTR_FS_RLS (1 << 11)
97 #define FCTR_FS_PDL (1 << 10)
98 #define FCTR_FS_PD (1 << 9)
99 #define FCTR_FS_WPB (1 << 7)
100 #define FCTR_FS_ISS (1 << 6)
101 #define FCTR_FS_RLD (1 << 5)
102 #define FCTR_FS_DCR (1 << 4)
103 #define FCTR_FS_WEB (1 << 2)
104 #define FCTR_FS_WRE (1 << 1)
105 #define FCTR_FS_CS (1 << 0)
106 /* FPTR bits */
107 #define FPTR_EN_T (1 << 15)
108 /* FTCTR bits */
109 #define FTCTR_FS_BYPASS_R (1 << 29)
110 #define FTCTR_FS_BYPASS_W (1 << 28)
111 /* FMSSTOP bits */
112 #define FMSSTOP_MISR_START (1 << 17)
113 /* EEMSSTOP bits */
114 #define EEMSSTOP_STRTBIST (1 << 31)
115
116 /* Index sector */
117 #define ISS_CUSTOMER_START1 (0x830)
118 #define ISS_CUSTOMER_END1 (0xA00)
119 #define ISS_CUSTOMER_SIZE1 (ISS_CUSTOMER_END1 - ISS_CUSTOMER_START1)
120 #define ISS_CUSTOMER_NWORDS1 (ISS_CUSTOMER_SIZE1 / 4)
121 #define ISS_CUSTOMER_START2 (0xA40)
122 #define ISS_CUSTOMER_END2 (0xC00)
123 #define ISS_CUSTOMER_SIZE2 (ISS_CUSTOMER_END2 - ISS_CUSTOMER_START2)
124 #define ISS_CUSTOMER_NWORDS2 (ISS_CUSTOMER_SIZE2 / 4)
125 #define ISS_CUSTOMER_SIZE (ISS_CUSTOMER_SIZE1 + ISS_CUSTOMER_SIZE2)
126
127
128
129 /**
130 * Private data for \c lpc2900 flash driver.
131 */
132 typedef struct lpc2900_flash_bank_s
133 {
134 /**
135 * Holds the value read from CHIPID register.
136 * The driver will not load if the chipid doesn't match the expected
137 * value of 0x209CE02B of the LPC2900 family. A probe will only be done
138 * if the chipid does not yet contain the expected value.
139 */
140 uint32_t chipid;
141
142 /**
143 * String holding device name.
144 * This string is set by the probe function to the type number of the
145 * device. It takes the form "LPC29xx".
146 */
147 char * target_name;
148
149 /**
150 * System clock frequency.
151 * Holds the clock frequency in Hz, as passed by the configuration file
152 * to the <tt>flash bank</tt> command.
153 */
154 uint32_t clk_sys_fmc;
155
156 /**
157 * Flag to indicate that dangerous operations are possible.
158 * This flag can be set by passing the correct password to the
159 * <tt>lpc2900 password</tt> command. If set, other dangerous commands,
160 * which operate on the index sector, can be executed.
161 */
162 uint32_t risky;
163
164 /**
165 * Maximum contiguous block of internal SRAM (bytes).
166 * Autodetected by the driver. Not the total amount of SRAM, only the
167 * the largest \em contiguous block!
168 */
169 uint32_t max_ram_block;
170
171 } lpc2900_flash_bank_t;
172
173
174 static uint32_t lpc2900_wait_status(flash_bank_t *bank, uint32_t mask, int timeout);
175 static void lpc2900_setup(struct flash_bank_s *bank);
176 static uint32_t lpc2900_is_ready(struct flash_bank_s *bank);
177 static uint32_t lpc2900_read_security_status(struct flash_bank_s *bank);
178 static uint32_t lpc2900_run_bist128(struct flash_bank_s *bank,
179 uint32_t addr_from, uint32_t addr_to,
180 uint32_t (*signature)[4] );
181 static uint32_t lpc2900_address2sector(struct flash_bank_s *bank, uint32_t offset);
182 static uint32_t lpc2900_calc_tr( uint32_t clock, uint32_t time );
183
184
185 /*********************** Helper functions **************************/
186
187
188 /**
189 * Wait for an event in mask to occur in INT_STATUS.
190 *
191 * Return when an event occurs, or after a timeout.
192 *
193 * @param[in] bank Pointer to the flash bank descriptor
194 * @param[in] mask Mask to be used for INT_STATUS
195 * @param[in] timeout Timeout in ms
196 */
197 static uint32_t lpc2900_wait_status( flash_bank_t *bank,
198 uint32_t mask,
199 int timeout )
200 {
201 uint32_t int_status;
202 target_t *target = bank->target;
203
204
205 do
206 {
207 alive_sleep(1);
208 timeout--;
209 target_read_u32(target, INT_STATUS, &int_status);
210 }
211 while( ((int_status & mask) == 0) && (timeout != 0) );
212
213 if (timeout == 0)
214 {
215 LOG_DEBUG("Timeout!");
216 return ERROR_FLASH_OPERATION_FAILED;
217 }
218
219 return ERROR_OK;
220 }
221
222
223
224 /**
225 * Set up the flash for erase/program operations.
226 *
227 * Enable the flash, and set the correct CRA clock of 66 kHz.
228 *
229 * @param bank Pointer to the flash bank descriptor
230 */
231 static void lpc2900_setup( struct flash_bank_s *bank )
232 {
233 uint32_t fcra;
234 lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
235
236
237 /* Power up the flash block */
238 target_write_u32( bank->target, FCTR, FCTR_FS_WEB | FCTR_FS_CS );
239
240
241 fcra = (lpc2900_info->clk_sys_fmc / (3 * 66000)) - 1;
242 target_write_u32( bank->target, FCRA, fcra );
243 }
244
245
246
247 /**
248 * Check if device is ready.
249 *
250 * Check if device is ready for flash operation:
251 * Must have been successfully probed.
252 * Must be halted.
253 */
254 static uint32_t lpc2900_is_ready( struct flash_bank_s *bank )
255 {
256 lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
257
258 if( lpc2900_info->chipid != EXPECTED_CHIPID )
259 {
260 return ERROR_FLASH_BANK_NOT_PROBED;
261 }
262
263 if( bank->target->state != TARGET_HALTED )
264 {
265 LOG_ERROR( "Target not halted" );
266 return ERROR_TARGET_NOT_HALTED;
267 }
268
269 return ERROR_OK;
270 }
271
272
273 /**
274 * Read the status of sector security from the index sector.
275 *
276 * @param bank Pointer to the flash bank descriptor
277 */
278 static uint32_t lpc2900_read_security_status( struct flash_bank_s *bank )
279 {
280 uint32_t status;
281 if( (status = lpc2900_is_ready( bank )) != ERROR_OK )
282 {
283 return status;
284 }
285
286 target_t *target = bank->target;
287
288 /* Enable ISS access */
289 target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB | FCTR_FS_ISS);
290
291 /* Read the relevant block of memory from the ISS sector */
292 uint32_t iss_secured_field[ 0x230/16 ][ 4 ];
293 target_read_memory(target, bank->base + 0xC00, 4, 0x230/4,
294 (uint8_t *)iss_secured_field);
295
296 /* Disable ISS access */
297 target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB);
298
299 /* Check status of each sector. Note that the sector numbering in the LPC2900
300 * is different from the logical sector numbers used in OpenOCD!
301 * Refer to the user manual for details.
302 *
303 * All zeros (16x 0x00) are treated as a secured sector (is_protected = 1)
304 * All ones (16x 0xFF) are treated as a non-secured sector (is_protected = 0)
305 * Anything else is undefined (is_protected = -1). This is treated as
306 * a protected sector!
307 */
308 int sector;
309 int index;
310 for( sector = 0; sector < bank->num_sectors; sector++ )
311 {
312 /* Convert logical sector number to physical sector number */
313 if( sector <= 4 )
314 {
315 index = sector + 11;
316 }
317 else if( sector <= 7 )
318 {
319 index = sector + 27;
320 }
321 else
322 {
323 index = sector - 8;
324 }
325
326 bank->sectors[sector].is_protected = -1;
327
328 if (
329 (iss_secured_field[index][0] == 0x00000000) &&
330 (iss_secured_field[index][1] == 0x00000000) &&
331 (iss_secured_field[index][2] == 0x00000000) &&
332 (iss_secured_field[index][3] == 0x00000000) )
333 {
334 bank->sectors[sector].is_protected = 1;
335 }
336
337 if (
338 (iss_secured_field[index][0] == 0xFFFFFFFF) &&
339 (iss_secured_field[index][1] == 0xFFFFFFFF) &&
340 (iss_secured_field[index][2] == 0xFFFFFFFF) &&
341 (iss_secured_field[index][3] == 0xFFFFFFFF) )
342 {
343 bank->sectors[sector].is_protected = 0;
344 }
345 }
346
347 return ERROR_OK;
348 }
349
350
351 /**
352 * Use BIST to calculate a 128-bit hash value over a range of flash.
353 *
354 * @param bank Pointer to the flash bank descriptor
355 * @param addr_from
356 * @param addr_to
357 * @param signature
358 */
359 static uint32_t lpc2900_run_bist128(struct flash_bank_s *bank,
360 uint32_t addr_from,
361 uint32_t addr_to,
362 uint32_t (*signature)[4] )
363 {
364 target_t *target = bank->target;
365
366 /* Clear END_OF_MISR interrupt status */
367 target_write_u32( target, INT_CLR_STATUS, INTSRC_END_OF_MISR );
368
369 /* Start address */
370 target_write_u32( target, FMSSTART, addr_from >> 4);
371 /* End address, and issue start command */
372 target_write_u32( target, FMSSTOP, (addr_to >> 4) | FMSSTOP_MISR_START );
373
374 /* Poll for end of operation. Calculate a reasonable timeout. */
375 if( lpc2900_wait_status( bank, INTSRC_END_OF_MISR, 1000 ) != ERROR_OK )
376 {
377 return ERROR_FLASH_OPERATION_FAILED;
378 }
379
380 /* Return the signature */
381 target_read_memory( target, FMSW0, 4, 4, (uint8_t *)signature );
382
383 return ERROR_OK;
384 }
385
386
387 /**
388 * Return sector number for given address.
389 *
390 * Return the (logical) sector number for a given relative address.
391 * No sanity check is done. It assumed that the address is valid.
392 *
393 * @param bank Pointer to the flash bank descriptor
394 * @param offset Offset address relative to bank start
395 */
396 static uint32_t lpc2900_address2sector( struct flash_bank_s *bank,
397 uint32_t offset )
398 {
399 uint32_t address = bank->base + offset;
400
401
402 /* Run through all sectors of this bank */
403 int sector;
404 for( sector = 0; sector < bank->num_sectors; sector++ )
405 {
406 /* Return immediately if address is within the current sector */
407 if( address < (bank->sectors[sector].offset + bank->sectors[sector].size) )
408 {
409 return sector;
410 }
411 }
412
413 /* We should never come here. If we do, return an arbitrary sector number. */
414 return 0;
415 }
416
417
418
419
420 /**
421 * Write one page to the index sector.
422 *
423 * @param bank Pointer to the flash bank descriptor
424 * @param pagenum Page number (0...7)
425 * @param page Page array (FLASH_PAGE_SIZE bytes)
426 */
427 static int lpc2900_write_index_page( struct flash_bank_s *bank,
428 int pagenum,
429 uint8_t (*page)[FLASH_PAGE_SIZE] )
430 {
431 /* Only pages 4...7 are user writable */
432 if ((pagenum < 4) || (pagenum > 7))
433 {
434 LOG_ERROR("Refuse to burn index sector page %d", pagenum);
435 return ERROR_COMMAND_ARGUMENT_INVALID;
436 }
437
438 /* Get target, and check if it's halted */
439 target_t *target = bank->target;
440 if( target->state != TARGET_HALTED )
441 {
442 LOG_ERROR( "Target not halted" );
443 return ERROR_TARGET_NOT_HALTED;
444 }
445
446 /* Private info */
447 lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
448
449 /* Enable flash block and set the correct CRA clock of 66 kHz */
450 lpc2900_setup( bank );
451
452 /* Un-protect the index sector */
453 target_write_u32( target, bank->base, 0 );
454 target_write_u32( target, FCTR,
455 FCTR_FS_LOADREQ | FCTR_FS_WPB | FCTR_FS_ISS |
456 FCTR_FS_WEB | FCTR_FS_WRE | FCTR_FS_CS );
457
458 /* Set latch load mode */
459 target_write_u32( target, FCTR,
460 FCTR_FS_ISS | FCTR_FS_WEB | FCTR_FS_WRE | FCTR_FS_CS );
461
462 /* Write whole page to flash data latches */
463 if( target_write_memory( target,
464 bank->base + pagenum * FLASH_PAGE_SIZE,
465 4, FLASH_PAGE_SIZE / 4, (uint8_t *)page) != ERROR_OK )
466 {
467 LOG_ERROR("Index sector write failed @ page %d", pagenum);
468 target_write_u32( target, FCTR, FCTR_FS_CS | FCTR_FS_WEB );
469
470 return ERROR_FLASH_OPERATION_FAILED;
471 }
472
473 /* Clear END_OF_BURN interrupt status */
474 target_write_u32( target, INT_CLR_STATUS, INTSRC_END_OF_BURN );
475
476 /* Set the program/erase time to FLASH_PROGRAM_TIME */
477 target_write_u32(target, FPTR,
478 FPTR_EN_T | lpc2900_calc_tr( lpc2900_info->clk_sys_fmc,
479 FLASH_PROGRAM_TIME ));
480
481 /* Trigger flash write */
482 target_write_u32( target, FCTR,
483 FCTR_FS_PROGREQ | FCTR_FS_ISS |
484 FCTR_FS_WPB | FCTR_FS_WRE | FCTR_FS_CS );
485
486 /* Wait for the end of the write operation. If it's not over after one
487 * second, something went dreadfully wrong... :-(
488 */
489 if (lpc2900_wait_status(bank, INTSRC_END_OF_BURN, 1000) != ERROR_OK)
490 {
491 LOG_ERROR("Index sector write failed @ page %d", pagenum);
492 target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB);
493
494 return ERROR_FLASH_OPERATION_FAILED;
495 }
496
497 target_write_u32( target, FCTR, FCTR_FS_CS | FCTR_FS_WEB );
498
499 return ERROR_OK;
500 }
501
502
503
504 /**
505 * Calculate FPTR.TR register value for desired program/erase time.
506 *
507 * @param clock System clock in Hz
508 * @param time Program/erase time in µs
509 */
510 static uint32_t lpc2900_calc_tr( uint32_t clock, uint32_t time )
511 {
512 /* ((time[µs]/1e6) * f[Hz]) + 511
513 * FPTR.TR = -------------------------------
514 * 512
515 *
516 * The result is the
517 */
518
519 uint32_t tr_val = (uint32_t)((((time / 1e6) * clock) + 511.0) / 512.0);
520
521 return tr_val;
522 }
523
524
525 /*********************** Private flash commands **************************/
526
527
528 /**
529 * Command to determine the signature of the whole flash.
530 *
531 * Uses the Built-In-Self-Test (BIST) to generate a 128-bit hash value
532 * of the flash content.
533 */
534 COMMAND_HANDLER(lpc2900_handle_signature_command)
535 {
536 uint32_t status;
537 uint32_t signature[4];
538
539
540 if( argc < 1 )
541 {
542 LOG_WARNING( "Too few arguments. Call: lpc2900 signature <bank#>" );
543 return ERROR_FLASH_BANK_INVALID;
544 }
545
546 flash_bank_t *bank;
547 int retval = flash_command_get_bank_by_num(cmd_ctx, args[0], &bank);
548 if (ERROR_OK != retval)
549 return retval;
550
551 if( bank->target->state != TARGET_HALTED )
552 {
553 LOG_ERROR( "Target not halted" );
554 return ERROR_TARGET_NOT_HALTED;
555 }
556
557 /* Run BIST over whole flash range */
558 if( (status = lpc2900_run_bist128( bank,
559 bank->base,
560 bank->base + (bank->size - 1),
561 &signature)
562 ) != ERROR_OK )
563 {
564 return status;
565 }
566
567 command_print( cmd_ctx, "signature: 0x%8.8" PRIx32
568 ":0x%8.8" PRIx32
569 ":0x%8.8" PRIx32
570 ":0x%8.8" PRIx32,
571 signature[3], signature[2], signature[1], signature[0] );
572
573 return ERROR_OK;
574 }
575
576
577
578 /**
579 * Store customer info in file.
580 *
581 * Read customer info from index sector, and store that block of data into
582 * a disk file. The format is binary.
583 */
584 COMMAND_HANDLER(lpc2900_handle_read_custom_command)
585 {
586 if( argc < 2 )
587 {
588 return ERROR_COMMAND_SYNTAX_ERROR;
589 }
590
591 flash_bank_t *bank;
592 int retval = flash_command_get_bank_by_num(cmd_ctx, args[0], &bank);
593 if (ERROR_OK != retval)
594 return retval;
595
596 lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
597 lpc2900_info->risky = 0;
598
599 /* Get target, and check if it's halted */
600 target_t *target = bank->target;
601 if( target->state != TARGET_HALTED )
602 {
603 LOG_ERROR( "Target not halted" );
604 return ERROR_TARGET_NOT_HALTED;
605 }
606
607 /* Storage for customer info. Read in two parts */
608 uint32_t customer[ ISS_CUSTOMER_NWORDS1 + ISS_CUSTOMER_NWORDS2 ];
609
610 /* Enable access to index sector */
611 target_write_u32( target, FCTR, FCTR_FS_CS | FCTR_FS_WEB | FCTR_FS_ISS );
612
613 /* Read two parts */
614 target_read_memory( target, bank->base+ISS_CUSTOMER_START1, 4,
615 ISS_CUSTOMER_NWORDS1,
616 (uint8_t *)&customer[0] );
617 target_read_memory( target, bank->base+ISS_CUSTOMER_START2, 4,
618 ISS_CUSTOMER_NWORDS2,
619 (uint8_t *)&customer[ISS_CUSTOMER_NWORDS1] );
620
621 /* Deactivate access to index sector */
622 target_write_u32( target, FCTR, FCTR_FS_CS | FCTR_FS_WEB );
623
624 /* Try and open the file */
625 fileio_t fileio;
626 const char *filename = args[1];
627 int ret = fileio_open( &fileio, filename, FILEIO_WRITE, FILEIO_BINARY );
628 if( ret != ERROR_OK )
629 {
630 LOG_WARNING( "Could not open file %s", filename );
631 return ret;
632 }
633
634 uint32_t nwritten;
635 ret = fileio_write( &fileio, sizeof(customer),
636 (const uint8_t *)customer, &nwritten );
637 if( ret != ERROR_OK )
638 {
639 LOG_ERROR( "Write operation to file %s failed", filename );
640 fileio_close( &fileio );
641 return ret;
642 }
643
644 fileio_close( &fileio );
645
646 return ERROR_OK;
647 }
648
649
650
651
652 /**
653 * Enter password to enable potentially dangerous options.
654 */
655 COMMAND_HANDLER(lpc2900_handle_password_command)
656 {
657 if (argc < 2)
658 {
659 return ERROR_COMMAND_SYNTAX_ERROR;
660 }
661
662 flash_bank_t *bank;
663 int retval = flash_command_get_bank_by_num(cmd_ctx, args[0], &bank);
664 if (ERROR_OK != retval)
665 return retval;
666
667 lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
668
669 #define ISS_PASSWORD "I_know_what_I_am_doing"
670
671 lpc2900_info->risky = !strcmp( args[1], ISS_PASSWORD );
672
673 if( !lpc2900_info->risky )
674 {
675 command_print(cmd_ctx, "Wrong password (use '%s')", ISS_PASSWORD);
676 return ERROR_COMMAND_ARGUMENT_INVALID;
677 }
678
679 command_print(cmd_ctx,
680 "Potentially dangerous operation allowed in next command!");
681
682 return ERROR_OK;
683 }
684
685
686
687 /**
688 * Write customer info from file to the index sector.
689 */
690 COMMAND_HANDLER(lpc2900_handle_write_custom_command)
691 {
692 if (argc < 2)
693 {
694 return ERROR_COMMAND_SYNTAX_ERROR;
695 }
696
697 flash_bank_t *bank;
698 int retval = flash_command_get_bank_by_num(cmd_ctx, args[0], &bank);
699 if (ERROR_OK != retval)
700 return retval;
701
702 lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
703
704 /* Check if command execution is allowed. */
705 if( !lpc2900_info->risky )
706 {
707 command_print( cmd_ctx, "Command execution not allowed!" );
708 return ERROR_COMMAND_ARGUMENT_INVALID;
709 }
710 lpc2900_info->risky = 0;
711
712 /* Get target, and check if it's halted */
713 target_t *target = bank->target;
714 if (target->state != TARGET_HALTED)
715 {
716 LOG_ERROR("Target not halted");
717 return ERROR_TARGET_NOT_HALTED;
718 }
719
720 /* The image will always start at offset 0 */
721 image_t image;
722 image.base_address_set = 1;
723 image.base_address = 0;
724 image.start_address_set = 0;
725
726 const char *filename = args[1];
727 const char *type = (argc >= 3) ? args[2] : NULL;
728 retval = image_open(&image, filename, type);
729 if (retval != ERROR_OK)
730 {
731 return retval;
732 }
733
734 /* Do a sanity check: The image must be exactly the size of the customer
735 programmable area. Any other size is rejected. */
736 if( image.num_sections != 1 )
737 {
738 LOG_ERROR("Only one section allowed in image file.");
739 return ERROR_COMMAND_SYNTAX_ERROR;
740 }
741 if( (image.sections[0].base_address != 0) ||
742 (image.sections[0].size != ISS_CUSTOMER_SIZE) )
743 {
744 LOG_ERROR("Incorrect image file size. Expected %d, "
745 "got %" PRIu32,
746 ISS_CUSTOMER_SIZE, image.sections[0].size);
747 return ERROR_COMMAND_SYNTAX_ERROR;
748 }
749
750 /* Well boys, I reckon this is it... */
751
752 /* Customer info is split into two blocks in pages 4 and 5. */
753 uint8_t page[FLASH_PAGE_SIZE];
754
755 /* Page 4 */
756 uint32_t offset = ISS_CUSTOMER_START1 % FLASH_PAGE_SIZE;
757 memset( page, 0xff, FLASH_PAGE_SIZE );
758 uint32_t size_read;
759 retval = image_read_section( &image, 0, 0,
760 ISS_CUSTOMER_SIZE1, &page[offset], &size_read);
761 if( retval != ERROR_OK )
762 {
763 LOG_ERROR("couldn't read from file '%s'", filename);
764 image_close(&image);
765 return retval;
766 }
767 if( (retval = lpc2900_write_index_page( bank, 4, &page )) != ERROR_OK )
768 {
769 image_close(&image);
770 return retval;
771 }
772
773 /* Page 5 */
774 offset = ISS_CUSTOMER_START2 % FLASH_PAGE_SIZE;
775 memset( page, 0xff, FLASH_PAGE_SIZE );
776 retval = image_read_section( &image, 0, ISS_CUSTOMER_SIZE1,
777 ISS_CUSTOMER_SIZE2, &page[offset], &size_read);
778 if( retval != ERROR_OK )
779 {
780 LOG_ERROR("couldn't read from file '%s'", filename);
781 image_close(&image);
782 return retval;
783 }
784 if( (retval = lpc2900_write_index_page( bank, 5, &page )) != ERROR_OK )
785 {
786 image_close(&image);
787 return retval;
788 }
789
790 image_close(&image);
791
792 return ERROR_OK;
793 }
794
795
796
797 /**
798 * Activate 'sector security' for a range of sectors.
799 */
800 COMMAND_HANDLER(lpc2900_handle_secure_sector_command)
801 {
802 if (argc < 3)
803 {
804 return ERROR_COMMAND_SYNTAX_ERROR;
805 }
806
807 /* Get the bank descriptor */
808 flash_bank_t *bank;
809 int retval = flash_command_get_bank_by_num(cmd_ctx, args[0], &bank);
810 if (ERROR_OK != retval)
811 return retval;
812
813 lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
814
815 /* Check if command execution is allowed. */
816 if( !lpc2900_info->risky )
817 {
818 command_print( cmd_ctx, "Command execution not allowed! "
819 "(use 'password' command first)");
820 return ERROR_COMMAND_ARGUMENT_INVALID;
821 }
822 lpc2900_info->risky = 0;
823
824 /* Read sector range, and do a sanity check. */
825 int first, last;
826 COMMAND_PARSE_NUMBER(int, args[1], first);
827 COMMAND_PARSE_NUMBER(int, args[2], last);
828 if( (first >= bank->num_sectors) ||
829 (last >= bank->num_sectors) ||
830 (first > last) )
831 {
832 command_print( cmd_ctx, "Illegal sector range" );
833 return ERROR_COMMAND_ARGUMENT_INVALID;
834 }
835
836 uint8_t page[FLASH_PAGE_SIZE];
837 int sector;
838
839 /* Sectors in page 6 */
840 if( (first <= 4) || (last >= 8) )
841 {
842 memset( &page, 0xff, FLASH_PAGE_SIZE );
843 for( sector = first; sector <= last; sector++ )
844 {
845 if( sector <= 4 )
846 {
847 memset( &page[0xB0 + 16*sector], 0, 16 );
848 }
849 else if( sector >= 8 )
850 {
851 memset( &page[0x00 + 16*(sector - 8)], 0, 16 );
852 }
853 }
854
855 if( (retval = lpc2900_write_index_page( bank, 6, &page )) != ERROR_OK )
856 {
857 LOG_ERROR("failed to update index sector page 6");
858 return retval;
859 }
860 }
861
862 /* Sectors in page 7 */
863 if( (first <= 7) && (last >= 5) )
864 {
865 memset( &page, 0xff, FLASH_PAGE_SIZE );
866 for( sector = first; sector <= last; sector++ )
867 {
868 if( (sector >= 5) && (sector <= 7) )
869 {
870 memset( &page[0x00 + 16*(sector - 5)], 0, 16 );
871 }
872 }
873
874 if( (retval = lpc2900_write_index_page( bank, 7, &page )) != ERROR_OK )
875 {
876 LOG_ERROR("failed to update index sector page 7");
877 return retval;
878 }
879 }
880
881 command_print( cmd_ctx,
882 "Sectors security will become effective after next power cycle");
883
884 /* Update the sector security status */
885 if ( lpc2900_read_security_status(bank) != ERROR_OK )
886 {
887 LOG_ERROR( "Cannot determine sector security status" );
888 return ERROR_FLASH_OPERATION_FAILED;
889 }
890
891 return ERROR_OK;
892 }
893
894
895
896 /**
897 * Activate JTAG protection.
898 */
899 COMMAND_HANDLER(lpc2900_handle_secure_jtag_command)
900 {
901 if (argc < 1)
902 {
903 return ERROR_COMMAND_SYNTAX_ERROR;
904 }
905
906 /* Get the bank descriptor */
907 flash_bank_t *bank;
908 int retval = flash_command_get_bank_by_num(cmd_ctx, args[0], &bank);
909 if (ERROR_OK != retval)
910 return retval;
911
912 lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
913
914 /* Check if command execution is allowed. */
915 if( !lpc2900_info->risky )
916 {
917 command_print( cmd_ctx, "Command execution not allowed! "
918 "(use 'password' command first)");
919 return ERROR_COMMAND_ARGUMENT_INVALID;
920 }
921 lpc2900_info->risky = 0;
922
923 /* Prepare page */
924 uint8_t page[FLASH_PAGE_SIZE];
925 memset( &page, 0xff, FLASH_PAGE_SIZE );
926
927
928 /* Insert "soft" protection word */
929 page[0x30 + 15] = 0x7F;
930 page[0x30 + 11] = 0x7F;
931 page[0x30 + 7] = 0x7F;
932 page[0x30 + 3] = 0x7F;
933
934 /* Write to page 5 */
935 if( (retval = lpc2900_write_index_page( bank, 5, &page ))
936 != ERROR_OK )
937 {
938 LOG_ERROR("failed to update index sector page 5");
939 return retval;
940 }
941
942 LOG_INFO("JTAG security set. Good bye!");
943
944 return ERROR_OK;
945 }
946
947
948
949 /*********************** Flash interface functions **************************/
950
951
952 /**
953 * Register private command handlers.
954 */
955 static int lpc2900_register_commands(struct command_context_s *cmd_ctx)
956 {
957 command_t *lpc2900_cmd = register_command(cmd_ctx, NULL, "lpc2900",
958 NULL, COMMAND_ANY, NULL);
959
960 register_command(
961 cmd_ctx,
962 lpc2900_cmd,
963 "signature",
964 lpc2900_handle_signature_command,
965 COMMAND_EXEC,
966 "<bank> | "
967 "print device signature of flash bank");
968
969 register_command(
970 cmd_ctx,
971 lpc2900_cmd,
972 "read_custom",
973 lpc2900_handle_read_custom_command,
974 COMMAND_EXEC,
975 "<bank> <filename> | "
976 "read customer information from index sector to file");
977
978 register_command(
979 cmd_ctx,
980 lpc2900_cmd,
981 "password",
982 lpc2900_handle_password_command,
983 COMMAND_EXEC,
984 "<bank> <password> | "
985 "enter password to enable 'dangerous' options");
986
987 register_command(
988 cmd_ctx,
989 lpc2900_cmd,
990 "write_custom",
991 lpc2900_handle_write_custom_command,
992 COMMAND_EXEC,
993 "<bank> <filename> [<type>] | "
994 "write customer info from file to index sector");
995
996 register_command(
997 cmd_ctx,
998 lpc2900_cmd,
999 "secure_sector",
1000 lpc2900_handle_secure_sector_command,
1001 COMMAND_EXEC,
1002 "<bank> <first> <last> | "
1003 "activate sector security for a range of sectors");
1004
1005 register_command(
1006 cmd_ctx,
1007 lpc2900_cmd,
1008 "secure_jtag",
1009 lpc2900_handle_secure_jtag_command,
1010 COMMAND_EXEC,
1011 "<bank> <level> | "
1012 "activate JTAG security");
1013
1014 return ERROR_OK;
1015 }
1016
1017
1018 /// Evaluate flash bank command.
1019 static int lpc2900_flash_bank_command(struct command_context_s *cmd_ctx,
1020 char *cmd, char **args, int argc,
1021 struct flash_bank_s *bank)
1022 {
1023 lpc2900_flash_bank_t *lpc2900_info;
1024
1025 if (argc < 6)
1026 {
1027 LOG_WARNING("incomplete flash_bank LPC2900 configuration");
1028 return ERROR_FLASH_BANK_INVALID;
1029 }
1030
1031 lpc2900_info = malloc(sizeof(lpc2900_flash_bank_t));
1032 bank->driver_priv = lpc2900_info;
1033
1034 /* Get flash clock.
1035 * Reject it if we can't meet the requirements for program time
1036 * (if clock too slow), or for erase time (clock too fast).
1037 */
1038 uint32_t clk_sys_fmc;
1039 COMMAND_PARSE_NUMBER(u32, args[6], clk_sys_fmc);
1040 lpc2900_info->clk_sys_fmc = clk_sys_fmc * 1000;
1041
1042 uint32_t clock_limit;
1043 /* Check program time limit */
1044 clock_limit = 512000000l / FLASH_PROGRAM_TIME;
1045 if (lpc2900_info->clk_sys_fmc < clock_limit)
1046 {
1047 LOG_WARNING("flash clock must be at least %" PRIu32 " kHz",
1048 (clock_limit / 1000));
1049 return ERROR_FLASH_BANK_INVALID;
1050 }
1051
1052 /* Check erase time limit */
1053 clock_limit = (uint32_t)((32767.0 * 512.0 * 1e6) / FLASH_ERASE_TIME);
1054 if (lpc2900_info->clk_sys_fmc > clock_limit)
1055 {
1056 LOG_WARNING("flash clock must be a maximum of %" PRIu32" kHz",
1057 (clock_limit / 1000));
1058 return ERROR_FLASH_BANK_INVALID;
1059 }
1060
1061 /* Chip ID will be obtained by probing the device later */
1062 lpc2900_info->chipid = 0;
1063
1064 return ERROR_OK;
1065 }
1066
1067
1068 /**
1069 * Erase sector(s).
1070 *
1071 * @param bank Pointer to the flash bank descriptor
1072 * @param first First sector to be erased
1073 * @param last Last sector (including) to be erased
1074 */
1075 static int lpc2900_erase(struct flash_bank_s *bank, int first, int last)
1076 {
1077 uint32_t status;
1078 int sector;
1079 int last_unsecured_sector;
1080 target_t *target = bank->target;
1081 lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
1082
1083
1084 status = lpc2900_is_ready(bank);
1085 if (status != ERROR_OK)
1086 {
1087 return status;
1088 }
1089
1090 /* Sanity check on sector range */
1091 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
1092 {
1093 LOG_INFO("Bad sector range");
1094 return ERROR_FLASH_SECTOR_INVALID;
1095 }
1096
1097 /* Update the info about secured sectors */
1098 lpc2900_read_security_status( bank );
1099
1100 /* The selected sector range might include secured sectors. An attempt
1101 * to erase such a sector will cause the erase to fail also for unsecured
1102 * sectors. It is necessary to determine the last unsecured sector now,
1103 * because we have to treat the last relevant sector in the list in
1104 * a special way.
1105 */
1106 last_unsecured_sector = -1;
1107 for (sector = first; sector <= last; sector++)
1108 {
1109 if ( !bank->sectors[sector].is_protected )
1110 {
1111 last_unsecured_sector = sector;
1112 }
1113 }
1114
1115 /* Exit now, in case of the rare constellation where all sectors in range
1116 * are secured. This is regarded a success, since erasing/programming of
1117 * secured sectors shall be handled transparently.
1118 */
1119 if ( last_unsecured_sector == -1 )
1120 {
1121 return ERROR_OK;
1122 }
1123
1124 /* Enable flash block and set the correct CRA clock of 66 kHz */
1125 lpc2900_setup(bank);
1126
1127 /* Clear END_OF_ERASE interrupt status */
1128 target_write_u32(target, INT_CLR_STATUS, INTSRC_END_OF_ERASE);
1129
1130 /* Set the program/erase timer to FLASH_ERASE_TIME */
1131 target_write_u32(target, FPTR,
1132 FPTR_EN_T | lpc2900_calc_tr( lpc2900_info->clk_sys_fmc,
1133 FLASH_ERASE_TIME ));
1134
1135 /* Sectors are marked for erasure, then erased all together */
1136 for (sector = first; sector <= last_unsecured_sector; sector++)
1137 {
1138 /* Only mark sectors that aren't secured. Any attempt to erase a group
1139 * of sectors will fail if any single one of them is secured!
1140 */
1141 if ( !bank->sectors[sector].is_protected )
1142 {
1143 /* Unprotect the sector */
1144 target_write_u32(target, bank->sectors[sector].offset, 0);
1145 target_write_u32(target, FCTR,
1146 FCTR_FS_LOADREQ | FCTR_FS_WPB |
1147 FCTR_FS_WEB | FCTR_FS_WRE | FCTR_FS_CS);
1148
1149 /* Mark the sector for erasure. The last sector in the list
1150 triggers the erasure. */
1151 target_write_u32(target, bank->sectors[sector].offset, 0);
1152 if ( sector == last_unsecured_sector )
1153 {
1154 target_write_u32(target, FCTR,
1155 FCTR_FS_PROGREQ | FCTR_FS_WPB | FCTR_FS_CS);
1156 }
1157 else
1158 {
1159 target_write_u32(target, FCTR,
1160 FCTR_FS_LOADREQ | FCTR_FS_WPB |
1161 FCTR_FS_WEB | FCTR_FS_CS);
1162 }
1163 }
1164 }
1165
1166 /* Wait for the end of the erase operation. If it's not over after two seconds,
1167 * something went dreadfully wrong... :-(
1168 */
1169 if( lpc2900_wait_status(bank, INTSRC_END_OF_ERASE, 2000) != ERROR_OK )
1170 {
1171 return ERROR_FLASH_OPERATION_FAILED;
1172 }
1173
1174 /* Normal flash operating mode */
1175 target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB);
1176
1177 return ERROR_OK;
1178 }
1179
1180
1181
1182 static int lpc2900_protect(struct flash_bank_s *bank, int set, int first, int last)
1183 {
1184 /* This command is not supported.
1185 * "Protection" in LPC2900 terms is handled transparently. Sectors will
1186 * automatically be unprotected as needed.
1187 * Instead we use the concept of sector security. A secured sector is shown
1188 * as "protected" in OpenOCD. Sector security is a permanent feature, and
1189 * cannot be disabled once activated.
1190 */
1191
1192 return ERROR_OK;
1193 }
1194
1195
1196 /**
1197 * Write data to flash.
1198 *
1199 * @param bank Pointer to the flash bank descriptor
1200 * @param buffer Buffer with data
1201 * @param offset Start address (relative to bank start)
1202 * @param count Number of bytes to be programmed
1203 */
1204 static int lpc2900_write(struct flash_bank_s *bank, uint8_t *buffer,
1205 uint32_t offset, uint32_t count)
1206 {
1207 uint8_t page[FLASH_PAGE_SIZE];
1208 uint32_t status;
1209 uint32_t num_bytes;
1210 target_t *target = bank->target;
1211 lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
1212 int sector;
1213 int retval;
1214
1215 static const uint32_t write_target_code[] = {
1216 /* Set auto latch mode: FCTR=CS|WRE|WEB */
1217 0xe3a0a007, /* loop mov r10, #0x007 */
1218 0xe583a000, /* str r10,[r3,#0] */
1219
1220 /* Load complete page into latches */
1221 0xe3a06020, /* mov r6,#(512/16) */
1222 0xe8b00f00, /* next ldmia r0!,{r8-r11} */
1223 0xe8a10f00, /* stmia r1!,{r8-r11} */
1224 0xe2566001, /* subs r6,#1 */
1225 0x1afffffb, /* bne next */
1226
1227 /* Clear END_OF_BURN interrupt status */
1228 0xe3a0a002, /* mov r10,#(1 << 1) */
1229 0xe583afe8, /* str r10,[r3,#0xfe8] */
1230
1231 /* Set the erase time to FLASH_PROGRAM_TIME */
1232 0xe5834008, /* str r4,[r3,#8] */
1233
1234 /* Trigger flash write
1235 FCTR = CS | WRE | WPB | PROGREQ */
1236 0xe3a0a083, /* mov r10,#0x83 */
1237 0xe38aaa01, /* orr r10,#0x1000 */
1238 0xe583a000, /* str r10,[r3,#0] */
1239
1240 /* Wait for end of burn */
1241 0xe593afe0, /* wait ldr r10,[r3,#0xfe0] */
1242 0xe21aa002, /* ands r10,#(1 << 1) */
1243 0x0afffffc, /* beq wait */
1244
1245 /* End? */
1246 0xe2522001, /* subs r2,#1 */
1247 0x1affffed, /* bne loop */
1248
1249 0xeafffffe /* done b done */
1250 };
1251
1252
1253 status = lpc2900_is_ready(bank);
1254 if (status != ERROR_OK)
1255 {
1256 return status;
1257 }
1258
1259 /* Enable flash block and set the correct CRA clock of 66 kHz */
1260 lpc2900_setup(bank);
1261
1262 /* Update the info about secured sectors */
1263 lpc2900_read_security_status( bank );
1264
1265 /* Unprotect all involved sectors */
1266 for (sector = 0; sector < bank->num_sectors; sector++)
1267 {
1268 /* Start address in or before this sector? */
1269 /* End address in or behind this sector? */
1270 if ( ((bank->base + offset) <
1271 (bank->sectors[sector].offset + bank->sectors[sector].size)) &&
1272 ((bank->base + (offset + count - 1)) >= bank->sectors[sector].offset) )
1273 {
1274 /* This sector is involved and needs to be unprotected.
1275 * Don't do it for secured sectors.
1276 */
1277 if ( !bank->sectors[sector].is_protected )
1278 {
1279 target_write_u32(target, bank->sectors[sector].offset, 0);
1280 target_write_u32(target, FCTR,
1281 FCTR_FS_LOADREQ | FCTR_FS_WPB |
1282 FCTR_FS_WEB | FCTR_FS_WRE | FCTR_FS_CS);
1283 }
1284 }
1285 }
1286
1287 /* Set the program/erase time to FLASH_PROGRAM_TIME */
1288 uint32_t prog_time = FPTR_EN_T | lpc2900_calc_tr( lpc2900_info->clk_sys_fmc,
1289 FLASH_PROGRAM_TIME );
1290
1291 /* If there is a working area of reasonable size, use it to program via
1292 a target algorithm. If not, fall back to host programming. */
1293
1294 /* We need some room for target code. */
1295 uint32_t target_code_size = sizeof(write_target_code);
1296
1297 /* Try working area allocation. Start with a large buffer, and try with
1298 reduced size if that fails. */
1299 working_area_t *warea;
1300 uint32_t buffer_size = lpc2900_info->max_ram_block - 1 * KiB;
1301 while( (retval = target_alloc_working_area(target,
1302 buffer_size + target_code_size,
1303 &warea)) != ERROR_OK )
1304 {
1305 /* Try a smaller buffer now, and stop if it's too small. */
1306 buffer_size -= 1 * KiB;
1307 if (buffer_size < 2 * KiB)
1308 {
1309 LOG_INFO( "no (large enough) working area"
1310 ", falling back to host mode" );
1311 warea = NULL;
1312 break;
1313 }
1314 };
1315
1316 if( warea )
1317 {
1318 reg_param_t reg_params[5];
1319 armv4_5_algorithm_t armv4_5_info;
1320
1321 /* We can use target mode. Download the algorithm. */
1322 retval = target_write_buffer( target,
1323 (warea->address)+buffer_size,
1324 target_code_size,
1325 (uint8_t *)write_target_code);
1326 if (retval != ERROR_OK)
1327 {
1328 LOG_ERROR("Unable to write block write code to target");
1329 target_free_all_working_areas(target);
1330 return ERROR_FLASH_OPERATION_FAILED;
1331 }
1332
1333 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1334 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1335 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1336 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1337 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1338
1339 /* Write to flash in large blocks */
1340 while ( count != 0 )
1341 {
1342 uint32_t this_npages;
1343 uint8_t *this_buffer;
1344 int start_sector = lpc2900_address2sector( bank, offset );
1345
1346 /* First page / last page / rest */
1347 if( offset % FLASH_PAGE_SIZE )
1348 {
1349 /* Block doesn't start on page boundary.
1350 Burn first partial page separately. */
1351 memset( &page, 0xff, sizeof(page) );
1352 memcpy( &page[offset % FLASH_PAGE_SIZE],
1353 buffer,
1354 FLASH_PAGE_SIZE - (offset % FLASH_PAGE_SIZE) );
1355 this_npages = 1;
1356 this_buffer = &page[0];
1357 count = count + (offset % FLASH_PAGE_SIZE);
1358 offset = offset - (offset % FLASH_PAGE_SIZE);
1359 }
1360 else if( count < FLASH_PAGE_SIZE )
1361 {
1362 /* Download last incomplete page separately. */
1363 memset( &page, 0xff, sizeof(page) );
1364 memcpy( &page, buffer, count );
1365 this_npages = 1;
1366 this_buffer = &page[0];
1367 count = FLASH_PAGE_SIZE;
1368 }
1369 else
1370 {
1371 /* Download as many full pages as possible */
1372 this_npages = (count < buffer_size) ?
1373 count / FLASH_PAGE_SIZE :
1374 buffer_size / FLASH_PAGE_SIZE;
1375 this_buffer = buffer;
1376
1377 /* Make sure we stop at the next secured sector */
1378 int sector = start_sector + 1;
1379 while( sector < bank->num_sectors )
1380 {
1381 /* Secured? */
1382 if( bank->sectors[sector].is_protected )
1383 {
1384 /* Is that next sector within the current block? */
1385 if( (bank->sectors[sector].offset - bank->base) <
1386 (offset + (this_npages * FLASH_PAGE_SIZE)) )
1387 {
1388 /* Yes! Split the block */
1389 this_npages =
1390 (bank->sectors[sector].offset - bank->base - offset)
1391 / FLASH_PAGE_SIZE;
1392 break;
1393 }
1394 }
1395
1396 sector++;
1397 }
1398 }
1399
1400 /* Skip the current sector if it is secured */
1401 if (bank->sectors[start_sector].is_protected)
1402 {
1403 LOG_DEBUG("Skip secured sector %d",
1404 start_sector);
1405
1406 /* Stop if this is the last sector */
1407 if (start_sector == bank->num_sectors - 1)
1408 {
1409 break;
1410 }
1411
1412 /* Skip */
1413 uint32_t nskip = bank->sectors[start_sector].size -
1414 (offset % bank->sectors[start_sector].size);
1415 offset += nskip;
1416 buffer += nskip;
1417 count = (count >= nskip) ? (count - nskip) : 0;
1418 continue;
1419 }
1420
1421 /* Execute buffer download */
1422 if ((retval = target_write_buffer(target,
1423 warea->address,
1424 this_npages * FLASH_PAGE_SIZE,
1425 this_buffer)) != ERROR_OK)
1426 {
1427 LOG_ERROR("Unable to write data to target");
1428 target_free_all_working_areas(target);
1429 return ERROR_FLASH_OPERATION_FAILED;
1430 }
1431
1432 /* Prepare registers */
1433 buf_set_u32(reg_params[0].value, 0, 32, warea->address);
1434 buf_set_u32(reg_params[1].value, 0, 32, offset);
1435 buf_set_u32(reg_params[2].value, 0, 32, this_npages);
1436 buf_set_u32(reg_params[3].value, 0, 32, FCTR);
1437 buf_set_u32(reg_params[4].value, 0, 32, FPTR_EN_T | prog_time);
1438
1439 /* Execute algorithm, assume breakpoint for last instruction */
1440 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1441 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1442 armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1443
1444 retval = target_run_algorithm(target, 0, NULL, 5, reg_params,
1445 (warea->address) + buffer_size,
1446 (warea->address) + buffer_size + target_code_size - 4,
1447 10000, /* 10s should be enough for max. 16 KiB of data */
1448 &armv4_5_info);
1449
1450 if (retval != ERROR_OK)
1451 {
1452 LOG_ERROR("Execution of flash algorithm failed.");
1453 target_free_all_working_areas(target);
1454 retval = ERROR_FLASH_OPERATION_FAILED;
1455 break;
1456 }
1457
1458 count -= this_npages * FLASH_PAGE_SIZE;
1459 buffer += this_npages * FLASH_PAGE_SIZE;
1460 offset += this_npages * FLASH_PAGE_SIZE;
1461 }
1462
1463 /* Free all resources */
1464 destroy_reg_param(&reg_params[0]);
1465 destroy_reg_param(&reg_params[1]);
1466 destroy_reg_param(&reg_params[2]);
1467 destroy_reg_param(&reg_params[3]);
1468 destroy_reg_param(&reg_params[4]);
1469 target_free_all_working_areas(target);
1470 }
1471 else
1472 {
1473 /* Write to flash memory page-wise */
1474 while ( count != 0 )
1475 {
1476 /* How many bytes do we copy this time? */
1477 num_bytes = (count >= FLASH_PAGE_SIZE) ?
1478 FLASH_PAGE_SIZE - (offset % FLASH_PAGE_SIZE) :
1479 count;
1480
1481 /* Don't do anything with it if the page is in a secured sector. */
1482 if ( !bank->sectors[lpc2900_address2sector(bank, offset)].is_protected )
1483 {
1484 /* Set latch load mode */
1485 target_write_u32(target, FCTR,
1486 FCTR_FS_CS | FCTR_FS_WRE | FCTR_FS_WEB);
1487
1488 /* Always clear the buffer (a little overhead, but who cares) */
1489 memset(page, 0xFF, FLASH_PAGE_SIZE);
1490
1491 /* Copy them to the buffer */
1492 memcpy( &page[offset % FLASH_PAGE_SIZE],
1493 &buffer[offset % FLASH_PAGE_SIZE],
1494 num_bytes );
1495
1496 /* Write whole page to flash data latches */
1497 if (target_write_memory(
1498 target,
1499 bank->base + (offset - (offset % FLASH_PAGE_SIZE)),
1500 4, FLASH_PAGE_SIZE / 4, page) != ERROR_OK)
1501 {
1502 LOG_ERROR("Write failed @ 0x%8.8" PRIx32, offset);
1503 target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB);
1504
1505 return ERROR_FLASH_OPERATION_FAILED;
1506 }
1507
1508 /* Clear END_OF_BURN interrupt status */
1509 target_write_u32(target, INT_CLR_STATUS, INTSRC_END_OF_BURN);
1510
1511 /* Set the programming time */
1512 target_write_u32(target, FPTR, FPTR_EN_T | prog_time);
1513
1514 /* Trigger flash write */
1515 target_write_u32(target, FCTR,
1516 FCTR_FS_CS | FCTR_FS_WRE | FCTR_FS_WPB | FCTR_FS_PROGREQ);
1517
1518 /* Wait for the end of the write operation. If it's not over
1519 * after one second, something went dreadfully wrong... :-(
1520 */
1521 if (lpc2900_wait_status(bank, INTSRC_END_OF_BURN, 1000) != ERROR_OK)
1522 {
1523 LOG_ERROR("Write failed @ 0x%8.8" PRIx32, offset);
1524 target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB);
1525
1526 return ERROR_FLASH_OPERATION_FAILED;
1527 }
1528 }
1529
1530 /* Update pointers and counters */
1531 offset += num_bytes;
1532 buffer += num_bytes;
1533 count -= num_bytes;
1534 }
1535
1536 retval = ERROR_OK;
1537 }
1538
1539 /* Normal flash operating mode */
1540 target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB);
1541
1542 return retval;
1543 }
1544
1545
1546 /**
1547 * Try and identify the device.
1548 *
1549 * Determine type number and its memory layout.
1550 *
1551 * @param bank Pointer to the flash bank descriptor
1552 */
1553 static int lpc2900_probe(struct flash_bank_s *bank)
1554 {
1555 lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
1556 target_t *target = bank->target;
1557 int i = 0;
1558 uint32_t offset;
1559
1560
1561 if (target->state != TARGET_HALTED)
1562 {
1563 LOG_ERROR("Target not halted");
1564 return ERROR_TARGET_NOT_HALTED;
1565 }
1566
1567 /* We want to do this only once. Check if we already have a valid CHIPID,
1568 * because then we will have already successfully probed the device.
1569 */
1570 if (lpc2900_info->chipid == EXPECTED_CHIPID)
1571 {
1572 return ERROR_OK;
1573 }
1574
1575 /* Probing starts with reading the CHIPID register. We will continue only
1576 * if this identifies as an LPC2900 device.
1577 */
1578 target_read_u32(target, CHIPID, &lpc2900_info->chipid);
1579
1580 if (lpc2900_info->chipid != EXPECTED_CHIPID)
1581 {
1582 LOG_WARNING("Device is not an LPC29xx");
1583 return ERROR_FLASH_OPERATION_FAILED;
1584 }
1585
1586 /* It's an LPC29xx device. Now read the feature register FEAT0...FEAT3. */
1587 uint32_t feat0, feat1, feat2, feat3;
1588 target_read_u32(target, FEAT0, &feat0);
1589 target_read_u32(target, FEAT1, &feat1);
1590 target_read_u32(target, FEAT2, &feat2);
1591 target_read_u32(target, FEAT3, &feat3);
1592
1593 /* Base address */
1594 bank->base = 0x20000000;
1595
1596 /* Determine flash layout from FEAT2 register */
1597 uint32_t num_64k_sectors = (feat2 >> 16) & 0xFF;
1598 uint32_t num_8k_sectors = (feat2 >> 0) & 0xFF;
1599 bank->num_sectors = num_64k_sectors + num_8k_sectors;
1600 bank->size = KiB * (64 * num_64k_sectors + 8 * num_8k_sectors);
1601
1602 /* Determine maximum contiguous RAM block */
1603 lpc2900_info->max_ram_block = 16 * KiB;
1604 if( (feat1 & 0x30) == 0x30 )
1605 {
1606 lpc2900_info->max_ram_block = 32 * KiB;
1607 if( (feat1 & 0x0C) == 0x0C )
1608 {
1609 lpc2900_info->max_ram_block = 48 * KiB;
1610 }
1611 }
1612
1613 /* Determine package code and ITCM size */
1614 uint32_t package_code = feat0 & 0x0F;
1615 uint32_t itcm_code = (feat1 >> 16) & 0x1F;
1616
1617 /* Determine the exact type number. */
1618 uint32_t found = 1;
1619 if ( (package_code == 4) && (itcm_code == 5) )
1620 {
1621 /* Old LPC2917 or LPC2919 (non-/01 devices) */
1622 lpc2900_info->target_name = (bank->size == 768*KiB) ? "LPC2919" : "LPC2917";
1623 }
1624 else
1625 {
1626 if ( package_code == 2 )
1627 {
1628 /* 100-pin package */
1629 if ( bank->size == 128*KiB )
1630 {
1631 lpc2900_info->target_name = "LPC2921";
1632 }
1633 else if ( bank->size == 256*KiB )
1634 {
1635 lpc2900_info->target_name = "LPC2923";
1636 }
1637 else if ( bank->size == 512*KiB )
1638 {
1639 lpc2900_info->target_name = "LPC2925";
1640 }
1641 else
1642 {
1643 found = 0;
1644 }
1645 }
1646 else if ( package_code == 4 )
1647 {
1648 /* 144-pin package */
1649 if ( (bank->size == 512*KiB) && (feat3 == 0xFFFFFCF0) )
1650 {
1651 lpc2900_info->target_name = "LPC2917/01";
1652 }
1653 else if ( (bank->size == 512*KiB) && (feat3 == 0xFFFFFFF1) )
1654 {
1655 lpc2900_info->target_name = "LPC2927";
1656 }
1657 else if ( (bank->size == 768*KiB) && (feat3 == 0xFFFFFCF8) )
1658 {
1659 lpc2900_info->target_name = "LPC2919/01";
1660 }
1661 else if ( (bank->size == 768*KiB) && (feat3 == 0xFFFFFFF9) )
1662 {
1663 lpc2900_info->target_name = "LPC2929";
1664 }
1665 else
1666 {
1667 found = 0;
1668 }
1669 }
1670 else if ( package_code == 5 )
1671 {
1672 /* 208-pin package */
1673 lpc2900_info->target_name = (bank->size == 0) ? "LPC2930" : "LPC2939";
1674 }
1675 else
1676 {
1677 found = 0;
1678 }
1679 }
1680
1681 if ( !found )
1682 {
1683 LOG_WARNING("Unknown LPC29xx derivative");
1684 return ERROR_FLASH_OPERATION_FAILED;
1685 }
1686
1687 /* Show detected device */
1688 LOG_INFO("Flash bank %d"
1689 ": Device %s, %" PRIu32
1690 " KiB in %d sectors",
1691 bank->bank_number,
1692 lpc2900_info->target_name, bank->size / KiB,
1693 bank->num_sectors);
1694
1695 /* Flashless devices cannot be handled */
1696 if ( bank->num_sectors == 0 )
1697 {
1698 LOG_WARNING("Flashless device cannot be handled");
1699 return ERROR_FLASH_OPERATION_FAILED;
1700 }
1701
1702 /* Sector layout.
1703 * These are logical sector numbers. When doing real flash operations,
1704 * the logical flash number are translated into the physical flash numbers
1705 * of the device.
1706 */
1707 bank->sectors = malloc(sizeof(flash_sector_t) * bank->num_sectors);
1708
1709 offset = 0;
1710 for (i = 0; i < bank->num_sectors; i++)
1711 {
1712 bank->sectors[i].offset = offset;
1713 bank->sectors[i].is_erased = -1;
1714 bank->sectors[i].is_protected = -1;
1715
1716 if ( i <= 7 )
1717 {
1718 bank->sectors[i].size = 8 * KiB;
1719 }
1720 else if ( i <= 18 )
1721 {
1722 bank->sectors[i].size = 64 * KiB;
1723 }
1724 else
1725 {
1726 /* We shouldn't come here. But there might be a new part out there
1727 * that has more than 19 sectors. Politely ask for a fix then.
1728 */
1729 bank->sectors[i].size = 0;
1730 LOG_ERROR("Never heard about sector %d", i);
1731 }
1732
1733 offset += bank->sectors[i].size;
1734 }
1735
1736 /* Read sector security status */
1737 if ( lpc2900_read_security_status(bank) != ERROR_OK )
1738 {
1739 LOG_ERROR("Cannot determine sector security status");
1740 return ERROR_FLASH_OPERATION_FAILED;
1741 }
1742
1743 return ERROR_OK;
1744 }
1745
1746
1747 /**
1748 * Run a blank check for each sector.
1749 *
1750 * For speed reasons, the device isn't read word by word.
1751 * A hash value is calculated by the hardware ("BIST") for each sector.
1752 * This value is then compared against the known hash of an empty sector.
1753 *
1754 * @param bank Pointer to the flash bank descriptor
1755 */
1756 static int lpc2900_erase_check(struct flash_bank_s *bank)
1757 {
1758 uint32_t status = lpc2900_is_ready(bank);
1759 if (status != ERROR_OK)
1760 {
1761 LOG_INFO("Processor not halted/not probed");
1762 return status;
1763 }
1764
1765 /* Use the BIST (Built-In Selft Test) to generate a signature of each flash
1766 * sector. Compare against the expected signature of an empty sector.
1767 */
1768 int sector;
1769 for ( sector = 0; sector < bank->num_sectors; sector++ )
1770 {
1771 uint32_t signature[4];
1772 if ( (status = lpc2900_run_bist128( bank,
1773 bank->sectors[sector].offset,
1774 bank->sectors[sector].offset +
1775 (bank->sectors[sector].size - 1),
1776 &signature)) != ERROR_OK )
1777 {
1778 return status;
1779 }
1780
1781 /* The expected signatures for an empty sector are different
1782 * for 8 KiB and 64 KiB sectors.
1783 */
1784 if ( bank->sectors[sector].size == 8*KiB )
1785 {
1786 bank->sectors[sector].is_erased =
1787 (signature[3] == 0x01ABAAAA) &&
1788 (signature[2] == 0xAAAAAAAA) &&
1789 (signature[1] == 0xAAAAAAAA) &&
1790 (signature[0] == 0xAAA00AAA);
1791 }
1792 if ( bank->sectors[sector].size == 64*KiB )
1793 {
1794 bank->sectors[sector].is_erased =
1795 (signature[3] == 0x11801222) &&
1796 (signature[2] == 0xB88844FF) &&
1797 (signature[1] == 0x11A22008) &&
1798 (signature[0] == 0x2B1BFE44);
1799 }
1800 }
1801
1802 return ERROR_OK;
1803 }
1804
1805
1806 /**
1807 * Get protection (sector security) status.
1808 *
1809 * Determine the status of "sector security" for each sector.
1810 * A secured sector is one that can never be erased/programmed again.
1811 *
1812 * @param bank Pointer to the flash bank descriptor
1813 */
1814 static int lpc2900_protect_check(struct flash_bank_s *bank)
1815 {
1816 return lpc2900_read_security_status(bank);
1817 }
1818
1819
1820 /**
1821 * Print info about the driver (not the device).
1822 *
1823 * @param bank Pointer to the flash bank descriptor
1824 * @param buf Buffer to take the string
1825 * @param buf_size Maximum number of characters that the buffer can take
1826 */
1827 static int lpc2900_info(struct flash_bank_s *bank, char *buf, int buf_size)
1828 {
1829 snprintf(buf, buf_size, "lpc2900 flash driver");
1830
1831 return ERROR_OK;
1832 }
1833
1834
1835 flash_driver_t lpc2900_flash =
1836 {
1837 .name = "lpc2900",
1838 .register_commands = lpc2900_register_commands,
1839 .flash_bank_command = lpc2900_flash_bank_command,
1840 .erase = lpc2900_erase,
1841 .protect = lpc2900_protect,
1842 .write = lpc2900_write,
1843 .probe = lpc2900_probe,
1844 .auto_probe = lpc2900_probe,
1845 .erase_check = lpc2900_erase_check,
1846 .protect_check = lpc2900_protect_check,
1847 .info = lpc2900_info
1848 };

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)