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[openocd.git] / src / flash / mx3_nand.c
1
2 /***************************************************************************
3 * Copyright (C) 2009 by Alexei Babich *
4 * Rezonans plc., Chelyabinsk, Russia *
5 * impatt@mail.ru *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22
23 /*
24 * Freescale iMX3* OpenOCD NAND Flash controller support.
25 *
26 * Many thanks to Ben Dooks for writing s3c24xx driver.
27 */
28
29 /*
30 driver tested with STMicro NAND512W3A @imx31
31 tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
32 get_next_halfword_from_sram_buffer() not tested
33 */
34 #ifdef HAVE_CONFIG_H
35 #include "config.h"
36 #endif
37
38 #include "mx3_nand.h"
39
40 static const char target_not_halted_err_msg[] =
41 "target must be halted to use mx3 NAND flash controller";
42 static const char data_block_size_err_msg[] =
43 "minimal granularity is one half-word, %" PRId32 " is incorrect";
44 static const char sram_buffer_bounds_err_msg[] =
45 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
46 static const char get_status_register_err_msg[] = "can't get NAND status";
47 static uint32_t in_sram_address;
48 unsigned char sign_of_sequental_byte_read;
49
50 static int test_iomux_settings (target_t * target, uint32_t value,
51 uint32_t mask, const char *text);
52 static int initialize_nf_controller (struct nand_device_s *device);
53 static int get_next_byte_from_sram_buffer (target_t * target, uint8_t * value);
54 static int get_next_halfword_from_sram_buffer (target_t * target,
55 uint16_t * value);
56 static int poll_for_complete_op (target_t * target, const char *text);
57 static int validate_target_state (struct nand_device_s *device);
58 static int do_data_output (struct nand_device_s *device);
59
60 static int imx31_command (struct nand_device_s *device, uint8_t command);
61 static int imx31_address (struct nand_device_s *device, uint8_t address);
62 static int imx31_controller_ready (struct nand_device_s *device, int tout);
63
64 static int imx31_nand_device_command (struct command_context_s *cmd_ctx,
65 char *cmd, char **args, int argc,
66 struct nand_device_s *device)
67 {
68 mx3_nf_controller_t *mx3_nf_info;
69 mx3_nf_info = malloc (sizeof (mx3_nf_controller_t));
70 if (mx3_nf_info == NULL)
71 {
72 LOG_ERROR ("no memory for nand controller");
73 return ERROR_FAIL;
74 }
75
76 device->controller_priv = mx3_nf_info;
77
78 mx3_nf_info->target = get_target (args[1]);
79 if (mx3_nf_info->target == NULL)
80 {
81 LOG_ERROR ("target '%s' not defined", args[1]);
82 return ERROR_FAIL;
83 }
84 if (argc < 3)
85 {
86 LOG_ERROR ("use \"nand device imx31 target noecc|hwecc\"");
87 return ERROR_FAIL;
88 }
89 /*
90 * check hwecc requirements
91 */
92 {
93 int hwecc_needed;
94 hwecc_needed = strcmp (args[2], "hwecc");
95 if (hwecc_needed == 0)
96 {
97 mx3_nf_info->flags.hw_ecc_enabled = 1;
98 }
99 else
100 {
101 mx3_nf_info->flags.hw_ecc_enabled = 0;
102 }
103 }
104
105 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
106 mx3_nf_info->fin = MX3_NF_FIN_NONE;
107 mx3_nf_info->flags.target_little_endian =
108 (mx3_nf_info->target->endianness == TARGET_LITTLE_ENDIAN);
109 /*
110 * testing host endianess
111 */
112 {
113 int x = 1;
114 if (*(char *) &x == 1)
115 {
116 mx3_nf_info->flags.host_little_endian = 1;
117 }
118 else
119 {
120 mx3_nf_info->flags.host_little_endian = 0;
121 }
122 }
123 return ERROR_OK;
124 }
125
126 static int imx31_init (struct nand_device_s *device)
127 {
128 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
129 target_t *target = mx3_nf_info->target;
130
131 {
132 /*
133 * validate target state
134 */
135 int validate_target_result;
136 validate_target_result = validate_target_state (device);
137 if (validate_target_result != ERROR_OK)
138 {
139 return validate_target_result;
140 }
141 }
142
143 {
144 uint16_t buffsize_register_content;
145 target_read_u16 (target, MX3_NF_BUFSIZ, &buffsize_register_content);
146 mx3_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
147 }
148
149 {
150 uint32_t pcsr_register_content;
151 target_read_u32 (target, MX3_PCSR, &pcsr_register_content);
152 if (!device->bus_width)
153 {
154 device->bus_width =
155 (pcsr_register_content & 0x80000000) ? 16 : 8;
156 }
157 else
158 {
159 pcsr_register_content |=
160 ((device->bus_width == 16) ? 0x80000000 : 0x00000000);
161 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
162 }
163
164 if (!device->page_size)
165 {
166 device->page_size =
167 (pcsr_register_content & 0x40000000) ? 2048 : 512;
168 }
169 else
170 {
171 pcsr_register_content |=
172 ((device->page_size == 2048) ? 0x40000000 : 0x00000000);
173 target_write_u32 (target, MX3_PCSR, pcsr_register_content);
174 }
175 if (mx3_nf_info->flags.one_kb_sram && (device->page_size == 2048))
176 {
177 LOG_ERROR
178 ("NAND controller have only 1 kb SRAM, so pagesize 2048 is incompatible with it");
179 }
180 }
181
182 {
183 uint32_t cgr_register_content;
184 target_read_u32 (target, MX3_CCM_CGR2, &cgr_register_content);
185 if (!(cgr_register_content & 0x00000300))
186 {
187 LOG_ERROR ("clock gating to EMI disabled");
188 return ERROR_FAIL;
189 }
190 }
191
192 {
193 uint32_t gpr_register_content;
194 target_read_u32 (target, MX3_GPR, &gpr_register_content);
195 if (gpr_register_content & 0x00000060)
196 {
197 LOG_ERROR ("pins mode overrided by GPR");
198 return ERROR_FAIL;
199 }
200 }
201
202 {
203 /*
204 * testing IOMUX settings; must be in "functional-mode output and
205 * functional-mode input" mode
206 */
207 int test_iomux;
208 test_iomux = ERROR_OK;
209 test_iomux |=
210 test_iomux_settings (target, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
211 test_iomux |=
212 test_iomux_settings (target, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
213 test_iomux |=
214 test_iomux_settings (target, 0x43fac0c8, 0x0000007f, "d7");
215 if (device->bus_width == 16)
216 {
217 test_iomux |=
218 test_iomux_settings (target, 0x43fac0c8, 0x7f7f7f00,
219 "d8,d9,d10");
220 test_iomux |=
221 test_iomux_settings (target, 0x43fac0cc, 0x7f7f7f7f,
222 "d11,d12,d13,d14");
223 test_iomux |=
224 test_iomux_settings (target, 0x43fac0d0, 0x0000007f, "d15");
225 }
226 test_iomux |=
227 test_iomux_settings (target, 0x43fac0d0, 0x7f7f7f00,
228 "nfwp,nfce,nfrb");
229 test_iomux |=
230 test_iomux_settings (target, 0x43fac0d4, 0x7f7f7f7f,
231 "nfwe,nfre,nfale,nfcle");
232 if (test_iomux != ERROR_OK)
233 {
234 return ERROR_FAIL;
235 }
236 }
237
238 initialize_nf_controller (device);
239
240 {
241 int retval;
242 uint16_t nand_status_content;
243 retval = ERROR_OK;
244 retval |= imx31_command (device, NAND_CMD_STATUS);
245 retval |= imx31_address (device, 0x00);
246 retval |= do_data_output (device);
247 if (retval != ERROR_OK)
248 {
249 LOG_ERROR (get_status_register_err_msg);
250 return ERROR_FAIL;
251 }
252 target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
253 if (!(nand_status_content & 0x0080))
254 {
255 /*
256 * is host-big-endian correctly ??
257 */
258 LOG_INFO ("NAND read-only");
259 mx3_nf_info->flags.nand_readonly = 1;
260 }
261 else
262 {
263 mx3_nf_info->flags.nand_readonly = 0;
264 }
265 }
266 return ERROR_OK;
267 }
268
269 static int imx31_read_data (struct nand_device_s *device, void *data)
270 {
271 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
272 target_t *target = mx3_nf_info->target;
273 {
274 /*
275 * validate target state
276 */
277 int validate_target_result;
278 validate_target_result = validate_target_state (device);
279 if (validate_target_result != ERROR_OK)
280 {
281 return validate_target_result;
282 }
283 }
284
285 {
286 /*
287 * get data from nand chip
288 */
289 int try_data_output_from_nand_chip;
290 try_data_output_from_nand_chip = do_data_output (device);
291 if (try_data_output_from_nand_chip != ERROR_OK)
292 {
293 return try_data_output_from_nand_chip;
294 }
295 }
296
297 if (device->bus_width == 16)
298 {
299 get_next_halfword_from_sram_buffer (target, data);
300 }
301 else
302 {
303 get_next_byte_from_sram_buffer (target, data);
304 }
305
306 return ERROR_OK;
307 }
308
309 static int imx31_write_data (struct nand_device_s *device, uint16_t data)
310 {
311 LOG_ERROR ("write_data() not implemented");
312 return ERROR_NAND_OPERATION_FAILED;
313 }
314
315 static int imx31_nand_ready (struct nand_device_s *device, int timeout)
316 {
317 return imx31_controller_ready (device, timeout);
318 }
319
320 static int imx31_register_commands (struct command_context_s *cmd_ctx)
321 {
322 return ERROR_OK;
323 }
324
325 static int imx31_reset (struct nand_device_s *device)
326 {
327 /*
328 * validate target state
329 */
330 int validate_target_result;
331 validate_target_result = validate_target_state (device);
332 if (validate_target_result != ERROR_OK)
333 {
334 return validate_target_result;
335 }
336 initialize_nf_controller (device);
337 return ERROR_OK;
338 }
339
340 static int imx31_command (struct nand_device_s *device, uint8_t command)
341 {
342 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
343 target_t *target = mx3_nf_info->target;
344 {
345 /*
346 * validate target state
347 */
348 int validate_target_result;
349 validate_target_result = validate_target_state (device);
350 if (validate_target_result != ERROR_OK)
351 {
352 return validate_target_result;
353 }
354 }
355
356 switch (command)
357 {
358 case NAND_CMD_READOOB:
359 command = NAND_CMD_READ0;
360 in_sram_address = MX3_NF_SPARE_BUFFER0; /* set read point for
361 * data_read() and
362 * read_block_data() to
363 * spare area in SRAM
364 * buffer */
365 break;
366 case NAND_CMD_READ1:
367 command = NAND_CMD_READ0;
368 /*
369 * offset == one half of page size
370 */
371 in_sram_address =
372 MX3_NF_MAIN_BUFFER0 + (device->page_size >> 1);
373 default:
374 in_sram_address = MX3_NF_MAIN_BUFFER0;
375 }
376
377 target_write_u16 (target, MX3_NF_FCMD, command);
378 /*
379 * start command input operation (set MX3_NF_BIT_OP_DONE==0)
380 */
381 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FCI);
382 {
383 int poll_result;
384 poll_result = poll_for_complete_op (target, "command");
385 if (poll_result != ERROR_OK)
386 {
387 return poll_result;
388 }
389 }
390 /*
391 * reset cursor to begin of the buffer
392 */
393 sign_of_sequental_byte_read = 0;
394 switch (command)
395 {
396 case NAND_CMD_READID:
397 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDID;
398 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
399 break;
400 case NAND_CMD_STATUS:
401 mx3_nf_info->optype = MX3_NF_DATAOUT_NANDSTATUS;
402 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
403 break;
404 case NAND_CMD_READ0:
405 mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
406 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
407 break;
408 default:
409 mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
410 }
411 return ERROR_OK;
412 }
413
414 static int imx31_address (struct nand_device_s *device, uint8_t address)
415 {
416 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
417 target_t *target = mx3_nf_info->target;
418 {
419 /*
420 * validate target state
421 */
422 int validate_target_result;
423 validate_target_result = validate_target_state (device);
424 if (validate_target_result != ERROR_OK)
425 {
426 return validate_target_result;
427 }
428 }
429
430 target_write_u16 (target, MX3_NF_FADDR, address);
431 /*
432 * start address input operation (set MX3_NF_BIT_OP_DONE==0)
433 */
434 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FAI);
435 {
436 int poll_result;
437 poll_result = poll_for_complete_op (target, "address");
438 if (poll_result != ERROR_OK)
439 {
440 return poll_result;
441 }
442 }
443 return ERROR_OK;
444 }
445
446 static int imx31_controller_ready (struct nand_device_s *device, int tout)
447 {
448 uint16_t poll_complete_status;
449 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
450 target_t *target = mx3_nf_info->target;
451
452 {
453 /*
454 * validate target state
455 */
456 int validate_target_result;
457 validate_target_result = validate_target_state (device);
458 if (validate_target_result != ERROR_OK)
459 {
460 return validate_target_result;
461 }
462 }
463
464 do
465 {
466 target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
467 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
468 {
469 return tout;
470 }
471 alive_sleep (1);
472 }
473 while (tout-- > 0);
474 return tout;
475 }
476
477 static int imx31_write_page (struct nand_device_s *device, uint32_t page,
478 uint8_t * data, uint32_t data_size, uint8_t * oob,
479 uint32_t oob_size)
480 {
481 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
482 target_t *target = mx3_nf_info->target;
483
484 if (data_size % 2)
485 {
486 LOG_ERROR (data_block_size_err_msg, data_size);
487 return ERROR_NAND_OPERATION_FAILED;
488 }
489 if (oob_size % 2)
490 {
491 LOG_ERROR (data_block_size_err_msg, oob_size);
492 return ERROR_NAND_OPERATION_FAILED;
493 }
494 if (!data)
495 {
496 LOG_ERROR ("nothing to program");
497 return ERROR_NAND_OPERATION_FAILED;
498 }
499 {
500 /*
501 * validate target state
502 */
503 int retval;
504 retval = validate_target_state (device);
505 if (retval != ERROR_OK)
506 {
507 return retval;
508 }
509 }
510 {
511 int retval = ERROR_OK;
512 retval |= imx31_command (device, NAND_CMD_SEQIN);
513 retval |= imx31_address (device, 0x00);
514 retval |= imx31_address (device, page & 0xff);
515 retval |= imx31_address (device, (page >> 8) & 0xff);
516 if (device->address_cycles >= 4)
517 {
518 retval |= imx31_address (device, (page >> 16) & 0xff);
519 if (device->address_cycles >= 5)
520 {
521 retval |= imx31_address (device, (page >> 24) & 0xff);
522 }
523 }
524 target_write_buffer (target, MX3_NF_MAIN_BUFFER0, data_size, data);
525 if (oob)
526 {
527 if (mx3_nf_info->flags.hw_ecc_enabled)
528 {
529 /*
530 * part of spare block will be overrided by hardware
531 * ECC generator
532 */
533 LOG_DEBUG
534 ("part of spare block will be overrided by hardware ECC generator");
535 }
536 target_write_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
537 oob);
538 }
539 /*
540 * start data input operation (set MX3_NF_BIT_OP_DONE==0)
541 */
542 target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FDI);
543 {
544 int poll_result;
545 poll_result = poll_for_complete_op (target, "data input");
546 if (poll_result != ERROR_OK)
547 {
548 return poll_result;
549 }
550 }
551 retval |= imx31_command (device, NAND_CMD_PAGEPROG);
552 if (retval != ERROR_OK)
553 {
554 return retval;
555 }
556
557 /*
558 * check status register
559 */
560 {
561 uint16_t nand_status_content;
562 retval = ERROR_OK;
563 retval |= imx31_command (device, NAND_CMD_STATUS);
564 retval |= imx31_address (device, 0x00);
565 retval |= do_data_output (device);
566 if (retval != ERROR_OK)
567 {
568 LOG_ERROR (get_status_register_err_msg);
569 return retval;
570 }
571 target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
572 if (nand_status_content & 0x0001)
573 {
574 /*
575 * is host-big-endian correctly ??
576 */
577 return ERROR_NAND_OPERATION_FAILED;
578 }
579 }
580 }
581 return ERROR_OK;
582 }
583
584 static int imx31_read_page (struct nand_device_s *device, uint32_t page,
585 uint8_t * data, uint32_t data_size, uint8_t * oob,
586 uint32_t oob_size)
587 {
588 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
589 target_t *target = mx3_nf_info->target;
590
591 if (data_size % 2)
592 {
593 LOG_ERROR (data_block_size_err_msg, data_size);
594 return ERROR_NAND_OPERATION_FAILED;
595 }
596 if (oob_size % 2)
597 {
598 LOG_ERROR (data_block_size_err_msg, oob_size);
599 return ERROR_NAND_OPERATION_FAILED;
600 }
601
602 {
603 /*
604 * validate target state
605 */
606 int retval;
607 retval = validate_target_state (device);
608 if (retval != ERROR_OK)
609 {
610 return retval;
611 }
612 }
613 {
614 int retval = ERROR_OK;
615 retval |= imx31_command (device, NAND_CMD_READ0);
616 retval |= imx31_address (device, 0x00);
617 retval |= imx31_address (device, page & 0xff);
618 retval |= imx31_address (device, (page >> 8) & 0xff);
619 if (device->address_cycles >= 4)
620 {
621 retval |= imx31_address (device, (page >> 16) & 0xff);
622 if (device->address_cycles >= 5)
623 {
624 retval |= imx31_address (device, (page >> 24) & 0xff);
625 retval |= imx31_command (device, NAND_CMD_READSTART);
626 }
627 }
628 retval |= do_data_output (device);
629 if (retval != ERROR_OK)
630 {
631 return retval;
632 }
633
634 if (data)
635 {
636 target_read_buffer (target, MX3_NF_MAIN_BUFFER0, data_size,
637 data);
638 }
639 if (oob)
640 {
641 target_read_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
642 oob);
643 }
644 }
645 return ERROR_OK;
646 }
647
648 static int test_iomux_settings (target_t * target, uint32_t address,
649 uint32_t mask, const char *text)
650 {
651 uint32_t register_content;
652 target_read_u32 (target, address, &register_content);
653 if ((register_content & mask) != (0x12121212 & mask))
654 {
655 LOG_ERROR ("IOMUX for {%s} is bad", text);
656 return ERROR_FAIL;
657 }
658 return ERROR_OK;
659 }
660
661 static int initialize_nf_controller (struct nand_device_s *device)
662 {
663 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
664 target_t *target = mx3_nf_info->target;
665 /*
666 * resets NAND flash controller in zero time ? I dont know.
667 */
668 target_write_u16 (target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
669 {
670 uint16_t work_mode;
671 work_mode = MX3_NF_BIT_INT_DIS; /* disable interrupt */
672 if (target->endianness == TARGET_BIG_ENDIAN)
673 {
674 work_mode |= MX3_NF_BIT_BE_EN;
675 }
676 if (mx3_nf_info->flags.hw_ecc_enabled)
677 {
678 work_mode |= MX3_NF_BIT_ECC_EN;
679 }
680 target_write_u16 (target, MX3_NF_CFG1, work_mode);
681 }
682 /*
683 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
684 */
685 target_write_u16 (target, MX3_NF_BUFCFG, 2);
686 {
687 uint16_t temp;
688 target_read_u16 (target, MX3_NF_FWP, &temp);
689 if ((temp & 0x0007) == 1)
690 {
691 LOG_ERROR ("NAND flash is tight-locked, reset needed");
692 return ERROR_FAIL;
693 }
694
695 }
696 /*
697 * unlock NAND flash for write
698 */
699 target_write_u16 (target, MX3_NF_FWP, 4);
700 target_write_u16 (target, MX3_NF_LOCKSTART, 0x0000);
701 target_write_u16 (target, MX3_NF_LOCKEND, 0xFFFF);
702 /*
703 * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
704 */
705 target_write_u16 (target, MX3_NF_BUFADDR, 0x0000);
706 /*
707 * address of SRAM buffer
708 */
709 in_sram_address = MX3_NF_MAIN_BUFFER0;
710 sign_of_sequental_byte_read = 0;
711 return ERROR_OK;
712 }
713
714 static int get_next_byte_from_sram_buffer (target_t * target, uint8_t * value)
715 {
716 static uint8_t even_byte = 0;
717 /*
718 * host-big_endian ??
719 */
720 if (sign_of_sequental_byte_read == 0)
721 {
722 even_byte = 0;
723 }
724 if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
725 {
726 LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
727 *value = 0;
728 sign_of_sequental_byte_read = 0;
729 even_byte = 0;
730 return ERROR_NAND_OPERATION_FAILED;
731 }
732 else
733 {
734 uint16_t temp;
735 target_read_u16 (target, in_sram_address, &temp);
736 if (even_byte)
737 {
738 *value = temp >> 8;
739 even_byte = 0;
740 in_sram_address += 2;
741 }
742 else
743 {
744 *value = temp & 0xff;
745 even_byte = 1;
746 }
747 }
748 sign_of_sequental_byte_read = 1;
749 return ERROR_OK;
750 }
751
752 static int get_next_halfword_from_sram_buffer (target_t * target,
753 uint16_t * value)
754 {
755 if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
756 {
757 LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
758 *value = 0;
759 return ERROR_NAND_OPERATION_FAILED;
760 }
761 else
762 {
763 target_read_u16 (target, in_sram_address, value);
764 in_sram_address += 2;
765 }
766 return ERROR_OK;
767 }
768
769 static int poll_for_complete_op (target_t * target, const char *text)
770 {
771 uint16_t poll_complete_status;
772 for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++)
773 {
774 usleep (25);
775 target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
776 if (poll_complete_status & MX3_NF_BIT_OP_DONE)
777 {
778 break;
779 }
780 }
781 if (!(poll_complete_status & MX3_NF_BIT_OP_DONE))
782 {
783 LOG_ERROR ("%s sending timeout", text);
784 return ERROR_NAND_OPERATION_FAILED;
785 }
786 return ERROR_OK;
787 }
788
789 static int validate_target_state (struct nand_device_s *device)
790 {
791 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
792 target_t *target = mx3_nf_info->target;
793
794 if (target->state != TARGET_HALTED)
795 {
796 LOG_ERROR (target_not_halted_err_msg);
797 return ERROR_NAND_OPERATION_FAILED;
798 }
799
800 if (mx3_nf_info->flags.target_little_endian !=
801 (target->endianness == TARGET_LITTLE_ENDIAN))
802 {
803 /*
804 * endianness changed after NAND controller probed
805 */
806 return ERROR_NAND_OPERATION_FAILED;
807 }
808 return ERROR_OK;
809 }
810
811 static int do_data_output (struct nand_device_s *device)
812 {
813 mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
814 target_t *target = mx3_nf_info->target;
815 switch (mx3_nf_info->fin)
816 {
817 case MX3_NF_FIN_DATAOUT:
818 /*
819 * start data output operation (set MX3_NF_BIT_OP_DONE==0)
820 */
821 target_write_u16 (target, MX3_NF_CFG2,
822 MX3_NF_BIT_DATAOUT_TYPE (mx3_nf_info->
823 optype));
824 {
825 int poll_result;
826 poll_result = poll_for_complete_op (target, "data output");
827 if (poll_result != ERROR_OK)
828 {
829 return poll_result;
830 }
831 }
832 mx3_nf_info->fin = MX3_NF_FIN_NONE;
833 /*
834 * ECC stuff
835 */
836 if ((mx3_nf_info->optype == MX3_NF_DATAOUT_PAGE)
837 && mx3_nf_info->flags.hw_ecc_enabled)
838 {
839 uint16_t ecc_status;
840 target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
841 switch (ecc_status & 0x000c)
842 {
843 case 1 << 2:
844 LOG_DEBUG
845 ("main area readed with 1 (correctable) error");
846 break;
847 case 2 << 2:
848 LOG_DEBUG
849 ("main area readed with more than 1 (incorrectable) error");
850 return ERROR_NAND_OPERATION_FAILED;
851 break;
852 }
853 switch (ecc_status & 0x0003)
854 {
855 case 1:
856 LOG_DEBUG
857 ("spare area readed with 1 (correctable) error");
858 break;
859 case 2:
860 LOG_DEBUG
861 ("main area readed with more than 1 (incorrectable) error");
862 return ERROR_NAND_OPERATION_FAILED;
863 break;
864 }
865 }
866 break;
867 case MX3_NF_FIN_NONE:
868 break;
869 }
870 return ERROR_OK;
871 }
872
873 nand_flash_controller_t imx31_nand_flash_controller = {
874 .name = "imx31",
875 .nand_device_command = &imx31_nand_device_command,
876 .register_commands = &imx31_register_commands,
877 .init = &imx31_init,
878 .reset = &imx31_reset,
879 .command = &imx31_command,
880 .address = &imx31_address,
881 .write_data = &imx31_write_data,
882 .read_data = &imx31_read_data,
883 .write_page = &imx31_write_page,
884 .read_page = &imx31_read_page,
885 .controller_ready = &imx31_controller_ready,
886 .nand_ready = &imx31_nand_ready,
887 };
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