Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
split NAND driver handling into nand/driver.[ch]
[openocd.git] / src / flash / nand.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "nand.h"
28 #include "common.h"
29 #include <helper/time_support.h>
30 #include <helper/fileio.h>
31
32 static int nand_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
33 //static int nand_read_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size);
34
35 static int nand_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
36
37 /* configured NAND devices and NAND Flash command handler */
38 static struct nand_device *nand_devices = NULL;
39
40 /* Chip ID list
41 *
42 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
43 * options
44 *
45 * Pagesize; 0, 256, 512
46 * 0 get this information from the extended chip ID
47 * 256 256 Byte page size
48 * 512 512 Byte page size
49 */
50 static struct nand_info nand_flash_ids[] =
51 {
52 /* start "museum" IDs */
53 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
54 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
55 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
56 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
57 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
58 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
59 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
60 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
61 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
62 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
63
64 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
65 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
66 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
67 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
68 /* end "museum" IDs */
69
70 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
71 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
72 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
73 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
74
75 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
76 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
77 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
78 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
79
80 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
81 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
82 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
83 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
84
85 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
86 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
87 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
88 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
89 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
90 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
91 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
92
93 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
94
95 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
96 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
97 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
98 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
99
100 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
101 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
102 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
103 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
104
105 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
106 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
107 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
108 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
109
110 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
111 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
112 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
113 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
114
115 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
116 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
117 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
118 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
119
120 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
121 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
122 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
123 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
124
125 {NULL, 0, 0, 0, 0, 0 }
126 };
127
128 /* Manufacturer ID list
129 */
130 static struct nand_manufacturer nand_manuf_ids[] =
131 {
132 {0x0, "unknown"},
133 {NAND_MFR_TOSHIBA, "Toshiba"},
134 {NAND_MFR_SAMSUNG, "Samsung"},
135 {NAND_MFR_FUJITSU, "Fujitsu"},
136 {NAND_MFR_NATIONAL, "National"},
137 {NAND_MFR_RENESAS, "Renesas"},
138 {NAND_MFR_STMICRO, "ST Micro"},
139 {NAND_MFR_HYNIX, "Hynix"},
140 {NAND_MFR_MICRON, "Micron"},
141 {0x0, NULL},
142 };
143
144 /*
145 * Define default oob placement schemes for large and small page devices
146 */
147
148 #if 0
149 static struct nand_ecclayout nand_oob_8 = {
150 .eccbytes = 3,
151 .eccpos = {0, 1, 2},
152 .oobfree = {
153 {.offset = 3,
154 .length = 2},
155 {.offset = 6,
156 .length = 2}}
157 };
158 #endif
159
160 static struct nand_ecclayout nand_oob_16 = {
161 .eccbytes = 6,
162 .eccpos = {0, 1, 2, 3, 6, 7},
163 .oobfree = {
164 {.offset = 8,
165 . length = 8}}
166 };
167
168 static struct nand_ecclayout nand_oob_64 = {
169 .eccbytes = 24,
170 .eccpos = {
171 40, 41, 42, 43, 44, 45, 46, 47,
172 48, 49, 50, 51, 52, 53, 54, 55,
173 56, 57, 58, 59, 60, 61, 62, 63},
174 .oobfree = {
175 {.offset = 2,
176 .length = 38}}
177 };
178
179 int nand_list_walker(struct nand_flash_controller *c, void *x)
180 {
181 struct command_context *cmd_ctx = (struct command_context *)x;
182 command_print(cmd_ctx, " %s", c->name);
183 return ERROR_OK;
184 }
185 COMMAND_HANDLER(handle_nand_list_drivers)
186 {
187 command_print(CMD_CTX, "Available NAND flash controller drivers:");
188 return nand_driver_walk(&nand_list_walker, CMD_CTX);
189 }
190
191 static COMMAND_HELPER(create_nand_device, const char *bank_name,
192 struct nand_flash_controller *controller)
193 {
194 if (NULL != controller->commands)
195 {
196 int retval = register_commands(CMD_CTX, NULL,
197 controller->commands);
198 if (ERROR_OK != retval)
199 return retval;
200 }
201 struct nand_device *c = malloc(sizeof(struct nand_device));
202
203 c->name = strdup(bank_name);
204 c->controller = controller;
205 c->controller_priv = NULL;
206 c->manufacturer = NULL;
207 c->device = NULL;
208 c->bus_width = 0;
209 c->address_cycles = 0;
210 c->page_size = 0;
211 c->use_raw = 0;
212 c->next = NULL;
213
214 int retval = CALL_COMMAND_HANDLER(controller->nand_device_command, c);
215 if (ERROR_OK != retval)
216 {
217 LOG_ERROR("'%s' driver rejected nand flash", controller->name);
218 free(c);
219 return ERROR_OK;
220 }
221
222 if (nand_devices) {
223 struct nand_device *p = nand_devices;
224 while (p && p->next) p = p->next;
225 p->next = c;
226 } else
227 nand_devices = c;
228
229 return ERROR_OK;
230 }
231
232 COMMAND_HANDLER(handle_nand_device_command)
233 {
234 if (CMD_ARGC < 1)
235 {
236 LOG_ERROR("incomplete nand device configuration");
237 return ERROR_FLASH_BANK_INVALID;
238 }
239
240 // save name and increment (for compatibility) with drivers
241 const char *bank_name = *CMD_ARGV++;
242 CMD_ARGC--;
243
244 const char *driver_name = CMD_ARGV[0];
245 struct nand_flash_controller *controller;
246 controller = nand_driver_find_by_name(CMD_ARGV[0]);
247 if (NULL == controller)
248 {
249 LOG_ERROR("No valid NAND flash driver found (%s)", driver_name);
250 return CALL_COMMAND_HANDLER(handle_nand_list_drivers);
251 }
252 return CALL_COMMAND_HANDLER(create_nand_device, bank_name, controller);
253 }
254
255
256 COMMAND_HANDLER(handle_nand_init_command);
257
258 static const struct command_registration nand_config_command_handlers[] = {
259 {
260 .name = "device",
261 .handler = &handle_nand_device_command,
262 .mode = COMMAND_CONFIG,
263 .help = "defines a new NAND bank",
264 },
265 {
266 .name = "drivers",
267 .handler = &handle_nand_list_drivers,
268 .mode = COMMAND_ANY,
269 .help = "lists available NAND drivers",
270 },
271 {
272 .name = "init",
273 .mode = COMMAND_CONFIG,
274 .handler = &handle_nand_init_command,
275 .help = "initialize NAND devices",
276 },
277 COMMAND_REGISTRATION_DONE
278 };
279 static const struct command_registration nand_command_handlers[] = {
280 {
281 .name = "nand",
282 .mode = COMMAND_ANY,
283 .help = "NAND flash command group",
284 .chain = nand_config_command_handlers,
285 },
286 COMMAND_REGISTRATION_DONE
287 };
288
289 int nand_register_commands(struct command_context *cmd_ctx)
290 {
291 return register_commands(cmd_ctx, NULL, nand_command_handlers);
292 }
293
294 struct nand_device *get_nand_device_by_name(const char *name)
295 {
296 unsigned requested = get_flash_name_index(name);
297 unsigned found = 0;
298
299 struct nand_device *nand;
300 for (nand = nand_devices; NULL != nand; nand = nand->next)
301 {
302 if (strcmp(nand->name, name) == 0)
303 return nand;
304 if (!flash_driver_name_matches(nand->controller->name, name))
305 continue;
306 if (++found < requested)
307 continue;
308 return nand;
309 }
310 return NULL;
311 }
312
313 struct nand_device *get_nand_device_by_num(int num)
314 {
315 struct nand_device *p;
316 int i = 0;
317
318 for (p = nand_devices; p; p = p->next)
319 {
320 if (i++ == num)
321 {
322 return p;
323 }
324 }
325
326 return NULL;
327 }
328
329 COMMAND_HELPER(nand_command_get_device, unsigned name_index,
330 struct nand_device **nand)
331 {
332 const char *str = CMD_ARGV[name_index];
333 *nand = get_nand_device_by_name(str);
334 if (*nand)
335 return ERROR_OK;
336
337 unsigned num;
338 COMMAND_PARSE_NUMBER(uint, str, num);
339 *nand = get_nand_device_by_num(num);
340 if (!*nand) {
341 command_print(CMD_CTX, "NAND flash device '%s' not found", str);
342 return ERROR_INVALID_ARGUMENTS;
343 }
344 return ERROR_OK;
345 }
346
347 static int nand_build_bbt(struct nand_device *nand, int first, int last)
348 {
349 uint32_t page = 0x0;
350 int i;
351 uint8_t oob[6];
352
353 if ((first < 0) || (first >= nand->num_blocks))
354 first = 0;
355
356 if ((last >= nand->num_blocks) || (last == -1))
357 last = nand->num_blocks - 1;
358
359 for (i = first; i < last; i++)
360 {
361 nand_read_page(nand, page, NULL, 0, oob, 6);
362
363 if (((nand->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
364 || (((nand->page_size == 512) && (oob[5] != 0xff)) ||
365 ((nand->page_size == 2048) && (oob[0] != 0xff))))
366 {
367 LOG_WARNING("bad block: %i", i);
368 nand->blocks[i].is_bad = 1;
369 }
370 else
371 {
372 nand->blocks[i].is_bad = 0;
373 }
374
375 page += (nand->erase_size / nand->page_size);
376 }
377
378 return ERROR_OK;
379 }
380
381 int nand_read_status(struct nand_device *nand, uint8_t *status)
382 {
383 if (!nand->device)
384 return ERROR_NAND_DEVICE_NOT_PROBED;
385
386 /* Send read status command */
387 nand->controller->command(nand, NAND_CMD_STATUS);
388
389 alive_sleep(1);
390
391 /* read status */
392 if (nand->device->options & NAND_BUSWIDTH_16)
393 {
394 uint16_t data;
395 nand->controller->read_data(nand, &data);
396 *status = data & 0xff;
397 }
398 else
399 {
400 nand->controller->read_data(nand, status);
401 }
402
403 return ERROR_OK;
404 }
405
406 static int nand_poll_ready(struct nand_device *nand, int timeout)
407 {
408 uint8_t status;
409
410 nand->controller->command(nand, NAND_CMD_STATUS);
411 do {
412 if (nand->device->options & NAND_BUSWIDTH_16) {
413 uint16_t data;
414 nand->controller->read_data(nand, &data);
415 status = data & 0xff;
416 } else {
417 nand->controller->read_data(nand, &status);
418 }
419 if (status & NAND_STATUS_READY)
420 break;
421 alive_sleep(1);
422 } while (timeout--);
423
424 return (status & NAND_STATUS_READY) != 0;
425 }
426
427 int nand_probe(struct nand_device *nand)
428 {
429 uint8_t manufacturer_id, device_id;
430 uint8_t id_buff[6];
431 int retval;
432 int i;
433
434 /* clear device data */
435 nand->device = NULL;
436 nand->manufacturer = NULL;
437
438 /* clear device parameters */
439 nand->bus_width = 0;
440 nand->address_cycles = 0;
441 nand->page_size = 0;
442 nand->erase_size = 0;
443
444 /* initialize controller (device parameters are zero, use controller default) */
445 if ((retval = nand->controller->init(nand) != ERROR_OK))
446 {
447 switch (retval)
448 {
449 case ERROR_NAND_OPERATION_FAILED:
450 LOG_DEBUG("controller initialization failed");
451 return ERROR_NAND_OPERATION_FAILED;
452 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
453 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
454 return ERROR_NAND_OPERATION_FAILED;
455 default:
456 LOG_ERROR("BUG: unknown controller initialization failure");
457 return ERROR_NAND_OPERATION_FAILED;
458 }
459 }
460
461 nand->controller->command(nand, NAND_CMD_RESET);
462 nand->controller->reset(nand);
463
464 nand->controller->command(nand, NAND_CMD_READID);
465 nand->controller->address(nand, 0x0);
466
467 if (nand->bus_width == 8)
468 {
469 nand->controller->read_data(nand, &manufacturer_id);
470 nand->controller->read_data(nand, &device_id);
471 }
472 else
473 {
474 uint16_t data_buf;
475 nand->controller->read_data(nand, &data_buf);
476 manufacturer_id = data_buf & 0xff;
477 nand->controller->read_data(nand, &data_buf);
478 device_id = data_buf & 0xff;
479 }
480
481 for (i = 0; nand_flash_ids[i].name; i++)
482 {
483 if (nand_flash_ids[i].id == device_id)
484 {
485 nand->device = &nand_flash_ids[i];
486 break;
487 }
488 }
489
490 for (i = 0; nand_manuf_ids[i].name; i++)
491 {
492 if (nand_manuf_ids[i].id == manufacturer_id)
493 {
494 nand->manufacturer = &nand_manuf_ids[i];
495 break;
496 }
497 }
498
499 if (!nand->manufacturer)
500 {
501 nand->manufacturer = &nand_manuf_ids[0];
502 nand->manufacturer->id = manufacturer_id;
503 }
504
505 if (!nand->device)
506 {
507 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
508 manufacturer_id, device_id);
509 return ERROR_NAND_OPERATION_FAILED;
510 }
511
512 LOG_DEBUG("found %s (%s)", nand->device->name, nand->manufacturer->name);
513
514 /* initialize device parameters */
515
516 /* bus width */
517 if (nand->device->options & NAND_BUSWIDTH_16)
518 nand->bus_width = 16;
519 else
520 nand->bus_width = 8;
521
522 /* Do we need extended device probe information? */
523 if (nand->device->page_size == 0 ||
524 nand->device->erase_size == 0)
525 {
526 if (nand->bus_width == 8)
527 {
528 nand->controller->read_data(nand, id_buff + 3);
529 nand->controller->read_data(nand, id_buff + 4);
530 nand->controller->read_data(nand, id_buff + 5);
531 }
532 else
533 {
534 uint16_t data_buf;
535
536 nand->controller->read_data(nand, &data_buf);
537 id_buff[3] = data_buf;
538
539 nand->controller->read_data(nand, &data_buf);
540 id_buff[4] = data_buf;
541
542 nand->controller->read_data(nand, &data_buf);
543 id_buff[5] = data_buf >> 8;
544 }
545 }
546
547 /* page size */
548 if (nand->device->page_size == 0)
549 {
550 nand->page_size = 1 << (10 + (id_buff[4] & 3));
551 }
552 else if (nand->device->page_size == 256)
553 {
554 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
555 return ERROR_NAND_OPERATION_FAILED;
556 }
557 else
558 {
559 nand->page_size = nand->device->page_size;
560 }
561
562 /* number of address cycles */
563 if (nand->page_size <= 512)
564 {
565 /* small page devices */
566 if (nand->device->chip_size <= 32)
567 nand->address_cycles = 3;
568 else if (nand->device->chip_size <= 8*1024)
569 nand->address_cycles = 4;
570 else
571 {
572 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
573 nand->address_cycles = 5;
574 }
575 }
576 else
577 {
578 /* large page devices */
579 if (nand->device->chip_size <= 128)
580 nand->address_cycles = 4;
581 else if (nand->device->chip_size <= 32*1024)
582 nand->address_cycles = 5;
583 else
584 {
585 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
586 nand->address_cycles = 6;
587 }
588 }
589
590 /* erase size */
591 if (nand->device->erase_size == 0)
592 {
593 switch ((id_buff[4] >> 4) & 3) {
594 case 0:
595 nand->erase_size = 64 << 10;
596 break;
597 case 1:
598 nand->erase_size = 128 << 10;
599 break;
600 case 2:
601 nand->erase_size = 256 << 10;
602 break;
603 case 3:
604 nand->erase_size =512 << 10;
605 break;
606 }
607 }
608 else
609 {
610 nand->erase_size = nand->device->erase_size;
611 }
612
613 /* initialize controller, but leave parameters at the controllers default */
614 if ((retval = nand->controller->init(nand) != ERROR_OK))
615 {
616 switch (retval)
617 {
618 case ERROR_NAND_OPERATION_FAILED:
619 LOG_DEBUG("controller initialization failed");
620 return ERROR_NAND_OPERATION_FAILED;
621 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
622 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
623 nand->bus_width, nand->address_cycles, nand->page_size);
624 return ERROR_NAND_OPERATION_FAILED;
625 default:
626 LOG_ERROR("BUG: unknown controller initialization failure");
627 return ERROR_NAND_OPERATION_FAILED;
628 }
629 }
630
631 nand->num_blocks = (nand->device->chip_size * 1024) / (nand->erase_size / 1024);
632 nand->blocks = malloc(sizeof(struct nand_block) * nand->num_blocks);
633
634 for (i = 0; i < nand->num_blocks; i++)
635 {
636 nand->blocks[i].size = nand->erase_size;
637 nand->blocks[i].offset = i * nand->erase_size;
638 nand->blocks[i].is_erased = -1;
639 nand->blocks[i].is_bad = -1;
640 }
641
642 return ERROR_OK;
643 }
644
645 static int nand_erase(struct nand_device *nand, int first_block, int last_block)
646 {
647 int i;
648 uint32_t page;
649 uint8_t status;
650 int retval;
651
652 if (!nand->device)
653 return ERROR_NAND_DEVICE_NOT_PROBED;
654
655 if ((first_block < 0) || (last_block > nand->num_blocks))
656 return ERROR_INVALID_ARGUMENTS;
657
658 /* make sure we know if a block is bad before erasing it */
659 for (i = first_block; i <= last_block; i++)
660 {
661 if (nand->blocks[i].is_bad == -1)
662 {
663 nand_build_bbt(nand, i, last_block);
664 break;
665 }
666 }
667
668 for (i = first_block; i <= last_block; i++)
669 {
670 /* Send erase setup command */
671 nand->controller->command(nand, NAND_CMD_ERASE1);
672
673 page = i * (nand->erase_size / nand->page_size);
674
675 /* Send page address */
676 if (nand->page_size <= 512)
677 {
678 /* row */
679 nand->controller->address(nand, page & 0xff);
680 nand->controller->address(nand, (page >> 8) & 0xff);
681
682 /* 3rd cycle only on devices with more than 32 MiB */
683 if (nand->address_cycles >= 4)
684 nand->controller->address(nand, (page >> 16) & 0xff);
685
686 /* 4th cycle only on devices with more than 8 GiB */
687 if (nand->address_cycles >= 5)
688 nand->controller->address(nand, (page >> 24) & 0xff);
689 }
690 else
691 {
692 /* row */
693 nand->controller->address(nand, page & 0xff);
694 nand->controller->address(nand, (page >> 8) & 0xff);
695
696 /* 3rd cycle only on devices with more than 128 MiB */
697 if (nand->address_cycles >= 5)
698 nand->controller->address(nand, (page >> 16) & 0xff);
699 }
700
701 /* Send erase confirm command */
702 nand->controller->command(nand, NAND_CMD_ERASE2);
703
704 retval = nand->controller->nand_ready ?
705 nand->controller->nand_ready(nand, 1000) :
706 nand_poll_ready(nand, 1000);
707 if (!retval) {
708 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
709 return ERROR_NAND_OPERATION_TIMEOUT;
710 }
711
712 if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
713 {
714 LOG_ERROR("couldn't read status");
715 return ERROR_NAND_OPERATION_FAILED;
716 }
717
718 if (status & 0x1)
719 {
720 LOG_ERROR("didn't erase %sblock %d; status: 0x%2.2x",
721 (nand->blocks[i].is_bad == 1)
722 ? "bad " : "",
723 i, status);
724 /* continue; other blocks might still be erasable */
725 }
726
727 nand->blocks[i].is_erased = 1;
728 }
729
730 return ERROR_OK;
731 }
732
733 #if 0
734 static int nand_read_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size)
735 {
736 uint8_t *page;
737
738 if (!nand->device)
739 return ERROR_NAND_DEVICE_NOT_PROBED;
740
741 if (address % nand->page_size)
742 {
743 LOG_ERROR("reads need to be page aligned");
744 return ERROR_NAND_OPERATION_FAILED;
745 }
746
747 page = malloc(nand->page_size);
748
749 while (data_size > 0)
750 {
751 uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
752 uint32_t page_address;
753
754
755 page_address = address / nand->page_size;
756
757 nand_read_page(nand, page_address, page, nand->page_size, NULL, 0);
758
759 memcpy(data, page, thisrun_size);
760
761 address += thisrun_size;
762 data += thisrun_size;
763 data_size -= thisrun_size;
764 }
765
766 free(page);
767
768 return ERROR_OK;
769 }
770
771 static int nand_write_plain(struct nand_device *nand, uint32_t address, uint8_t *data, uint32_t data_size)
772 {
773 uint8_t *page;
774
775 if (!nand->device)
776 return ERROR_NAND_DEVICE_NOT_PROBED;
777
778 if (address % nand->page_size)
779 {
780 LOG_ERROR("writes need to be page aligned");
781 return ERROR_NAND_OPERATION_FAILED;
782 }
783
784 page = malloc(nand->page_size);
785
786 while (data_size > 0)
787 {
788 uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
789 uint32_t page_address;
790
791 memset(page, 0xff, nand->page_size);
792 memcpy(page, data, thisrun_size);
793
794 page_address = address / nand->page_size;
795
796 nand_write_page(nand, page_address, page, nand->page_size, NULL, 0);
797
798 address += thisrun_size;
799 data += thisrun_size;
800 data_size -= thisrun_size;
801 }
802
803 free(page);
804
805 return ERROR_OK;
806 }
807 #endif
808
809 int nand_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
810 {
811 uint32_t block;
812
813 if (!nand->device)
814 return ERROR_NAND_DEVICE_NOT_PROBED;
815
816 block = page / (nand->erase_size / nand->page_size);
817 if (nand->blocks[block].is_erased == 1)
818 nand->blocks[block].is_erased = 0;
819
820 if (nand->use_raw || nand->controller->write_page == NULL)
821 return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
822 else
823 return nand->controller->write_page(nand, page, data, data_size, oob, oob_size);
824 }
825
826 static int nand_read_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
827 {
828 if (!nand->device)
829 return ERROR_NAND_DEVICE_NOT_PROBED;
830
831 if (nand->use_raw || nand->controller->read_page == NULL)
832 return nand_read_page_raw(nand, page, data, data_size, oob, oob_size);
833 else
834 return nand->controller->read_page(nand, page, data, data_size, oob, oob_size);
835 }
836
837 int nand_page_command(struct nand_device *nand, uint32_t page,
838 uint8_t cmd, bool oob_only)
839 {
840 if (!nand->device)
841 return ERROR_NAND_DEVICE_NOT_PROBED;
842
843 if (oob_only && NAND_CMD_READ0 == cmd && nand->page_size <= 512)
844 cmd = NAND_CMD_READOOB;
845
846 nand->controller->command(nand, cmd);
847
848 if (nand->page_size <= 512) {
849 /* small page device */
850
851 /* column (always 0, we start at the beginning of a page/OOB area) */
852 nand->controller->address(nand, 0x0);
853
854 /* row */
855 nand->controller->address(nand, page & 0xff);
856 nand->controller->address(nand, (page >> 8) & 0xff);
857
858 /* 4th cycle only on devices with more than 32 MiB */
859 if (nand->address_cycles >= 4)
860 nand->controller->address(nand, (page >> 16) & 0xff);
861
862 /* 5th cycle only on devices with more than 8 GiB */
863 if (nand->address_cycles >= 5)
864 nand->controller->address(nand, (page >> 24) & 0xff);
865 } else {
866 /* large page device */
867
868 /* column (0 when we start at the beginning of a page,
869 * or 2048 for the beginning of OOB area)
870 */
871 nand->controller->address(nand, 0x0);
872 if (oob_only)
873 nand->controller->address(nand, 0x8);
874 else
875 nand->controller->address(nand, 0x0);
876
877 /* row */
878 nand->controller->address(nand, page & 0xff);
879 nand->controller->address(nand, (page >> 8) & 0xff);
880
881 /* 5th cycle only on devices with more than 128 MiB */
882 if (nand->address_cycles >= 5)
883 nand->controller->address(nand, (page >> 16) & 0xff);
884
885 /* large page devices need a start command if reading */
886 if (NAND_CMD_READ0 == cmd)
887 nand->controller->command(nand, NAND_CMD_READSTART);
888 }
889
890 if (nand->controller->nand_ready) {
891 if (!nand->controller->nand_ready(nand, 100))
892 return ERROR_NAND_OPERATION_TIMEOUT;
893 } else {
894 alive_sleep(1);
895 }
896
897 return ERROR_OK;
898 }
899
900 int nand_read_page_raw(struct nand_device *nand, uint32_t page,
901 uint8_t *data, uint32_t data_size,
902 uint8_t *oob, uint32_t oob_size)
903 {
904 uint32_t i;
905 int retval;
906
907 retval = nand_page_command(nand, page, NAND_CMD_READ0, !data);
908 if (ERROR_OK != retval)
909 return retval;
910
911 if (data)
912 {
913 if (nand->controller->read_block_data != NULL)
914 (nand->controller->read_block_data)(nand, data, data_size);
915 else
916 {
917 for (i = 0; i < data_size;)
918 {
919 if (nand->device->options & NAND_BUSWIDTH_16)
920 {
921 nand->controller->read_data(nand, data);
922 data += 2;
923 i += 2;
924 }
925 else
926 {
927 nand->controller->read_data(nand, data);
928 data += 1;
929 i += 1;
930 }
931 }
932 }
933 }
934
935 if (oob)
936 {
937 if (nand->controller->read_block_data != NULL)
938 (nand->controller->read_block_data)(nand, oob, oob_size);
939 else
940 {
941 for (i = 0; i < oob_size;)
942 {
943 if (nand->device->options & NAND_BUSWIDTH_16)
944 {
945 nand->controller->read_data(nand, oob);
946 oob += 2;
947 i += 2;
948 }
949 else
950 {
951 nand->controller->read_data(nand, oob);
952 oob += 1;
953 i += 1;
954 }
955 }
956 }
957 }
958
959 return ERROR_OK;
960 }
961
962 int nand_write_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
963 {
964 uint32_t i;
965 int retval;
966 uint8_t status;
967
968 retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
969 if (ERROR_OK != retval)
970 return retval;
971
972 if (data)
973 {
974 if (nand->controller->write_block_data != NULL)
975 (nand->controller->write_block_data)(nand, data, data_size);
976 else
977 {
978 for (i = 0; i < data_size;)
979 {
980 if (nand->device->options & NAND_BUSWIDTH_16)
981 {
982 uint16_t data_buf = le_to_h_u16(data);
983 nand->controller->write_data(nand, data_buf);
984 data += 2;
985 i += 2;
986 }
987 else
988 {
989 nand->controller->write_data(nand, *data);
990 data += 1;
991 i += 1;
992 }
993 }
994 }
995 }
996
997 if (oob)
998 {
999 if (nand->controller->write_block_data != NULL)
1000 (nand->controller->write_block_data)(nand, oob, oob_size);
1001 else
1002 {
1003 for (i = 0; i < oob_size;)
1004 {
1005 if (nand->device->options & NAND_BUSWIDTH_16)
1006 {
1007 uint16_t oob_buf = le_to_h_u16(data);
1008 nand->controller->write_data(nand, oob_buf);
1009 oob += 2;
1010 i += 2;
1011 }
1012 else
1013 {
1014 nand->controller->write_data(nand, *oob);
1015 oob += 1;
1016 i += 1;
1017 }
1018 }
1019 }
1020 }
1021
1022 nand->controller->command(nand, NAND_CMD_PAGEPROG);
1023
1024 retval = nand->controller->nand_ready ?
1025 nand->controller->nand_ready(nand, 100) :
1026 nand_poll_ready(nand, 100);
1027 if (!retval)
1028 return ERROR_NAND_OPERATION_TIMEOUT;
1029
1030 if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
1031 {
1032 LOG_ERROR("couldn't read status");
1033 return ERROR_NAND_OPERATION_FAILED;
1034 }
1035
1036 if (status & NAND_STATUS_FAIL)
1037 {
1038 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1039 return ERROR_NAND_OPERATION_FAILED;
1040 }
1041
1042 return ERROR_OK;
1043 }
1044
1045 COMMAND_HANDLER(handle_nand_list_command)
1046 {
1047 struct nand_device *p;
1048 int i;
1049
1050 if (!nand_devices)
1051 {
1052 command_print(CMD_CTX, "no NAND flash devices configured");
1053 return ERROR_OK;
1054 }
1055
1056 for (p = nand_devices, i = 0; p; p = p->next, i++)
1057 {
1058 if (p->device)
1059 command_print(CMD_CTX, "#%i: %s (%s) "
1060 "pagesize: %i, buswidth: %i,\n\t"
1061 "blocksize: %i, blocks: %i",
1062 i, p->device->name, p->manufacturer->name,
1063 p->page_size, p->bus_width,
1064 p->erase_size, p->num_blocks);
1065 else
1066 command_print(CMD_CTX, "#%i: not probed", i);
1067 }
1068
1069 return ERROR_OK;
1070 }
1071
1072 COMMAND_HANDLER(handle_nand_info_command)
1073 {
1074 int i = 0;
1075 int j = 0;
1076 int first = -1;
1077 int last = -1;
1078
1079 switch (CMD_ARGC) {
1080 default:
1081 return ERROR_COMMAND_SYNTAX_ERROR;
1082 case 1:
1083 first = 0;
1084 last = INT32_MAX;
1085 break;
1086 case 2:
1087 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], i);
1088 first = last = i;
1089 i = 0;
1090 break;
1091 case 3:
1092 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], first);
1093 COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], last);
1094 break;
1095 }
1096
1097 struct nand_device *p;
1098 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
1099 if (ERROR_OK != retval)
1100 return retval;
1101
1102 if (NULL == p->device)
1103 {
1104 command_print(CMD_CTX, "#%s: not probed", CMD_ARGV[0]);
1105 return ERROR_OK;
1106 }
1107
1108 if (first >= p->num_blocks)
1109 first = p->num_blocks - 1;
1110
1111 if (last >= p->num_blocks)
1112 last = p->num_blocks - 1;
1113
1114 command_print(CMD_CTX, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1115 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1116
1117 for (j = first; j <= last; j++)
1118 {
1119 char *erase_state, *bad_state;
1120
1121 if (p->blocks[j].is_erased == 0)
1122 erase_state = "not erased";
1123 else if (p->blocks[j].is_erased == 1)
1124 erase_state = "erased";
1125 else
1126 erase_state = "erase state unknown";
1127
1128 if (p->blocks[j].is_bad == 0)
1129 bad_state = "";
1130 else if (p->blocks[j].is_bad == 1)
1131 bad_state = " (marked bad)";
1132 else
1133 bad_state = " (block condition unknown)";
1134
1135 command_print(CMD_CTX,
1136 "\t#%i: 0x%8.8" PRIx32 " (%" PRId32 "kB) %s%s",
1137 j,
1138 p->blocks[j].offset,
1139 p->blocks[j].size / 1024,
1140 erase_state,
1141 bad_state);
1142 }
1143
1144 return ERROR_OK;
1145 }
1146
1147 COMMAND_HANDLER(handle_nand_probe_command)
1148 {
1149 if (CMD_ARGC != 1)
1150 {
1151 return ERROR_COMMAND_SYNTAX_ERROR;
1152 }
1153
1154 struct nand_device *p;
1155 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
1156 if (ERROR_OK != retval)
1157 return retval;
1158
1159 if ((retval = nand_probe(p)) == ERROR_OK)
1160 {
1161 command_print(CMD_CTX, "NAND flash device '%s' found", p->device->name);
1162 }
1163 else if (retval == ERROR_NAND_OPERATION_FAILED)
1164 {
1165 command_print(CMD_CTX, "probing failed for NAND flash device");
1166 }
1167 else
1168 {
1169 command_print(CMD_CTX, "unknown error when probing NAND flash device");
1170 }
1171
1172 return ERROR_OK;
1173 }
1174
1175 COMMAND_HANDLER(handle_nand_erase_command)
1176 {
1177 if (CMD_ARGC != 1 && CMD_ARGC != 3)
1178 {
1179 return ERROR_COMMAND_SYNTAX_ERROR;
1180
1181 }
1182
1183 struct nand_device *p;
1184 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
1185 if (ERROR_OK != retval)
1186 return retval;
1187
1188 unsigned long offset;
1189 unsigned long length;
1190
1191 /* erase specified part of the chip; or else everything */
1192 if (CMD_ARGC == 3) {
1193 unsigned long size = p->erase_size * p->num_blocks;
1194
1195 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], offset);
1196 if ((offset % p->erase_size) != 0 || offset >= size)
1197 return ERROR_INVALID_ARGUMENTS;
1198
1199 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], length);
1200 if ((length == 0) || (length % p->erase_size) != 0
1201 || (length + offset) > size)
1202 return ERROR_INVALID_ARGUMENTS;
1203
1204 offset /= p->erase_size;
1205 length /= p->erase_size;
1206 } else {
1207 offset = 0;
1208 length = p->num_blocks;
1209 }
1210
1211 retval = nand_erase(p, offset, offset + length - 1);
1212 if (retval == ERROR_OK)
1213 {
1214 command_print(CMD_CTX, "erased blocks %lu to %lu "
1215 "on NAND flash device #%s '%s'",
1216 offset, offset + length,
1217 CMD_ARGV[0], p->device->name);
1218 }
1219 else if (retval == ERROR_NAND_OPERATION_FAILED)
1220 {
1221 command_print(CMD_CTX, "erase failed");
1222 }
1223 else
1224 {
1225 command_print(CMD_CTX, "unknown error when erasing NAND flash device");
1226 }
1227
1228 return ERROR_OK;
1229 }
1230
1231 COMMAND_HANDLER(handle_nand_check_bad_blocks_command)
1232 {
1233 int first = -1;
1234 int last = -1;
1235
1236 if ((CMD_ARGC < 1) || (CMD_ARGC > 3) || (CMD_ARGC == 2))
1237 {
1238 return ERROR_COMMAND_SYNTAX_ERROR;
1239
1240 }
1241
1242 struct nand_device *p;
1243 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
1244 if (ERROR_OK != retval)
1245 return retval;
1246
1247 if (CMD_ARGC == 3)
1248 {
1249 unsigned long offset;
1250 unsigned long length;
1251
1252 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[1], offset);
1253 if (offset % p->erase_size)
1254 return ERROR_INVALID_ARGUMENTS;
1255 offset /= p->erase_size;
1256
1257 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], length);
1258 if (length % p->erase_size)
1259 return ERROR_INVALID_ARGUMENTS;
1260
1261 length -= 1;
1262 length /= p->erase_size;
1263
1264 first = offset;
1265 last = offset + length;
1266 }
1267
1268 retval = nand_build_bbt(p, first, last);
1269 if (retval == ERROR_OK)
1270 {
1271 command_print(CMD_CTX, "checked NAND flash device for bad blocks, "
1272 "use \"nand info\" command to list blocks");
1273 }
1274 else if (retval == ERROR_NAND_OPERATION_FAILED)
1275 {
1276 command_print(CMD_CTX, "error when checking for bad blocks on "
1277 "NAND flash device");
1278 }
1279 else
1280 {
1281 command_print(CMD_CTX, "unknown error when checking for bad "
1282 "blocks on NAND flash device");
1283 }
1284
1285 return ERROR_OK;
1286 }
1287
1288 struct nand_fileio_state {
1289 uint32_t address;
1290 uint32_t size;
1291
1292 uint8_t *page;
1293 uint32_t page_size;
1294
1295 enum oob_formats oob_format;
1296 uint8_t *oob;
1297 uint32_t oob_size;
1298
1299 const int *eccpos;
1300
1301 bool file_opened;
1302 struct fileio fileio;
1303
1304 struct duration bench;
1305 };
1306
1307 static void nand_fileio_init(struct nand_fileio_state *state)
1308 {
1309 memset(state, 0, sizeof(*state));
1310 state->oob_format = NAND_OOB_NONE;
1311 }
1312
1313 static int nand_fileio_start(struct command_context *cmd_ctx,
1314 struct nand_device *nand, const char *filename, int filemode,
1315 struct nand_fileio_state *state)
1316 {
1317 if (state->address % nand->page_size)
1318 {
1319 command_print(cmd_ctx, "only page-aligned addresses are supported");
1320 return ERROR_COMMAND_SYNTAX_ERROR;
1321 }
1322
1323 duration_start(&state->bench);
1324
1325 if (NULL != filename)
1326 {
1327 int retval = fileio_open(&state->fileio, filename, filemode, FILEIO_BINARY);
1328 if (ERROR_OK != retval)
1329 {
1330 const char *msg = (FILEIO_READ == filemode) ? "read" : "write";
1331 command_print(cmd_ctx, "failed to open '%s' for %s access",
1332 filename, msg);
1333 return retval;
1334 }
1335 state->file_opened = true;
1336 }
1337
1338 if (!(state->oob_format & NAND_OOB_ONLY))
1339 {
1340 state->page_size = nand->page_size;
1341 state->page = malloc(nand->page_size);
1342 }
1343
1344 if (state->oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC | NAND_OOB_SW_ECC_KW))
1345 {
1346 if (nand->page_size == 512)
1347 {
1348 state->oob_size = 16;
1349 state->eccpos = nand_oob_16.eccpos;
1350 }
1351 else if (nand->page_size == 2048)
1352 {
1353 state->oob_size = 64;
1354 state->eccpos = nand_oob_64.eccpos;
1355 }
1356 state->oob = malloc(state->oob_size);
1357 }
1358
1359 return ERROR_OK;
1360 }
1361 static int nand_fileio_cleanup(struct nand_fileio_state *state)
1362 {
1363 if (state->file_opened)
1364 fileio_close(&state->fileio);
1365
1366 if (state->oob)
1367 {
1368 free(state->oob);
1369 state->oob = NULL;
1370 }
1371 if (state->page)
1372 {
1373 free(state->page);
1374 state->page = NULL;
1375 }
1376 return ERROR_OK;
1377 }
1378 static int nand_fileio_finish(struct nand_fileio_state *state)
1379 {
1380 nand_fileio_cleanup(state);
1381 return duration_measure(&state->bench);
1382 }
1383
1384 static COMMAND_HELPER(nand_fileio_parse_args, struct nand_fileio_state *state,
1385 struct nand_device **dev, enum fileio_access filemode,
1386 bool need_size, bool sw_ecc)
1387 {
1388 nand_fileio_init(state);
1389
1390 unsigned minargs = need_size ? 4 : 3;
1391 if (CMD_ARGC < minargs)
1392 return ERROR_COMMAND_SYNTAX_ERROR;
1393
1394 struct nand_device *nand;
1395 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand);
1396 if (ERROR_OK != retval)
1397 return retval;
1398
1399 if (NULL == nand->device)
1400 {
1401 command_print(CMD_CTX, "#%s: not probed", CMD_ARGV[0]);
1402 return ERROR_OK;
1403 }
1404
1405 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], state->address);
1406 if (need_size)
1407 {
1408 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[3], state->size);
1409 if (state->size % nand->page_size)
1410 {
1411 command_print(CMD_CTX, "only page-aligned sizes are supported");
1412 return ERROR_COMMAND_SYNTAX_ERROR;
1413 }
1414 }
1415
1416 if (CMD_ARGC > minargs)
1417 {
1418 for (unsigned i = minargs; i < CMD_ARGC; i++)
1419 {
1420 if (!strcmp(CMD_ARGV[i], "oob_raw"))
1421 state->oob_format |= NAND_OOB_RAW;
1422 else if (!strcmp(CMD_ARGV[i], "oob_only"))
1423 state->oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1424 else if (sw_ecc && !strcmp(CMD_ARGV[i], "oob_softecc"))
1425 state->oob_format |= NAND_OOB_SW_ECC;
1426 else if (sw_ecc && !strcmp(CMD_ARGV[i], "oob_softecc_kw"))
1427 state->oob_format |= NAND_OOB_SW_ECC_KW;
1428 else
1429 {
1430 command_print(CMD_CTX, "unknown option: %s", CMD_ARGV[i]);
1431 return ERROR_COMMAND_SYNTAX_ERROR;
1432 }
1433 }
1434 }
1435
1436 retval = nand_fileio_start(CMD_CTX, nand, CMD_ARGV[1], filemode, state);
1437 if (ERROR_OK != retval)
1438 return retval;
1439
1440 if (!need_size)
1441 state->size = state->fileio.size;
1442
1443 *dev = nand;
1444
1445 return ERROR_OK;
1446 }
1447
1448 /**
1449 * @returns If no error occurred, returns number of bytes consumed;
1450 * otherwise, returns a negative error code.)
1451 */
1452 static int nand_fileio_read(struct nand_device *nand,
1453 struct nand_fileio_state *s)
1454 {
1455 size_t total_read = 0;
1456 size_t one_read;
1457
1458 if (NULL != s->page)
1459 {
1460 fileio_read(&s->fileio, s->page_size, s->page, &one_read);
1461 if (one_read < s->page_size)
1462 memset(s->page + one_read, 0xff, s->page_size - one_read);
1463 total_read += one_read;
1464 }
1465
1466 if (s->oob_format & NAND_OOB_SW_ECC)
1467 {
1468 uint8_t ecc[3];
1469 memset(s->oob, 0xff, s->oob_size);
1470 for (uint32_t i = 0, j = 0; i < s->page_size; i += 256)
1471 {
1472 nand_calculate_ecc(nand, s->page + i, ecc);
1473 s->oob[s->eccpos[j++]] = ecc[0];
1474 s->oob[s->eccpos[j++]] = ecc[1];
1475 s->oob[s->eccpos[j++]] = ecc[2];
1476 }
1477 }
1478 else if (s->oob_format & NAND_OOB_SW_ECC_KW)
1479 {
1480 /*
1481 * In this case eccpos is not used as
1482 * the ECC data is always stored contigously
1483 * at the end of the OOB area. It consists
1484 * of 10 bytes per 512-byte data block.
1485 */
1486 uint8_t *ecc = s->oob + s->oob_size - s->page_size / 512 * 10;
1487 memset(s->oob, 0xff, s->oob_size);
1488 for (uint32_t i = 0; i < s->page_size; i += 512)
1489 {
1490 nand_calculate_ecc_kw(nand, s->page + i, ecc);
1491 ecc += 10;
1492 }
1493 }
1494 else if (NULL != s->oob)
1495 {
1496 fileio_read(&s->fileio, s->oob_size, s->oob, &one_read);
1497 if (one_read < s->oob_size)
1498 memset(s->oob + one_read, 0xff, s->oob_size - one_read);
1499 total_read += one_read;
1500 }
1501 return total_read;
1502 }
1503
1504 COMMAND_HANDLER(handle_nand_write_command)
1505 {
1506 struct nand_device *nand = NULL;
1507 struct nand_fileio_state s;
1508 int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
1509 &s, &nand, FILEIO_READ, false, true);
1510 if (ERROR_OK != retval)
1511 return retval;
1512
1513 uint32_t total_bytes = s.size;
1514 while (s.size > 0)
1515 {
1516 int bytes_read = nand_fileio_read(nand, &s);
1517 if (bytes_read <= 0)
1518 {
1519 command_print(CMD_CTX, "error while reading file");
1520 return nand_fileio_cleanup(&s);
1521 }
1522 s.size -= bytes_read;
1523
1524 retval = nand_write_page(nand, s.address / nand->page_size,
1525 s.page, s.page_size, s.oob, s.oob_size);
1526 if (ERROR_OK != retval)
1527 {
1528 command_print(CMD_CTX, "failed writing file %s "
1529 "to NAND flash %s at offset 0x%8.8" PRIx32,
1530 CMD_ARGV[1], CMD_ARGV[0], s.address);
1531 return nand_fileio_cleanup(&s);
1532 }
1533 s.address += s.page_size;
1534 }
1535
1536 if (nand_fileio_finish(&s))
1537 {
1538 command_print(CMD_CTX, "wrote file %s to NAND flash %s up to "
1539 "offset 0x%8.8" PRIx32 " in %fs (%0.3f kb/s)",
1540 CMD_ARGV[1], CMD_ARGV[0], s.address, duration_elapsed(&s.bench),
1541 duration_kbps(&s.bench, total_bytes));
1542 }
1543 return ERROR_OK;
1544 }
1545
1546 COMMAND_HANDLER(handle_nand_verify_command)
1547 {
1548 struct nand_device *nand = NULL;
1549 struct nand_fileio_state file;
1550 int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
1551 &file, &nand, FILEIO_READ, false, true);
1552 if (ERROR_OK != retval)
1553 return retval;
1554
1555 struct nand_fileio_state dev;
1556 nand_fileio_init(&dev);
1557 dev.address = file.address;
1558 dev.size = file.size;
1559 dev.oob_format = file.oob_format;
1560 retval = nand_fileio_start(CMD_CTX, nand, NULL, FILEIO_NONE, &dev);
1561 if (ERROR_OK != retval)
1562 return retval;
1563
1564 while (file.size > 0)
1565 {
1566 int retval = nand_read_page(nand, dev.address / dev.page_size,
1567 dev.page, dev.page_size, dev.oob, dev.oob_size);
1568 if (ERROR_OK != retval)
1569 {
1570 command_print(CMD_CTX, "reading NAND flash page failed");
1571 nand_fileio_cleanup(&dev);
1572 return nand_fileio_cleanup(&file);
1573 }
1574
1575 int bytes_read = nand_fileio_read(nand, &file);
1576 if (bytes_read <= 0)
1577 {
1578 command_print(CMD_CTX, "error while reading file");
1579 nand_fileio_cleanup(&dev);
1580 return nand_fileio_cleanup(&file);
1581 }
1582
1583 if ((dev.page && memcmp(dev.page, file.page, dev.page_size)) ||
1584 (dev.oob && memcmp(dev.oob, file.oob, dev.oob_size)) )
1585 {
1586 command_print(CMD_CTX, "NAND flash contents differ "
1587 "at 0x%8.8" PRIx32, dev.address);
1588 nand_fileio_cleanup(&dev);
1589 return nand_fileio_cleanup(&file);
1590 }
1591
1592 file.size -= bytes_read;
1593 dev.address += nand->page_size;
1594 }
1595
1596 if (nand_fileio_finish(&file) == ERROR_OK)
1597 {
1598 command_print(CMD_CTX, "verified file %s in NAND flash %s "
1599 "up to offset 0x%8.8" PRIx32 " in %fs (%0.3f kb/s)",
1600 CMD_ARGV[1], CMD_ARGV[0], dev.address, duration_elapsed(&file.bench),
1601 duration_kbps(&file.bench, dev.size));
1602 }
1603
1604 return nand_fileio_cleanup(&dev);
1605 }
1606
1607 COMMAND_HANDLER(handle_nand_dump_command)
1608 {
1609 struct nand_device *nand = NULL;
1610 struct nand_fileio_state s;
1611 int retval = CALL_COMMAND_HANDLER(nand_fileio_parse_args,
1612 &s, &nand, FILEIO_WRITE, true, false);
1613 if (ERROR_OK != retval)
1614 return retval;
1615
1616 while (s.size > 0)
1617 {
1618 size_t size_written;
1619 int retval = nand_read_page(nand, s.address / nand->page_size,
1620 s.page, s.page_size, s.oob, s.oob_size);
1621 if (ERROR_OK != retval)
1622 {
1623 command_print(CMD_CTX, "reading NAND flash page failed");
1624 return nand_fileio_cleanup(&s);
1625 }
1626
1627 if (NULL != s.page)
1628 fileio_write(&s.fileio, s.page_size, s.page, &size_written);
1629
1630 if (NULL != s.oob)
1631 fileio_write(&s.fileio, s.oob_size, s.oob, &size_written);
1632
1633 s.size -= nand->page_size;
1634 s.address += nand->page_size;
1635 }
1636
1637 if (nand_fileio_finish(&s) == ERROR_OK)
1638 {
1639 command_print(CMD_CTX, "dumped %zu bytes in %fs (%0.3f kb/s)",
1640 s.fileio.size, duration_elapsed(&s.bench),
1641 duration_kbps(&s.bench, s.fileio.size));
1642 }
1643 return ERROR_OK;
1644 }
1645
1646 COMMAND_HANDLER(handle_nand_raw_access_command)
1647 {
1648 if ((CMD_ARGC < 1) || (CMD_ARGC > 2))
1649 {
1650 return ERROR_COMMAND_SYNTAX_ERROR;
1651 }
1652
1653 struct nand_device *p;
1654 int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &p);
1655 if (ERROR_OK != retval)
1656 return retval;
1657
1658 if (NULL == p->device)
1659 {
1660 command_print(CMD_CTX, "#%s: not probed", CMD_ARGV[0]);
1661 return ERROR_OK;
1662 }
1663
1664 if (CMD_ARGC == 2)
1665 COMMAND_PARSE_ENABLE(CMD_ARGV[1], p->use_raw);
1666
1667 const char *msg = p->use_raw ? "enabled" : "disabled";
1668 command_print(CMD_CTX, "raw access is %s", msg);
1669
1670 return ERROR_OK;
1671 }
1672
1673 static const struct command_registration nand_exec_command_handlers[] = {
1674 {
1675 .name = "list",
1676 .handler = &handle_nand_list_command,
1677 .mode = COMMAND_EXEC,
1678 .help = "list configured NAND flash devices",
1679 },
1680 {
1681 .name = "info",
1682 .handler = &handle_nand_info_command,
1683 .mode = COMMAND_EXEC,
1684 .usage = "<bank>",
1685 .help = "print info about a NAND flash device",
1686 },
1687 {
1688 .name = "probe",
1689 .handler = &handle_nand_probe_command,
1690 .mode = COMMAND_EXEC,
1691 .usage = "<bank>",
1692 .help = "identify NAND flash device <num>",
1693
1694 },
1695 {
1696 .name = "check_bad_blocks",
1697 .handler = &handle_nand_check_bad_blocks_command,
1698 .mode = COMMAND_EXEC,
1699 .usage = "<bank> [<offset> <length>]",
1700 .help = "check NAND flash device <num> for bad blocks",
1701 },
1702 {
1703 .name = "erase",
1704 .handler = &handle_nand_erase_command,
1705 .mode = COMMAND_EXEC,
1706 .usage = "<bank> [<offset> <length>]",
1707 .help = "erase blocks on NAND flash device",
1708 },
1709 {
1710 .name = "dump",
1711 .handler = &handle_nand_dump_command,
1712 .mode = COMMAND_EXEC,
1713 .usage = "<bank> <filename> <offset> <length> "
1714 "[oob_raw | oob_only]",
1715 .help = "dump from NAND flash device",
1716 },
1717 {
1718 .name = "verify",
1719 .handler = &handle_nand_verify_command,
1720 .mode = COMMAND_EXEC,
1721 .usage = "<bank> <filename> <offset> "
1722 "[oob_raw | oob_only | oob_softecc | oob_softecc_kw]",
1723 .help = "verify NAND flash device",
1724 },
1725 {
1726 .name = "write",
1727 .handler = &handle_nand_write_command,
1728 .mode = COMMAND_EXEC,
1729 .usage = "<bank> <filename> <offset> "
1730 "[oob_raw | oob_only | oob_softecc | oob_softecc_kw]",
1731 .help = "write to NAND flash device",
1732 },
1733 {
1734 .name = "raw_access",
1735 .handler = &handle_nand_raw_access_command,
1736 .mode = COMMAND_EXEC,
1737 .usage = "<num> ['enable'|'disable']",
1738 .help = "raw access to NAND flash device",
1739 },
1740 COMMAND_REGISTRATION_DONE
1741 };
1742
1743 int nand_init(struct command_context *cmd_ctx)
1744 {
1745 if (!nand_devices)
1746 return ERROR_OK;
1747 struct command *parent = command_find_in_context(cmd_ctx, "nand");
1748 return register_commands(cmd_ctx, parent, nand_exec_command_handlers);
1749 }
1750
1751 COMMAND_HANDLER(handle_nand_init_command)
1752 {
1753 if (CMD_ARGC != 0)
1754 return ERROR_COMMAND_SYNTAX_ERROR;
1755
1756 static bool nand_initialized = false;
1757 if (nand_initialized)
1758 {
1759 LOG_INFO("'nand init' has already been called");
1760 return ERROR_OK;
1761 }
1762 nand_initialized = true;
1763
1764 LOG_DEBUG("Initializing NAND devices...");
1765 return nand_init(CMD_CTX);
1766 }
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)