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Alexei Babich <a.babich@rez.ru> imx31 nand flash controller support
[openocd.git] / src / flash / nand.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "nand.h"
28 #include "time_support.h"
29 #include "fileio.h"
30
31 static int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
32 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
33 static int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
34 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
35 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
36 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
37 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
38
39 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40
41 static int nand_read_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
42 //static int nand_read_plain(struct nand_device_s *device, uint32_t address, uint8_t *data, uint32_t data_size);
43
44 static int nand_write_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
45
46 /* NAND flash controller
47 */
48 extern nand_flash_controller_t davinci_nand_controller;
49 extern nand_flash_controller_t lpc3180_nand_controller;
50 extern nand_flash_controller_t orion_nand_controller;
51 extern nand_flash_controller_t s3c2410_nand_controller;
52 extern nand_flash_controller_t s3c2412_nand_controller;
53 extern nand_flash_controller_t s3c2440_nand_controller;
54 extern nand_flash_controller_t s3c2443_nand_controller;
55 extern nand_flash_controller_t imx31_nand_flash_controller;
56
57 /* extern nand_flash_controller_t boundary_scan_nand_controller; */
58
59 static nand_flash_controller_t *nand_flash_controllers[] =
60 {
61 &davinci_nand_controller,
62 &lpc3180_nand_controller,
63 &orion_nand_controller,
64 &s3c2410_nand_controller,
65 &s3c2412_nand_controller,
66 &s3c2440_nand_controller,
67 &s3c2443_nand_controller,
68 &imx31_nand_flash_controller,
69 /* &boundary_scan_nand_controller, */
70 NULL
71 };
72
73 /* configured NAND devices and NAND Flash command handler */
74 static nand_device_t *nand_devices = NULL;
75 static command_t *nand_cmd;
76
77 /* Chip ID list
78 *
79 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
80 * options
81 *
82 * Pagesize; 0, 256, 512
83 * 0 get this information from the extended chip ID
84 * 256 256 Byte page size
85 * 512 512 Byte page size
86 */
87 static nand_info_t nand_flash_ids[] =
88 {
89 /* start "museum" IDs */
90 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
91 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
92 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
93 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
94 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
95 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
96 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
97 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
98 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
99 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
100
101 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
102 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
103 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
104 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
105 /* end "museum" IDs */
106
107 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
108 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
109 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
110 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
111
112 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
113 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
114 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
115 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
116
117 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
118 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
119 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
120 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
121
122 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
123 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
124 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
125 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
126 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
127 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
128 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
129
130 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
131
132 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
133 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
134 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
135 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
136
137 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
138 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
139 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
140 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
141
142 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
143 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
144 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
145 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
146
147 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
148 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
149 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
150 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
151
152 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
153 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
154 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
155 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
156
157 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
158 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
159 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
160 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
161
162 {NULL, 0, 0, 0, 0, 0 }
163 };
164
165 /* Manufacturer ID list
166 */
167 static nand_manufacturer_t nand_manuf_ids[] =
168 {
169 {0x0, "unknown"},
170 {NAND_MFR_TOSHIBA, "Toshiba"},
171 {NAND_MFR_SAMSUNG, "Samsung"},
172 {NAND_MFR_FUJITSU, "Fujitsu"},
173 {NAND_MFR_NATIONAL, "National"},
174 {NAND_MFR_RENESAS, "Renesas"},
175 {NAND_MFR_STMICRO, "ST Micro"},
176 {NAND_MFR_HYNIX, "Hynix"},
177 {NAND_MFR_MICRON, "Micron"},
178 {0x0, NULL},
179 };
180
181 /*
182 * Define default oob placement schemes for large and small page devices
183 */
184
185 #if 0
186 static nand_ecclayout_t nand_oob_8 = {
187 .eccbytes = 3,
188 .eccpos = {0, 1, 2},
189 .oobfree = {
190 {.offset = 3,
191 .length = 2},
192 {.offset = 6,
193 .length = 2}}
194 };
195 #endif
196
197 static nand_ecclayout_t nand_oob_16 = {
198 .eccbytes = 6,
199 .eccpos = {0, 1, 2, 3, 6, 7},
200 .oobfree = {
201 {.offset = 8,
202 . length = 8}}
203 };
204
205 static nand_ecclayout_t nand_oob_64 = {
206 .eccbytes = 24,
207 .eccpos = {
208 40, 41, 42, 43, 44, 45, 46, 47,
209 48, 49, 50, 51, 52, 53, 54, 55,
210 56, 57, 58, 59, 60, 61, 62, 63},
211 .oobfree = {
212 {.offset = 2,
213 .length = 38}}
214 };
215
216 /* nand device <nand_controller> [controller options]
217 */
218 static int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
219 {
220 int i;
221 int retval;
222
223 if (argc < 1)
224 {
225 LOG_WARNING("incomplete flash device nand configuration");
226 return ERROR_FLASH_BANK_INVALID;
227 }
228
229 for (i = 0; nand_flash_controllers[i]; i++)
230 {
231 nand_device_t *p, *c;
232
233 if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
234 {
235 /* register flash specific commands */
236 if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
237 {
238 LOG_ERROR("couldn't register '%s' commands", args[0]);
239 return retval;
240 }
241
242 c = malloc(sizeof(nand_device_t));
243
244 c->controller = nand_flash_controllers[i];
245 c->controller_priv = NULL;
246 c->manufacturer = NULL;
247 c->device = NULL;
248 c->bus_width = 0;
249 c->address_cycles = 0;
250 c->page_size = 0;
251 c->use_raw = 0;
252 c->next = NULL;
253
254 if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
255 {
256 LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
257 free(c);
258 return ERROR_OK;
259 }
260
261 /* put NAND device in linked list */
262 if (nand_devices)
263 {
264 /* find last flash device */
265 for (p = nand_devices; p && p->next; p = p->next);
266 if (p)
267 p->next = c;
268 }
269 else
270 {
271 nand_devices = c;
272 }
273
274 return ERROR_OK;
275 }
276 }
277
278 /* no valid NAND controller was found (i.e. the configuration option,
279 * didn't match one of the compiled-in controllers)
280 */
281 LOG_ERROR("No valid NAND flash controller found (%s)", args[0]);
282 LOG_ERROR("compiled-in NAND flash controllers:");
283 for (i = 0; nand_flash_controllers[i]; i++)
284 {
285 LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
286 }
287
288 return ERROR_OK;
289 }
290
291 int nand_register_commands(struct command_context_s *cmd_ctx)
292 {
293 nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
294
295 register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
296
297 return ERROR_OK;
298 }
299
300 int nand_init(struct command_context_s *cmd_ctx)
301 {
302 if (nand_devices)
303 {
304 register_command(cmd_ctx, nand_cmd, "list", handle_nand_list_command, COMMAND_EXEC,
305 "list configured NAND flash devices");
306 register_command(cmd_ctx, nand_cmd, "info", handle_nand_info_command, COMMAND_EXEC,
307 "print info about NAND flash device <num>");
308 register_command(cmd_ctx, nand_cmd, "probe", handle_nand_probe_command, COMMAND_EXEC,
309 "identify NAND flash device <num>");
310 register_command(cmd_ctx, nand_cmd, "check_bad_blocks", handle_nand_check_bad_blocks_command, COMMAND_EXEC,
311 "check NAND flash device <num> for bad blocks [<offset> <length>]");
312 register_command(cmd_ctx, nand_cmd, "erase", handle_nand_erase_command, COMMAND_EXEC,
313 "erase blocks on NAND flash device <num> <offset> <length>");
314 register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
315 "dump from NAND flash device <num> <filename> "
316 "<offset> <length> [oob_raw | oob_only]");
317 register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC,
318 "write to NAND flash device <num> <filename> <offset> [oob_raw | oob_only | oob_softecc | oob_softecc_kw]");
319 register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
320 "raw access to NAND flash device <num> ['enable'|'disable']");
321 }
322
323 return ERROR_OK;
324 }
325
326 nand_device_t *get_nand_device_by_num(int num)
327 {
328 nand_device_t *p;
329 int i = 0;
330
331 for (p = nand_devices; p; p = p->next)
332 {
333 if (i++ == num)
334 {
335 return p;
336 }
337 }
338
339 return NULL;
340 }
341
342 static int nand_build_bbt(struct nand_device_s *device, int first, int last)
343 {
344 uint32_t page = 0x0;
345 int i;
346 uint8_t oob[6];
347
348 if ((first < 0) || (first >= device->num_blocks))
349 first = 0;
350
351 if ((last >= device->num_blocks) || (last == -1))
352 last = device->num_blocks - 1;
353
354 for (i = first; i < last; i++)
355 {
356 nand_read_page(device, page, NULL, 0, oob, 6);
357
358 if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
359 || (((device->page_size == 512) && (oob[5] != 0xff)) ||
360 ((device->page_size == 2048) && (oob[0] != 0xff))))
361 {
362 LOG_WARNING("bad block: %i", i);
363 device->blocks[i].is_bad = 1;
364 }
365 else
366 {
367 device->blocks[i].is_bad = 0;
368 }
369
370 page += (device->erase_size / device->page_size);
371 }
372
373 return ERROR_OK;
374 }
375
376 int nand_read_status(struct nand_device_s *device, uint8_t *status)
377 {
378 if (!device->device)
379 return ERROR_NAND_DEVICE_NOT_PROBED;
380
381 /* Send read status command */
382 device->controller->command(device, NAND_CMD_STATUS);
383
384 alive_sleep(1);
385
386 /* read status */
387 if (device->device->options & NAND_BUSWIDTH_16)
388 {
389 uint16_t data;
390 device->controller->read_data(device, &data);
391 *status = data & 0xff;
392 }
393 else
394 {
395 device->controller->read_data(device, status);
396 }
397
398 return ERROR_OK;
399 }
400
401 static int nand_poll_ready(struct nand_device_s *device, int timeout)
402 {
403 uint8_t status;
404
405 device->controller->command(device, NAND_CMD_STATUS);
406 do {
407 if (device->device->options & NAND_BUSWIDTH_16) {
408 uint16_t data;
409 device->controller->read_data(device, &data);
410 status = data & 0xff;
411 } else {
412 device->controller->read_data(device, &status);
413 }
414 if (status & NAND_STATUS_READY)
415 break;
416 alive_sleep(1);
417 } while (timeout--);
418
419 return (status & NAND_STATUS_READY) != 0;
420 }
421
422 int nand_probe(struct nand_device_s *device)
423 {
424 uint8_t manufacturer_id, device_id;
425 uint8_t id_buff[6];
426 int retval;
427 int i;
428
429 /* clear device data */
430 device->device = NULL;
431 device->manufacturer = NULL;
432
433 /* clear device parameters */
434 device->bus_width = 0;
435 device->address_cycles = 0;
436 device->page_size = 0;
437 device->erase_size = 0;
438
439 /* initialize controller (device parameters are zero, use controller default) */
440 if ((retval = device->controller->init(device) != ERROR_OK))
441 {
442 switch (retval)
443 {
444 case ERROR_NAND_OPERATION_FAILED:
445 LOG_DEBUG("controller initialization failed");
446 return ERROR_NAND_OPERATION_FAILED;
447 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
448 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
449 return ERROR_NAND_OPERATION_FAILED;
450 default:
451 LOG_ERROR("BUG: unknown controller initialization failure");
452 return ERROR_NAND_OPERATION_FAILED;
453 }
454 }
455
456 device->controller->command(device, NAND_CMD_RESET);
457 device->controller->reset(device);
458
459 device->controller->command(device, NAND_CMD_READID);
460 device->controller->address(device, 0x0);
461
462 if (device->bus_width == 8)
463 {
464 device->controller->read_data(device, &manufacturer_id);
465 device->controller->read_data(device, &device_id);
466 }
467 else
468 {
469 uint16_t data_buf;
470 device->controller->read_data(device, &data_buf);
471 manufacturer_id = data_buf & 0xff;
472 device->controller->read_data(device, &data_buf);
473 device_id = data_buf & 0xff;
474 }
475
476 for (i = 0; nand_flash_ids[i].name; i++)
477 {
478 if (nand_flash_ids[i].id == device_id)
479 {
480 device->device = &nand_flash_ids[i];
481 break;
482 }
483 }
484
485 for (i = 0; nand_manuf_ids[i].name; i++)
486 {
487 if (nand_manuf_ids[i].id == manufacturer_id)
488 {
489 device->manufacturer = &nand_manuf_ids[i];
490 break;
491 }
492 }
493
494 if (!device->manufacturer)
495 {
496 device->manufacturer = &nand_manuf_ids[0];
497 device->manufacturer->id = manufacturer_id;
498 }
499
500 if (!device->device)
501 {
502 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
503 manufacturer_id, device_id);
504 return ERROR_NAND_OPERATION_FAILED;
505 }
506
507 LOG_DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
508
509 /* initialize device parameters */
510
511 /* bus width */
512 if (device->device->options & NAND_BUSWIDTH_16)
513 device->bus_width = 16;
514 else
515 device->bus_width = 8;
516
517 /* Do we need extended device probe information? */
518 if (device->device->page_size == 0 ||
519 device->device->erase_size == 0)
520 {
521 if (device->bus_width == 8)
522 {
523 device->controller->read_data(device, id_buff + 3);
524 device->controller->read_data(device, id_buff + 4);
525 device->controller->read_data(device, id_buff + 5);
526 }
527 else
528 {
529 uint16_t data_buf;
530
531 device->controller->read_data(device, &data_buf);
532 id_buff[3] = data_buf;
533
534 device->controller->read_data(device, &data_buf);
535 id_buff[4] = data_buf;
536
537 device->controller->read_data(device, &data_buf);
538 id_buff[5] = data_buf >> 8;
539 }
540 }
541
542 /* page size */
543 if (device->device->page_size == 0)
544 {
545 device->page_size = 1 << (10 + (id_buff[4] & 3));
546 }
547 else if (device->device->page_size == 256)
548 {
549 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
550 return ERROR_NAND_OPERATION_FAILED;
551 }
552 else
553 {
554 device->page_size = device->device->page_size;
555 }
556
557 /* number of address cycles */
558 if (device->page_size <= 512)
559 {
560 /* small page devices */
561 if (device->device->chip_size <= 32)
562 device->address_cycles = 3;
563 else if (device->device->chip_size <= 8*1024)
564 device->address_cycles = 4;
565 else
566 {
567 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
568 device->address_cycles = 5;
569 }
570 }
571 else
572 {
573 /* large page devices */
574 if (device->device->chip_size <= 128)
575 device->address_cycles = 4;
576 else if (device->device->chip_size <= 32*1024)
577 device->address_cycles = 5;
578 else
579 {
580 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
581 device->address_cycles = 6;
582 }
583 }
584
585 /* erase size */
586 if (device->device->erase_size == 0)
587 {
588 switch ((id_buff[4] >> 4) & 3) {
589 case 0:
590 device->erase_size = 64 << 10;
591 break;
592 case 1:
593 device->erase_size = 128 << 10;
594 break;
595 case 2:
596 device->erase_size = 256 << 10;
597 break;
598 case 3:
599 device->erase_size =512 << 10;
600 break;
601 }
602 }
603 else
604 {
605 device->erase_size = device->device->erase_size;
606 }
607
608 /* initialize controller, but leave parameters at the controllers default */
609 if ((retval = device->controller->init(device) != ERROR_OK))
610 {
611 switch (retval)
612 {
613 case ERROR_NAND_OPERATION_FAILED:
614 LOG_DEBUG("controller initialization failed");
615 return ERROR_NAND_OPERATION_FAILED;
616 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
617 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
618 device->bus_width, device->address_cycles, device->page_size);
619 return ERROR_NAND_OPERATION_FAILED;
620 default:
621 LOG_ERROR("BUG: unknown controller initialization failure");
622 return ERROR_NAND_OPERATION_FAILED;
623 }
624 }
625
626 device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
627 device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
628
629 for (i = 0; i < device->num_blocks; i++)
630 {
631 device->blocks[i].size = device->erase_size;
632 device->blocks[i].offset = i * device->erase_size;
633 device->blocks[i].is_erased = -1;
634 device->blocks[i].is_bad = -1;
635 }
636
637 return ERROR_OK;
638 }
639
640 int nand_erase(struct nand_device_s *device, int first_block, int last_block)
641 {
642 int i;
643 uint32_t page;
644 uint8_t status;
645 int retval;
646
647 if (!device->device)
648 return ERROR_NAND_DEVICE_NOT_PROBED;
649
650 if ((first_block < 0) || (last_block > device->num_blocks))
651 return ERROR_INVALID_ARGUMENTS;
652
653 /* make sure we know if a block is bad before erasing it */
654 for (i = first_block; i <= last_block; i++)
655 {
656 if (device->blocks[i].is_bad == -1)
657 {
658 nand_build_bbt(device, i, last_block);
659 break;
660 }
661 }
662
663 for (i = first_block; i <= last_block; i++)
664 {
665 /* Send erase setup command */
666 device->controller->command(device, NAND_CMD_ERASE1);
667
668 page = i * (device->erase_size / device->page_size);
669
670 /* Send page address */
671 if (device->page_size <= 512)
672 {
673 /* row */
674 device->controller->address(device, page & 0xff);
675 device->controller->address(device, (page >> 8) & 0xff);
676
677 /* 3rd cycle only on devices with more than 32 MiB */
678 if (device->address_cycles >= 4)
679 device->controller->address(device, (page >> 16) & 0xff);
680
681 /* 4th cycle only on devices with more than 8 GiB */
682 if (device->address_cycles >= 5)
683 device->controller->address(device, (page >> 24) & 0xff);
684 }
685 else
686 {
687 /* row */
688 device->controller->address(device, page & 0xff);
689 device->controller->address(device, (page >> 8) & 0xff);
690
691 /* 3rd cycle only on devices with more than 128 MiB */
692 if (device->address_cycles >= 5)
693 device->controller->address(device, (page >> 16) & 0xff);
694 }
695
696 /* Send erase confirm command */
697 device->controller->command(device, NAND_CMD_ERASE2);
698
699 retval = device->controller->nand_ready ?
700 device->controller->nand_ready(device, 1000) :
701 nand_poll_ready(device, 1000);
702 if (!retval) {
703 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
704 return ERROR_NAND_OPERATION_TIMEOUT;
705 }
706
707 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
708 {
709 LOG_ERROR("couldn't read status");
710 return ERROR_NAND_OPERATION_FAILED;
711 }
712
713 if (status & 0x1)
714 {
715 LOG_ERROR("erase operation didn't pass, status: 0x%2.2x", status);
716 return ERROR_NAND_OPERATION_FAILED;
717 }
718
719 device->blocks[i].is_erased = 1;
720 }
721
722 return ERROR_OK;
723 }
724
725 #if 0
726 static int nand_read_plain(struct nand_device_s *device, uint32_t address, uint8_t *data, uint32_t data_size)
727 {
728 uint8_t *page;
729
730 if (!device->device)
731 return ERROR_NAND_DEVICE_NOT_PROBED;
732
733 if (address % device->page_size)
734 {
735 LOG_ERROR("reads need to be page aligned");
736 return ERROR_NAND_OPERATION_FAILED;
737 }
738
739 page = malloc(device->page_size);
740
741 while (data_size > 0)
742 {
743 uint32_t thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
744 uint32_t page_address;
745
746
747 page_address = address / device->page_size;
748
749 nand_read_page(device, page_address, page, device->page_size, NULL, 0);
750
751 memcpy(data, page, thisrun_size);
752
753 address += thisrun_size;
754 data += thisrun_size;
755 data_size -= thisrun_size;
756 }
757
758 free(page);
759
760 return ERROR_OK;
761 }
762
763 static int nand_write_plain(struct nand_device_s *device, uint32_t address, uint8_t *data, uint32_t data_size)
764 {
765 uint8_t *page;
766
767 if (!device->device)
768 return ERROR_NAND_DEVICE_NOT_PROBED;
769
770 if (address % device->page_size)
771 {
772 LOG_ERROR("writes need to be page aligned");
773 return ERROR_NAND_OPERATION_FAILED;
774 }
775
776 page = malloc(device->page_size);
777
778 while (data_size > 0)
779 {
780 uint32_t thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
781 uint32_t page_address;
782
783 memset(page, 0xff, device->page_size);
784 memcpy(page, data, thisrun_size);
785
786 page_address = address / device->page_size;
787
788 nand_write_page(device, page_address, page, device->page_size, NULL, 0);
789
790 address += thisrun_size;
791 data += thisrun_size;
792 data_size -= thisrun_size;
793 }
794
795 free(page);
796
797 return ERROR_OK;
798 }
799 #endif
800
801 int nand_write_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
802 {
803 uint32_t block;
804
805 if (!device->device)
806 return ERROR_NAND_DEVICE_NOT_PROBED;
807
808 block = page / (device->erase_size / device->page_size);
809 if (device->blocks[block].is_erased == 1)
810 device->blocks[block].is_erased = 0;
811
812 if (device->use_raw || device->controller->write_page == NULL)
813 return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
814 else
815 return device->controller->write_page(device, page, data, data_size, oob, oob_size);
816 }
817
818 static int nand_read_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
819 {
820 if (!device->device)
821 return ERROR_NAND_DEVICE_NOT_PROBED;
822
823 if (device->use_raw || device->controller->read_page == NULL)
824 return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
825 else
826 return device->controller->read_page(device, page, data, data_size, oob, oob_size);
827 }
828
829 int nand_read_page_raw(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
830 {
831 uint32_t i;
832
833 if (!device->device)
834 return ERROR_NAND_DEVICE_NOT_PROBED;
835
836 if (device->page_size <= 512)
837 {
838 /* small page device */
839 if (data)
840 device->controller->command(device, NAND_CMD_READ0);
841 else
842 device->controller->command(device, NAND_CMD_READOOB);
843
844 /* column (always 0, we start at the beginning of a page/OOB area) */
845 device->controller->address(device, 0x0);
846
847 /* row */
848 device->controller->address(device, page & 0xff);
849 device->controller->address(device, (page >> 8) & 0xff);
850
851 /* 4th cycle only on devices with more than 32 MiB */
852 if (device->address_cycles >= 4)
853 device->controller->address(device, (page >> 16) & 0xff);
854
855 /* 5th cycle only on devices with more than 8 GiB */
856 if (device->address_cycles >= 5)
857 device->controller->address(device, (page >> 24) & 0xff);
858 }
859 else
860 {
861 /* large page device */
862 device->controller->command(device, NAND_CMD_READ0);
863
864 /* column (0 when we start at the beginning of a page,
865 * or 2048 for the beginning of OOB area)
866 */
867 device->controller->address(device, 0x0);
868 if (data)
869 device->controller->address(device, 0x0);
870 else
871 device->controller->address(device, 0x8);
872
873 /* row */
874 device->controller->address(device, page & 0xff);
875 device->controller->address(device, (page >> 8) & 0xff);
876
877 /* 5th cycle only on devices with more than 128 MiB */
878 if (device->address_cycles >= 5)
879 device->controller->address(device, (page >> 16) & 0xff);
880
881 /* large page devices need a start command */
882 device->controller->command(device, NAND_CMD_READSTART);
883 }
884
885 if (device->controller->nand_ready) {
886 if (!device->controller->nand_ready(device, 100))
887 return ERROR_NAND_OPERATION_TIMEOUT;
888 } else {
889 alive_sleep(1);
890 }
891
892 if (data)
893 {
894 if (device->controller->read_block_data != NULL)
895 (device->controller->read_block_data)(device, data, data_size);
896 else
897 {
898 for (i = 0; i < data_size;)
899 {
900 if (device->device->options & NAND_BUSWIDTH_16)
901 {
902 device->controller->read_data(device, data);
903 data += 2;
904 i += 2;
905 }
906 else
907 {
908 device->controller->read_data(device, data);
909 data += 1;
910 i += 1;
911 }
912 }
913 }
914 }
915
916 if (oob)
917 {
918 if (device->controller->read_block_data != NULL)
919 (device->controller->read_block_data)(device, oob, oob_size);
920 else
921 {
922 for (i = 0; i < oob_size;)
923 {
924 if (device->device->options & NAND_BUSWIDTH_16)
925 {
926 device->controller->read_data(device, oob);
927 oob += 2;
928 i += 2;
929 }
930 else
931 {
932 device->controller->read_data(device, oob);
933 oob += 1;
934 i += 1;
935 }
936 }
937 }
938 }
939
940 return ERROR_OK;
941 }
942
943 int nand_write_page_raw(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
944 {
945 uint32_t i;
946 int retval;
947 uint8_t status;
948
949 if (!device->device)
950 return ERROR_NAND_DEVICE_NOT_PROBED;
951
952 device->controller->command(device, NAND_CMD_SEQIN);
953
954 if (device->page_size <= 512)
955 {
956 /* column (always 0, we start at the beginning of a page/OOB area) */
957 device->controller->address(device, 0x0);
958
959 /* row */
960 device->controller->address(device, page & 0xff);
961 device->controller->address(device, (page >> 8) & 0xff);
962
963 /* 4th cycle only on devices with more than 32 MiB */
964 if (device->address_cycles >= 4)
965 device->controller->address(device, (page >> 16) & 0xff);
966
967 /* 5th cycle only on devices with more than 8 GiB */
968 if (device->address_cycles >= 5)
969 device->controller->address(device, (page >> 24) & 0xff);
970 }
971 else
972 {
973 /* column (0 when we start at the beginning of a page,
974 * or 2048 for the beginning of OOB area)
975 */
976 device->controller->address(device, 0x0);
977 if (data)
978 device->controller->address(device, 0x0);
979 else
980 device->controller->address(device, 0x8);
981
982 /* row */
983 device->controller->address(device, page & 0xff);
984 device->controller->address(device, (page >> 8) & 0xff);
985
986 /* 5th cycle only on devices with more than 128 MiB */
987 if (device->address_cycles >= 5)
988 device->controller->address(device, (page >> 16) & 0xff);
989 }
990
991 if (data)
992 {
993 if (device->controller->write_block_data != NULL)
994 (device->controller->write_block_data)(device, data, data_size);
995 else
996 {
997 for (i = 0; i < data_size;)
998 {
999 if (device->device->options & NAND_BUSWIDTH_16)
1000 {
1001 uint16_t data_buf = le_to_h_u16(data);
1002 device->controller->write_data(device, data_buf);
1003 data += 2;
1004 i += 2;
1005 }
1006 else
1007 {
1008 device->controller->write_data(device, *data);
1009 data += 1;
1010 i += 1;
1011 }
1012 }
1013 }
1014 }
1015
1016 if (oob)
1017 {
1018 if (device->controller->write_block_data != NULL)
1019 (device->controller->write_block_data)(device, oob, oob_size);
1020 else
1021 {
1022 for (i = 0; i < oob_size;)
1023 {
1024 if (device->device->options & NAND_BUSWIDTH_16)
1025 {
1026 uint16_t oob_buf = le_to_h_u16(data);
1027 device->controller->write_data(device, oob_buf);
1028 oob += 2;
1029 i += 2;
1030 }
1031 else
1032 {
1033 device->controller->write_data(device, *oob);
1034 oob += 1;
1035 i += 1;
1036 }
1037 }
1038 }
1039 }
1040
1041 device->controller->command(device, NAND_CMD_PAGEPROG);
1042
1043 retval = device->controller->nand_ready ?
1044 device->controller->nand_ready(device, 100) :
1045 nand_poll_ready(device, 100);
1046 if (!retval)
1047 return ERROR_NAND_OPERATION_TIMEOUT;
1048
1049 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
1050 {
1051 LOG_ERROR("couldn't read status");
1052 return ERROR_NAND_OPERATION_FAILED;
1053 }
1054
1055 if (status & NAND_STATUS_FAIL)
1056 {
1057 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1058 return ERROR_NAND_OPERATION_FAILED;
1059 }
1060
1061 return ERROR_OK;
1062 }
1063
1064 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1065 {
1066 nand_device_t *p;
1067 int i;
1068
1069 if (!nand_devices)
1070 {
1071 command_print(cmd_ctx, "no NAND flash devices configured");
1072 return ERROR_OK;
1073 }
1074
1075 for (p = nand_devices, i = 0; p; p = p->next, i++)
1076 {
1077 if (p->device)
1078 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1079 i, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1080 else
1081 command_print(cmd_ctx, "#%i: not probed", i);
1082 }
1083
1084 return ERROR_OK;
1085 }
1086
1087 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1088 {
1089 nand_device_t *p;
1090 int i = 0;
1091 int j = 0;
1092 int first = -1;
1093 int last = -1;
1094
1095 switch (argc) {
1096 default:
1097 return ERROR_COMMAND_SYNTAX_ERROR;
1098 case 1:
1099 first = 0;
1100 last = INT32_MAX;
1101 break;
1102 case 2:
1103 first = last = strtoul(args[1], NULL, 0);
1104 break;
1105 case 3:
1106 first = strtoul(args[1], NULL, 0);
1107 last = strtoul(args[2], NULL, 0);
1108 break;
1109 }
1110
1111 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1112 if (p)
1113 {
1114 if (p->device)
1115 {
1116 if (first >= p->num_blocks)
1117 first = p->num_blocks - 1;
1118
1119 if (last >= p->num_blocks)
1120 last = p->num_blocks - 1;
1121
1122 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1123 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1124
1125 for (j = first; j <= last; j++)
1126 {
1127 char *erase_state, *bad_state;
1128
1129 if (p->blocks[j].is_erased == 0)
1130 erase_state = "not erased";
1131 else if (p->blocks[j].is_erased == 1)
1132 erase_state = "erased";
1133 else
1134 erase_state = "erase state unknown";
1135
1136 if (p->blocks[j].is_bad == 0)
1137 bad_state = "";
1138 else if (p->blocks[j].is_bad == 1)
1139 bad_state = " (marked bad)";
1140 else
1141 bad_state = " (block condition unknown)";
1142
1143 command_print(cmd_ctx,
1144 "\t#%i: 0x%8.8" PRIx32 " (%" PRId32 "kB) %s%s",
1145 j,
1146 p->blocks[j].offset,
1147 p->blocks[j].size / 1024,
1148 erase_state,
1149 bad_state);
1150 }
1151 }
1152 else
1153 {
1154 command_print(cmd_ctx, "#%s: not probed", args[0]);
1155 }
1156 }
1157
1158 return ERROR_OK;
1159 }
1160
1161 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1162 {
1163 nand_device_t *p;
1164 int retval;
1165
1166 if (argc != 1)
1167 {
1168 return ERROR_COMMAND_SYNTAX_ERROR;
1169 }
1170
1171 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1172 if (p)
1173 {
1174 if ((retval = nand_probe(p)) == ERROR_OK)
1175 {
1176 command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
1177 }
1178 else if (retval == ERROR_NAND_OPERATION_FAILED)
1179 {
1180 command_print(cmd_ctx, "probing failed for NAND flash device");
1181 }
1182 else
1183 {
1184 command_print(cmd_ctx, "unknown error when probing NAND flash device");
1185 }
1186 }
1187 else
1188 {
1189 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1190 }
1191
1192 return ERROR_OK;
1193 }
1194
1195 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1196 {
1197 nand_device_t *p;
1198 int retval;
1199
1200 if (argc != 3)
1201 {
1202 return ERROR_COMMAND_SYNTAX_ERROR;
1203
1204 }
1205
1206 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1207 if (p)
1208 {
1209 char *cp;
1210 unsigned long offset;
1211 unsigned long length;
1212
1213 offset = strtoul(args[1], &cp, 0);
1214 if (*cp || offset == ULONG_MAX || offset % p->erase_size)
1215 {
1216 return ERROR_INVALID_ARGUMENTS;
1217 }
1218 offset /= p->erase_size;
1219
1220 length = strtoul(args[2], &cp, 0);
1221 if (*cp || length == ULONG_MAX || length % p->erase_size)
1222 {
1223 return ERROR_INVALID_ARGUMENTS;
1224 }
1225 length -= 1;
1226 length /= p->erase_size;
1227
1228 retval = nand_erase(p, offset, offset + length);
1229 if (retval == ERROR_OK)
1230 {
1231 command_print(cmd_ctx, "successfully erased blocks "
1232 "%lu to %lu on NAND flash device '%s'",
1233 offset, offset + length, p->device->name);
1234 }
1235 else if (retval == ERROR_NAND_OPERATION_FAILED)
1236 {
1237 command_print(cmd_ctx, "erase failed");
1238 }
1239 else
1240 {
1241 command_print(cmd_ctx, "unknown error when erasing NAND flash device");
1242 }
1243 }
1244 else
1245 {
1246 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1247 }
1248
1249 return ERROR_OK;
1250 }
1251
1252 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1253 {
1254 nand_device_t *p;
1255 int retval;
1256 int first = -1;
1257 int last = -1;
1258
1259 if ((argc < 1) || (argc > 3) || (argc == 2))
1260 {
1261 return ERROR_COMMAND_SYNTAX_ERROR;
1262
1263 }
1264
1265 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1266 if (!p) {
1267 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds",
1268 args[0]);
1269 return ERROR_INVALID_ARGUMENTS;
1270 }
1271
1272 if (argc == 3)
1273 {
1274 char *cp;
1275 unsigned long offset;
1276 unsigned long length;
1277
1278 offset = strtoul(args[1], &cp, 0);
1279 if (*cp || offset == ULONG_MAX || offset % p->erase_size)
1280 {
1281 return ERROR_INVALID_ARGUMENTS;
1282 }
1283 offset /= p->erase_size;
1284
1285 length = strtoul(args[2], &cp, 0);
1286 if (*cp || length == ULONG_MAX || length % p->erase_size)
1287 {
1288 return ERROR_INVALID_ARGUMENTS;
1289 }
1290 length -= 1;
1291 length /= p->erase_size;
1292
1293 first = offset;
1294 last = offset + length;
1295 }
1296
1297 retval = nand_build_bbt(p, first, last);
1298 if (retval == ERROR_OK)
1299 {
1300 command_print(cmd_ctx, "checked NAND flash device for bad blocks, "
1301 "use \"nand info\" command to list blocks");
1302 }
1303 else if (retval == ERROR_NAND_OPERATION_FAILED)
1304 {
1305 command_print(cmd_ctx, "error when checking for bad blocks on "
1306 "NAND flash device");
1307 }
1308 else
1309 {
1310 command_print(cmd_ctx, "unknown error when checking for bad "
1311 "blocks on NAND flash device");
1312 }
1313
1314 return ERROR_OK;
1315 }
1316
1317 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1318 {
1319 uint32_t offset;
1320 uint32_t binary_size;
1321 uint32_t buf_cnt;
1322 enum oob_formats oob_format = NAND_OOB_NONE;
1323
1324 fileio_t fileio;
1325
1326 duration_t duration;
1327 char *duration_text;
1328
1329 nand_device_t *p;
1330
1331 if (argc < 3)
1332 {
1333 return ERROR_COMMAND_SYNTAX_ERROR;
1334
1335 }
1336
1337 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1338 if (p)
1339 {
1340 uint8_t *page = NULL;
1341 uint32_t page_size = 0;
1342 uint8_t *oob = NULL;
1343 uint32_t oob_size = 0;
1344 const int *eccpos = NULL;
1345
1346 offset = strtoul(args[2], NULL, 0);
1347
1348 if (argc > 3)
1349 {
1350 int i;
1351 for (i = 3; i < argc; i++)
1352 {
1353 if (!strcmp(args[i], "oob_raw"))
1354 oob_format |= NAND_OOB_RAW;
1355 else if (!strcmp(args[i], "oob_only"))
1356 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1357 else if (!strcmp(args[i], "oob_softecc"))
1358 oob_format |= NAND_OOB_SW_ECC;
1359 else if (!strcmp(args[i], "oob_softecc_kw"))
1360 oob_format |= NAND_OOB_SW_ECC_KW;
1361 else
1362 {
1363 command_print(cmd_ctx, "unknown option: %s", args[i]);
1364 return ERROR_COMMAND_SYNTAX_ERROR;
1365 }
1366 }
1367 }
1368
1369 duration_start_measure(&duration);
1370
1371 if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1372 {
1373 return ERROR_OK;
1374 }
1375
1376 buf_cnt = binary_size = fileio.size;
1377
1378 if (!(oob_format & NAND_OOB_ONLY))
1379 {
1380 page_size = p->page_size;
1381 page = malloc(p->page_size);
1382 }
1383
1384 if (oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC | NAND_OOB_SW_ECC_KW))
1385 {
1386 if (p->page_size == 512) {
1387 oob_size = 16;
1388 eccpos = nand_oob_16.eccpos;
1389 } else if (p->page_size == 2048) {
1390 oob_size = 64;
1391 eccpos = nand_oob_64.eccpos;
1392 }
1393 oob = malloc(oob_size);
1394 }
1395
1396 if (offset % p->page_size)
1397 {
1398 command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
1399 fileio_close(&fileio);
1400 free(oob);
1401 free(page);
1402 return ERROR_OK;
1403 }
1404
1405 while (buf_cnt > 0)
1406 {
1407 uint32_t size_read;
1408
1409 if (NULL != page)
1410 {
1411 fileio_read(&fileio, page_size, page, &size_read);
1412 buf_cnt -= size_read;
1413 if (size_read < page_size)
1414 {
1415 memset(page + size_read, 0xff, page_size - size_read);
1416 }
1417 }
1418
1419 if (oob_format & NAND_OOB_SW_ECC)
1420 {
1421 uint32_t i, j;
1422 uint8_t ecc[3];
1423 memset(oob, 0xff, oob_size);
1424 for (i = 0, j = 0; i < page_size; i += 256) {
1425 nand_calculate_ecc(p, page + i, ecc);
1426 oob[eccpos[j++]] = ecc[0];
1427 oob[eccpos[j++]] = ecc[1];
1428 oob[eccpos[j++]] = ecc[2];
1429 }
1430 } else if (oob_format & NAND_OOB_SW_ECC_KW)
1431 {
1432 /*
1433 * In this case eccpos is not used as
1434 * the ECC data is always stored contigously
1435 * at the end of the OOB area. It consists
1436 * of 10 bytes per 512-byte data block.
1437 */
1438 uint32_t i;
1439 uint8_t *ecc = oob + oob_size - page_size/512 * 10;
1440 memset(oob, 0xff, oob_size);
1441 for (i = 0; i < page_size; i += 512) {
1442 nand_calculate_ecc_kw(p, page + i, ecc);
1443 ecc += 10;
1444 }
1445 }
1446 else if (NULL != oob)
1447 {
1448 fileio_read(&fileio, oob_size, oob, &size_read);
1449 buf_cnt -= size_read;
1450 if (size_read < oob_size)
1451 {
1452 memset(oob + size_read, 0xff, oob_size - size_read);
1453 }
1454 }
1455
1456 if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
1457 {
1458 command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8" PRIx32 "",
1459 args[1], args[0], offset);
1460
1461 fileio_close(&fileio);
1462 free(oob);
1463 free(page);
1464
1465 return ERROR_OK;
1466 }
1467 offset += page_size;
1468 }
1469
1470 fileio_close(&fileio);
1471 free(oob);
1472 free(page);
1473 oob = NULL;
1474 page = NULL;
1475 duration_stop_measure(&duration, &duration_text);
1476 command_print(cmd_ctx, "wrote file %s to NAND flash %s up to offset 0x%8.8" PRIx32 " in %s",
1477 args[1], args[0], offset, duration_text);
1478 free(duration_text);
1479 duration_text = NULL;
1480 }
1481 else
1482 {
1483 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1484 }
1485
1486 return ERROR_OK;
1487 }
1488
1489 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1490 {
1491 nand_device_t *p;
1492
1493 if (argc < 4)
1494 {
1495 return ERROR_COMMAND_SYNTAX_ERROR;
1496 }
1497
1498 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1499 if (p)
1500 {
1501 if (p->device)
1502 {
1503 fileio_t fileio;
1504 duration_t duration;
1505 char *duration_text;
1506 int retval;
1507
1508 uint8_t *page = NULL;
1509 uint32_t page_size = 0;
1510 uint8_t *oob = NULL;
1511 uint32_t oob_size = 0;
1512 uint32_t address = strtoul(args[2], NULL, 0);
1513 uint32_t size = strtoul(args[3], NULL, 0);
1514 uint32_t bytes_done = 0;
1515 enum oob_formats oob_format = NAND_OOB_NONE;
1516
1517 if (argc > 4)
1518 {
1519 int i;
1520 for (i = 4; i < argc; i++)
1521 {
1522 if (!strcmp(args[i], "oob_raw"))
1523 oob_format |= NAND_OOB_RAW;
1524 else if (!strcmp(args[i], "oob_only"))
1525 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1526 else
1527 command_print(cmd_ctx, "unknown option: '%s'", args[i]);
1528 }
1529 }
1530
1531 if ((address % p->page_size) || (size % p->page_size))
1532 {
1533 command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
1534 return ERROR_OK;
1535 }
1536
1537 if (!(oob_format & NAND_OOB_ONLY))
1538 {
1539 page_size = p->page_size;
1540 page = malloc(p->page_size);
1541 }
1542
1543 if (oob_format & NAND_OOB_RAW)
1544 {
1545 if (p->page_size == 512)
1546 oob_size = 16;
1547 else if (p->page_size == 2048)
1548 oob_size = 64;
1549 oob = malloc(oob_size);
1550 }
1551
1552 if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1553 {
1554 return ERROR_OK;
1555 }
1556
1557 duration_start_measure(&duration);
1558
1559 while (size > 0)
1560 {
1561 uint32_t size_written;
1562 if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
1563 {
1564 command_print(cmd_ctx, "reading NAND flash page failed");
1565 free(page);
1566 free(oob);
1567 fileio_close(&fileio);
1568 return ERROR_OK;
1569 }
1570
1571 if (NULL != page)
1572 {
1573 fileio_write(&fileio, page_size, page, &size_written);
1574 bytes_done += page_size;
1575 }
1576
1577 if (NULL != oob)
1578 {
1579 fileio_write(&fileio, oob_size, oob, &size_written);
1580 bytes_done += oob_size;
1581 }
1582
1583 size -= p->page_size;
1584 address += p->page_size;
1585 }
1586
1587 free(page);
1588 page = NULL;
1589 free(oob);
1590 oob = NULL;
1591 fileio_close(&fileio);
1592
1593 duration_stop_measure(&duration, &duration_text);
1594 command_print(cmd_ctx, "dumped %lld byte in %s", fileio.size, duration_text);
1595 free(duration_text);
1596 duration_text = NULL;
1597 }
1598 else
1599 {
1600 command_print(cmd_ctx, "#%s: not probed", args[0]);
1601 }
1602 }
1603 else
1604 {
1605 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1606 }
1607
1608 return ERROR_OK;
1609 }
1610
1611 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1612 {
1613 nand_device_t *p;
1614
1615 if ((argc < 1) || (argc > 2))
1616 {
1617 return ERROR_COMMAND_SYNTAX_ERROR;
1618 }
1619
1620 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1621 if (p)
1622 {
1623 if (p->device)
1624 {
1625 if (argc == 2)
1626 {
1627 if (strcmp("enable", args[1]) == 0)
1628 {
1629 p->use_raw = 1;
1630 }
1631 else if (strcmp("disable", args[1]) == 0)
1632 {
1633 p->use_raw = 0;
1634 }
1635 else
1636 {
1637 return ERROR_COMMAND_SYNTAX_ERROR;
1638 }
1639 }
1640
1641 command_print(cmd_ctx, "raw access is %s", (p->use_raw) ? "enabled" : "disabled");
1642 }
1643 else
1644 {
1645 command_print(cmd_ctx, "#%s: not probed", args[0]);
1646 }
1647 }
1648 else
1649 {
1650 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1651 }
1652
1653 return ERROR_OK;
1654 }
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