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Zach Welch <zw@superlucidity.net> fix signed/unsigned comparisons
[openocd.git] / src / flash / nand.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "replacements.h"
28 #include "log.h"
29
30 #include <stdlib.h>
31 #include <string.h>
32 #include <inttypes.h>
33
34 #include <errno.h>
35
36 #include "nand.h"
37 #include "flash.h"
38 #include "time_support.h"
39 #include "fileio.h"
40 #include "image.h"
41
42 static int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44 static int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
45 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46 static int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
48 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
49 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50
51 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52
53 static int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
54 //static int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size);
55
56 static int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
57
58 /* NAND flash controller
59 */
60 extern nand_flash_controller_t lpc3180_nand_controller;
61 extern nand_flash_controller_t orion_nand_controller;
62 extern nand_flash_controller_t s3c2410_nand_controller;
63 extern nand_flash_controller_t s3c2412_nand_controller;
64 extern nand_flash_controller_t s3c2440_nand_controller;
65 extern nand_flash_controller_t s3c2443_nand_controller;
66
67 /* extern nand_flash_controller_t boundary_scan_nand_controller; */
68
69 static nand_flash_controller_t *nand_flash_controllers[] =
70 {
71 &lpc3180_nand_controller,
72 &orion_nand_controller,
73 &s3c2410_nand_controller,
74 &s3c2412_nand_controller,
75 &s3c2440_nand_controller,
76 &s3c2443_nand_controller,
77 /* &boundary_scan_nand_controller, */
78 NULL
79 };
80
81 /* configured NAND devices and NAND Flash command handler */
82 static nand_device_t *nand_devices = NULL;
83 static command_t *nand_cmd;
84
85 /* Chip ID list
86 *
87 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
88 * options
89 *
90 * Pagesize; 0, 256, 512
91 * 0 get this information from the extended chip ID
92 * 256 256 Byte page size
93 * 512 512 Byte page size
94 */
95 static nand_info_t nand_flash_ids[] =
96 {
97 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
98 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
99 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
100 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
101 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
102 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
103 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
104 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
105 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
106 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
107
108 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
109 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
110 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
111 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
112
113 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
114 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
115 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
116 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
117
118 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
119 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
120 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
121 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
122
123 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
124 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
125 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
126 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
127
128 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
129 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
130 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
131 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
132 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
133 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
134 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
135
136 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
137
138 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
139 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
140 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
141 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
142
143 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
144 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
145 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
146 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
147
148 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
149 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
150 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
151 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
152
153 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
154 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
155 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
156 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
157
158 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
159 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
160 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
161 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
162
163 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
164 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
165 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
166 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
167
168 {NULL, 0,}
169 };
170
171 /* Manufacturer ID list
172 */
173 static nand_manufacturer_t nand_manuf_ids[] =
174 {
175 {0x0, "unknown"},
176 {NAND_MFR_TOSHIBA, "Toshiba"},
177 {NAND_MFR_SAMSUNG, "Samsung"},
178 {NAND_MFR_FUJITSU, "Fujitsu"},
179 {NAND_MFR_NATIONAL, "National"},
180 {NAND_MFR_RENESAS, "Renesas"},
181 {NAND_MFR_STMICRO, "ST Micro"},
182 {NAND_MFR_HYNIX, "Hynix"},
183 {0x0, NULL},
184 };
185
186 /*
187 * Define default oob placement schemes for large and small page devices
188 */
189
190 #if 0
191 static nand_ecclayout_t nand_oob_8 = {
192 .eccbytes = 3,
193 .eccpos = {0, 1, 2},
194 .oobfree = {
195 {.offset = 3,
196 .length = 2},
197 {.offset = 6,
198 .length = 2}}
199 };
200 #endif
201
202 static nand_ecclayout_t nand_oob_16 = {
203 .eccbytes = 6,
204 .eccpos = {0, 1, 2, 3, 6, 7},
205 .oobfree = {
206 {.offset = 8,
207 . length = 8}}
208 };
209
210 static nand_ecclayout_t nand_oob_64 = {
211 .eccbytes = 24,
212 .eccpos = {
213 40, 41, 42, 43, 44, 45, 46, 47,
214 48, 49, 50, 51, 52, 53, 54, 55,
215 56, 57, 58, 59, 60, 61, 62, 63},
216 .oobfree = {
217 {.offset = 2,
218 .length = 38}}
219 };
220
221 /* nand device <nand_controller> [controller options]
222 */
223 static int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
224 {
225 int i;
226 int retval;
227
228 if (argc < 1)
229 {
230 LOG_WARNING("incomplete flash device nand configuration");
231 return ERROR_FLASH_BANK_INVALID;
232 }
233
234 for (i = 0; nand_flash_controllers[i]; i++)
235 {
236 nand_device_t *p, *c;
237
238 if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
239 {
240 /* register flash specific commands */
241 if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
242 {
243 LOG_ERROR("couldn't register '%s' commands", args[0]);
244 return retval;
245 }
246
247 c = malloc(sizeof(nand_device_t));
248
249 c->controller = nand_flash_controllers[i];
250 c->controller_priv = NULL;
251 c->manufacturer = NULL;
252 c->device = NULL;
253 c->bus_width = 0;
254 c->address_cycles = 0;
255 c->page_size = 0;
256 c->use_raw = 0;
257 c->next = NULL;
258
259 if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
260 {
261 LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
262 free(c);
263 return ERROR_OK;
264 }
265
266 /* put NAND device in linked list */
267 if (nand_devices)
268 {
269 /* find last flash device */
270 for (p = nand_devices; p && p->next; p = p->next);
271 if (p)
272 p->next = c;
273 }
274 else
275 {
276 nand_devices = c;
277 }
278
279 return ERROR_OK;
280 }
281 }
282
283 /* no valid NAND controller was found (i.e. the configuration option,
284 * didn't match one of the compiled-in controllers)
285 */
286 LOG_ERROR("No valid NAND flash controller found (%s)", args[0]);
287 LOG_ERROR("compiled-in NAND flash controllers:");
288 for (i = 0; nand_flash_controllers[i]; i++)
289 {
290 LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
291 }
292
293 return ERROR_OK;
294 }
295
296 int nand_register_commands(struct command_context_s *cmd_ctx)
297 {
298 nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
299
300 register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
301
302 return ERROR_OK;
303 }
304
305 int nand_init(struct command_context_s *cmd_ctx)
306 {
307 if (nand_devices)
308 {
309 register_command(cmd_ctx, nand_cmd, "list", handle_nand_list_command, COMMAND_EXEC,
310 "list configured NAND flash devices");
311 register_command(cmd_ctx, nand_cmd, "info", handle_nand_info_command, COMMAND_EXEC,
312 "print info about NAND flash device <num>");
313 register_command(cmd_ctx, nand_cmd, "probe", handle_nand_probe_command, COMMAND_EXEC,
314 "identify NAND flash device <num>");
315 register_command(cmd_ctx, nand_cmd, "check_bad_blocks", handle_nand_check_bad_blocks_command, COMMAND_EXEC,
316 "check NAND flash device <num> for bad blocks [<first> <last>]");
317 register_command(cmd_ctx, nand_cmd, "erase", handle_nand_erase_command, COMMAND_EXEC,
318 "erase blocks on NAND flash device <num> <first> <last>");
319 register_command(cmd_ctx, nand_cmd, "copy", handle_nand_copy_command, COMMAND_EXEC,
320 "copy from NAND flash device <num> <offset> <length> <ram-address>");
321 register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
322 "dump from NAND flash device <num> <filename> <offset> <size> [options]");
323 register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC,
324 "write to NAND flash device <num> <filename> <offset> [oob_raw|oob_only|oob_softecc]");
325 register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
326 "raw access to NAND flash device <num> ['enable'|'disable']");
327 }
328
329 return ERROR_OK;
330 }
331
332 nand_device_t *get_nand_device_by_num(int num)
333 {
334 nand_device_t *p;
335 int i = 0;
336
337 for (p = nand_devices; p; p = p->next)
338 {
339 if (i++ == num)
340 {
341 return p;
342 }
343 }
344
345 return NULL;
346 }
347
348 static int nand_build_bbt(struct nand_device_s *device, int first, int last)
349 {
350 u32 page = 0x0;
351 int i;
352 u8 oob[6];
353
354 if ((first < 0) || (first >= device->num_blocks))
355 first = 0;
356
357 if ((last >= device->num_blocks) || (last == -1))
358 last = device->num_blocks - 1;
359
360 for (i = first; i < last; i++)
361 {
362 nand_read_page(device, page, NULL, 0, oob, 6);
363
364 if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
365 || (((device->page_size == 512) && (oob[5] != 0xff)) ||
366 ((device->page_size == 2048) && (oob[0] != 0xff))))
367 {
368 LOG_WARNING("invalid block: %i", i);
369 device->blocks[i].is_bad = 1;
370 }
371 else
372 {
373 device->blocks[i].is_bad = 0;
374 }
375
376 page += (device->erase_size / device->page_size);
377 }
378
379 return ERROR_OK;
380 }
381
382 int nand_read_status(struct nand_device_s *device, u8 *status)
383 {
384 if (!device->device)
385 return ERROR_NAND_DEVICE_NOT_PROBED;
386
387 /* Send read status command */
388 device->controller->command(device, NAND_CMD_STATUS);
389
390 alive_sleep(1);
391
392 /* read status */
393 if (device->device->options & NAND_BUSWIDTH_16)
394 {
395 u16 data;
396 device->controller->read_data(device, &data);
397 *status = data & 0xff;
398 }
399 else
400 {
401 device->controller->read_data(device, status);
402 }
403
404 return ERROR_OK;
405 }
406
407 static int nand_poll_ready(struct nand_device_s *device, int timeout)
408 {
409 u8 status;
410
411 device->controller->command(device, NAND_CMD_STATUS);
412 do {
413 if (device->device->options & NAND_BUSWIDTH_16) {
414 u16 data;
415 device->controller->read_data(device, &data);
416 status = data & 0xff;
417 } else {
418 device->controller->read_data(device, &status);
419 }
420 if (status & NAND_STATUS_READY)
421 break;
422 alive_sleep(1);
423 } while (timeout--);
424
425 return (status & NAND_STATUS_READY) != 0;
426 }
427
428 int nand_probe(struct nand_device_s *device)
429 {
430 u8 manufacturer_id, device_id;
431 u8 id_buff[6];
432 int retval;
433 int i;
434
435 /* clear device data */
436 device->device = NULL;
437 device->manufacturer = NULL;
438
439 /* clear device parameters */
440 device->bus_width = 0;
441 device->address_cycles = 0;
442 device->page_size = 0;
443 device->erase_size = 0;
444
445 /* initialize controller (device parameters are zero, use controller default) */
446 if ((retval = device->controller->init(device) != ERROR_OK))
447 {
448 switch (retval)
449 {
450 case ERROR_NAND_OPERATION_FAILED:
451 LOG_DEBUG("controller initialization failed");
452 return ERROR_NAND_OPERATION_FAILED;
453 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
454 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
455 return ERROR_NAND_OPERATION_FAILED;
456 default:
457 LOG_ERROR("BUG: unknown controller initialization failure");
458 return ERROR_NAND_OPERATION_FAILED;
459 }
460 }
461
462 device->controller->command(device, NAND_CMD_RESET);
463 device->controller->reset(device);
464
465 device->controller->command(device, NAND_CMD_READID);
466 device->controller->address(device, 0x0);
467
468 if (device->bus_width == 8)
469 {
470 device->controller->read_data(device, &manufacturer_id);
471 device->controller->read_data(device, &device_id);
472 }
473 else
474 {
475 u16 data_buf;
476 device->controller->read_data(device, &data_buf);
477 manufacturer_id = data_buf & 0xff;
478 device->controller->read_data(device, &data_buf);
479 device_id = data_buf & 0xff;
480 }
481
482 for (i = 0; nand_flash_ids[i].name; i++)
483 {
484 if (nand_flash_ids[i].id == device_id)
485 {
486 device->device = &nand_flash_ids[i];
487 break;
488 }
489 }
490
491 for (i = 0; nand_manuf_ids[i].name; i++)
492 {
493 if (nand_manuf_ids[i].id == manufacturer_id)
494 {
495 device->manufacturer = &nand_manuf_ids[i];
496 break;
497 }
498 }
499
500 if (!device->manufacturer)
501 {
502 device->manufacturer = &nand_manuf_ids[0];
503 device->manufacturer->id = manufacturer_id;
504 }
505
506 if (!device->device)
507 {
508 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
509 manufacturer_id, device_id);
510 return ERROR_NAND_OPERATION_FAILED;
511 }
512
513 LOG_DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
514
515 /* initialize device parameters */
516
517 /* bus width */
518 if (device->device->options & NAND_BUSWIDTH_16)
519 device->bus_width = 16;
520 else
521 device->bus_width = 8;
522
523 /* Do we need extended device probe information? */
524 if (device->device->page_size == 0 ||
525 device->device->erase_size == 0)
526 {
527 if (device->bus_width == 8)
528 {
529 device->controller->read_data(device, id_buff+3);
530 device->controller->read_data(device, id_buff+4);
531 device->controller->read_data(device, id_buff+5);
532 }
533 else
534 {
535 u16 data_buf;
536
537 device->controller->read_data(device, &data_buf);
538 id_buff[3] = data_buf;
539
540 device->controller->read_data(device, &data_buf);
541 id_buff[4] = data_buf;
542
543 device->controller->read_data(device, &data_buf);
544 id_buff[5] = data_buf >> 8;
545 }
546 }
547
548 /* page size */
549 if (device->device->page_size == 0)
550 {
551 device->page_size = 1 << (10 + (id_buff[4] & 3));
552 }
553 else if (device->device->page_size == 256)
554 {
555 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
556 return ERROR_NAND_OPERATION_FAILED;
557 }
558 else
559 {
560 device->page_size = device->device->page_size;
561 }
562
563 /* number of address cycles */
564 if (device->page_size <= 512)
565 {
566 /* small page devices */
567 if (device->device->chip_size <= 32)
568 device->address_cycles = 3;
569 else if (device->device->chip_size <= 8*1024)
570 device->address_cycles = 4;
571 else
572 {
573 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
574 device->address_cycles = 5;
575 }
576 }
577 else
578 {
579 /* large page devices */
580 if (device->device->chip_size <= 128)
581 device->address_cycles = 4;
582 else if (device->device->chip_size <= 32*1024)
583 device->address_cycles = 5;
584 else
585 {
586 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
587 device->address_cycles = 6;
588 }
589 }
590
591 /* erase size */
592 if (device->device->erase_size == 0)
593 {
594 switch ((id_buff[4] >> 4) & 3) {
595 case 0:
596 device->erase_size = 64 << 10;
597 break;
598 case 1:
599 device->erase_size = 128 << 10;
600 break;
601 case 2:
602 device->erase_size = 256 << 10;
603 break;
604 case 3:
605 device->erase_size =512 << 10;
606 break;
607 }
608 }
609 else
610 {
611 device->erase_size = device->device->erase_size;
612 }
613
614 /* initialize controller, but leave parameters at the controllers default */
615 if ((retval = device->controller->init(device) != ERROR_OK))
616 {
617 switch (retval)
618 {
619 case ERROR_NAND_OPERATION_FAILED:
620 LOG_DEBUG("controller initialization failed");
621 return ERROR_NAND_OPERATION_FAILED;
622 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
623 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
624 device->bus_width, device->address_cycles, device->page_size);
625 return ERROR_NAND_OPERATION_FAILED;
626 default:
627 LOG_ERROR("BUG: unknown controller initialization failure");
628 return ERROR_NAND_OPERATION_FAILED;
629 }
630 }
631
632 device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
633 device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
634
635 for (i = 0; i < device->num_blocks; i++)
636 {
637 device->blocks[i].size = device->erase_size;
638 device->blocks[i].offset = i * device->erase_size;
639 device->blocks[i].is_erased = -1;
640 device->blocks[i].is_bad = -1;
641 }
642
643 return ERROR_OK;
644 }
645
646 int nand_erase(struct nand_device_s *device, int first_block, int last_block)
647 {
648 int i;
649 u32 page;
650 u8 status;
651 int retval;
652
653 if (!device->device)
654 return ERROR_NAND_DEVICE_NOT_PROBED;
655
656 if ((first_block < 0) || (last_block > device->num_blocks))
657 return ERROR_INVALID_ARGUMENTS;
658
659 /* make sure we know if a block is bad before erasing it */
660 for (i = first_block; i <= last_block; i++)
661 {
662 if (device->blocks[i].is_bad == -1)
663 {
664 nand_build_bbt(device, i, last_block);
665 break;
666 }
667 }
668
669 for (i = first_block; i <= last_block; i++)
670 {
671 /* Send erase setup command */
672 device->controller->command(device, NAND_CMD_ERASE1);
673
674 page = i * (device->erase_size / device->page_size);
675
676 /* Send page address */
677 if (device->page_size <= 512)
678 {
679 /* row */
680 device->controller->address(device, page & 0xff);
681 device->controller->address(device, (page >> 8) & 0xff);
682
683 /* 3rd cycle only on devices with more than 32 MiB */
684 if (device->address_cycles >= 4)
685 device->controller->address(device, (page >> 16) & 0xff);
686
687 /* 4th cycle only on devices with more than 8 GiB */
688 if (device->address_cycles >= 5)
689 device->controller->address(device, (page >> 24) & 0xff);
690 }
691 else
692 {
693 /* row */
694 device->controller->address(device, page & 0xff);
695 device->controller->address(device, (page >> 8) & 0xff);
696
697 /* 3rd cycle only on devices with more than 128 MiB */
698 if (device->address_cycles >= 5)
699 device->controller->address(device, (page >> 16) & 0xff);
700 }
701
702 /* Send erase confirm command */
703 device->controller->command(device, NAND_CMD_ERASE2);
704
705 retval = device->controller->nand_ready ?
706 device->controller->nand_ready(device, 1000) :
707 nand_poll_ready(device, 1000);
708 if (!retval) {
709 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
710 return ERROR_NAND_OPERATION_TIMEOUT;
711 }
712
713 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
714 {
715 LOG_ERROR("couldn't read status");
716 return ERROR_NAND_OPERATION_FAILED;
717 }
718
719 if (status & 0x1)
720 {
721 LOG_ERROR("erase operation didn't pass, status: 0x%2.2x", status);
722 return ERROR_NAND_OPERATION_FAILED;
723 }
724
725 device->blocks[i].is_erased = 1;
726 }
727
728 return ERROR_OK;
729 }
730
731 #if 0
732 static int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
733 {
734 u8 *page;
735
736 if (!device->device)
737 return ERROR_NAND_DEVICE_NOT_PROBED;
738
739 if (address % device->page_size)
740 {
741 LOG_ERROR("reads need to be page aligned");
742 return ERROR_NAND_OPERATION_FAILED;
743 }
744
745 page = malloc(device->page_size);
746
747 while (data_size > 0 )
748 {
749 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
750 u32 page_address;
751
752
753 page_address = address / device->page_size;
754
755 nand_read_page(device, page_address, page, device->page_size, NULL, 0);
756
757 memcpy(data, page, thisrun_size);
758
759 address += thisrun_size;
760 data += thisrun_size;
761 data_size -= thisrun_size;
762 }
763
764 free(page);
765
766 return ERROR_OK;
767 }
768
769 static int nand_write_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
770 {
771 u8 *page;
772
773 if (!device->device)
774 return ERROR_NAND_DEVICE_NOT_PROBED;
775
776 if (address % device->page_size)
777 {
778 LOG_ERROR("writes need to be page aligned");
779 return ERROR_NAND_OPERATION_FAILED;
780 }
781
782 page = malloc(device->page_size);
783
784 while (data_size > 0 )
785 {
786 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
787 u32 page_address;
788
789 memset(page, 0xff, device->page_size);
790 memcpy(page, data, thisrun_size);
791
792 page_address = address / device->page_size;
793
794 nand_write_page(device, page_address, page, device->page_size, NULL, 0);
795
796 address += thisrun_size;
797 data += thisrun_size;
798 data_size -= thisrun_size;
799 }
800
801 free(page);
802
803 return ERROR_OK;
804 }
805 #endif
806
807 int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
808 {
809 u32 block;
810
811 if (!device->device)
812 return ERROR_NAND_DEVICE_NOT_PROBED;
813
814 block = page / (device->erase_size / device->page_size);
815 if (device->blocks[block].is_erased == 1)
816 device->blocks[block].is_erased = 0;
817
818 if (device->use_raw || device->controller->write_page == NULL)
819 return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
820 else
821 return device->controller->write_page(device, page, data, data_size, oob, oob_size);
822 }
823
824 static int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
825 {
826 if (!device->device)
827 return ERROR_NAND_DEVICE_NOT_PROBED;
828
829 if (device->use_raw || device->controller->read_page == NULL)
830 return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
831 else
832 return device->controller->read_page(device, page, data, data_size, oob, oob_size);
833 }
834
835 int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
836 {
837 u32 i;
838
839 if (!device->device)
840 return ERROR_NAND_DEVICE_NOT_PROBED;
841
842 if (device->page_size <= 512)
843 {
844 /* small page device */
845 if (data)
846 device->controller->command(device, NAND_CMD_READ0);
847 else
848 device->controller->command(device, NAND_CMD_READOOB);
849
850 /* column (always 0, we start at the beginning of a page/OOB area) */
851 device->controller->address(device, 0x0);
852
853 /* row */
854 device->controller->address(device, page & 0xff);
855 device->controller->address(device, (page >> 8) & 0xff);
856
857 /* 4th cycle only on devices with more than 32 MiB */
858 if (device->address_cycles >= 4)
859 device->controller->address(device, (page >> 16) & 0xff);
860
861 /* 5th cycle only on devices with more than 8 GiB */
862 if (device->address_cycles >= 5)
863 device->controller->address(device, (page >> 24) & 0xff);
864 }
865 else
866 {
867 /* large page device */
868 device->controller->command(device, NAND_CMD_READ0);
869
870 /* column (0 when we start at the beginning of a page,
871 * or 2048 for the beginning of OOB area)
872 */
873 device->controller->address(device, 0x0);
874 if (data)
875 device->controller->address(device, 0x0);
876 else
877 device->controller->address(device, 0x8);
878
879 /* row */
880 device->controller->address(device, page & 0xff);
881 device->controller->address(device, (page >> 8) & 0xff);
882
883 /* 5th cycle only on devices with more than 128 MiB */
884 if (device->address_cycles >= 5)
885 device->controller->address(device, (page >> 16) & 0xff);
886
887 /* large page devices need a start command */
888 device->controller->command(device, NAND_CMD_READSTART);
889 }
890
891 if (device->controller->nand_ready) {
892 if (!device->controller->nand_ready(device, 100))
893 return ERROR_NAND_OPERATION_TIMEOUT;
894 } else {
895 alive_sleep(1);
896 }
897
898 if (data)
899 {
900 if (device->controller->read_block_data != NULL)
901 (device->controller->read_block_data)(device, data, data_size);
902 else
903 {
904 for (i = 0; i < data_size;)
905 {
906 if (device->device->options & NAND_BUSWIDTH_16)
907 {
908 device->controller->read_data(device, data);
909 data += 2;
910 i += 2;
911 }
912 else
913 {
914 device->controller->read_data(device, data);
915 data += 1;
916 i += 1;
917 }
918 }
919 }
920 }
921
922 if (oob)
923 {
924 if (device->controller->read_block_data != NULL)
925 (device->controller->read_block_data)(device, oob, oob_size);
926 else
927 {
928 for (i = 0; i < oob_size;)
929 {
930 if (device->device->options & NAND_BUSWIDTH_16)
931 {
932 device->controller->read_data(device, oob);
933 oob += 2;
934 i += 2;
935 }
936 else
937 {
938 device->controller->read_data(device, oob);
939 oob += 1;
940 i += 1;
941 }
942 }
943 }
944 }
945
946 return ERROR_OK;
947 }
948
949 int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
950 {
951 u32 i;
952 int retval;
953 u8 status;
954
955 if (!device->device)
956 return ERROR_NAND_DEVICE_NOT_PROBED;
957
958 device->controller->command(device, NAND_CMD_SEQIN);
959
960 if (device->page_size <= 512)
961 {
962 /* column (always 0, we start at the beginning of a page/OOB area) */
963 device->controller->address(device, 0x0);
964
965 /* row */
966 device->controller->address(device, page & 0xff);
967 device->controller->address(device, (page >> 8) & 0xff);
968
969 /* 4th cycle only on devices with more than 32 MiB */
970 if (device->address_cycles >= 4)
971 device->controller->address(device, (page >> 16) & 0xff);
972
973 /* 5th cycle only on devices with more than 8 GiB */
974 if (device->address_cycles >= 5)
975 device->controller->address(device, (page >> 24) & 0xff);
976 }
977 else
978 {
979 /* column (0 when we start at the beginning of a page,
980 * or 2048 for the beginning of OOB area)
981 */
982 device->controller->address(device, 0x0);
983 if (data)
984 device->controller->address(device, 0x0);
985 else
986 device->controller->address(device, 0x8);
987
988 /* row */
989 device->controller->address(device, page & 0xff);
990 device->controller->address(device, (page >> 8) & 0xff);
991
992 /* 5th cycle only on devices with more than 128 MiB */
993 if (device->address_cycles >= 5)
994 device->controller->address(device, (page >> 16) & 0xff);
995 }
996
997 if (data)
998 {
999 if (device->controller->write_block_data != NULL)
1000 (device->controller->write_block_data)(device, data, data_size);
1001 else
1002 {
1003 for (i = 0; i < data_size;)
1004 {
1005 if (device->device->options & NAND_BUSWIDTH_16)
1006 {
1007 u16 data_buf = le_to_h_u16(data);
1008 device->controller->write_data(device, data_buf);
1009 data += 2;
1010 i += 2;
1011 }
1012 else
1013 {
1014 device->controller->write_data(device, *data);
1015 data += 1;
1016 i += 1;
1017 }
1018 }
1019 }
1020 }
1021
1022 if (oob)
1023 {
1024 if (device->controller->write_block_data != NULL)
1025 (device->controller->write_block_data)(device, oob, oob_size);
1026 else
1027 {
1028 for (i = 0; i < oob_size;)
1029 {
1030 if (device->device->options & NAND_BUSWIDTH_16)
1031 {
1032 u16 oob_buf = le_to_h_u16(data);
1033 device->controller->write_data(device, oob_buf);
1034 oob += 2;
1035 i += 2;
1036 }
1037 else
1038 {
1039 device->controller->write_data(device, *oob);
1040 oob += 1;
1041 i += 1;
1042 }
1043 }
1044 }
1045 }
1046
1047 device->controller->command(device, NAND_CMD_PAGEPROG);
1048
1049 retval = device->controller->nand_ready ?
1050 device->controller->nand_ready(device, 100) :
1051 nand_poll_ready(device, 100);
1052 if (!retval)
1053 return ERROR_NAND_OPERATION_TIMEOUT;
1054
1055 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
1056 {
1057 LOG_ERROR("couldn't read status");
1058 return ERROR_NAND_OPERATION_FAILED;
1059 }
1060
1061 if (status & NAND_STATUS_FAIL)
1062 {
1063 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1064 return ERROR_NAND_OPERATION_FAILED;
1065 }
1066
1067 return ERROR_OK;
1068 }
1069
1070 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1071 {
1072 nand_device_t *p;
1073 int i = 0;
1074
1075 if (!nand_devices)
1076 {
1077 command_print(cmd_ctx, "no NAND flash devices configured");
1078 return ERROR_OK;
1079 }
1080
1081 for (p = nand_devices; p; p = p->next)
1082 {
1083 if (p->device)
1084 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1085 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1086 else
1087 command_print(cmd_ctx, "#%i: not probed");
1088 }
1089
1090 return ERROR_OK;
1091 }
1092
1093 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1094 {
1095 nand_device_t *p;
1096 int i = 0;
1097 int j = 0;
1098 int first = -1;
1099 int last = -1;
1100
1101 if ((argc < 1) || (argc > 3))
1102 {
1103 return ERROR_COMMAND_SYNTAX_ERROR;
1104
1105 }
1106
1107 if (argc == 2)
1108 {
1109 first = last = strtoul(args[1], NULL, 0);
1110 }
1111 else if (argc == 3)
1112 {
1113 first = strtoul(args[1], NULL, 0);
1114 last = strtoul(args[2], NULL, 0);
1115 }
1116
1117 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1118 if (p)
1119 {
1120 if (p->device)
1121 {
1122 if (first >= p->num_blocks)
1123 first = p->num_blocks - 1;
1124
1125 if (last >= p->num_blocks)
1126 last = p->num_blocks - 1;
1127
1128 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1129 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1130
1131 for (j = first; j <= last; j++)
1132 {
1133 char *erase_state, *bad_state;
1134
1135 if (p->blocks[j].is_erased == 0)
1136 erase_state = "not erased";
1137 else if (p->blocks[j].is_erased == 1)
1138 erase_state = "erased";
1139 else
1140 erase_state = "erase state unknown";
1141
1142 if (p->blocks[j].is_bad == 0)
1143 bad_state = "";
1144 else if (p->blocks[j].is_bad == 1)
1145 bad_state = " (marked bad)";
1146 else
1147 bad_state = " (block condition unknown)";
1148
1149 command_print(cmd_ctx, "\t#%i: 0x%8.8x (0x%xkB) %s%s",
1150 j, p->blocks[j].offset, p->blocks[j].size / 1024,
1151 erase_state, bad_state);
1152 }
1153 }
1154 else
1155 {
1156 command_print(cmd_ctx, "#%i: not probed");
1157 }
1158 }
1159
1160 return ERROR_OK;
1161 }
1162
1163 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1164 {
1165 nand_device_t *p;
1166 int retval;
1167
1168 if (argc != 1)
1169 {
1170 return ERROR_COMMAND_SYNTAX_ERROR;
1171 }
1172
1173 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1174 if (p)
1175 {
1176 if ((retval = nand_probe(p)) == ERROR_OK)
1177 {
1178 command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
1179 }
1180 else if (retval == ERROR_NAND_OPERATION_FAILED)
1181 {
1182 command_print(cmd_ctx, "probing failed for NAND flash device");
1183 }
1184 else
1185 {
1186 command_print(cmd_ctx, "unknown error when probing NAND flash device");
1187 }
1188 }
1189 else
1190 {
1191 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1192 }
1193
1194 return ERROR_OK;
1195 }
1196
1197 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1198 {
1199 nand_device_t *p;
1200 int retval;
1201
1202 if (argc != 3)
1203 {
1204 return ERROR_COMMAND_SYNTAX_ERROR;
1205
1206 }
1207
1208 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1209 if (p)
1210 {
1211 int first = strtoul(args[1], NULL, 0);
1212 int last = strtoul(args[2], NULL, 0);
1213
1214 if ((retval = nand_erase(p, first, last)) == ERROR_OK)
1215 {
1216 command_print(cmd_ctx, "successfully erased blocks %i to %i on NAND flash device '%s'", first, last, p->device->name);
1217 }
1218 else if (retval == ERROR_NAND_OPERATION_FAILED)
1219 {
1220 command_print(cmd_ctx, "erase failed");
1221 }
1222 else
1223 {
1224 command_print(cmd_ctx, "unknown error when erasing NAND flash device");
1225 }
1226 }
1227 else
1228 {
1229 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1230 }
1231
1232 return ERROR_OK;
1233 }
1234
1235 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1236 {
1237 nand_device_t *p;
1238 int retval;
1239 int first = -1;
1240 int last = -1;
1241
1242 if ((argc < 1) || (argc > 3) || (argc == 2))
1243 {
1244 return ERROR_COMMAND_SYNTAX_ERROR;
1245
1246 }
1247
1248 if (argc == 3)
1249 {
1250 first = strtoul(args[1], NULL, 0);
1251 last = strtoul(args[2], NULL, 0);
1252 }
1253
1254 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1255 if (p)
1256 {
1257 if ((retval = nand_build_bbt(p, first, last)) == ERROR_OK)
1258 {
1259 command_print(cmd_ctx, "checked NAND flash device for bad blocks, use \"nand info\" command to list blocks", p->device->name);
1260 }
1261 else if (retval == ERROR_NAND_OPERATION_FAILED)
1262 {
1263 command_print(cmd_ctx, "error when checking for bad blocks on NAND flash device");
1264 }
1265 else
1266 {
1267 command_print(cmd_ctx, "unknown error when checking for bad blocks on NAND flash device");
1268 }
1269 }
1270 else
1271 {
1272 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1273 }
1274
1275 return ERROR_OK;
1276 }
1277
1278 static int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1279 {
1280 nand_device_t *p;
1281
1282 if (argc != 4)
1283 {
1284 return ERROR_COMMAND_SYNTAX_ERROR;
1285
1286 }
1287
1288 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1289 if (p)
1290 {
1291
1292 }
1293 else
1294 {
1295 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1296 }
1297
1298 return ERROR_OK;
1299 }
1300
1301 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1302 {
1303 u32 offset;
1304 u32 binary_size;
1305 u32 buf_cnt;
1306 enum oob_formats oob_format = NAND_OOB_NONE;
1307
1308 fileio_t fileio;
1309
1310 duration_t duration;
1311 char *duration_text;
1312
1313 nand_device_t *p;
1314
1315 if (argc < 3)
1316 {
1317 return ERROR_COMMAND_SYNTAX_ERROR;
1318
1319 }
1320
1321 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1322 if (p)
1323 {
1324 u8 *page = NULL;
1325 u32 page_size = 0;
1326 u8 *oob = NULL;
1327 u32 oob_size = 0;
1328 const int *eccpos = NULL;
1329
1330 offset = strtoul(args[2], NULL, 0);
1331
1332 if (argc > 3)
1333 {
1334 int i;
1335 for (i = 3; i < argc; i++)
1336 {
1337 if (!strcmp(args[i], "oob_raw"))
1338 oob_format |= NAND_OOB_RAW;
1339 else if (!strcmp(args[i], "oob_only"))
1340 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1341 else if (!strcmp(args[i], "oob_softecc"))
1342 oob_format |= NAND_OOB_SW_ECC;
1343 else
1344 {
1345 command_print(cmd_ctx, "unknown option: %s", args[i]);
1346 return ERROR_COMMAND_SYNTAX_ERROR;
1347 }
1348 }
1349 }
1350
1351 duration_start_measure(&duration);
1352
1353 if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1354 {
1355 return ERROR_OK;
1356 }
1357
1358 buf_cnt = binary_size = fileio.size;
1359
1360 if (!(oob_format & NAND_OOB_ONLY))
1361 {
1362 page_size = p->page_size;
1363 page = malloc(p->page_size);
1364 }
1365
1366 if (oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC))
1367 {
1368 if (p->page_size == 512) {
1369 oob_size = 16;
1370 eccpos = nand_oob_16.eccpos;
1371 } else if (p->page_size == 2048) {
1372 oob_size = 64;
1373 eccpos = nand_oob_64.eccpos;
1374 }
1375 oob = malloc(oob_size);
1376 }
1377
1378 if (offset % p->page_size)
1379 {
1380 command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
1381 fileio_close(&fileio);
1382 free(oob);
1383 free(page);
1384 return ERROR_OK;
1385 }
1386
1387 while (buf_cnt > 0)
1388 {
1389 u32 size_read;
1390
1391 if (NULL != page)
1392 {
1393 fileio_read(&fileio, page_size, page, &size_read);
1394 buf_cnt -= size_read;
1395 if (size_read < page_size)
1396 {
1397 memset(page + size_read, 0xff, page_size - size_read);
1398 }
1399 }
1400
1401 if (oob_format & NAND_OOB_SW_ECC)
1402 {
1403 u32 i, j;
1404 u8 ecc[3];
1405 memset(oob, 0xff, oob_size);
1406 for (i = 0, j = 0; i < page_size; i += 256) {
1407 nand_calculate_ecc(p, page+i, ecc);
1408 oob[eccpos[j++]] = ecc[0];
1409 oob[eccpos[j++]] = ecc[1];
1410 oob[eccpos[j++]] = ecc[2];
1411 }
1412 }
1413 else if (NULL != oob)
1414 {
1415 fileio_read(&fileio, oob_size, oob, &size_read);
1416 buf_cnt -= size_read;
1417 if (size_read < oob_size)
1418 {
1419 memset(oob + size_read, 0xff, oob_size - size_read);
1420 }
1421 }
1422
1423 if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
1424 {
1425 command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8x",
1426 args[1], args[0], offset);
1427
1428 fileio_close(&fileio);
1429 free(oob);
1430 free(page);
1431
1432 return ERROR_OK;
1433 }
1434 offset += page_size;
1435 }
1436
1437 fileio_close(&fileio);
1438 free(oob);
1439 free(page);
1440 oob = NULL;
1441 page = NULL;
1442 duration_stop_measure(&duration, &duration_text);
1443 command_print(cmd_ctx, "wrote file %s to NAND flash %s up to offset 0x%8.8x in %s",
1444 args[1], args[0], offset, duration_text);
1445 free(duration_text);
1446 duration_text = NULL;
1447 }
1448 else
1449 {
1450 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1451 }
1452
1453 return ERROR_OK;
1454 }
1455
1456 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1457 {
1458 nand_device_t *p;
1459
1460 if (argc < 4)
1461 {
1462 return ERROR_COMMAND_SYNTAX_ERROR;
1463 }
1464
1465 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1466 if (p)
1467 {
1468 if (p->device)
1469 {
1470 fileio_t fileio;
1471 duration_t duration;
1472 char *duration_text;
1473 int retval;
1474
1475 u8 *page = NULL;
1476 u32 page_size = 0;
1477 u8 *oob = NULL;
1478 u32 oob_size = 0;
1479 u32 address = strtoul(args[2], NULL, 0);
1480 u32 size = strtoul(args[3], NULL, 0);
1481 u32 bytes_done = 0;
1482 enum oob_formats oob_format = NAND_OOB_NONE;
1483
1484 if (argc > 4)
1485 {
1486 int i;
1487 for (i = 4; i < argc; i++)
1488 {
1489 if (!strcmp(args[i], "oob_raw"))
1490 oob_format |= NAND_OOB_RAW;
1491 else if (!strcmp(args[i], "oob_only"))
1492 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1493 else
1494 command_print(cmd_ctx, "unknown option: '%s'", args[i]);
1495 }
1496 }
1497
1498 if ((address % p->page_size) || (size % p->page_size))
1499 {
1500 command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
1501 return ERROR_OK;
1502 }
1503
1504 if (!(oob_format & NAND_OOB_ONLY))
1505 {
1506 page_size = p->page_size;
1507 page = malloc(p->page_size);
1508 }
1509
1510 if (oob_format & NAND_OOB_RAW)
1511 {
1512 if (p->page_size == 512)
1513 oob_size = 16;
1514 else if (p->page_size == 2048)
1515 oob_size = 64;
1516 oob = malloc(oob_size);
1517 }
1518
1519 if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1520 {
1521 return ERROR_OK;
1522 }
1523
1524 duration_start_measure(&duration);
1525
1526 while (size > 0)
1527 {
1528 u32 size_written;
1529 if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
1530 {
1531 command_print(cmd_ctx, "reading NAND flash page failed");
1532 free(page);
1533 free(oob);
1534 fileio_close(&fileio);
1535 return ERROR_OK;
1536 }
1537
1538 if (NULL != page)
1539 {
1540 fileio_write(&fileio, page_size, page, &size_written);
1541 bytes_done += page_size;
1542 }
1543
1544 if (NULL != oob)
1545 {
1546 fileio_write(&fileio, oob_size, oob, &size_written);
1547 bytes_done += oob_size;
1548 }
1549
1550 size -= p->page_size;
1551 address += p->page_size;
1552 }
1553
1554 free(page);
1555 page = NULL;
1556 free(oob);
1557 oob = NULL;
1558 fileio_close(&fileio);
1559
1560 duration_stop_measure(&duration, &duration_text);
1561 command_print(cmd_ctx, "dumped %"PRIi64" byte in %s", fileio.size, duration_text);
1562 free(duration_text);
1563 duration_text = NULL;
1564 }
1565 else
1566 {
1567 command_print(cmd_ctx, "#%i: not probed");
1568 }
1569 }
1570 else
1571 {
1572 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1573 }
1574
1575 return ERROR_OK;
1576 }
1577
1578 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1579 {
1580 nand_device_t *p;
1581
1582 if ((argc < 1) || (argc > 2))
1583 {
1584 return ERROR_COMMAND_SYNTAX_ERROR;
1585 }
1586
1587 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1588 if (p)
1589 {
1590 if (p->device)
1591 {
1592 if (argc == 2)
1593 {
1594 if (strcmp("enable", args[1]) == 0)
1595 {
1596 p->use_raw = 1;
1597 }
1598 else if (strcmp("disable", args[1]) == 0)
1599 {
1600 p->use_raw = 0;
1601 }
1602 else
1603 {
1604 return ERROR_COMMAND_SYNTAX_ERROR;
1605 }
1606 }
1607
1608 command_print(cmd_ctx, "raw access is %s", (p->use_raw) ? "enabled" : "disabled");
1609 }
1610 else
1611 {
1612 command_print(cmd_ctx, "#%i: not probed");
1613 }
1614 }
1615 else
1616 {
1617 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1618 }
1619
1620 return ERROR_OK;
1621 }
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