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David Brownell <david-b@pacbell.net>:
[openocd.git] / src / flash / nand.c
1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
23 #ifdef HAVE_CONFIG_H
24 #include "config.h"
25 #endif
26
27 #include "nand.h"
28 #include "time_support.h"
29 #include "fileio.h"
30
31 #include <inttypes.h>
32
33
34 static int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
35 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
36 static int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
37 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
38 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
40 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41
42 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
43
44 static int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
45 //static int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size);
46
47 static int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
48
49 /* NAND flash controller
50 */
51 extern nand_flash_controller_t davinci_nand_controller;
52 extern nand_flash_controller_t lpc3180_nand_controller;
53 extern nand_flash_controller_t orion_nand_controller;
54 extern nand_flash_controller_t s3c2410_nand_controller;
55 extern nand_flash_controller_t s3c2412_nand_controller;
56 extern nand_flash_controller_t s3c2440_nand_controller;
57 extern nand_flash_controller_t s3c2443_nand_controller;
58
59 /* extern nand_flash_controller_t boundary_scan_nand_controller; */
60
61 static nand_flash_controller_t *nand_flash_controllers[] =
62 {
63 &davinci_nand_controller,
64 &lpc3180_nand_controller,
65 &orion_nand_controller,
66 &s3c2410_nand_controller,
67 &s3c2412_nand_controller,
68 &s3c2440_nand_controller,
69 &s3c2443_nand_controller,
70 /* &boundary_scan_nand_controller, */
71 NULL
72 };
73
74 /* configured NAND devices and NAND Flash command handler */
75 static nand_device_t *nand_devices = NULL;
76 static command_t *nand_cmd;
77
78 /* Chip ID list
79 *
80 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
81 * options
82 *
83 * Pagesize; 0, 256, 512
84 * 0 get this information from the extended chip ID
85 * 256 256 Byte page size
86 * 512 512 Byte page size
87 */
88 static nand_info_t nand_flash_ids[] =
89 {
90 /* start "museum" IDs */
91 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
92 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
93 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
94 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
95 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
96 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
97 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
98 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
99 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
100 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
101
102 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
103 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
104 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
105 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
106 /* end "museum" IDs */
107
108 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
109 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
110 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
111 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
112
113 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
114 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
115 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
116 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
117
118 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
119 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
120 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
121 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
122
123 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
124 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
125 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
126 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
127 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
128 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
129 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
130
131 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
132
133 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
134 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
135 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
136 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
137
138 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
139 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
140 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
141 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
142
143 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
144 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
145 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
146 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
147
148 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
149 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
150 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
151 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
152
153 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
154 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
155 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
156 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
157
158 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
159 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
160 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
161 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
162
163 {NULL, 0, 0, 0, 0, 0 }
164 };
165
166 /* Manufacturer ID list
167 */
168 static nand_manufacturer_t nand_manuf_ids[] =
169 {
170 {0x0, "unknown"},
171 {NAND_MFR_TOSHIBA, "Toshiba"},
172 {NAND_MFR_SAMSUNG, "Samsung"},
173 {NAND_MFR_FUJITSU, "Fujitsu"},
174 {NAND_MFR_NATIONAL, "National"},
175 {NAND_MFR_RENESAS, "Renesas"},
176 {NAND_MFR_STMICRO, "ST Micro"},
177 {NAND_MFR_HYNIX, "Hynix"},
178 {NAND_MFR_MICRON, "Micron"},
179 {0x0, NULL},
180 };
181
182 /*
183 * Define default oob placement schemes for large and small page devices
184 */
185
186 #if 0
187 static nand_ecclayout_t nand_oob_8 = {
188 .eccbytes = 3,
189 .eccpos = {0, 1, 2},
190 .oobfree = {
191 {.offset = 3,
192 .length = 2},
193 {.offset = 6,
194 .length = 2}}
195 };
196 #endif
197
198 static nand_ecclayout_t nand_oob_16 = {
199 .eccbytes = 6,
200 .eccpos = {0, 1, 2, 3, 6, 7},
201 .oobfree = {
202 {.offset = 8,
203 . length = 8}}
204 };
205
206 static nand_ecclayout_t nand_oob_64 = {
207 .eccbytes = 24,
208 .eccpos = {
209 40, 41, 42, 43, 44, 45, 46, 47,
210 48, 49, 50, 51, 52, 53, 54, 55,
211 56, 57, 58, 59, 60, 61, 62, 63},
212 .oobfree = {
213 {.offset = 2,
214 .length = 38}}
215 };
216
217 /* nand device <nand_controller> [controller options]
218 */
219 static int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
220 {
221 int i;
222 int retval;
223
224 if (argc < 1)
225 {
226 LOG_WARNING("incomplete flash device nand configuration");
227 return ERROR_FLASH_BANK_INVALID;
228 }
229
230 for (i = 0; nand_flash_controllers[i]; i++)
231 {
232 nand_device_t *p, *c;
233
234 if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
235 {
236 /* register flash specific commands */
237 if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
238 {
239 LOG_ERROR("couldn't register '%s' commands", args[0]);
240 return retval;
241 }
242
243 c = malloc(sizeof(nand_device_t));
244
245 c->controller = nand_flash_controllers[i];
246 c->controller_priv = NULL;
247 c->manufacturer = NULL;
248 c->device = NULL;
249 c->bus_width = 0;
250 c->address_cycles = 0;
251 c->page_size = 0;
252 c->use_raw = 0;
253 c->next = NULL;
254
255 if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
256 {
257 LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
258 free(c);
259 return ERROR_OK;
260 }
261
262 /* put NAND device in linked list */
263 if (nand_devices)
264 {
265 /* find last flash device */
266 for (p = nand_devices; p && p->next; p = p->next);
267 if (p)
268 p->next = c;
269 }
270 else
271 {
272 nand_devices = c;
273 }
274
275 return ERROR_OK;
276 }
277 }
278
279 /* no valid NAND controller was found (i.e. the configuration option,
280 * didn't match one of the compiled-in controllers)
281 */
282 LOG_ERROR("No valid NAND flash controller found (%s)", args[0]);
283 LOG_ERROR("compiled-in NAND flash controllers:");
284 for (i = 0; nand_flash_controllers[i]; i++)
285 {
286 LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
287 }
288
289 return ERROR_OK;
290 }
291
292 int nand_register_commands(struct command_context_s *cmd_ctx)
293 {
294 nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
295
296 register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
297
298 return ERROR_OK;
299 }
300
301 int nand_init(struct command_context_s *cmd_ctx)
302 {
303 if (nand_devices)
304 {
305 register_command(cmd_ctx, nand_cmd, "list", handle_nand_list_command, COMMAND_EXEC,
306 "list configured NAND flash devices");
307 register_command(cmd_ctx, nand_cmd, "info", handle_nand_info_command, COMMAND_EXEC,
308 "print info about NAND flash device <num>");
309 register_command(cmd_ctx, nand_cmd, "probe", handle_nand_probe_command, COMMAND_EXEC,
310 "identify NAND flash device <num>");
311 register_command(cmd_ctx, nand_cmd, "check_bad_blocks", handle_nand_check_bad_blocks_command, COMMAND_EXEC,
312 "check NAND flash device <num> for bad blocks [<offset> <length>]");
313 register_command(cmd_ctx, nand_cmd, "erase", handle_nand_erase_command, COMMAND_EXEC,
314 "erase blocks on NAND flash device <num> <offset> <length>");
315 register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
316 "dump from NAND flash device <num> <filename> "
317 "<offset> <length> [oob_raw|oob_only]");
318 register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC,
319 "write to NAND flash device <num> <filename> <offset> [oob_raw|oob_only|oob_softecc|oob_softecc_kw]");
320 register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
321 "raw access to NAND flash device <num> ['enable'|'disable']");
322 }
323
324 return ERROR_OK;
325 }
326
327 nand_device_t *get_nand_device_by_num(int num)
328 {
329 nand_device_t *p;
330 int i = 0;
331
332 for (p = nand_devices; p; p = p->next)
333 {
334 if (i++ == num)
335 {
336 return p;
337 }
338 }
339
340 return NULL;
341 }
342
343 static int nand_build_bbt(struct nand_device_s *device, int first, int last)
344 {
345 u32 page = 0x0;
346 int i;
347 u8 oob[6];
348
349 if ((first < 0) || (first >= device->num_blocks))
350 first = 0;
351
352 if ((last >= device->num_blocks) || (last == -1))
353 last = device->num_blocks - 1;
354
355 for (i = first; i < last; i++)
356 {
357 nand_read_page(device, page, NULL, 0, oob, 6);
358
359 if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
360 || (((device->page_size == 512) && (oob[5] != 0xff)) ||
361 ((device->page_size == 2048) && (oob[0] != 0xff))))
362 {
363 LOG_WARNING("bad block: %i", i);
364 device->blocks[i].is_bad = 1;
365 }
366 else
367 {
368 device->blocks[i].is_bad = 0;
369 }
370
371 page += (device->erase_size / device->page_size);
372 }
373
374 return ERROR_OK;
375 }
376
377 int nand_read_status(struct nand_device_s *device, u8 *status)
378 {
379 if (!device->device)
380 return ERROR_NAND_DEVICE_NOT_PROBED;
381
382 /* Send read status command */
383 device->controller->command(device, NAND_CMD_STATUS);
384
385 alive_sleep(1);
386
387 /* read status */
388 if (device->device->options & NAND_BUSWIDTH_16)
389 {
390 u16 data;
391 device->controller->read_data(device, &data);
392 *status = data & 0xff;
393 }
394 else
395 {
396 device->controller->read_data(device, status);
397 }
398
399 return ERROR_OK;
400 }
401
402 static int nand_poll_ready(struct nand_device_s *device, int timeout)
403 {
404 u8 status;
405
406 device->controller->command(device, NAND_CMD_STATUS);
407 do {
408 if (device->device->options & NAND_BUSWIDTH_16) {
409 u16 data;
410 device->controller->read_data(device, &data);
411 status = data & 0xff;
412 } else {
413 device->controller->read_data(device, &status);
414 }
415 if (status & NAND_STATUS_READY)
416 break;
417 alive_sleep(1);
418 } while (timeout--);
419
420 return (status & NAND_STATUS_READY) != 0;
421 }
422
423 int nand_probe(struct nand_device_s *device)
424 {
425 u8 manufacturer_id, device_id;
426 u8 id_buff[6];
427 int retval;
428 int i;
429
430 /* clear device data */
431 device->device = NULL;
432 device->manufacturer = NULL;
433
434 /* clear device parameters */
435 device->bus_width = 0;
436 device->address_cycles = 0;
437 device->page_size = 0;
438 device->erase_size = 0;
439
440 /* initialize controller (device parameters are zero, use controller default) */
441 if ((retval = device->controller->init(device) != ERROR_OK))
442 {
443 switch (retval)
444 {
445 case ERROR_NAND_OPERATION_FAILED:
446 LOG_DEBUG("controller initialization failed");
447 return ERROR_NAND_OPERATION_FAILED;
448 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
449 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
450 return ERROR_NAND_OPERATION_FAILED;
451 default:
452 LOG_ERROR("BUG: unknown controller initialization failure");
453 return ERROR_NAND_OPERATION_FAILED;
454 }
455 }
456
457 device->controller->command(device, NAND_CMD_RESET);
458 device->controller->reset(device);
459
460 device->controller->command(device, NAND_CMD_READID);
461 device->controller->address(device, 0x0);
462
463 if (device->bus_width == 8)
464 {
465 device->controller->read_data(device, &manufacturer_id);
466 device->controller->read_data(device, &device_id);
467 }
468 else
469 {
470 u16 data_buf;
471 device->controller->read_data(device, &data_buf);
472 manufacturer_id = data_buf & 0xff;
473 device->controller->read_data(device, &data_buf);
474 device_id = data_buf & 0xff;
475 }
476
477 for (i = 0; nand_flash_ids[i].name; i++)
478 {
479 if (nand_flash_ids[i].id == device_id)
480 {
481 device->device = &nand_flash_ids[i];
482 break;
483 }
484 }
485
486 for (i = 0; nand_manuf_ids[i].name; i++)
487 {
488 if (nand_manuf_ids[i].id == manufacturer_id)
489 {
490 device->manufacturer = &nand_manuf_ids[i];
491 break;
492 }
493 }
494
495 if (!device->manufacturer)
496 {
497 device->manufacturer = &nand_manuf_ids[0];
498 device->manufacturer->id = manufacturer_id;
499 }
500
501 if (!device->device)
502 {
503 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
504 manufacturer_id, device_id);
505 return ERROR_NAND_OPERATION_FAILED;
506 }
507
508 LOG_DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
509
510 /* initialize device parameters */
511
512 /* bus width */
513 if (device->device->options & NAND_BUSWIDTH_16)
514 device->bus_width = 16;
515 else
516 device->bus_width = 8;
517
518 /* Do we need extended device probe information? */
519 if (device->device->page_size == 0 ||
520 device->device->erase_size == 0)
521 {
522 if (device->bus_width == 8)
523 {
524 device->controller->read_data(device, id_buff+3);
525 device->controller->read_data(device, id_buff+4);
526 device->controller->read_data(device, id_buff+5);
527 }
528 else
529 {
530 u16 data_buf;
531
532 device->controller->read_data(device, &data_buf);
533 id_buff[3] = data_buf;
534
535 device->controller->read_data(device, &data_buf);
536 id_buff[4] = data_buf;
537
538 device->controller->read_data(device, &data_buf);
539 id_buff[5] = data_buf >> 8;
540 }
541 }
542
543 /* page size */
544 if (device->device->page_size == 0)
545 {
546 device->page_size = 1 << (10 + (id_buff[4] & 3));
547 }
548 else if (device->device->page_size == 256)
549 {
550 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
551 return ERROR_NAND_OPERATION_FAILED;
552 }
553 else
554 {
555 device->page_size = device->device->page_size;
556 }
557
558 /* number of address cycles */
559 if (device->page_size <= 512)
560 {
561 /* small page devices */
562 if (device->device->chip_size <= 32)
563 device->address_cycles = 3;
564 else if (device->device->chip_size <= 8*1024)
565 device->address_cycles = 4;
566 else
567 {
568 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
569 device->address_cycles = 5;
570 }
571 }
572 else
573 {
574 /* large page devices */
575 if (device->device->chip_size <= 128)
576 device->address_cycles = 4;
577 else if (device->device->chip_size <= 32*1024)
578 device->address_cycles = 5;
579 else
580 {
581 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
582 device->address_cycles = 6;
583 }
584 }
585
586 /* erase size */
587 if (device->device->erase_size == 0)
588 {
589 switch ((id_buff[4] >> 4) & 3) {
590 case 0:
591 device->erase_size = 64 << 10;
592 break;
593 case 1:
594 device->erase_size = 128 << 10;
595 break;
596 case 2:
597 device->erase_size = 256 << 10;
598 break;
599 case 3:
600 device->erase_size =512 << 10;
601 break;
602 }
603 }
604 else
605 {
606 device->erase_size = device->device->erase_size;
607 }
608
609 /* initialize controller, but leave parameters at the controllers default */
610 if ((retval = device->controller->init(device) != ERROR_OK))
611 {
612 switch (retval)
613 {
614 case ERROR_NAND_OPERATION_FAILED:
615 LOG_DEBUG("controller initialization failed");
616 return ERROR_NAND_OPERATION_FAILED;
617 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
618 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
619 device->bus_width, device->address_cycles, device->page_size);
620 return ERROR_NAND_OPERATION_FAILED;
621 default:
622 LOG_ERROR("BUG: unknown controller initialization failure");
623 return ERROR_NAND_OPERATION_FAILED;
624 }
625 }
626
627 device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
628 device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
629
630 for (i = 0; i < device->num_blocks; i++)
631 {
632 device->blocks[i].size = device->erase_size;
633 device->blocks[i].offset = i * device->erase_size;
634 device->blocks[i].is_erased = -1;
635 device->blocks[i].is_bad = -1;
636 }
637
638 return ERROR_OK;
639 }
640
641 int nand_erase(struct nand_device_s *device, int first_block, int last_block)
642 {
643 int i;
644 u32 page;
645 u8 status;
646 int retval;
647
648 if (!device->device)
649 return ERROR_NAND_DEVICE_NOT_PROBED;
650
651 if ((first_block < 0) || (last_block > device->num_blocks))
652 return ERROR_INVALID_ARGUMENTS;
653
654 /* make sure we know if a block is bad before erasing it */
655 for (i = first_block; i <= last_block; i++)
656 {
657 if (device->blocks[i].is_bad == -1)
658 {
659 nand_build_bbt(device, i, last_block);
660 break;
661 }
662 }
663
664 for (i = first_block; i <= last_block; i++)
665 {
666 /* Send erase setup command */
667 device->controller->command(device, NAND_CMD_ERASE1);
668
669 page = i * (device->erase_size / device->page_size);
670
671 /* Send page address */
672 if (device->page_size <= 512)
673 {
674 /* row */
675 device->controller->address(device, page & 0xff);
676 device->controller->address(device, (page >> 8) & 0xff);
677
678 /* 3rd cycle only on devices with more than 32 MiB */
679 if (device->address_cycles >= 4)
680 device->controller->address(device, (page >> 16) & 0xff);
681
682 /* 4th cycle only on devices with more than 8 GiB */
683 if (device->address_cycles >= 5)
684 device->controller->address(device, (page >> 24) & 0xff);
685 }
686 else
687 {
688 /* row */
689 device->controller->address(device, page & 0xff);
690 device->controller->address(device, (page >> 8) & 0xff);
691
692 /* 3rd cycle only on devices with more than 128 MiB */
693 if (device->address_cycles >= 5)
694 device->controller->address(device, (page >> 16) & 0xff);
695 }
696
697 /* Send erase confirm command */
698 device->controller->command(device, NAND_CMD_ERASE2);
699
700 retval = device->controller->nand_ready ?
701 device->controller->nand_ready(device, 1000) :
702 nand_poll_ready(device, 1000);
703 if (!retval) {
704 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
705 return ERROR_NAND_OPERATION_TIMEOUT;
706 }
707
708 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
709 {
710 LOG_ERROR("couldn't read status");
711 return ERROR_NAND_OPERATION_FAILED;
712 }
713
714 if (status & 0x1)
715 {
716 LOG_ERROR("erase operation didn't pass, status: 0x%2.2x", status);
717 return ERROR_NAND_OPERATION_FAILED;
718 }
719
720 device->blocks[i].is_erased = 1;
721 }
722
723 return ERROR_OK;
724 }
725
726 #if 0
727 static int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
728 {
729 u8 *page;
730
731 if (!device->device)
732 return ERROR_NAND_DEVICE_NOT_PROBED;
733
734 if (address % device->page_size)
735 {
736 LOG_ERROR("reads need to be page aligned");
737 return ERROR_NAND_OPERATION_FAILED;
738 }
739
740 page = malloc(device->page_size);
741
742 while (data_size > 0 )
743 {
744 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
745 u32 page_address;
746
747
748 page_address = address / device->page_size;
749
750 nand_read_page(device, page_address, page, device->page_size, NULL, 0);
751
752 memcpy(data, page, thisrun_size);
753
754 address += thisrun_size;
755 data += thisrun_size;
756 data_size -= thisrun_size;
757 }
758
759 free(page);
760
761 return ERROR_OK;
762 }
763
764 static int nand_write_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
765 {
766 u8 *page;
767
768 if (!device->device)
769 return ERROR_NAND_DEVICE_NOT_PROBED;
770
771 if (address % device->page_size)
772 {
773 LOG_ERROR("writes need to be page aligned");
774 return ERROR_NAND_OPERATION_FAILED;
775 }
776
777 page = malloc(device->page_size);
778
779 while (data_size > 0 )
780 {
781 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
782 u32 page_address;
783
784 memset(page, 0xff, device->page_size);
785 memcpy(page, data, thisrun_size);
786
787 page_address = address / device->page_size;
788
789 nand_write_page(device, page_address, page, device->page_size, NULL, 0);
790
791 address += thisrun_size;
792 data += thisrun_size;
793 data_size -= thisrun_size;
794 }
795
796 free(page);
797
798 return ERROR_OK;
799 }
800 #endif
801
802 int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
803 {
804 u32 block;
805
806 if (!device->device)
807 return ERROR_NAND_DEVICE_NOT_PROBED;
808
809 block = page / (device->erase_size / device->page_size);
810 if (device->blocks[block].is_erased == 1)
811 device->blocks[block].is_erased = 0;
812
813 if (device->use_raw || device->controller->write_page == NULL)
814 return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
815 else
816 return device->controller->write_page(device, page, data, data_size, oob, oob_size);
817 }
818
819 static int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
820 {
821 if (!device->device)
822 return ERROR_NAND_DEVICE_NOT_PROBED;
823
824 if (device->use_raw || device->controller->read_page == NULL)
825 return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
826 else
827 return device->controller->read_page(device, page, data, data_size, oob, oob_size);
828 }
829
830 int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
831 {
832 u32 i;
833
834 if (!device->device)
835 return ERROR_NAND_DEVICE_NOT_PROBED;
836
837 if (device->page_size <= 512)
838 {
839 /* small page device */
840 if (data)
841 device->controller->command(device, NAND_CMD_READ0);
842 else
843 device->controller->command(device, NAND_CMD_READOOB);
844
845 /* column (always 0, we start at the beginning of a page/OOB area) */
846 device->controller->address(device, 0x0);
847
848 /* row */
849 device->controller->address(device, page & 0xff);
850 device->controller->address(device, (page >> 8) & 0xff);
851
852 /* 4th cycle only on devices with more than 32 MiB */
853 if (device->address_cycles >= 4)
854 device->controller->address(device, (page >> 16) & 0xff);
855
856 /* 5th cycle only on devices with more than 8 GiB */
857 if (device->address_cycles >= 5)
858 device->controller->address(device, (page >> 24) & 0xff);
859 }
860 else
861 {
862 /* large page device */
863 device->controller->command(device, NAND_CMD_READ0);
864
865 /* column (0 when we start at the beginning of a page,
866 * or 2048 for the beginning of OOB area)
867 */
868 device->controller->address(device, 0x0);
869 if (data)
870 device->controller->address(device, 0x0);
871 else
872 device->controller->address(device, 0x8);
873
874 /* row */
875 device->controller->address(device, page & 0xff);
876 device->controller->address(device, (page >> 8) & 0xff);
877
878 /* 5th cycle only on devices with more than 128 MiB */
879 if (device->address_cycles >= 5)
880 device->controller->address(device, (page >> 16) & 0xff);
881
882 /* large page devices need a start command */
883 device->controller->command(device, NAND_CMD_READSTART);
884 }
885
886 if (device->controller->nand_ready) {
887 if (!device->controller->nand_ready(device, 100))
888 return ERROR_NAND_OPERATION_TIMEOUT;
889 } else {
890 alive_sleep(1);
891 }
892
893 if (data)
894 {
895 if (device->controller->read_block_data != NULL)
896 (device->controller->read_block_data)(device, data, data_size);
897 else
898 {
899 for (i = 0; i < data_size;)
900 {
901 if (device->device->options & NAND_BUSWIDTH_16)
902 {
903 device->controller->read_data(device, data);
904 data += 2;
905 i += 2;
906 }
907 else
908 {
909 device->controller->read_data(device, data);
910 data += 1;
911 i += 1;
912 }
913 }
914 }
915 }
916
917 if (oob)
918 {
919 if (device->controller->read_block_data != NULL)
920 (device->controller->read_block_data)(device, oob, oob_size);
921 else
922 {
923 for (i = 0; i < oob_size;)
924 {
925 if (device->device->options & NAND_BUSWIDTH_16)
926 {
927 device->controller->read_data(device, oob);
928 oob += 2;
929 i += 2;
930 }
931 else
932 {
933 device->controller->read_data(device, oob);
934 oob += 1;
935 i += 1;
936 }
937 }
938 }
939 }
940
941 return ERROR_OK;
942 }
943
944 int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
945 {
946 u32 i;
947 int retval;
948 u8 status;
949
950 if (!device->device)
951 return ERROR_NAND_DEVICE_NOT_PROBED;
952
953 device->controller->command(device, NAND_CMD_SEQIN);
954
955 if (device->page_size <= 512)
956 {
957 /* column (always 0, we start at the beginning of a page/OOB area) */
958 device->controller->address(device, 0x0);
959
960 /* row */
961 device->controller->address(device, page & 0xff);
962 device->controller->address(device, (page >> 8) & 0xff);
963
964 /* 4th cycle only on devices with more than 32 MiB */
965 if (device->address_cycles >= 4)
966 device->controller->address(device, (page >> 16) & 0xff);
967
968 /* 5th cycle only on devices with more than 8 GiB */
969 if (device->address_cycles >= 5)
970 device->controller->address(device, (page >> 24) & 0xff);
971 }
972 else
973 {
974 /* column (0 when we start at the beginning of a page,
975 * or 2048 for the beginning of OOB area)
976 */
977 device->controller->address(device, 0x0);
978 if (data)
979 device->controller->address(device, 0x0);
980 else
981 device->controller->address(device, 0x8);
982
983 /* row */
984 device->controller->address(device, page & 0xff);
985 device->controller->address(device, (page >> 8) & 0xff);
986
987 /* 5th cycle only on devices with more than 128 MiB */
988 if (device->address_cycles >= 5)
989 device->controller->address(device, (page >> 16) & 0xff);
990 }
991
992 if (data)
993 {
994 if (device->controller->write_block_data != NULL)
995 (device->controller->write_block_data)(device, data, data_size);
996 else
997 {
998 for (i = 0; i < data_size;)
999 {
1000 if (device->device->options & NAND_BUSWIDTH_16)
1001 {
1002 u16 data_buf = le_to_h_u16(data);
1003 device->controller->write_data(device, data_buf);
1004 data += 2;
1005 i += 2;
1006 }
1007 else
1008 {
1009 device->controller->write_data(device, *data);
1010 data += 1;
1011 i += 1;
1012 }
1013 }
1014 }
1015 }
1016
1017 if (oob)
1018 {
1019 if (device->controller->write_block_data != NULL)
1020 (device->controller->write_block_data)(device, oob, oob_size);
1021 else
1022 {
1023 for (i = 0; i < oob_size;)
1024 {
1025 if (device->device->options & NAND_BUSWIDTH_16)
1026 {
1027 u16 oob_buf = le_to_h_u16(data);
1028 device->controller->write_data(device, oob_buf);
1029 oob += 2;
1030 i += 2;
1031 }
1032 else
1033 {
1034 device->controller->write_data(device, *oob);
1035 oob += 1;
1036 i += 1;
1037 }
1038 }
1039 }
1040 }
1041
1042 device->controller->command(device, NAND_CMD_PAGEPROG);
1043
1044 retval = device->controller->nand_ready ?
1045 device->controller->nand_ready(device, 100) :
1046 nand_poll_ready(device, 100);
1047 if (!retval)
1048 return ERROR_NAND_OPERATION_TIMEOUT;
1049
1050 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
1051 {
1052 LOG_ERROR("couldn't read status");
1053 return ERROR_NAND_OPERATION_FAILED;
1054 }
1055
1056 if (status & NAND_STATUS_FAIL)
1057 {
1058 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1059 return ERROR_NAND_OPERATION_FAILED;
1060 }
1061
1062 return ERROR_OK;
1063 }
1064
1065 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1066 {
1067 nand_device_t *p;
1068 int i;
1069
1070 if (!nand_devices)
1071 {
1072 command_print(cmd_ctx, "no NAND flash devices configured");
1073 return ERROR_OK;
1074 }
1075
1076 for (p = nand_devices, i = 0; p; p = p->next, i++)
1077 {
1078 if (p->device)
1079 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1080 i, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1081 else
1082 command_print(cmd_ctx, "#%i: not probed", i);
1083 }
1084
1085 return ERROR_OK;
1086 }
1087
1088 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1089 {
1090 nand_device_t *p;
1091 int i = 0;
1092 int j = 0;
1093 int first = -1;
1094 int last = -1;
1095
1096 switch (argc) {
1097 default:
1098 return ERROR_COMMAND_SYNTAX_ERROR;
1099 case 1:
1100 first = 0;
1101 last = INT32_MAX;
1102 break;
1103 case 2:
1104 first = last = strtoul(args[1], NULL, 0);
1105 break;
1106 case 3:
1107 first = strtoul(args[1], NULL, 0);
1108 last = strtoul(args[2], NULL, 0);
1109 break;
1110 }
1111
1112 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1113 if (p)
1114 {
1115 if (p->device)
1116 {
1117 if (first >= p->num_blocks)
1118 first = p->num_blocks - 1;
1119
1120 if (last >= p->num_blocks)
1121 last = p->num_blocks - 1;
1122
1123 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1124 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1125
1126 for (j = first; j <= last; j++)
1127 {
1128 char *erase_state, *bad_state;
1129
1130 if (p->blocks[j].is_erased == 0)
1131 erase_state = "not erased";
1132 else if (p->blocks[j].is_erased == 1)
1133 erase_state = "erased";
1134 else
1135 erase_state = "erase state unknown";
1136
1137 if (p->blocks[j].is_bad == 0)
1138 bad_state = "";
1139 else if (p->blocks[j].is_bad == 1)
1140 bad_state = " (marked bad)";
1141 else
1142 bad_state = " (block condition unknown)";
1143
1144 command_print(cmd_ctx, "\t#%i: 0x%8.8x (%dkB) %s%s",
1145 j, p->blocks[j].offset, p->blocks[j].size / 1024,
1146 erase_state, bad_state);
1147 }
1148 }
1149 else
1150 {
1151 command_print(cmd_ctx, "#%s: not probed", args[0]);
1152 }
1153 }
1154
1155 return ERROR_OK;
1156 }
1157
1158 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1159 {
1160 nand_device_t *p;
1161 int retval;
1162
1163 if (argc != 1)
1164 {
1165 return ERROR_COMMAND_SYNTAX_ERROR;
1166 }
1167
1168 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1169 if (p)
1170 {
1171 if ((retval = nand_probe(p)) == ERROR_OK)
1172 {
1173 command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
1174 }
1175 else if (retval == ERROR_NAND_OPERATION_FAILED)
1176 {
1177 command_print(cmd_ctx, "probing failed for NAND flash device");
1178 }
1179 else
1180 {
1181 command_print(cmd_ctx, "unknown error when probing NAND flash device");
1182 }
1183 }
1184 else
1185 {
1186 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1187 }
1188
1189 return ERROR_OK;
1190 }
1191
1192 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1193 {
1194 nand_device_t *p;
1195 int retval;
1196
1197 if (argc != 3)
1198 {
1199 return ERROR_COMMAND_SYNTAX_ERROR;
1200
1201 }
1202
1203 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1204 if (p)
1205 {
1206 char *cp;
1207 unsigned long offset;
1208 unsigned long length;
1209
1210 offset = strtoul(args[1], &cp, 0);
1211 if (*cp || offset == ULONG_MAX || offset % p->erase_size)
1212 {
1213 return ERROR_INVALID_ARGUMENTS;
1214 }
1215 offset /= p->erase_size;
1216
1217 length = strtoul(args[2], &cp, 0);
1218 if (*cp || length == ULONG_MAX || length % p->erase_size)
1219 {
1220 return ERROR_INVALID_ARGUMENTS;
1221 }
1222 length -= 1;
1223 length /= p->erase_size;
1224
1225 retval = nand_erase(p, offset, offset + length);
1226 if (retval == ERROR_OK)
1227 {
1228 command_print(cmd_ctx, "successfully erased blocks "
1229 "%lu to %lu on NAND flash device '%s'",
1230 offset, offset + length, p->device->name);
1231 }
1232 else if (retval == ERROR_NAND_OPERATION_FAILED)
1233 {
1234 command_print(cmd_ctx, "erase failed");
1235 }
1236 else
1237 {
1238 command_print(cmd_ctx, "unknown error when erasing NAND flash device");
1239 }
1240 }
1241 else
1242 {
1243 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1244 }
1245
1246 return ERROR_OK;
1247 }
1248
1249 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1250 {
1251 nand_device_t *p;
1252 int retval;
1253 int first = -1;
1254 int last = -1;
1255
1256 if ((argc < 1) || (argc > 3) || (argc == 2))
1257 {
1258 return ERROR_COMMAND_SYNTAX_ERROR;
1259
1260 }
1261
1262 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1263 if (!p) {
1264 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds",
1265 args[0]);
1266 return ERROR_INVALID_ARGUMENTS;
1267 }
1268
1269 if (argc == 3)
1270 {
1271 char *cp;
1272 unsigned long offset;
1273 unsigned long length;
1274
1275 offset = strtoul(args[1], &cp, 0);
1276 if (*cp || offset == ULONG_MAX || offset % p->erase_size)
1277 {
1278 return ERROR_INVALID_ARGUMENTS;
1279 }
1280 offset /= p->erase_size;
1281
1282 length = strtoul(args[2], &cp, 0);
1283 if (*cp || length == ULONG_MAX || length % p->erase_size)
1284 {
1285 return ERROR_INVALID_ARGUMENTS;
1286 }
1287 length -= 1;
1288 length /= p->erase_size;
1289
1290 first = offset;
1291 last = offset + length;
1292 }
1293
1294 retval = nand_build_bbt(p, first, last);
1295 if (retval == ERROR_OK)
1296 {
1297 command_print(cmd_ctx, "checked NAND flash device for bad blocks, "
1298 "use \"nand info\" command to list blocks");
1299 }
1300 else if (retval == ERROR_NAND_OPERATION_FAILED)
1301 {
1302 command_print(cmd_ctx, "error when checking for bad blocks on "
1303 "NAND flash device");
1304 }
1305 else
1306 {
1307 command_print(cmd_ctx, "unknown error when checking for bad "
1308 "blocks on NAND flash device");
1309 }
1310
1311 return ERROR_OK;
1312 }
1313
1314 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1315 {
1316 u32 offset;
1317 u32 binary_size;
1318 u32 buf_cnt;
1319 enum oob_formats oob_format = NAND_OOB_NONE;
1320
1321 fileio_t fileio;
1322
1323 duration_t duration;
1324 char *duration_text;
1325
1326 nand_device_t *p;
1327
1328 if (argc < 3)
1329 {
1330 return ERROR_COMMAND_SYNTAX_ERROR;
1331
1332 }
1333
1334 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1335 if (p)
1336 {
1337 u8 *page = NULL;
1338 u32 page_size = 0;
1339 u8 *oob = NULL;
1340 u32 oob_size = 0;
1341 const int *eccpos = NULL;
1342
1343 offset = strtoul(args[2], NULL, 0);
1344
1345 if (argc > 3)
1346 {
1347 int i;
1348 for (i = 3; i < argc; i++)
1349 {
1350 if (!strcmp(args[i], "oob_raw"))
1351 oob_format |= NAND_OOB_RAW;
1352 else if (!strcmp(args[i], "oob_only"))
1353 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1354 else if (!strcmp(args[i], "oob_softecc"))
1355 oob_format |= NAND_OOB_SW_ECC;
1356 else if (!strcmp(args[i], "oob_softecc_kw"))
1357 oob_format |= NAND_OOB_SW_ECC_KW;
1358 else
1359 {
1360 command_print(cmd_ctx, "unknown option: %s", args[i]);
1361 return ERROR_COMMAND_SYNTAX_ERROR;
1362 }
1363 }
1364 }
1365
1366 duration_start_measure(&duration);
1367
1368 if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1369 {
1370 return ERROR_OK;
1371 }
1372
1373 buf_cnt = binary_size = fileio.size;
1374
1375 if (!(oob_format & NAND_OOB_ONLY))
1376 {
1377 page_size = p->page_size;
1378 page = malloc(p->page_size);
1379 }
1380
1381 if (oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC | NAND_OOB_SW_ECC_KW))
1382 {
1383 if (p->page_size == 512) {
1384 oob_size = 16;
1385 eccpos = nand_oob_16.eccpos;
1386 } else if (p->page_size == 2048) {
1387 oob_size = 64;
1388 eccpos = nand_oob_64.eccpos;
1389 }
1390 oob = malloc(oob_size);
1391 }
1392
1393 if (offset % p->page_size)
1394 {
1395 command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
1396 fileio_close(&fileio);
1397 free(oob);
1398 free(page);
1399 return ERROR_OK;
1400 }
1401
1402 while (buf_cnt > 0)
1403 {
1404 u32 size_read;
1405
1406 if (NULL != page)
1407 {
1408 fileio_read(&fileio, page_size, page, &size_read);
1409 buf_cnt -= size_read;
1410 if (size_read < page_size)
1411 {
1412 memset(page + size_read, 0xff, page_size - size_read);
1413 }
1414 }
1415
1416 if (oob_format & NAND_OOB_SW_ECC)
1417 {
1418 u32 i, j;
1419 u8 ecc[3];
1420 memset(oob, 0xff, oob_size);
1421 for (i = 0, j = 0; i < page_size; i += 256) {
1422 nand_calculate_ecc(p, page+i, ecc);
1423 oob[eccpos[j++]] = ecc[0];
1424 oob[eccpos[j++]] = ecc[1];
1425 oob[eccpos[j++]] = ecc[2];
1426 }
1427 } else if (oob_format & NAND_OOB_SW_ECC_KW)
1428 {
1429 /*
1430 * In this case eccpos is not used as
1431 * the ECC data is always stored contigously
1432 * at the end of the OOB area. It consists
1433 * of 10 bytes per 512-byte data block.
1434 */
1435 u32 i;
1436 u8 *ecc = oob + oob_size - page_size/512 * 10;
1437 memset(oob, 0xff, oob_size);
1438 for (i = 0; i < page_size; i += 512) {
1439 nand_calculate_ecc_kw(p, page+i, ecc);
1440 ecc += 10;
1441 }
1442 }
1443 else if (NULL != oob)
1444 {
1445 fileio_read(&fileio, oob_size, oob, &size_read);
1446 buf_cnt -= size_read;
1447 if (size_read < oob_size)
1448 {
1449 memset(oob + size_read, 0xff, oob_size - size_read);
1450 }
1451 }
1452
1453 if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
1454 {
1455 command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8x",
1456 args[1], args[0], offset);
1457
1458 fileio_close(&fileio);
1459 free(oob);
1460 free(page);
1461
1462 return ERROR_OK;
1463 }
1464 offset += page_size;
1465 }
1466
1467 fileio_close(&fileio);
1468 free(oob);
1469 free(page);
1470 oob = NULL;
1471 page = NULL;
1472 duration_stop_measure(&duration, &duration_text);
1473 command_print(cmd_ctx, "wrote file %s to NAND flash %s up to offset 0x%8.8x in %s",
1474 args[1], args[0], offset, duration_text);
1475 free(duration_text);
1476 duration_text = NULL;
1477 }
1478 else
1479 {
1480 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1481 }
1482
1483 return ERROR_OK;
1484 }
1485
1486 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1487 {
1488 nand_device_t *p;
1489
1490 if (argc < 4)
1491 {
1492 return ERROR_COMMAND_SYNTAX_ERROR;
1493 }
1494
1495 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1496 if (p)
1497 {
1498 if (p->device)
1499 {
1500 fileio_t fileio;
1501 duration_t duration;
1502 char *duration_text;
1503 int retval;
1504
1505 u8 *page = NULL;
1506 u32 page_size = 0;
1507 u8 *oob = NULL;
1508 u32 oob_size = 0;
1509 u32 address = strtoul(args[2], NULL, 0);
1510 u32 size = strtoul(args[3], NULL, 0);
1511 u32 bytes_done = 0;
1512 enum oob_formats oob_format = NAND_OOB_NONE;
1513
1514 if (argc > 4)
1515 {
1516 int i;
1517 for (i = 4; i < argc; i++)
1518 {
1519 if (!strcmp(args[i], "oob_raw"))
1520 oob_format |= NAND_OOB_RAW;
1521 else if (!strcmp(args[i], "oob_only"))
1522 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1523 else
1524 command_print(cmd_ctx, "unknown option: '%s'", args[i]);
1525 }
1526 }
1527
1528 if ((address % p->page_size) || (size % p->page_size))
1529 {
1530 command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
1531 return ERROR_OK;
1532 }
1533
1534 if (!(oob_format & NAND_OOB_ONLY))
1535 {
1536 page_size = p->page_size;
1537 page = malloc(p->page_size);
1538 }
1539
1540 if (oob_format & NAND_OOB_RAW)
1541 {
1542 if (p->page_size == 512)
1543 oob_size = 16;
1544 else if (p->page_size == 2048)
1545 oob_size = 64;
1546 oob = malloc(oob_size);
1547 }
1548
1549 if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1550 {
1551 return ERROR_OK;
1552 }
1553
1554 duration_start_measure(&duration);
1555
1556 while (size > 0)
1557 {
1558 u32 size_written;
1559 if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
1560 {
1561 command_print(cmd_ctx, "reading NAND flash page failed");
1562 free(page);
1563 free(oob);
1564 fileio_close(&fileio);
1565 return ERROR_OK;
1566 }
1567
1568 if (NULL != page)
1569 {
1570 fileio_write(&fileio, page_size, page, &size_written);
1571 bytes_done += page_size;
1572 }
1573
1574 if (NULL != oob)
1575 {
1576 fileio_write(&fileio, oob_size, oob, &size_written);
1577 bytes_done += oob_size;
1578 }
1579
1580 size -= p->page_size;
1581 address += p->page_size;
1582 }
1583
1584 free(page);
1585 page = NULL;
1586 free(oob);
1587 oob = NULL;
1588 fileio_close(&fileio);
1589
1590 duration_stop_measure(&duration, &duration_text);
1591 command_print(cmd_ctx, "dumped %lld byte in %s", fileio.size, duration_text);
1592 free(duration_text);
1593 duration_text = NULL;
1594 }
1595 else
1596 {
1597 command_print(cmd_ctx, "#%s: not probed", args[0]);
1598 }
1599 }
1600 else
1601 {
1602 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1603 }
1604
1605 return ERROR_OK;
1606 }
1607
1608 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1609 {
1610 nand_device_t *p;
1611
1612 if ((argc < 1) || (argc > 2))
1613 {
1614 return ERROR_COMMAND_SYNTAX_ERROR;
1615 }
1616
1617 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1618 if (p)
1619 {
1620 if (p->device)
1621 {
1622 if (argc == 2)
1623 {
1624 if (strcmp("enable", args[1]) == 0)
1625 {
1626 p->use_raw = 1;
1627 }
1628 else if (strcmp("disable", args[1]) == 0)
1629 {
1630 p->use_raw = 0;
1631 }
1632 else
1633 {
1634 return ERROR_COMMAND_SYNTAX_ERROR;
1635 }
1636 }
1637
1638 command_print(cmd_ctx, "raw access is %s", (p->use_raw) ? "enabled" : "disabled");
1639 }
1640 else
1641 {
1642 command_print(cmd_ctx, "#%s: not probed", args[0]);
1643 }
1644 }
1645 else
1646 {
1647 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1648 }
1649
1650 return ERROR_OK;
1651 }
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