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NAND/MX2: remove private "target" copy
[openocd.git] / src / flash / nand / mx2.c
1 /***************************************************************************
2 * Copyright (C) 2009 by Alexei Babich *
3 * Rezonans plc., Chelyabinsk, Russia *
4 * impatt@mail.ru *
5 * *
6 * Copyright (C) 2010 by Gaetan CARLIER *
7 * Trump s.a., Belgium *
8 * *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
13 * *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
18 * *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
24
25 /*
26 * Freescale iMX2* OpenOCD NAND Flash controller support.
27 * based on Freescale iMX3* OpenOCD NAND Flash controller support.
28 */
29
30 /*
31 * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @imx27
32 * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
33 * "nand write # file 0", "nand verify"
34 *
35 * get_next_halfword_from_sram_buffer() not tested
36 * !! all function only tested with 2k page nand device; imx27_write_page
37 * writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
38 * !! oob must be be used due to NFS bug
39 */
40 #ifdef HAVE_CONFIG_H
41 #include "config.h"
42 #endif
43
44 #include "imp.h"
45 #include "mx2.h"
46 #include <target/target.h>
47
48 /* This permits to print (in LOG_INFO) how much bytes
49 * has been written after a page read or write.
50 * This is useful when OpenOCD is used with a graphical
51 * front-end to estimate progression of the global read/write
52 */
53 #undef _MX2_PRINT_STAT
54 //#define _MX2_PRINT_STAT
55
56 static const char target_not_halted_err_msg[] =
57 "target must be halted to use mx2 NAND flash controller";
58 static const char data_block_size_err_msg[] =
59 "minimal granularity is one half-word, %" PRId32 " is incorrect";
60 static const char sram_buffer_bounds_err_msg[] =
61 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
62 static const char get_status_register_err_msg[] = "can't get NAND status";
63 static uint32_t in_sram_address;
64 static unsigned char sign_of_sequental_byte_read;
65
66 static int initialize_nf_controller(struct nand_device *nand);
67 static int get_next_byte_from_sram_buffer(struct target * target, uint8_t * value);
68 static int get_next_halfword_from_sram_buffer(struct target * target,
69 uint16_t * value);
70 static int poll_for_complete_op(struct target * target, const char *text);
71 static int validate_target_state(struct nand_device *nand);
72 static int do_data_output(struct nand_device *nand);
73
74 static int imx27_command(struct nand_device *nand, uint8_t command);
75 static int imx27_address(struct nand_device *nand, uint8_t address);
76
77 NAND_DEVICE_COMMAND_HANDLER(imx27_nand_device_command)
78 {
79 struct mx2_nf_controller *mx2_nf_info;
80 int hwecc_needed;
81 int x;
82 mx2_nf_info = malloc(sizeof(struct mx2_nf_controller));
83 if (mx2_nf_info == NULL) {
84 LOG_ERROR("no memory for nand controller");
85 return ERROR_FAIL;
86 }
87
88 nand->controller_priv = mx2_nf_info;
89 if (CMD_ARGC < 3) {
90 LOG_ERROR("use \"nand device imx27 target noecc|hwecc\"");
91 return ERROR_FAIL;
92 }
93 /*
94 * check hwecc requirements
95 */
96
97 hwecc_needed = strcmp(CMD_ARGV[2], "hwecc");
98 if (hwecc_needed == 0)
99 mx2_nf_info->flags.hw_ecc_enabled = 1;
100 else
101 mx2_nf_info->flags.hw_ecc_enabled = 0;
102
103 mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE;
104 mx2_nf_info->fin = MX2_NF_FIN_NONE;
105 mx2_nf_info->flags.target_little_endian =
106 (nand->target->endianness == TARGET_LITTLE_ENDIAN);
107 /*
108 * testing host endianess
109 */
110 x = 1;
111 if (*(char *) &x == 1)
112 mx2_nf_info->flags.host_little_endian = 1;
113 else
114 mx2_nf_info->flags.host_little_endian = 0;
115 return ERROR_OK;
116 }
117
118 static int imx27_init(struct nand_device *nand)
119 {
120 struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
121 struct target *target = nand->target;
122
123 int validate_target_result;
124 uint16_t buffsize_register_content;
125 uint32_t pcsr_register_content;
126 int retval;
127 uint16_t nand_status_content;
128 /*
129 * validate target state
130 */
131 validate_target_result = validate_target_state(nand);
132 if (validate_target_result != ERROR_OK)
133 return validate_target_result;
134
135 target_read_u16(target, MX2_NF_BUFSIZ, &buffsize_register_content);
136 mx2_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
137
138 target_read_u32(target, MX2_FMCR, &pcsr_register_content);
139 if (!nand->bus_width) {
140 /* bus_width not yet defined. Read it from MX2_FMCR */
141 nand->bus_width =
142 (pcsr_register_content & MX2_FMCR_NF_16BIT_SEL) ? 16 : 8;
143 } else {
144 /* bus_width forced in soft. Sync it to MX2_FMCR */
145 pcsr_register_content |=
146 ((nand->bus_width == 16) ? MX2_FMCR_NF_16BIT_SEL : 0x00000000);
147 target_write_u32(target, MX2_FMCR, pcsr_register_content);
148 }
149 if (nand->bus_width == 16)
150 LOG_DEBUG("MX2_NF : bus is 16-bit width");
151 else
152 LOG_DEBUG("MX2_NF : bus is 8-bit width");
153
154 if (!nand->page_size) {
155 nand->page_size =
156 (pcsr_register_content & MX2_FMCR_NF_FMS) ? 2048 : 512;
157 } else {
158 pcsr_register_content |=
159 ((nand->page_size == 2048) ? MX2_FMCR_NF_FMS : 0x00000000);
160 target_write_u32(target, MX2_FMCR, pcsr_register_content);
161 }
162 if (mx2_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
163 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
164 "pagesize 2048 is incompatible with it");
165 } else {
166 LOG_DEBUG("MX2_NF : NAND controller can handle pagesize of 2048");
167 }
168
169 initialize_nf_controller(nand);
170
171 retval = ERROR_OK;
172 retval |= imx27_command(nand, NAND_CMD_STATUS);
173 retval |= imx27_address(nand, 0x00);
174 retval |= do_data_output(nand);
175 if (retval != ERROR_OK) {
176 LOG_ERROR(get_status_register_err_msg);
177 return ERROR_FAIL;
178 }
179 target_read_u16(target, MX2_NF_MAIN_BUFFER0, &nand_status_content);
180 if (!(nand_status_content & 0x0080)) {
181 LOG_INFO("NAND read-only");
182 mx2_nf_info->flags.nand_readonly = 1;
183 } else {
184 mx2_nf_info->flags.nand_readonly = 0;
185 }
186 return ERROR_OK;
187 }
188
189 static int imx27_read_data(struct nand_device *nand, void *data)
190 {
191 struct target *target = nand->target;
192 int validate_target_result;
193 int try_data_output_from_nand_chip;
194 /*
195 * validate target state
196 */
197 validate_target_result = validate_target_state(nand);
198 if (validate_target_result != ERROR_OK)
199 return validate_target_result;
200
201 /*
202 * get data from nand chip
203 */
204 try_data_output_from_nand_chip = do_data_output(nand);
205 if (try_data_output_from_nand_chip != ERROR_OK) {
206 LOG_ERROR("imx27_read_data : read data failed : '%x'",
207 try_data_output_from_nand_chip);
208 return try_data_output_from_nand_chip;
209 }
210
211 if (nand->bus_width == 16)
212 get_next_halfword_from_sram_buffer(target, data);
213 else
214 get_next_byte_from_sram_buffer(target, data);
215
216 return ERROR_OK;
217 }
218
219 static int imx27_write_data(struct nand_device *nand, uint16_t data)
220 {
221 LOG_ERROR("write_data() not implemented");
222 return ERROR_NAND_OPERATION_FAILED;
223 }
224
225 static int imx27_reset(struct nand_device *nand)
226 {
227 /*
228 * validate target state
229 */
230 int validate_target_result;
231 validate_target_result = validate_target_state(nand);
232 if (validate_target_result != ERROR_OK)
233 return validate_target_result;
234 initialize_nf_controller(nand);
235 return ERROR_OK;
236 }
237
238 static int imx27_command(struct nand_device *nand, uint8_t command)
239 {
240 struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
241 struct target *target = nand->target;
242 int validate_target_result;
243 int poll_result;
244 /*
245 * validate target state
246 */
247 validate_target_result = validate_target_state(nand);
248 if (validate_target_result != ERROR_OK)
249 return validate_target_result;
250
251 switch(command) {
252 case NAND_CMD_READOOB:
253 command = NAND_CMD_READ0;
254 /* set read point for data_read() and read_block_data() to
255 * spare area in SRAM buffer
256 */
257 in_sram_address = MX2_NF_SPARE_BUFFER0;
258 break;
259 case NAND_CMD_READ1:
260 command = NAND_CMD_READ0;
261 /*
262 * offset == one half of page size
263 */
264 in_sram_address =
265 MX2_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
266 break;
267 default:
268 in_sram_address = MX2_NF_MAIN_BUFFER0;
269 break;
270 }
271
272 target_write_u16(target, MX2_NF_FCMD, command);
273 /*
274 * start command input operation (set MX2_NF_BIT_OP_DONE==0)
275 */
276 target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FCI);
277 poll_result = poll_for_complete_op(target, "command");
278 if (poll_result != ERROR_OK)
279 return poll_result;
280 /*
281 * reset cursor to begin of the buffer
282 */
283 sign_of_sequental_byte_read = 0;
284 /* Handle special read command and adjust NF_CFG2(FDO) */
285 switch(command) {
286 case NAND_CMD_READID:
287 mx2_nf_info->optype = MX2_NF_DATAOUT_NANDID;
288 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
289 break;
290 case NAND_CMD_STATUS:
291 mx2_nf_info->optype = MX2_NF_DATAOUT_NANDSTATUS;
292 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
293 target_write_u16 (target, MX2_NF_BUFADDR, 0);
294 in_sram_address = 0;
295 break;
296 case NAND_CMD_READ0:
297 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
298 mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE;
299 break;
300 default:
301 /* Ohter command use the default 'One page data out' FDO */
302 mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE;
303 break;
304 }
305 return ERROR_OK;
306 }
307
308 static int imx27_address(struct nand_device *nand, uint8_t address)
309 {
310 struct target *target = nand->target;
311 int validate_target_result;
312 int poll_result;
313 /*
314 * validate target state
315 */
316 validate_target_result = validate_target_state(nand);
317 if (validate_target_result != ERROR_OK)
318 return validate_target_result;
319
320 target_write_u16(target, MX2_NF_FADDR, address);
321 /*
322 * start address input operation (set MX2_NF_BIT_OP_DONE==0)
323 */
324 target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FAI);
325 poll_result = poll_for_complete_op(target, "address");
326 if (poll_result != ERROR_OK)
327 return poll_result;
328
329 return ERROR_OK;
330 }
331
332 static int imx27_nand_ready(struct nand_device *nand, int tout)
333 {
334 uint16_t poll_complete_status;
335 struct target *target = nand->target;
336 int validate_target_result;
337
338 /*
339 * validate target state
340 */
341 validate_target_result = validate_target_state(nand);
342 if (validate_target_result != ERROR_OK)
343 return validate_target_result;
344
345 do {
346 target_read_u16(target, MX2_NF_CFG2, &poll_complete_status);
347 if (poll_complete_status & MX2_NF_BIT_OP_DONE)
348 return tout;
349
350 alive_sleep(1);
351 }
352 while (tout-- > 0);
353 return tout;
354 }
355
356 static int imx27_write_page(struct nand_device *nand, uint32_t page,
357 uint8_t * data, uint32_t data_size, uint8_t * oob,
358 uint32_t oob_size)
359 {
360 struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
361 struct target *target = nand->target;
362 int retval;
363 uint16_t nand_status_content;
364 uint16_t swap1, swap2, new_swap1;
365 int poll_result;
366 if (data_size % 2) {
367 LOG_ERROR(data_block_size_err_msg, data_size);
368 return ERROR_NAND_OPERATION_FAILED;
369 }
370 if (oob_size % 2) {
371 LOG_ERROR(data_block_size_err_msg, oob_size);
372 return ERROR_NAND_OPERATION_FAILED;
373 }
374 if (!data) {
375 LOG_ERROR("nothing to program");
376 return ERROR_NAND_OPERATION_FAILED;
377 }
378 /*
379 * validate target state
380 */
381 retval = validate_target_state(nand);
382 if (retval != ERROR_OK)
383 return retval;
384
385 in_sram_address = MX2_NF_MAIN_BUFFER0;
386 sign_of_sequental_byte_read = 0;
387 retval = ERROR_OK;
388 retval |= imx27_command(nand, NAND_CMD_SEQIN);
389 retval |= imx27_address(nand, 0); //col
390 retval |= imx27_address(nand, 0); //col
391 retval |= imx27_address(nand, page & 0xff); //page address
392 retval |= imx27_address(nand, (page >> 8) & 0xff); //page address
393 retval |= imx27_address(nand, (page >> 16) & 0xff); //page address
394
395 target_write_buffer(target, MX2_NF_MAIN_BUFFER0, data_size, data);
396 if (oob) {
397 if (mx2_nf_info->flags.hw_ecc_enabled) {
398 /*
399 * part of spare block will be overrided by hardware
400 * ECC generator
401 */
402 LOG_DEBUG("part of spare block will be overrided "
403 "by hardware ECC generator");
404 }
405 target_write_buffer(target, MX2_NF_SPARE_BUFFER0, oob_size,
406 oob);
407 }
408 //BI-swap - work-around of imx27 NFC for NAND device with page == 2kb
409 target_read_u16(target, MX2_NF_MAIN_BUFFER3 + 464, &swap1);
410 if (oob) {
411 LOG_ERROR("Due to NFC Bug, oob is not correctly implemented "
412 "in mx2 driver");
413 return ERROR_NAND_OPERATION_FAILED;
414 }
415 //target_read_u16 (target, MX2_NF_SPARE_BUFFER3 + 4, &swap2);
416 swap2 = 0xffff; //Spare buffer unused forced to 0xffff
417 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
418 swap2 = (swap1 << 8) | (swap2 & 0xFF);
419
420 target_write_u16(target, MX2_NF_MAIN_BUFFER3 + 464, new_swap1);
421 target_write_u16(target, MX2_NF_SPARE_BUFFER3 + 4, swap2);
422 /*
423 * start data input operation (set MX2_NF_BIT_OP_DONE==0)
424 */
425 target_write_u16(target, MX2_NF_BUFADDR, 0);
426 target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
427 poll_result = poll_for_complete_op(target, "data input");
428 if (poll_result != ERROR_OK)
429 return poll_result;
430
431 target_write_u16(target, MX2_NF_BUFADDR, 1);
432 target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
433 poll_result = poll_for_complete_op(target, "data input");
434 if (poll_result != ERROR_OK)
435 return poll_result;
436
437 target_write_u16(target, MX2_NF_BUFADDR, 2);
438 target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
439 poll_result = poll_for_complete_op(target, "data input");
440 if (poll_result != ERROR_OK)
441 return poll_result;
442
443 target_write_u16(target, MX2_NF_BUFADDR, 3);
444 target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_OP_FDI);
445 poll_result = poll_for_complete_op(target, "data input");
446 if (poll_result != ERROR_OK)
447 return poll_result;
448
449 retval |= imx27_command(nand, NAND_CMD_PAGEPROG);
450 if (retval != ERROR_OK)
451 return retval;
452
453 /*
454 * check status register
455 */
456 retval = ERROR_OK;
457 retval |= imx27_command(nand, NAND_CMD_STATUS);
458 target_write_u16 (target, MX2_NF_BUFADDR, 0);
459 mx2_nf_info->optype = MX2_NF_DATAOUT_NANDSTATUS;
460 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
461 retval |= do_data_output(nand);
462 if (retval != ERROR_OK) {
463 LOG_ERROR (get_status_register_err_msg);
464 return retval;
465 }
466 target_read_u16 (target, MX2_NF_MAIN_BUFFER0, &nand_status_content);
467 if (nand_status_content & 0x0001) {
468 /*
469 * page not correctly written
470 */
471 return ERROR_NAND_OPERATION_FAILED;
472 }
473 #ifdef _MX2_PRINT_STAT
474 LOG_INFO("%d bytes newly written", data_size);
475 #endif
476 return ERROR_OK;
477 }
478
479 static int imx27_read_page(struct nand_device *nand, uint32_t page,
480 uint8_t * data, uint32_t data_size, uint8_t * oob,
481 uint32_t oob_size)
482 {
483 struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
484 struct target *target = nand->target;
485 int retval;
486 uint16_t swap1, swap2, new_swap1;
487 if (data_size % 2) {
488 LOG_ERROR(data_block_size_err_msg, data_size);
489 return ERROR_NAND_OPERATION_FAILED;
490 }
491 if (oob_size % 2) {
492 LOG_ERROR(data_block_size_err_msg, oob_size);
493 return ERROR_NAND_OPERATION_FAILED;
494 }
495
496 /*
497 * validate target state
498 */
499 retval = validate_target_state(nand);
500 if (retval != ERROR_OK) {
501 return retval;
502 }
503 /* Reset address_cycles before imx27_command ?? */
504 retval = ERROR_OK;
505 retval |= imx27_command(nand, NAND_CMD_READ0);
506
507 retval |= imx27_address(nand, 0); //col
508 retval |= imx27_address(nand, 0); //col
509 retval |= imx27_address(nand, page & 0xff); //page address
510 retval |= imx27_address(nand, (page >> 8) & 0xff); //page address
511 retval |= imx27_address(nand, (page >> 16) & 0xff); //page address
512 retval |= imx27_command(nand, NAND_CMD_READSTART);
513
514 target_write_u16(target, MX2_NF_BUFADDR, 0);
515 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
516 retval = do_data_output(nand);
517 if (retval != ERROR_OK) {
518 LOG_ERROR("MX2_NF : Error reading page 0");
519 return retval;
520 }
521 //Test nand page size to know how much MAIN_BUFFER must be written
522 target_write_u16(target, MX2_NF_BUFADDR, 1);
523 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
524 retval = do_data_output(nand);
525 if (retval != ERROR_OK) {
526 LOG_ERROR("MX2_NF : Error reading page 1");
527 return retval;
528 }
529 target_write_u16(target, MX2_NF_BUFADDR, 2);
530 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
531 retval = do_data_output(nand);
532 if (retval != ERROR_OK) {
533 LOG_ERROR("MX2_NF : Error reading page 2");
534 return retval;
535 }
536 target_write_u16(target, MX2_NF_BUFADDR, 3);
537 mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
538 retval = do_data_output(nand);
539 if (retval != ERROR_OK) {
540 LOG_ERROR("MX2_NF : Error reading page 3");
541 return retval;
542 }
543 //BI-swap - work-around of imx27 NFC for NAND device with page == 2k
544 target_read_u16(target, MX2_NF_MAIN_BUFFER3 + 464, &swap1);
545 target_read_u16(target, MX2_NF_SPARE_BUFFER3 + 4, &swap2);
546 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
547 swap2 = (swap1 << 8) | (swap2 & 0xFF);
548 target_write_u16(target, MX2_NF_MAIN_BUFFER3 + 464, new_swap1);
549 target_write_u16(target, MX2_NF_SPARE_BUFFER3 + 4, swap2);
550
551 if (data)
552 target_read_buffer(target, MX2_NF_MAIN_BUFFER0, data_size, data);
553 if (oob)
554 target_read_buffer(target, MX2_NF_SPARE_BUFFER0, oob_size,
555 oob);
556 #ifdef _MX2_PRINT_STAT
557 if (data_size > 0) {
558 /* When Operation Status is read (when page is erased),
559 * this function is used but data_size is null.
560 */
561 LOG_INFO("%d bytes newly read", data_size);
562 }
563 #endif
564 return ERROR_OK;
565 }
566
567 static int initialize_nf_controller(struct nand_device *nand)
568 {
569 struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
570 struct target *target = nand->target;
571 uint16_t work_mode;
572 uint16_t temp;
573 /*
574 * resets NAND flash controller in zero time ? I dont know.
575 */
576 target_write_u16(target, MX2_NF_CFG1, MX2_NF_BIT_RESET_EN);
577 work_mode = MX2_NF_BIT_INT_DIS; /* disable interrupt */
578 if (target->endianness == TARGET_BIG_ENDIAN) {
579 LOG_DEBUG("MX2_NF : work in Big Endian mode");
580 work_mode |= MX2_NF_BIT_BE_EN;
581 } else {
582 LOG_DEBUG("MX2_NF : work in Little Endian mode");
583 }
584 if (mx2_nf_info->flags.hw_ecc_enabled) {
585 LOG_DEBUG("MX2_NF : work with ECC mode");
586 work_mode |= MX2_NF_BIT_ECC_EN;
587 } else {
588 LOG_DEBUG("MX2_NF : work without ECC mode");
589 }
590 target_write_u16(target, MX2_NF_CFG1, work_mode);
591 /*
592 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
593 */
594 target_write_u16(target, MX2_NF_BUFCFG, 2);
595 target_read_u16(target, MX2_NF_FWP, &temp);
596 if ((temp & 0x0007) == 1) {
597 LOG_ERROR("NAND flash is tight-locked, reset needed");
598 return ERROR_FAIL;
599 }
600
601 /*
602 * unlock NAND flash for write
603 */
604 target_write_u16(target, MX2_NF_FWP, 4);
605 target_write_u16(target, MX2_NF_LOCKSTART, 0x0000);
606 target_write_u16(target, MX2_NF_LOCKEND, 0xFFFF);
607 /*
608 * 0x0000 means that first SRAM buffer @0xD800_0000 will be used
609 */
610 target_write_u16(target, MX2_NF_BUFADDR, 0x0000);
611 /*
612 * address of SRAM buffer
613 */
614 in_sram_address = MX2_NF_MAIN_BUFFER0;
615 sign_of_sequental_byte_read = 0;
616 return ERROR_OK;
617 }
618
619 static int get_next_byte_from_sram_buffer(struct target * target, uint8_t * value)
620 {
621 static uint8_t even_byte = 0;
622 uint16_t temp;
623 /*
624 * host-big_endian ??
625 */
626 if (sign_of_sequental_byte_read == 0)
627 even_byte = 0;
628
629 if (in_sram_address > MX2_NF_LAST_BUFFER_ADDR) {
630 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
631 *value = 0;
632 sign_of_sequental_byte_read = 0;
633 even_byte = 0;
634 return ERROR_NAND_OPERATION_FAILED;
635 } else {
636 target_read_u16(target, in_sram_address, &temp);
637 if (even_byte) {
638 *value = temp >> 8;
639 even_byte = 0;
640 in_sram_address += 2;
641 } else {
642 *value = temp & 0xff;
643 even_byte = 1;
644 }
645 }
646 sign_of_sequental_byte_read = 1;
647 return ERROR_OK;
648 }
649
650 static int get_next_halfword_from_sram_buffer(struct target * target,
651 uint16_t * value)
652 {
653 if (in_sram_address > MX2_NF_LAST_BUFFER_ADDR) {
654 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
655 *value = 0;
656 return ERROR_NAND_OPERATION_FAILED;
657 } else {
658 target_read_u16(target, in_sram_address, value);
659 in_sram_address += 2;
660 }
661 return ERROR_OK;
662 }
663
664 static int poll_for_complete_op(struct target * target, const char *text)
665 {
666 uint16_t poll_complete_status;
667 for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++) {
668 target_read_u16(target, MX2_NF_CFG2, &poll_complete_status);
669 if (poll_complete_status & MX2_NF_BIT_OP_DONE)
670 break;
671
672 usleep(10);
673 }
674 if (!(poll_complete_status & MX2_NF_BIT_OP_DONE)) {
675 LOG_ERROR("%s sending timeout", text);
676 return ERROR_NAND_OPERATION_FAILED;
677 }
678 return ERROR_OK;
679 }
680
681 static int validate_target_state(struct nand_device *nand)
682 {
683 struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
684 struct target *target = nand->target;
685
686 if (target->state != TARGET_HALTED) {
687 LOG_ERROR(target_not_halted_err_msg);
688 return ERROR_NAND_OPERATION_FAILED;
689 }
690
691 if (mx2_nf_info->flags.target_little_endian !=
692 (target->endianness == TARGET_LITTLE_ENDIAN)) {
693 /*
694 * endianness changed after NAND controller probed
695 */
696 return ERROR_NAND_OPERATION_FAILED;
697 }
698 return ERROR_OK;
699 }
700
701 static int do_data_output(struct nand_device *nand)
702 {
703 struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
704 struct target *target = nand->target;
705 int poll_result;
706 uint16_t ecc_status;
707 switch(mx2_nf_info->fin) {
708 case MX2_NF_FIN_DATAOUT:
709 /*
710 * start data output operation (set MX2_NF_BIT_OP_DONE==0)
711 */
712 target_write_u16(target, MX2_NF_CFG2, MX2_NF_BIT_DATAOUT_TYPE(mx2_nf_info->optype));
713 poll_result = poll_for_complete_op(target, "data output");
714 if (poll_result != ERROR_OK)
715 return poll_result;
716
717 mx2_nf_info->fin = MX2_NF_FIN_NONE;
718 /*
719 * ECC stuff
720 */
721 if ((mx2_nf_info->optype == MX2_NF_DATAOUT_PAGE) && mx2_nf_info->flags.hw_ecc_enabled) {
722 target_read_u16(target, MX2_NF_ECCSTATUS, &ecc_status);
723 switch(ecc_status & 0x000c) {
724 case 1 << 2:
725 LOG_INFO("main area readed with 1 (correctable) error");
726 break;
727 case 2 << 2:
728 LOG_INFO("main area readed with more than 1 (incorrectable) error");
729 return ERROR_NAND_OPERATION_FAILED;
730 break;
731 }
732 switch(ecc_status & 0x0003) {
733 case 1:
734 LOG_INFO("spare area readed with 1 (correctable) error");
735 break;
736 case 2:
737 LOG_INFO("main area readed with more than 1 (incorrectable) error");
738 return ERROR_NAND_OPERATION_FAILED;
739 break;
740 }
741 }
742 break;
743 case MX2_NF_FIN_NONE:
744 break;
745 }
746 return ERROR_OK;
747 }
748
749 struct nand_flash_controller imx27_nand_flash_controller = {
750 .name = "imx27",
751 .nand_device_command = &imx27_nand_device_command,
752 .init = &imx27_init,
753 .reset = &imx27_reset,
754 .command = &imx27_command,
755 .address = &imx27_address,
756 .write_data = &imx27_write_data,
757 .read_data = &imx27_read_data,
758 .write_page = &imx27_write_page,
759 .read_page = &imx27_read_page,
760 .nand_ready = &imx27_nand_ready,
761 };
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