2 /***************************************************************************
3 * Copyright (C) 2009 by Alexei Babich *
4 * Rezonans plc., Chelyabinsk, Russia *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
24 * Freescale iMX3* OpenOCD NAND Flash controller support.
26 * Many thanks to Ben Dooks for writing s3c24xx driver.
30 driver tested with STMicro NAND512W3A @imx31
31 tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
32 get_next_halfword_from_sram_buffer() not tested
40 #include <target/target.h>
42 static const char target_not_halted_err_msg
[] =
43 "target must be halted to use mx3 NAND flash controller";
44 static const char data_block_size_err_msg
[] =
45 "minimal granularity is one half-word, %" PRId32
" is incorrect";
46 static const char sram_buffer_bounds_err_msg
[] =
47 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32
")";
48 static const char get_status_register_err_msg
[] = "can't get NAND status";
49 static uint32_t in_sram_address
;
50 static unsigned char sign_of_sequental_byte_read
;
52 static int test_iomux_settings (struct target
* target
, uint32_t value
,
53 uint32_t mask
, const char *text
);
54 static int initialize_nf_controller (struct nand_device
*nand
);
55 static int get_next_byte_from_sram_buffer (struct target
* target
, uint8_t * value
);
56 static int get_next_halfword_from_sram_buffer (struct target
* target
,
58 static int poll_for_complete_op (struct target
* target
, const char *text
);
59 static int validate_target_state (struct nand_device
*nand
);
60 static int do_data_output (struct nand_device
*nand
);
62 static int imx31_command (struct nand_device
*nand
, uint8_t command
);
63 static int imx31_address (struct nand_device
*nand
, uint8_t address
);
65 NAND_DEVICE_COMMAND_HANDLER(imx31_nand_device_command
)
67 struct mx3_nf_controller
*mx3_nf_info
;
68 mx3_nf_info
= malloc (sizeof (struct mx3_nf_controller
));
69 if (mx3_nf_info
== NULL
)
71 LOG_ERROR ("no memory for nand controller");
75 nand
->controller_priv
= mx3_nf_info
;
79 LOG_ERROR ("use \"nand device imx31 target noecc|hwecc\"");
83 * check hwecc requirements
87 hwecc_needed
= strcmp (CMD_ARGV
[2], "hwecc");
88 if (hwecc_needed
== 0)
90 mx3_nf_info
->flags
.hw_ecc_enabled
= 1;
94 mx3_nf_info
->flags
.hw_ecc_enabled
= 0;
98 mx3_nf_info
->optype
= MX3_NF_DATAOUT_PAGE
;
99 mx3_nf_info
->fin
= MX3_NF_FIN_NONE
;
100 mx3_nf_info
->flags
.target_little_endian
=
101 (nand
->target
->endianness
== TARGET_LITTLE_ENDIAN
);
103 * testing host endianness
107 if (*(char *) &x
== 1)
109 mx3_nf_info
->flags
.host_little_endian
= 1;
113 mx3_nf_info
->flags
.host_little_endian
= 0;
119 static int imx31_init (struct nand_device
*nand
)
121 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
122 struct target
*target
= nand
->target
;
126 * validate target state
128 int validate_target_result
;
129 validate_target_result
= validate_target_state(nand
);
130 if (validate_target_result
!= ERROR_OK
)
132 return validate_target_result
;
137 uint16_t buffsize_register_content
;
138 target_read_u16 (target
, MX3_NF_BUFSIZ
, &buffsize_register_content
);
139 mx3_nf_info
->flags
.one_kb_sram
= !(buffsize_register_content
& 0x000f);
143 uint32_t pcsr_register_content
;
144 target_read_u32 (target
, MX3_PCSR
, &pcsr_register_content
);
145 if (!nand
->bus_width
)
148 (pcsr_register_content
& 0x80000000) ? 16 : 8;
152 pcsr_register_content
|=
153 ((nand
->bus_width
== 16) ? 0x80000000 : 0x00000000);
154 target_write_u32 (target
, MX3_PCSR
, pcsr_register_content
);
157 if (!nand
->page_size
)
160 (pcsr_register_content
& 0x40000000) ? 2048 : 512;
164 pcsr_register_content
|=
165 ((nand
->page_size
== 2048) ? 0x40000000 : 0x00000000);
166 target_write_u32 (target
, MX3_PCSR
, pcsr_register_content
);
168 if (mx3_nf_info
->flags
.one_kb_sram
&& (nand
->page_size
== 2048))
171 ("NAND controller have only 1 kb SRAM, so pagesize 2048 is incompatible with it");
176 uint32_t cgr_register_content
;
177 target_read_u32 (target
, MX3_CCM_CGR2
, &cgr_register_content
);
178 if (!(cgr_register_content
& 0x00000300))
180 LOG_ERROR ("clock gating to EMI disabled");
186 uint32_t gpr_register_content
;
187 target_read_u32 (target
, MX3_GPR
, &gpr_register_content
);
188 if (gpr_register_content
& 0x00000060)
190 LOG_ERROR ("pins mode overrided by GPR");
197 * testing IOMUX settings; must be in "functional-mode output and
198 * functional-mode input" mode
201 test_iomux
= ERROR_OK
;
203 test_iomux_settings (target
, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
205 test_iomux_settings (target
, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
207 test_iomux_settings (target
, 0x43fac0c8, 0x0000007f, "d7");
208 if (nand
->bus_width
== 16)
211 test_iomux_settings (target
, 0x43fac0c8, 0x7f7f7f00,
214 test_iomux_settings (target
, 0x43fac0cc, 0x7f7f7f7f,
217 test_iomux_settings (target
, 0x43fac0d0, 0x0000007f, "d15");
220 test_iomux_settings (target
, 0x43fac0d0, 0x7f7f7f00,
223 test_iomux_settings (target
, 0x43fac0d4, 0x7f7f7f7f,
224 "nfwe,nfre,nfale,nfcle");
225 if (test_iomux
!= ERROR_OK
)
231 initialize_nf_controller (nand
);
235 uint16_t nand_status_content
;
237 retval
|= imx31_command (nand
, NAND_CMD_STATUS
);
238 retval
|= imx31_address (nand
, 0x00);
239 retval
|= do_data_output (nand
);
240 if (retval
!= ERROR_OK
)
242 LOG_ERROR (get_status_register_err_msg
);
245 target_read_u16 (target
, MX3_NF_MAIN_BUFFER0
, &nand_status_content
);
246 if (!(nand_status_content
& 0x0080))
249 * is host-big-endian correctly ??
251 LOG_INFO ("NAND read-only");
252 mx3_nf_info
->flags
.nand_readonly
= 1;
256 mx3_nf_info
->flags
.nand_readonly
= 0;
262 static int imx31_read_data (struct nand_device
*nand
, void *data
)
264 struct target
*target
= nand
->target
;
267 * validate target state
269 int validate_target_result
;
270 validate_target_result
= validate_target_state (nand
);
271 if (validate_target_result
!= ERROR_OK
)
273 return validate_target_result
;
279 * get data from nand chip
281 int try_data_output_from_nand_chip
;
282 try_data_output_from_nand_chip
= do_data_output (nand
);
283 if (try_data_output_from_nand_chip
!= ERROR_OK
)
285 return try_data_output_from_nand_chip
;
289 if (nand
->bus_width
== 16)
291 get_next_halfword_from_sram_buffer (target
, data
);
295 get_next_byte_from_sram_buffer (target
, data
);
301 static int imx31_write_data (struct nand_device
*nand
, uint16_t data
)
303 LOG_ERROR ("write_data() not implemented");
304 return ERROR_NAND_OPERATION_FAILED
;
307 static int imx31_reset (struct nand_device
*nand
)
310 * validate target state
312 int validate_target_result
;
313 validate_target_result
= validate_target_state (nand
);
314 if (validate_target_result
!= ERROR_OK
)
316 return validate_target_result
;
318 initialize_nf_controller (nand
);
322 static int imx31_command (struct nand_device
*nand
, uint8_t command
)
324 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
325 struct target
*target
= nand
->target
;
328 * validate target state
330 int validate_target_result
;
331 validate_target_result
= validate_target_state (nand
);
332 if (validate_target_result
!= ERROR_OK
)
334 return validate_target_result
;
340 case NAND_CMD_READOOB
:
341 command
= NAND_CMD_READ0
;
342 in_sram_address
= MX3_NF_SPARE_BUFFER0
; /* set read point for
344 * read_block_data() to
349 command
= NAND_CMD_READ0
;
351 * offset == one half of page size
354 MX3_NF_MAIN_BUFFER0
+ (nand
->page_size
>> 1);
356 in_sram_address
= MX3_NF_MAIN_BUFFER0
;
359 target_write_u16 (target
, MX3_NF_FCMD
, command
);
361 * start command input operation (set MX3_NF_BIT_OP_DONE==0)
363 target_write_u16 (target
, MX3_NF_CFG2
, MX3_NF_BIT_OP_FCI
);
366 poll_result
= poll_for_complete_op (target
, "command");
367 if (poll_result
!= ERROR_OK
)
373 * reset cursor to begin of the buffer
375 sign_of_sequental_byte_read
= 0;
378 case NAND_CMD_READID
:
379 mx3_nf_info
->optype
= MX3_NF_DATAOUT_NANDID
;
380 mx3_nf_info
->fin
= MX3_NF_FIN_DATAOUT
;
382 case NAND_CMD_STATUS
:
383 mx3_nf_info
->optype
= MX3_NF_DATAOUT_NANDSTATUS
;
384 mx3_nf_info
->fin
= MX3_NF_FIN_DATAOUT
;
387 mx3_nf_info
->fin
= MX3_NF_FIN_DATAOUT
;
388 mx3_nf_info
->optype
= MX3_NF_DATAOUT_PAGE
;
391 mx3_nf_info
->optype
= MX3_NF_DATAOUT_PAGE
;
396 static int imx31_address (struct nand_device
*nand
, uint8_t address
)
398 struct target
*target
= nand
->target
;
401 * validate target state
403 int validate_target_result
;
404 validate_target_result
= validate_target_state (nand
);
405 if (validate_target_result
!= ERROR_OK
)
407 return validate_target_result
;
411 target_write_u16 (target
, MX3_NF_FADDR
, address
);
413 * start address input operation (set MX3_NF_BIT_OP_DONE==0)
415 target_write_u16 (target
, MX3_NF_CFG2
, MX3_NF_BIT_OP_FAI
);
418 poll_result
= poll_for_complete_op (target
, "address");
419 if (poll_result
!= ERROR_OK
)
427 static int imx31_nand_ready (struct nand_device
*nand
, int tout
)
429 uint16_t poll_complete_status
;
430 struct target
*target
= nand
->target
;
434 * validate target state
436 int validate_target_result
;
437 validate_target_result
= validate_target_state (nand
);
438 if (validate_target_result
!= ERROR_OK
)
440 return validate_target_result
;
446 target_read_u16 (target
, MX3_NF_CFG2
, &poll_complete_status
);
447 if (poll_complete_status
& MX3_NF_BIT_OP_DONE
)
457 static int imx31_write_page (struct nand_device
*nand
, uint32_t page
,
458 uint8_t * data
, uint32_t data_size
, uint8_t * oob
,
461 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
462 struct target
*target
= nand
->target
;
466 LOG_ERROR (data_block_size_err_msg
, data_size
);
467 return ERROR_NAND_OPERATION_FAILED
;
471 LOG_ERROR (data_block_size_err_msg
, oob_size
);
472 return ERROR_NAND_OPERATION_FAILED
;
476 LOG_ERROR ("nothing to program");
477 return ERROR_NAND_OPERATION_FAILED
;
481 * validate target state
484 retval
= validate_target_state (nand
);
485 if (retval
!= ERROR_OK
)
491 int retval
= ERROR_OK
;
492 retval
|= imx31_command(nand
, NAND_CMD_SEQIN
);
493 retval
|= imx31_address(nand
, 0x00);
494 retval
|= imx31_address(nand
, page
& 0xff);
495 retval
|= imx31_address(nand
, (page
>> 8) & 0xff);
496 if (nand
->address_cycles
>= 4)
498 retval
|= imx31_address (nand
, (page
>> 16) & 0xff);
499 if (nand
->address_cycles
>= 5)
501 retval
|= imx31_address (nand
, (page
>> 24) & 0xff);
504 target_write_buffer (target
, MX3_NF_MAIN_BUFFER0
, data_size
, data
);
507 if (mx3_nf_info
->flags
.hw_ecc_enabled
)
510 * part of spare block will be overrided by hardware
514 ("part of spare block will be overrided by hardware ECC generator");
516 target_write_buffer (target
, MX3_NF_SPARE_BUFFER0
, oob_size
,
520 * start data input operation (set MX3_NF_BIT_OP_DONE==0)
522 target_write_u16 (target
, MX3_NF_CFG2
, MX3_NF_BIT_OP_FDI
);
525 poll_result
= poll_for_complete_op (target
, "data input");
526 if (poll_result
!= ERROR_OK
)
531 retval
|= imx31_command (nand
, NAND_CMD_PAGEPROG
);
532 if (retval
!= ERROR_OK
)
538 * check status register
541 uint16_t nand_status_content
;
543 retval
|= imx31_command(nand
, NAND_CMD_STATUS
);
544 retval
|= imx31_address(nand
, 0x00);
545 retval
|= do_data_output(nand
);
546 if (retval
!= ERROR_OK
)
548 LOG_ERROR (get_status_register_err_msg
);
551 target_read_u16 (target
, MX3_NF_MAIN_BUFFER0
, &nand_status_content
);
552 if (nand_status_content
& 0x0001)
555 * is host-big-endian correctly ??
557 return ERROR_NAND_OPERATION_FAILED
;
564 static int imx31_read_page (struct nand_device
*nand
, uint32_t page
,
565 uint8_t * data
, uint32_t data_size
, uint8_t * oob
,
568 struct target
*target
= nand
->target
;
572 LOG_ERROR (data_block_size_err_msg
, data_size
);
573 return ERROR_NAND_OPERATION_FAILED
;
577 LOG_ERROR (data_block_size_err_msg
, oob_size
);
578 return ERROR_NAND_OPERATION_FAILED
;
583 * validate target state
586 retval
= validate_target_state(nand
);
587 if (retval
!= ERROR_OK
)
593 int retval
= ERROR_OK
;
594 retval
|= imx31_command(nand
, NAND_CMD_READ0
);
595 retval
|= imx31_address(nand
, 0x00);
596 retval
|= imx31_address(nand
, page
& 0xff);
597 retval
|= imx31_address(nand
, (page
>> 8) & 0xff);
598 if (nand
->address_cycles
>= 4)
600 retval
|= imx31_address(nand
, (page
>> 16) & 0xff);
601 if (nand
->address_cycles
>= 5)
603 retval
|= imx31_address(nand
, (page
>> 24) & 0xff);
604 retval
|= imx31_command(nand
, NAND_CMD_READSTART
);
607 retval
|= do_data_output (nand
);
608 if (retval
!= ERROR_OK
)
615 target_read_buffer (target
, MX3_NF_MAIN_BUFFER0
, data_size
,
620 target_read_buffer (target
, MX3_NF_SPARE_BUFFER0
, oob_size
,
627 static int test_iomux_settings (struct target
* target
, uint32_t address
,
628 uint32_t mask
, const char *text
)
630 uint32_t register_content
;
631 target_read_u32 (target
, address
, ®ister_content
);
632 if ((register_content
& mask
) != (0x12121212 & mask
))
634 LOG_ERROR ("IOMUX for {%s} is bad", text
);
640 static int initialize_nf_controller (struct nand_device
*nand
)
642 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
643 struct target
*target
= nand
->target
;
645 * resets NAND flash controller in zero time ? I dont know.
647 target_write_u16 (target
, MX3_NF_CFG1
, MX3_NF_BIT_RESET_EN
);
650 work_mode
= MX3_NF_BIT_INT_DIS
; /* disable interrupt */
651 if (target
->endianness
== TARGET_BIG_ENDIAN
)
653 work_mode
|= MX3_NF_BIT_BE_EN
;
655 if (mx3_nf_info
->flags
.hw_ecc_enabled
)
657 work_mode
|= MX3_NF_BIT_ECC_EN
;
659 target_write_u16 (target
, MX3_NF_CFG1
, work_mode
);
662 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
664 target_write_u16 (target
, MX3_NF_BUFCFG
, 2);
667 target_read_u16 (target
, MX3_NF_FWP
, &temp
);
668 if ((temp
& 0x0007) == 1)
670 LOG_ERROR ("NAND flash is tight-locked, reset needed");
676 * unlock NAND flash for write
678 target_write_u16 (target
, MX3_NF_FWP
, 4);
679 target_write_u16 (target
, MX3_NF_LOCKSTART
, 0x0000);
680 target_write_u16 (target
, MX3_NF_LOCKEND
, 0xFFFF);
682 * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
684 target_write_u16 (target
, MX3_NF_BUFADDR
, 0x0000);
686 * address of SRAM buffer
688 in_sram_address
= MX3_NF_MAIN_BUFFER0
;
689 sign_of_sequental_byte_read
= 0;
693 static int get_next_byte_from_sram_buffer (struct target
* target
, uint8_t * value
)
695 static uint8_t even_byte
= 0;
699 if (sign_of_sequental_byte_read
== 0)
703 if (in_sram_address
> MX3_NF_LAST_BUFFER_ADDR
)
705 LOG_ERROR (sram_buffer_bounds_err_msg
, in_sram_address
);
707 sign_of_sequental_byte_read
= 0;
709 return ERROR_NAND_OPERATION_FAILED
;
714 target_read_u16 (target
, in_sram_address
, &temp
);
719 in_sram_address
+= 2;
723 *value
= temp
& 0xff;
727 sign_of_sequental_byte_read
= 1;
731 static int get_next_halfword_from_sram_buffer (struct target
* target
,
734 if (in_sram_address
> MX3_NF_LAST_BUFFER_ADDR
)
736 LOG_ERROR (sram_buffer_bounds_err_msg
, in_sram_address
);
738 return ERROR_NAND_OPERATION_FAILED
;
742 target_read_u16 (target
, in_sram_address
, value
);
743 in_sram_address
+= 2;
748 static int poll_for_complete_op (struct target
* target
, const char *text
)
750 uint16_t poll_complete_status
;
751 for (int poll_cycle_count
= 0; poll_cycle_count
< 100; poll_cycle_count
++)
754 target_read_u16 (target
, MX3_NF_CFG2
, &poll_complete_status
);
755 if (poll_complete_status
& MX3_NF_BIT_OP_DONE
)
760 if (!(poll_complete_status
& MX3_NF_BIT_OP_DONE
))
762 LOG_ERROR ("%s sending timeout", text
);
763 return ERROR_NAND_OPERATION_FAILED
;
768 static int validate_target_state (struct nand_device
*nand
)
770 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
771 struct target
*target
= nand
->target
;
773 if (target
->state
!= TARGET_HALTED
)
775 LOG_ERROR (target_not_halted_err_msg
);
776 return ERROR_NAND_OPERATION_FAILED
;
779 if (mx3_nf_info
->flags
.target_little_endian
!=
780 (target
->endianness
== TARGET_LITTLE_ENDIAN
))
783 * endianness changed after NAND controller probed
785 return ERROR_NAND_OPERATION_FAILED
;
790 static int do_data_output (struct nand_device
*nand
)
792 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
793 struct target
*target
= nand
->target
;
794 switch (mx3_nf_info
->fin
)
796 case MX3_NF_FIN_DATAOUT
:
798 * start data output operation (set MX3_NF_BIT_OP_DONE==0)
800 target_write_u16 (target
, MX3_NF_CFG2
,
801 MX3_NF_BIT_DATAOUT_TYPE (mx3_nf_info
->
805 poll_result
= poll_for_complete_op (target
, "data output");
806 if (poll_result
!= ERROR_OK
)
811 mx3_nf_info
->fin
= MX3_NF_FIN_NONE
;
815 if ((mx3_nf_info
->optype
== MX3_NF_DATAOUT_PAGE
)
816 && mx3_nf_info
->flags
.hw_ecc_enabled
)
819 target_read_u16 (target
, MX3_NF_ECCSTATUS
, &ecc_status
);
820 switch (ecc_status
& 0x000c)
824 ("main area readed with 1 (correctable) error");
828 ("main area readed with more than 1 (incorrectable) error");
829 return ERROR_NAND_OPERATION_FAILED
;
832 switch (ecc_status
& 0x0003)
836 ("spare area readed with 1 (correctable) error");
840 ("main area readed with more than 1 (incorrectable) error");
841 return ERROR_NAND_OPERATION_FAILED
;
846 case MX3_NF_FIN_NONE
:
852 struct nand_flash_controller imx31_nand_flash_controller
= {
854 .nand_device_command
= &imx31_nand_device_command
,
856 .reset
= &imx31_reset
,
857 .command
= &imx31_command
,
858 .address
= &imx31_address
,
859 .write_data
= &imx31_write_data
,
860 .read_data
= &imx31_read_data
,
861 .write_page
= &imx31_write_page
,
862 .read_page
= &imx31_read_page
,
863 .nand_ready
= &imx31_nand_ready
,
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then change URL to read
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to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)