2 /***************************************************************************
3 * Copyright (C) 2009 by Alexei Babich *
4 * Rezonans plc., Chelyabinsk, Russia *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
24 * Freescale iMX3* OpenOCD NAND Flash controller support.
26 * Many thanks to Ben Dooks for writing s3c24xx driver.
30 driver tested with STMicro NAND512W3A @imx31
31 tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
32 get_next_halfword_from_sram_buffer() not tested
40 #include <target/target.h>
42 static const char target_not_halted_err_msg
[] =
43 "target must be halted to use mx3 NAND flash controller";
44 static const char data_block_size_err_msg
[] =
45 "minimal granularity is one half-word, %" PRId32
" is incorrect";
46 static const char sram_buffer_bounds_err_msg
[] =
47 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32
")";
48 static const char get_status_register_err_msg
[] = "can't get NAND status";
49 static uint32_t in_sram_address
;
50 static unsigned char sign_of_sequental_byte_read
;
52 static int test_iomux_settings (struct target
* target
, uint32_t value
,
53 uint32_t mask
, const char *text
);
54 static int initialize_nf_controller (struct nand_device
*nand
);
55 static int get_next_byte_from_sram_buffer (struct target
* target
, uint8_t * value
);
56 static int get_next_halfword_from_sram_buffer (struct target
* target
,
58 static int poll_for_complete_op (struct target
* target
, const char *text
);
59 static int validate_target_state (struct nand_device
*nand
);
60 static int do_data_output (struct nand_device
*nand
);
62 static int imx31_command (struct nand_device
*nand
, uint8_t command
);
63 static int imx31_address (struct nand_device
*nand
, uint8_t address
);
65 NAND_DEVICE_COMMAND_HANDLER(imx31_nand_device_command
)
67 struct mx3_nf_controller
*mx3_nf_info
;
68 mx3_nf_info
= malloc (sizeof (struct mx3_nf_controller
));
69 if (mx3_nf_info
== NULL
)
71 LOG_ERROR ("no memory for nand controller");
75 nand
->controller_priv
= mx3_nf_info
;
79 return ERROR_COMMAND_SYNTAX_ERROR
;
82 * check hwecc requirements
86 hwecc_needed
= strcmp (CMD_ARGV
[2], "hwecc");
87 if (hwecc_needed
== 0)
89 mx3_nf_info
->flags
.hw_ecc_enabled
= 1;
93 mx3_nf_info
->flags
.hw_ecc_enabled
= 0;
97 mx3_nf_info
->optype
= MX3_NF_DATAOUT_PAGE
;
98 mx3_nf_info
->fin
= MX3_NF_FIN_NONE
;
99 mx3_nf_info
->flags
.target_little_endian
=
100 (nand
->target
->endianness
== TARGET_LITTLE_ENDIAN
);
102 * testing host endianness
106 if (*(char *) &x
== 1)
108 mx3_nf_info
->flags
.host_little_endian
= 1;
112 mx3_nf_info
->flags
.host_little_endian
= 0;
118 static int imx31_init (struct nand_device
*nand
)
120 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
121 struct target
*target
= nand
->target
;
125 * validate target state
127 int validate_target_result
;
128 validate_target_result
= validate_target_state(nand
);
129 if (validate_target_result
!= ERROR_OK
)
131 return validate_target_result
;
136 uint16_t buffsize_register_content
;
137 target_read_u16 (target
, MX3_NF_BUFSIZ
, &buffsize_register_content
);
138 mx3_nf_info
->flags
.one_kb_sram
= !(buffsize_register_content
& 0x000f);
142 uint32_t pcsr_register_content
;
143 target_read_u32 (target
, MX3_PCSR
, &pcsr_register_content
);
144 if (!nand
->bus_width
)
147 (pcsr_register_content
& 0x80000000) ? 16 : 8;
151 pcsr_register_content
|=
152 ((nand
->bus_width
== 16) ? 0x80000000 : 0x00000000);
153 target_write_u32 (target
, MX3_PCSR
, pcsr_register_content
);
156 if (!nand
->page_size
)
159 (pcsr_register_content
& 0x40000000) ? 2048 : 512;
163 pcsr_register_content
|=
164 ((nand
->page_size
== 2048) ? 0x40000000 : 0x00000000);
165 target_write_u32 (target
, MX3_PCSR
, pcsr_register_content
);
167 if (mx3_nf_info
->flags
.one_kb_sram
&& (nand
->page_size
== 2048))
170 ("NAND controller have only 1 kb SRAM, so pagesize 2048 is incompatible with it");
175 uint32_t cgr_register_content
;
176 target_read_u32 (target
, MX3_CCM_CGR2
, &cgr_register_content
);
177 if (!(cgr_register_content
& 0x00000300))
179 LOG_ERROR ("clock gating to EMI disabled");
185 uint32_t gpr_register_content
;
186 target_read_u32 (target
, MX3_GPR
, &gpr_register_content
);
187 if (gpr_register_content
& 0x00000060)
189 LOG_ERROR ("pins mode overrided by GPR");
196 * testing IOMUX settings; must be in "functional-mode output and
197 * functional-mode input" mode
200 test_iomux
= ERROR_OK
;
202 test_iomux_settings (target
, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
204 test_iomux_settings (target
, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
206 test_iomux_settings (target
, 0x43fac0c8, 0x0000007f, "d7");
207 if (nand
->bus_width
== 16)
210 test_iomux_settings (target
, 0x43fac0c8, 0x7f7f7f00,
213 test_iomux_settings (target
, 0x43fac0cc, 0x7f7f7f7f,
216 test_iomux_settings (target
, 0x43fac0d0, 0x0000007f, "d15");
219 test_iomux_settings (target
, 0x43fac0d0, 0x7f7f7f00,
222 test_iomux_settings (target
, 0x43fac0d4, 0x7f7f7f7f,
223 "nfwe,nfre,nfale,nfcle");
224 if (test_iomux
!= ERROR_OK
)
230 initialize_nf_controller (nand
);
234 uint16_t nand_status_content
;
236 retval
|= imx31_command (nand
, NAND_CMD_STATUS
);
237 retval
|= imx31_address (nand
, 0x00);
238 retval
|= do_data_output (nand
);
239 if (retval
!= ERROR_OK
)
241 LOG_ERROR (get_status_register_err_msg
);
244 target_read_u16 (target
, MX3_NF_MAIN_BUFFER0
, &nand_status_content
);
245 if (!(nand_status_content
& 0x0080))
248 * is host-big-endian correctly ??
250 LOG_INFO ("NAND read-only");
251 mx3_nf_info
->flags
.nand_readonly
= 1;
255 mx3_nf_info
->flags
.nand_readonly
= 0;
261 static int imx31_read_data (struct nand_device
*nand
, void *data
)
263 struct target
*target
= nand
->target
;
266 * validate target state
268 int validate_target_result
;
269 validate_target_result
= validate_target_state (nand
);
270 if (validate_target_result
!= ERROR_OK
)
272 return validate_target_result
;
278 * get data from nand chip
280 int try_data_output_from_nand_chip
;
281 try_data_output_from_nand_chip
= do_data_output (nand
);
282 if (try_data_output_from_nand_chip
!= ERROR_OK
)
284 return try_data_output_from_nand_chip
;
288 if (nand
->bus_width
== 16)
290 get_next_halfword_from_sram_buffer (target
, data
);
294 get_next_byte_from_sram_buffer (target
, data
);
300 static int imx31_write_data (struct nand_device
*nand
, uint16_t data
)
302 LOG_ERROR ("write_data() not implemented");
303 return ERROR_NAND_OPERATION_FAILED
;
306 static int imx31_reset (struct nand_device
*nand
)
309 * validate target state
311 int validate_target_result
;
312 validate_target_result
= validate_target_state (nand
);
313 if (validate_target_result
!= ERROR_OK
)
315 return validate_target_result
;
317 initialize_nf_controller (nand
);
321 static int imx31_command (struct nand_device
*nand
, uint8_t command
)
323 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
324 struct target
*target
= nand
->target
;
327 * validate target state
329 int validate_target_result
;
330 validate_target_result
= validate_target_state (nand
);
331 if (validate_target_result
!= ERROR_OK
)
333 return validate_target_result
;
339 case NAND_CMD_READOOB
:
340 command
= NAND_CMD_READ0
;
341 in_sram_address
= MX3_NF_SPARE_BUFFER0
; /* set read point for
343 * read_block_data() to
348 command
= NAND_CMD_READ0
;
350 * offset == one half of page size
353 MX3_NF_MAIN_BUFFER0
+ (nand
->page_size
>> 1);
355 in_sram_address
= MX3_NF_MAIN_BUFFER0
;
358 target_write_u16 (target
, MX3_NF_FCMD
, command
);
360 * start command input operation (set MX3_NF_BIT_OP_DONE==0)
362 target_write_u16 (target
, MX3_NF_CFG2
, MX3_NF_BIT_OP_FCI
);
365 poll_result
= poll_for_complete_op (target
, "command");
366 if (poll_result
!= ERROR_OK
)
372 * reset cursor to begin of the buffer
374 sign_of_sequental_byte_read
= 0;
377 case NAND_CMD_READID
:
378 mx3_nf_info
->optype
= MX3_NF_DATAOUT_NANDID
;
379 mx3_nf_info
->fin
= MX3_NF_FIN_DATAOUT
;
381 case NAND_CMD_STATUS
:
382 mx3_nf_info
->optype
= MX3_NF_DATAOUT_NANDSTATUS
;
383 mx3_nf_info
->fin
= MX3_NF_FIN_DATAOUT
;
386 mx3_nf_info
->fin
= MX3_NF_FIN_DATAOUT
;
387 mx3_nf_info
->optype
= MX3_NF_DATAOUT_PAGE
;
390 mx3_nf_info
->optype
= MX3_NF_DATAOUT_PAGE
;
395 static int imx31_address (struct nand_device
*nand
, uint8_t address
)
397 struct target
*target
= nand
->target
;
400 * validate target state
402 int validate_target_result
;
403 validate_target_result
= validate_target_state (nand
);
404 if (validate_target_result
!= ERROR_OK
)
406 return validate_target_result
;
410 target_write_u16 (target
, MX3_NF_FADDR
, address
);
412 * start address input operation (set MX3_NF_BIT_OP_DONE==0)
414 target_write_u16 (target
, MX3_NF_CFG2
, MX3_NF_BIT_OP_FAI
);
417 poll_result
= poll_for_complete_op (target
, "address");
418 if (poll_result
!= ERROR_OK
)
426 static int imx31_nand_ready (struct nand_device
*nand
, int tout
)
428 uint16_t poll_complete_status
;
429 struct target
*target
= nand
->target
;
433 * validate target state
435 int validate_target_result
;
436 validate_target_result
= validate_target_state (nand
);
437 if (validate_target_result
!= ERROR_OK
)
439 return validate_target_result
;
445 target_read_u16 (target
, MX3_NF_CFG2
, &poll_complete_status
);
446 if (poll_complete_status
& MX3_NF_BIT_OP_DONE
)
456 static int imx31_write_page (struct nand_device
*nand
, uint32_t page
,
457 uint8_t * data
, uint32_t data_size
, uint8_t * oob
,
460 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
461 struct target
*target
= nand
->target
;
465 LOG_ERROR (data_block_size_err_msg
, data_size
);
466 return ERROR_NAND_OPERATION_FAILED
;
470 LOG_ERROR (data_block_size_err_msg
, oob_size
);
471 return ERROR_NAND_OPERATION_FAILED
;
475 LOG_ERROR ("nothing to program");
476 return ERROR_NAND_OPERATION_FAILED
;
480 * validate target state
483 retval
= validate_target_state (nand
);
484 if (retval
!= ERROR_OK
)
490 int retval
= ERROR_OK
;
491 retval
|= imx31_command(nand
, NAND_CMD_SEQIN
);
492 retval
|= imx31_address(nand
, 0x00);
493 retval
|= imx31_address(nand
, page
& 0xff);
494 retval
|= imx31_address(nand
, (page
>> 8) & 0xff);
495 if (nand
->address_cycles
>= 4)
497 retval
|= imx31_address (nand
, (page
>> 16) & 0xff);
498 if (nand
->address_cycles
>= 5)
500 retval
|= imx31_address (nand
, (page
>> 24) & 0xff);
503 target_write_buffer (target
, MX3_NF_MAIN_BUFFER0
, data_size
, data
);
506 if (mx3_nf_info
->flags
.hw_ecc_enabled
)
509 * part of spare block will be overrided by hardware
513 ("part of spare block will be overrided by hardware ECC generator");
515 target_write_buffer (target
, MX3_NF_SPARE_BUFFER0
, oob_size
,
519 * start data input operation (set MX3_NF_BIT_OP_DONE==0)
521 target_write_u16 (target
, MX3_NF_CFG2
, MX3_NF_BIT_OP_FDI
);
524 poll_result
= poll_for_complete_op (target
, "data input");
525 if (poll_result
!= ERROR_OK
)
530 retval
|= imx31_command (nand
, NAND_CMD_PAGEPROG
);
531 if (retval
!= ERROR_OK
)
537 * check status register
540 uint16_t nand_status_content
;
542 retval
|= imx31_command(nand
, NAND_CMD_STATUS
);
543 retval
|= imx31_address(nand
, 0x00);
544 retval
|= do_data_output(nand
);
545 if (retval
!= ERROR_OK
)
547 LOG_ERROR (get_status_register_err_msg
);
550 target_read_u16 (target
, MX3_NF_MAIN_BUFFER0
, &nand_status_content
);
551 if (nand_status_content
& 0x0001)
554 * is host-big-endian correctly ??
556 return ERROR_NAND_OPERATION_FAILED
;
563 static int imx31_read_page (struct nand_device
*nand
, uint32_t page
,
564 uint8_t * data
, uint32_t data_size
, uint8_t * oob
,
567 struct target
*target
= nand
->target
;
571 LOG_ERROR (data_block_size_err_msg
, data_size
);
572 return ERROR_NAND_OPERATION_FAILED
;
576 LOG_ERROR (data_block_size_err_msg
, oob_size
);
577 return ERROR_NAND_OPERATION_FAILED
;
582 * validate target state
585 retval
= validate_target_state(nand
);
586 if (retval
!= ERROR_OK
)
592 int retval
= ERROR_OK
;
593 retval
|= imx31_command(nand
, NAND_CMD_READ0
);
594 retval
|= imx31_address(nand
, 0x00);
595 retval
|= imx31_address(nand
, page
& 0xff);
596 retval
|= imx31_address(nand
, (page
>> 8) & 0xff);
597 if (nand
->address_cycles
>= 4)
599 retval
|= imx31_address(nand
, (page
>> 16) & 0xff);
600 if (nand
->address_cycles
>= 5)
602 retval
|= imx31_address(nand
, (page
>> 24) & 0xff);
603 retval
|= imx31_command(nand
, NAND_CMD_READSTART
);
606 retval
|= do_data_output (nand
);
607 if (retval
!= ERROR_OK
)
614 target_read_buffer (target
, MX3_NF_MAIN_BUFFER0
, data_size
,
619 target_read_buffer (target
, MX3_NF_SPARE_BUFFER0
, oob_size
,
626 static int test_iomux_settings (struct target
* target
, uint32_t address
,
627 uint32_t mask
, const char *text
)
629 uint32_t register_content
;
630 target_read_u32 (target
, address
, ®ister_content
);
631 if ((register_content
& mask
) != (0x12121212 & mask
))
633 LOG_ERROR ("IOMUX for {%s} is bad", text
);
639 static int initialize_nf_controller (struct nand_device
*nand
)
641 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
642 struct target
*target
= nand
->target
;
644 * resets NAND flash controller in zero time ? I dont know.
646 target_write_u16 (target
, MX3_NF_CFG1
, MX3_NF_BIT_RESET_EN
);
649 work_mode
= MX3_NF_BIT_INT_DIS
; /* disable interrupt */
650 if (target
->endianness
== TARGET_BIG_ENDIAN
)
652 work_mode
|= MX3_NF_BIT_BE_EN
;
654 if (mx3_nf_info
->flags
.hw_ecc_enabled
)
656 work_mode
|= MX3_NF_BIT_ECC_EN
;
658 target_write_u16 (target
, MX3_NF_CFG1
, work_mode
);
661 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
663 target_write_u16 (target
, MX3_NF_BUFCFG
, 2);
666 target_read_u16 (target
, MX3_NF_FWP
, &temp
);
667 if ((temp
& 0x0007) == 1)
669 LOG_ERROR ("NAND flash is tight-locked, reset needed");
675 * unlock NAND flash for write
677 target_write_u16 (target
, MX3_NF_FWP
, 4);
678 target_write_u16 (target
, MX3_NF_LOCKSTART
, 0x0000);
679 target_write_u16 (target
, MX3_NF_LOCKEND
, 0xFFFF);
681 * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
683 target_write_u16 (target
, MX3_NF_BUFADDR
, 0x0000);
685 * address of SRAM buffer
687 in_sram_address
= MX3_NF_MAIN_BUFFER0
;
688 sign_of_sequental_byte_read
= 0;
692 static int get_next_byte_from_sram_buffer (struct target
* target
, uint8_t * value
)
694 static uint8_t even_byte
= 0;
698 if (sign_of_sequental_byte_read
== 0)
702 if (in_sram_address
> MX3_NF_LAST_BUFFER_ADDR
)
704 LOG_ERROR (sram_buffer_bounds_err_msg
, in_sram_address
);
706 sign_of_sequental_byte_read
= 0;
708 return ERROR_NAND_OPERATION_FAILED
;
713 target_read_u16 (target
, in_sram_address
, &temp
);
718 in_sram_address
+= 2;
722 *value
= temp
& 0xff;
726 sign_of_sequental_byte_read
= 1;
730 static int get_next_halfword_from_sram_buffer (struct target
* target
,
733 if (in_sram_address
> MX3_NF_LAST_BUFFER_ADDR
)
735 LOG_ERROR (sram_buffer_bounds_err_msg
, in_sram_address
);
737 return ERROR_NAND_OPERATION_FAILED
;
741 target_read_u16 (target
, in_sram_address
, value
);
742 in_sram_address
+= 2;
747 static int poll_for_complete_op (struct target
* target
, const char *text
)
749 uint16_t poll_complete_status
;
750 for (int poll_cycle_count
= 0; poll_cycle_count
< 100; poll_cycle_count
++)
753 target_read_u16 (target
, MX3_NF_CFG2
, &poll_complete_status
);
754 if (poll_complete_status
& MX3_NF_BIT_OP_DONE
)
759 if (!(poll_complete_status
& MX3_NF_BIT_OP_DONE
))
761 LOG_ERROR ("%s sending timeout", text
);
762 return ERROR_NAND_OPERATION_FAILED
;
767 static int validate_target_state (struct nand_device
*nand
)
769 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
770 struct target
*target
= nand
->target
;
772 if (target
->state
!= TARGET_HALTED
)
774 LOG_ERROR (target_not_halted_err_msg
);
775 return ERROR_NAND_OPERATION_FAILED
;
778 if (mx3_nf_info
->flags
.target_little_endian
!=
779 (target
->endianness
== TARGET_LITTLE_ENDIAN
))
782 * endianness changed after NAND controller probed
784 return ERROR_NAND_OPERATION_FAILED
;
789 static int do_data_output (struct nand_device
*nand
)
791 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
792 struct target
*target
= nand
->target
;
793 switch (mx3_nf_info
->fin
)
795 case MX3_NF_FIN_DATAOUT
:
797 * start data output operation (set MX3_NF_BIT_OP_DONE==0)
799 target_write_u16 (target
, MX3_NF_CFG2
,
800 MX3_NF_BIT_DATAOUT_TYPE (mx3_nf_info
->
804 poll_result
= poll_for_complete_op (target
, "data output");
805 if (poll_result
!= ERROR_OK
)
810 mx3_nf_info
->fin
= MX3_NF_FIN_NONE
;
814 if ((mx3_nf_info
->optype
== MX3_NF_DATAOUT_PAGE
)
815 && mx3_nf_info
->flags
.hw_ecc_enabled
)
818 target_read_u16 (target
, MX3_NF_ECCSTATUS
, &ecc_status
);
819 switch (ecc_status
& 0x000c)
823 ("main area readed with 1 (correctable) error");
827 ("main area readed with more than 1 (incorrectable) error");
828 return ERROR_NAND_OPERATION_FAILED
;
831 switch (ecc_status
& 0x0003)
835 ("spare area readed with 1 (correctable) error");
839 ("main area readed with more than 1 (incorrectable) error");
840 return ERROR_NAND_OPERATION_FAILED
;
845 case MX3_NF_FIN_NONE
:
851 struct nand_flash_controller imx31_nand_flash_controller
= {
853 .usage
= "nand device imx31 target noecc|hwecc",
854 .nand_device_command
= &imx31_nand_device_command
,
856 .reset
= &imx31_reset
,
857 .command
= &imx31_command
,
858 .address
= &imx31_address
,
859 .write_data
= &imx31_write_data
,
860 .read_data
= &imx31_read_data
,
861 .write_page
= &imx31_write_page
,
862 .read_page
= &imx31_read_page
,
863 .nand_ready
= &imx31_nand_ready
,
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