2 /***************************************************************************
3 * Copyright (C) 2009 by Alexei Babich *
4 * Rezonans plc., Chelyabinsk, Russia *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
24 * Freescale iMX3* OpenOCD NAND Flash controller support.
26 * Many thanks to Ben Dooks for writing s3c24xx driver.
30 driver tested with STMicro NAND512W3A @imx31
31 tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
32 get_next_halfword_from_sram_buffer() not tested
40 #include <target/target.h>
42 static const char target_not_halted_err_msg
[] =
43 "target must be halted to use mx3 NAND flash controller";
44 static const char data_block_size_err_msg
[] =
45 "minimal granularity is one half-word, %" PRId32
" is incorrect";
46 static const char sram_buffer_bounds_err_msg
[] =
47 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32
")";
48 static const char get_status_register_err_msg
[] = "can't get NAND status";
49 static uint32_t in_sram_address
;
50 static unsigned char sign_of_sequental_byte_read
;
52 static int test_iomux_settings (struct target
* target
, uint32_t value
,
53 uint32_t mask
, const char *text
);
54 static int initialize_nf_controller (struct nand_device
*nand
);
55 static int get_next_byte_from_sram_buffer (struct target
* target
, uint8_t * value
);
56 static int get_next_halfword_from_sram_buffer (struct target
* target
,
58 static int poll_for_complete_op (struct target
* target
, const char *text
);
59 static int validate_target_state (struct nand_device
*nand
);
60 static int do_data_output (struct nand_device
*nand
);
62 static int imx31_command (struct nand_device
*nand
, uint8_t command
);
63 static int imx31_address (struct nand_device
*nand
, uint8_t address
);
65 NAND_DEVICE_COMMAND_HANDLER(imx31_nand_device_command
)
67 struct mx3_nf_controller
*mx3_nf_info
;
68 mx3_nf_info
= malloc (sizeof (struct mx3_nf_controller
));
69 if (mx3_nf_info
== NULL
)
71 LOG_ERROR ("no memory for nand controller");
75 nand
->controller_priv
= mx3_nf_info
;
77 mx3_nf_info
->target
= get_target (CMD_ARGV
[1]);
78 if (mx3_nf_info
->target
== NULL
)
80 LOG_ERROR ("target '%s' not defined", CMD_ARGV
[1]);
85 LOG_ERROR ("use \"nand device imx31 target noecc|hwecc\"");
89 * check hwecc requirements
93 hwecc_needed
= strcmp (CMD_ARGV
[2], "hwecc");
94 if (hwecc_needed
== 0)
96 mx3_nf_info
->flags
.hw_ecc_enabled
= 1;
100 mx3_nf_info
->flags
.hw_ecc_enabled
= 0;
104 mx3_nf_info
->optype
= MX3_NF_DATAOUT_PAGE
;
105 mx3_nf_info
->fin
= MX3_NF_FIN_NONE
;
106 mx3_nf_info
->flags
.target_little_endian
=
107 (mx3_nf_info
->target
->endianness
== TARGET_LITTLE_ENDIAN
);
109 * testing host endianess
113 if (*(char *) &x
== 1)
115 mx3_nf_info
->flags
.host_little_endian
= 1;
119 mx3_nf_info
->flags
.host_little_endian
= 0;
125 static int imx31_init (struct nand_device
*nand
)
127 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
128 struct target
*target
= mx3_nf_info
->target
;
132 * validate target state
134 int validate_target_result
;
135 validate_target_result
= validate_target_state(nand
);
136 if (validate_target_result
!= ERROR_OK
)
138 return validate_target_result
;
143 uint16_t buffsize_register_content
;
144 target_read_u16 (target
, MX3_NF_BUFSIZ
, &buffsize_register_content
);
145 mx3_nf_info
->flags
.one_kb_sram
= !(buffsize_register_content
& 0x000f);
149 uint32_t pcsr_register_content
;
150 target_read_u32 (target
, MX3_PCSR
, &pcsr_register_content
);
151 if (!nand
->bus_width
)
154 (pcsr_register_content
& 0x80000000) ? 16 : 8;
158 pcsr_register_content
|=
159 ((nand
->bus_width
== 16) ? 0x80000000 : 0x00000000);
160 target_write_u32 (target
, MX3_PCSR
, pcsr_register_content
);
163 if (!nand
->page_size
)
166 (pcsr_register_content
& 0x40000000) ? 2048 : 512;
170 pcsr_register_content
|=
171 ((nand
->page_size
== 2048) ? 0x40000000 : 0x00000000);
172 target_write_u32 (target
, MX3_PCSR
, pcsr_register_content
);
174 if (mx3_nf_info
->flags
.one_kb_sram
&& (nand
->page_size
== 2048))
177 ("NAND controller have only 1 kb SRAM, so pagesize 2048 is incompatible with it");
182 uint32_t cgr_register_content
;
183 target_read_u32 (target
, MX3_CCM_CGR2
, &cgr_register_content
);
184 if (!(cgr_register_content
& 0x00000300))
186 LOG_ERROR ("clock gating to EMI disabled");
192 uint32_t gpr_register_content
;
193 target_read_u32 (target
, MX3_GPR
, &gpr_register_content
);
194 if (gpr_register_content
& 0x00000060)
196 LOG_ERROR ("pins mode overrided by GPR");
203 * testing IOMUX settings; must be in "functional-mode output and
204 * functional-mode input" mode
207 test_iomux
= ERROR_OK
;
209 test_iomux_settings (target
, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
211 test_iomux_settings (target
, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
213 test_iomux_settings (target
, 0x43fac0c8, 0x0000007f, "d7");
214 if (nand
->bus_width
== 16)
217 test_iomux_settings (target
, 0x43fac0c8, 0x7f7f7f00,
220 test_iomux_settings (target
, 0x43fac0cc, 0x7f7f7f7f,
223 test_iomux_settings (target
, 0x43fac0d0, 0x0000007f, "d15");
226 test_iomux_settings (target
, 0x43fac0d0, 0x7f7f7f00,
229 test_iomux_settings (target
, 0x43fac0d4, 0x7f7f7f7f,
230 "nfwe,nfre,nfale,nfcle");
231 if (test_iomux
!= ERROR_OK
)
237 initialize_nf_controller (nand
);
241 uint16_t nand_status_content
;
243 retval
|= imx31_command (nand
, NAND_CMD_STATUS
);
244 retval
|= imx31_address (nand
, 0x00);
245 retval
|= do_data_output (nand
);
246 if (retval
!= ERROR_OK
)
248 LOG_ERROR (get_status_register_err_msg
);
251 target_read_u16 (target
, MX3_NF_MAIN_BUFFER0
, &nand_status_content
);
252 if (!(nand_status_content
& 0x0080))
255 * is host-big-endian correctly ??
257 LOG_INFO ("NAND read-only");
258 mx3_nf_info
->flags
.nand_readonly
= 1;
262 mx3_nf_info
->flags
.nand_readonly
= 0;
268 static int imx31_read_data (struct nand_device
*nand
, void *data
)
270 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
271 struct target
*target
= mx3_nf_info
->target
;
274 * validate target state
276 int validate_target_result
;
277 validate_target_result
= validate_target_state (nand
);
278 if (validate_target_result
!= ERROR_OK
)
280 return validate_target_result
;
286 * get data from nand chip
288 int try_data_output_from_nand_chip
;
289 try_data_output_from_nand_chip
= do_data_output (nand
);
290 if (try_data_output_from_nand_chip
!= ERROR_OK
)
292 return try_data_output_from_nand_chip
;
296 if (nand
->bus_width
== 16)
298 get_next_halfword_from_sram_buffer (target
, data
);
302 get_next_byte_from_sram_buffer (target
, data
);
308 static int imx31_write_data (struct nand_device
*nand
, uint16_t data
)
310 LOG_ERROR ("write_data() not implemented");
311 return ERROR_NAND_OPERATION_FAILED
;
314 static int imx31_reset (struct nand_device
*nand
)
317 * validate target state
319 int validate_target_result
;
320 validate_target_result
= validate_target_state (nand
);
321 if (validate_target_result
!= ERROR_OK
)
323 return validate_target_result
;
325 initialize_nf_controller (nand
);
329 static int imx31_command (struct nand_device
*nand
, uint8_t command
)
331 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
332 struct target
*target
= mx3_nf_info
->target
;
335 * validate target state
337 int validate_target_result
;
338 validate_target_result
= validate_target_state (nand
);
339 if (validate_target_result
!= ERROR_OK
)
341 return validate_target_result
;
347 case NAND_CMD_READOOB
:
348 command
= NAND_CMD_READ0
;
349 in_sram_address
= MX3_NF_SPARE_BUFFER0
; /* set read point for
351 * read_block_data() to
356 command
= NAND_CMD_READ0
;
358 * offset == one half of page size
361 MX3_NF_MAIN_BUFFER0
+ (nand
->page_size
>> 1);
363 in_sram_address
= MX3_NF_MAIN_BUFFER0
;
366 target_write_u16 (target
, MX3_NF_FCMD
, command
);
368 * start command input operation (set MX3_NF_BIT_OP_DONE==0)
370 target_write_u16 (target
, MX3_NF_CFG2
, MX3_NF_BIT_OP_FCI
);
373 poll_result
= poll_for_complete_op (target
, "command");
374 if (poll_result
!= ERROR_OK
)
380 * reset cursor to begin of the buffer
382 sign_of_sequental_byte_read
= 0;
385 case NAND_CMD_READID
:
386 mx3_nf_info
->optype
= MX3_NF_DATAOUT_NANDID
;
387 mx3_nf_info
->fin
= MX3_NF_FIN_DATAOUT
;
389 case NAND_CMD_STATUS
:
390 mx3_nf_info
->optype
= MX3_NF_DATAOUT_NANDSTATUS
;
391 mx3_nf_info
->fin
= MX3_NF_FIN_DATAOUT
;
394 mx3_nf_info
->fin
= MX3_NF_FIN_DATAOUT
;
395 mx3_nf_info
->optype
= MX3_NF_DATAOUT_PAGE
;
398 mx3_nf_info
->optype
= MX3_NF_DATAOUT_PAGE
;
403 static int imx31_address (struct nand_device
*nand
, uint8_t address
)
405 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
406 struct target
*target
= mx3_nf_info
->target
;
409 * validate target state
411 int validate_target_result
;
412 validate_target_result
= validate_target_state (nand
);
413 if (validate_target_result
!= ERROR_OK
)
415 return validate_target_result
;
419 target_write_u16 (target
, MX3_NF_FADDR
, address
);
421 * start address input operation (set MX3_NF_BIT_OP_DONE==0)
423 target_write_u16 (target
, MX3_NF_CFG2
, MX3_NF_BIT_OP_FAI
);
426 poll_result
= poll_for_complete_op (target
, "address");
427 if (poll_result
!= ERROR_OK
)
435 static int imx31_nand_ready (struct nand_device
*nand
, int tout
)
437 uint16_t poll_complete_status
;
438 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
439 struct target
*target
= mx3_nf_info
->target
;
443 * validate target state
445 int validate_target_result
;
446 validate_target_result
= validate_target_state (nand
);
447 if (validate_target_result
!= ERROR_OK
)
449 return validate_target_result
;
455 target_read_u16 (target
, MX3_NF_CFG2
, &poll_complete_status
);
456 if (poll_complete_status
& MX3_NF_BIT_OP_DONE
)
466 static int imx31_write_page (struct nand_device
*nand
, uint32_t page
,
467 uint8_t * data
, uint32_t data_size
, uint8_t * oob
,
470 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
471 struct target
*target
= mx3_nf_info
->target
;
475 LOG_ERROR (data_block_size_err_msg
, data_size
);
476 return ERROR_NAND_OPERATION_FAILED
;
480 LOG_ERROR (data_block_size_err_msg
, oob_size
);
481 return ERROR_NAND_OPERATION_FAILED
;
485 LOG_ERROR ("nothing to program");
486 return ERROR_NAND_OPERATION_FAILED
;
490 * validate target state
493 retval
= validate_target_state (nand
);
494 if (retval
!= ERROR_OK
)
500 int retval
= ERROR_OK
;
501 retval
|= imx31_command(nand
, NAND_CMD_SEQIN
);
502 retval
|= imx31_address(nand
, 0x00);
503 retval
|= imx31_address(nand
, page
& 0xff);
504 retval
|= imx31_address(nand
, (page
>> 8) & 0xff);
505 if (nand
->address_cycles
>= 4)
507 retval
|= imx31_address (nand
, (page
>> 16) & 0xff);
508 if (nand
->address_cycles
>= 5)
510 retval
|= imx31_address (nand
, (page
>> 24) & 0xff);
513 target_write_buffer (target
, MX3_NF_MAIN_BUFFER0
, data_size
, data
);
516 if (mx3_nf_info
->flags
.hw_ecc_enabled
)
519 * part of spare block will be overrided by hardware
523 ("part of spare block will be overrided by hardware ECC generator");
525 target_write_buffer (target
, MX3_NF_SPARE_BUFFER0
, oob_size
,
529 * start data input operation (set MX3_NF_BIT_OP_DONE==0)
531 target_write_u16 (target
, MX3_NF_CFG2
, MX3_NF_BIT_OP_FDI
);
534 poll_result
= poll_for_complete_op (target
, "data input");
535 if (poll_result
!= ERROR_OK
)
540 retval
|= imx31_command (nand
, NAND_CMD_PAGEPROG
);
541 if (retval
!= ERROR_OK
)
547 * check status register
550 uint16_t nand_status_content
;
552 retval
|= imx31_command(nand
, NAND_CMD_STATUS
);
553 retval
|= imx31_address(nand
, 0x00);
554 retval
|= do_data_output(nand
);
555 if (retval
!= ERROR_OK
)
557 LOG_ERROR (get_status_register_err_msg
);
560 target_read_u16 (target
, MX3_NF_MAIN_BUFFER0
, &nand_status_content
);
561 if (nand_status_content
& 0x0001)
564 * is host-big-endian correctly ??
566 return ERROR_NAND_OPERATION_FAILED
;
573 static int imx31_read_page (struct nand_device
*nand
, uint32_t page
,
574 uint8_t * data
, uint32_t data_size
, uint8_t * oob
,
577 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
578 struct target
*target
= mx3_nf_info
->target
;
582 LOG_ERROR (data_block_size_err_msg
, data_size
);
583 return ERROR_NAND_OPERATION_FAILED
;
587 LOG_ERROR (data_block_size_err_msg
, oob_size
);
588 return ERROR_NAND_OPERATION_FAILED
;
593 * validate target state
596 retval
= validate_target_state(nand
);
597 if (retval
!= ERROR_OK
)
603 int retval
= ERROR_OK
;
604 retval
|= imx31_command(nand
, NAND_CMD_READ0
);
605 retval
|= imx31_address(nand
, 0x00);
606 retval
|= imx31_address(nand
, page
& 0xff);
607 retval
|= imx31_address(nand
, (page
>> 8) & 0xff);
608 if (nand
->address_cycles
>= 4)
610 retval
|= imx31_address(nand
, (page
>> 16) & 0xff);
611 if (nand
->address_cycles
>= 5)
613 retval
|= imx31_address(nand
, (page
>> 24) & 0xff);
614 retval
|= imx31_command(nand
, NAND_CMD_READSTART
);
617 retval
|= do_data_output (nand
);
618 if (retval
!= ERROR_OK
)
625 target_read_buffer (target
, MX3_NF_MAIN_BUFFER0
, data_size
,
630 target_read_buffer (target
, MX3_NF_SPARE_BUFFER0
, oob_size
,
637 static int test_iomux_settings (struct target
* target
, uint32_t address
,
638 uint32_t mask
, const char *text
)
640 uint32_t register_content
;
641 target_read_u32 (target
, address
, ®ister_content
);
642 if ((register_content
& mask
) != (0x12121212 & mask
))
644 LOG_ERROR ("IOMUX for {%s} is bad", text
);
650 static int initialize_nf_controller (struct nand_device
*nand
)
652 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
653 struct target
*target
= mx3_nf_info
->target
;
655 * resets NAND flash controller in zero time ? I dont know.
657 target_write_u16 (target
, MX3_NF_CFG1
, MX3_NF_BIT_RESET_EN
);
660 work_mode
= MX3_NF_BIT_INT_DIS
; /* disable interrupt */
661 if (target
->endianness
== TARGET_BIG_ENDIAN
)
663 work_mode
|= MX3_NF_BIT_BE_EN
;
665 if (mx3_nf_info
->flags
.hw_ecc_enabled
)
667 work_mode
|= MX3_NF_BIT_ECC_EN
;
669 target_write_u16 (target
, MX3_NF_CFG1
, work_mode
);
672 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
674 target_write_u16 (target
, MX3_NF_BUFCFG
, 2);
677 target_read_u16 (target
, MX3_NF_FWP
, &temp
);
678 if ((temp
& 0x0007) == 1)
680 LOG_ERROR ("NAND flash is tight-locked, reset needed");
686 * unlock NAND flash for write
688 target_write_u16 (target
, MX3_NF_FWP
, 4);
689 target_write_u16 (target
, MX3_NF_LOCKSTART
, 0x0000);
690 target_write_u16 (target
, MX3_NF_LOCKEND
, 0xFFFF);
692 * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
694 target_write_u16 (target
, MX3_NF_BUFADDR
, 0x0000);
696 * address of SRAM buffer
698 in_sram_address
= MX3_NF_MAIN_BUFFER0
;
699 sign_of_sequental_byte_read
= 0;
703 static int get_next_byte_from_sram_buffer (struct target
* target
, uint8_t * value
)
705 static uint8_t even_byte
= 0;
709 if (sign_of_sequental_byte_read
== 0)
713 if (in_sram_address
> MX3_NF_LAST_BUFFER_ADDR
)
715 LOG_ERROR (sram_buffer_bounds_err_msg
, in_sram_address
);
717 sign_of_sequental_byte_read
= 0;
719 return ERROR_NAND_OPERATION_FAILED
;
724 target_read_u16 (target
, in_sram_address
, &temp
);
729 in_sram_address
+= 2;
733 *value
= temp
& 0xff;
737 sign_of_sequental_byte_read
= 1;
741 static int get_next_halfword_from_sram_buffer (struct target
* target
,
744 if (in_sram_address
> MX3_NF_LAST_BUFFER_ADDR
)
746 LOG_ERROR (sram_buffer_bounds_err_msg
, in_sram_address
);
748 return ERROR_NAND_OPERATION_FAILED
;
752 target_read_u16 (target
, in_sram_address
, value
);
753 in_sram_address
+= 2;
758 static int poll_for_complete_op (struct target
* target
, const char *text
)
760 uint16_t poll_complete_status
;
761 for (int poll_cycle_count
= 0; poll_cycle_count
< 100; poll_cycle_count
++)
764 target_read_u16 (target
, MX3_NF_CFG2
, &poll_complete_status
);
765 if (poll_complete_status
& MX3_NF_BIT_OP_DONE
)
770 if (!(poll_complete_status
& MX3_NF_BIT_OP_DONE
))
772 LOG_ERROR ("%s sending timeout", text
);
773 return ERROR_NAND_OPERATION_FAILED
;
778 static int validate_target_state (struct nand_device
*nand
)
780 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
781 struct target
*target
= mx3_nf_info
->target
;
783 if (target
->state
!= TARGET_HALTED
)
785 LOG_ERROR (target_not_halted_err_msg
);
786 return ERROR_NAND_OPERATION_FAILED
;
789 if (mx3_nf_info
->flags
.target_little_endian
!=
790 (target
->endianness
== TARGET_LITTLE_ENDIAN
))
793 * endianness changed after NAND controller probed
795 return ERROR_NAND_OPERATION_FAILED
;
800 static int do_data_output (struct nand_device
*nand
)
802 struct mx3_nf_controller
*mx3_nf_info
= nand
->controller_priv
;
803 struct target
*target
= mx3_nf_info
->target
;
804 switch (mx3_nf_info
->fin
)
806 case MX3_NF_FIN_DATAOUT
:
808 * start data output operation (set MX3_NF_BIT_OP_DONE==0)
810 target_write_u16 (target
, MX3_NF_CFG2
,
811 MX3_NF_BIT_DATAOUT_TYPE (mx3_nf_info
->
815 poll_result
= poll_for_complete_op (target
, "data output");
816 if (poll_result
!= ERROR_OK
)
821 mx3_nf_info
->fin
= MX3_NF_FIN_NONE
;
825 if ((mx3_nf_info
->optype
== MX3_NF_DATAOUT_PAGE
)
826 && mx3_nf_info
->flags
.hw_ecc_enabled
)
829 target_read_u16 (target
, MX3_NF_ECCSTATUS
, &ecc_status
);
830 switch (ecc_status
& 0x000c)
834 ("main area readed with 1 (correctable) error");
838 ("main area readed with more than 1 (incorrectable) error");
839 return ERROR_NAND_OPERATION_FAILED
;
842 switch (ecc_status
& 0x0003)
846 ("spare area readed with 1 (correctable) error");
850 ("main area readed with more than 1 (incorrectable) error");
851 return ERROR_NAND_OPERATION_FAILED
;
856 case MX3_NF_FIN_NONE
:
862 struct nand_flash_controller imx31_nand_flash_controller
= {
864 .nand_device_command
= &imx31_nand_device_command
,
866 .reset
= &imx31_reset
,
867 .command
= &imx31_command
,
868 .address
= &imx31_address
,
869 .write_data
= &imx31_write_data
,
870 .read_data
= &imx31_read_data
,
871 .write_page
= &imx31_write_page
,
872 .read_page
= &imx31_read_page
,
873 .nand_ready
= &imx31_nand_ready
,
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