1 /***************************************************************************
2 * Copyright (C) 2009 by Alexei Babich *
3 * Rezonans plc., Chelyabinsk, Russia *
6 * Copyright (C) 2010 by Gaetan CARLIER *
7 * Trump s.a., Belgium *
9 * Copyright (C) 2011 by Erik Ahlen *
10 * Avalon Innovation, Sweden *
12 * This program is free software; you can redistribute it and/or modify *
13 * it under the terms of the GNU General Public License as published by *
14 * the Free Software Foundation; either version 2 of the License, or *
15 * (at your option) any later version. *
17 * This program is distributed in the hope that it will be useful, *
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
20 * GNU General Public License for more details. *
22 * You should have received a copy of the GNU General Public License *
23 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
24 ***************************************************************************/
27 * Freescale iMX OpenOCD NAND Flash controller support.
28 * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
32 * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @mxc
33 * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
34 * "nand write # file 0", "nand verify"
36 * get_next_halfword_from_sram_buffer() not tested
37 * !! all function only tested with 2k page nand device; mxc_write_page
38 * writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
39 * !! oob must be be used due to NFS bug
40 * !! oob must be 64 bytes per 2KiB page
48 #include <target/target.h>
52 #define nfc_is_v1() (mxc_nf_info->mxc_version == MXC_VERSION_MX27 || \
53 mxc_nf_info->mxc_version == MXC_VERSION_MX31)
54 #define nfc_is_v2() (mxc_nf_info->mxc_version == MXC_VERSION_MX25 || \
55 mxc_nf_info->mxc_version == MXC_VERSION_MX35)
57 /* This permits to print (in LOG_INFO) how much bytes
58 * has been written after a page read or write.
59 * This is useful when OpenOCD is used with a graphical
60 * front-end to estimate progression of the global read/write
62 #undef _MXC_PRINT_STAT
63 /* #define _MXC_PRINT_STAT */
65 static const char target_not_halted_err_msg
[] =
66 "target must be halted to use mxc NAND flash controller";
67 static const char data_block_size_err_msg
[] =
68 "minimal granularity is one half-word, %" PRId32
" is incorrect";
69 static const char sram_buffer_bounds_err_msg
[] =
70 "trying to access out of SRAM buffer bound (addr=0x%" PRIx32
")";
71 static const char get_status_register_err_msg
[] = "can't get NAND status";
72 static uint32_t in_sram_address
;
73 static unsigned char sign_of_sequental_byte_read
;
75 static uint32_t align_address_v2(struct nand_device
*nand
, uint32_t addr
);
76 static int initialize_nf_controller(struct nand_device
*nand
);
77 static int get_next_byte_from_sram_buffer(struct nand_device
*nand
, uint8_t *value
);
78 static int get_next_halfword_from_sram_buffer(struct nand_device
*nand
, uint16_t *value
);
79 static int poll_for_complete_op(struct nand_device
*nand
, const char *text
);
80 static int validate_target_state(struct nand_device
*nand
);
81 static int do_data_output(struct nand_device
*nand
);
83 static int mxc_command(struct nand_device
*nand
, uint8_t command
);
84 static int mxc_address(struct nand_device
*nand
, uint8_t address
);
86 NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command
)
88 struct mxc_nf_controller
*mxc_nf_info
;
91 mxc_nf_info
= malloc(sizeof(struct mxc_nf_controller
));
92 if (mxc_nf_info
== NULL
) {
93 LOG_ERROR("no memory for nand controller");
96 nand
->controller_priv
= mxc_nf_info
;
99 LOG_ERROR("use \"nand device mxc target mx25|mx27|mx31|mx35 noecc|hwecc [biswap]\"");
106 if (strcmp(CMD_ARGV
[2], "mx25") == 0) {
107 mxc_nf_info
->mxc_version
= MXC_VERSION_MX25
;
108 mxc_nf_info
->mxc_base_addr
= 0xBB000000;
109 mxc_nf_info
->mxc_regs_addr
= mxc_nf_info
->mxc_base_addr
+ 0x1E00;
110 } else if (strcmp(CMD_ARGV
[2], "mx27") == 0) {
111 mxc_nf_info
->mxc_version
= MXC_VERSION_MX27
;
112 mxc_nf_info
->mxc_base_addr
= 0xD8000000;
113 mxc_nf_info
->mxc_regs_addr
= mxc_nf_info
->mxc_base_addr
+ 0x0E00;
114 } else if (strcmp(CMD_ARGV
[2], "mx31") == 0) {
115 mxc_nf_info
->mxc_version
= MXC_VERSION_MX31
;
116 mxc_nf_info
->mxc_base_addr
= 0xB8000000;
117 mxc_nf_info
->mxc_regs_addr
= mxc_nf_info
->mxc_base_addr
+ 0x0E00;
118 } else if (strcmp(CMD_ARGV
[2], "mx35") == 0) {
119 mxc_nf_info
->mxc_version
= MXC_VERSION_MX35
;
120 mxc_nf_info
->mxc_base_addr
= 0xBB000000;
121 mxc_nf_info
->mxc_regs_addr
= mxc_nf_info
->mxc_base_addr
+ 0x1E00;
125 * check hwecc requirements
127 hwecc_needed
= strcmp(CMD_ARGV
[3], "hwecc");
128 if (hwecc_needed
== 0)
129 mxc_nf_info
->flags
.hw_ecc_enabled
= 1;
131 mxc_nf_info
->flags
.hw_ecc_enabled
= 0;
133 mxc_nf_info
->optype
= MXC_NF_DATAOUT_PAGE
;
134 mxc_nf_info
->fin
= MXC_NF_FIN_NONE
;
135 mxc_nf_info
->flags
.target_little_endian
=
136 (nand
->target
->endianness
== TARGET_LITTLE_ENDIAN
);
139 * should factory bad block indicator be swaped
140 * as a workaround for how the nfc handles pages.
142 if (CMD_ARGC
> 4 && strcmp(CMD_ARGV
[4], "biswap") == 0) {
143 LOG_DEBUG("BI-swap enabled");
144 mxc_nf_info
->flags
.biswap_enabled
= 1;
150 COMMAND_HANDLER(handle_mxc_biswap_command
)
152 struct nand_device
*nand
= NULL
;
153 struct mxc_nf_controller
*mxc_nf_info
= NULL
;
155 if (CMD_ARGC
< 1 || CMD_ARGC
> 2)
156 return ERROR_COMMAND_SYNTAX_ERROR
;
158 int retval
= CALL_COMMAND_HANDLER(nand_command_get_device
, 0, &nand
);
159 if (retval
!= ERROR_OK
) {
160 command_print(CMD_CTX
, "invalid nand device number or name: %s", CMD_ARGV
[0]);
161 return ERROR_COMMAND_ARGUMENT_INVALID
;
164 mxc_nf_info
= nand
->controller_priv
;
166 if (strcmp(CMD_ARGV
[1], "enable") == 0)
167 mxc_nf_info
->flags
.biswap_enabled
= true;
169 mxc_nf_info
->flags
.biswap_enabled
= false;
171 if (mxc_nf_info
->flags
.biswap_enabled
)
172 command_print(CMD_CTX
, "BI-swapping enabled on %s", nand
->name
);
174 command_print(CMD_CTX
, "BI-swapping disabled on %s", nand
->name
);
179 static const struct command_registration mxc_sub_command_handlers
[] = {
182 .mode
= COMMAND_EXEC
,
183 .handler
= handle_mxc_biswap_command
,
184 .help
= "Turns on/off bad block information swaping from main area, "
185 "without parameter query status.",
186 .usage
= "bank_id ['enable'|'disable']",
188 COMMAND_REGISTRATION_DONE
191 static const struct command_registration mxc_nand_command_handler
[] = {
195 .help
= "MXC NAND flash controller commands",
196 .chain
= mxc_sub_command_handlers
198 COMMAND_REGISTRATION_DONE
201 static int mxc_init(struct nand_device
*nand
)
203 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
204 struct target
*target
= nand
->target
;
206 int validate_target_result
;
207 uint16_t buffsize_register_content
;
208 uint32_t sreg_content
;
209 uint32_t SREG
= MX2_FMCR
;
210 uint32_t SEL_16BIT
= MX2_FMCR_NF_16BIT_SEL
;
211 uint32_t SEL_FMS
= MX2_FMCR_NF_FMS
;
213 uint16_t nand_status_content
;
215 * validate target state
217 validate_target_result
= validate_target_state(nand
);
218 if (validate_target_result
!= ERROR_OK
)
219 return validate_target_result
;
222 target_read_u16(target
, MXC_NF_BUFSIZ
, &buffsize_register_content
);
223 mxc_nf_info
->flags
.one_kb_sram
= !(buffsize_register_content
& 0x000f);
225 mxc_nf_info
->flags
.one_kb_sram
= 0;
227 if (mxc_nf_info
->mxc_version
== MXC_VERSION_MX31
) {
229 SEL_16BIT
= MX3_PCSR_NF_16BIT_SEL
;
230 SEL_FMS
= MX3_PCSR_NF_FMS
;
231 } else if (mxc_nf_info
->mxc_version
== MXC_VERSION_MX25
) {
233 SEL_16BIT
= MX25_RCSR_NF_16BIT_SEL
;
234 SEL_FMS
= MX25_RCSR_NF_FMS
;
235 } else if (mxc_nf_info
->mxc_version
== MXC_VERSION_MX35
) {
237 SEL_16BIT
= MX35_RCSR_NF_16BIT_SEL
;
238 SEL_FMS
= MX35_RCSR_NF_FMS
;
241 target_read_u32(target
, SREG
, &sreg_content
);
242 if (!nand
->bus_width
) {
243 /* bus_width not yet defined. Read it from MXC_FMCR */
244 nand
->bus_width
= (sreg_content
& SEL_16BIT
) ? 16 : 8;
246 /* bus_width forced in soft. Sync it to MXC_FMCR */
247 sreg_content
|= ((nand
->bus_width
== 16) ? SEL_16BIT
: 0x00000000);
248 target_write_u32(target
, SREG
, sreg_content
);
250 if (nand
->bus_width
== 16)
251 LOG_DEBUG("MXC_NF : bus is 16-bit width");
253 LOG_DEBUG("MXC_NF : bus is 8-bit width");
255 if (!nand
->page_size
)
256 nand
->page_size
= (sreg_content
& SEL_FMS
) ? 2048 : 512;
258 sreg_content
|= ((nand
->page_size
== 2048) ? SEL_FMS
: 0x00000000);
259 target_write_u32(target
, SREG
, sreg_content
);
261 if (mxc_nf_info
->flags
.one_kb_sram
&& (nand
->page_size
== 2048)) {
262 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
263 "pagesize 2048 is incompatible with it");
265 LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
267 if (nfc_is_v2() && sreg_content
& MX35_RCSR_NF_4K
)
268 LOG_ERROR("MXC driver does not have support for 4k pagesize.");
270 initialize_nf_controller(nand
);
273 retval
|= mxc_command(nand
, NAND_CMD_STATUS
);
274 retval
|= mxc_address(nand
, 0x00);
275 retval
|= do_data_output(nand
);
276 if (retval
!= ERROR_OK
) {
277 LOG_ERROR(get_status_register_err_msg
);
280 target_read_u16(target
, MXC_NF_MAIN_BUFFER0
, &nand_status_content
);
281 if (!(nand_status_content
& 0x0080)) {
282 LOG_INFO("NAND read-only");
283 mxc_nf_info
->flags
.nand_readonly
= 1;
285 mxc_nf_info
->flags
.nand_readonly
= 0;
289 static int mxc_read_data(struct nand_device
*nand
, void *data
)
291 int validate_target_result
;
292 int try_data_output_from_nand_chip
;
294 * validate target state
296 validate_target_result
= validate_target_state(nand
);
297 if (validate_target_result
!= ERROR_OK
)
298 return validate_target_result
;
301 * get data from nand chip
303 try_data_output_from_nand_chip
= do_data_output(nand
);
304 if (try_data_output_from_nand_chip
!= ERROR_OK
) {
305 LOG_ERROR("mxc_read_data : read data failed : '%x'",
306 try_data_output_from_nand_chip
);
307 return try_data_output_from_nand_chip
;
310 if (nand
->bus_width
== 16)
311 get_next_halfword_from_sram_buffer(nand
, data
);
313 get_next_byte_from_sram_buffer(nand
, data
);
318 static int mxc_write_data(struct nand_device
*nand
, uint16_t data
)
320 LOG_ERROR("write_data() not implemented");
321 return ERROR_NAND_OPERATION_FAILED
;
324 static int mxc_reset(struct nand_device
*nand
)
327 * validate target state
329 int validate_target_result
;
330 validate_target_result
= validate_target_state(nand
);
331 if (validate_target_result
!= ERROR_OK
)
332 return validate_target_result
;
333 initialize_nf_controller(nand
);
337 static int mxc_command(struct nand_device
*nand
, uint8_t command
)
339 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
340 struct target
*target
= nand
->target
;
341 int validate_target_result
;
344 * validate target state
346 validate_target_result
= validate_target_state(nand
);
347 if (validate_target_result
!= ERROR_OK
)
348 return validate_target_result
;
351 case NAND_CMD_READOOB
:
352 command
= NAND_CMD_READ0
;
353 /* set read point for data_read() and read_block_data() to
354 * spare area in SRAM buffer
357 in_sram_address
= MXC_NF_V1_SPARE_BUFFER0
;
359 in_sram_address
= MXC_NF_V2_SPARE_BUFFER0
;
362 command
= NAND_CMD_READ0
;
364 * offset == one half of page size
366 in_sram_address
= MXC_NF_MAIN_BUFFER0
+ (nand
->page_size
>> 1);
369 in_sram_address
= MXC_NF_MAIN_BUFFER0
;
373 target_write_u16(target
, MXC_NF_FCMD
, command
);
375 * start command input operation (set MXC_NF_BIT_OP_DONE==0)
377 target_write_u16(target
, MXC_NF_CFG2
, MXC_NF_BIT_OP_FCI
);
378 poll_result
= poll_for_complete_op(nand
, "command");
379 if (poll_result
!= ERROR_OK
)
382 * reset cursor to begin of the buffer
384 sign_of_sequental_byte_read
= 0;
385 /* Handle special read command and adjust NF_CFG2(FDO) */
387 case NAND_CMD_READID
:
388 mxc_nf_info
->optype
= MXC_NF_DATAOUT_NANDID
;
389 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
391 case NAND_CMD_STATUS
:
392 mxc_nf_info
->optype
= MXC_NF_DATAOUT_NANDSTATUS
;
393 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
394 target_write_u16 (target
, MXC_NF_BUFADDR
, 0);
398 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
399 mxc_nf_info
->optype
= MXC_NF_DATAOUT_PAGE
;
402 /* Ohter command use the default 'One page data out' FDO */
403 mxc_nf_info
->optype
= MXC_NF_DATAOUT_PAGE
;
409 static int mxc_address(struct nand_device
*nand
, uint8_t address
)
411 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
412 struct target
*target
= nand
->target
;
413 int validate_target_result
;
416 * validate target state
418 validate_target_result
= validate_target_state(nand
);
419 if (validate_target_result
!= ERROR_OK
)
420 return validate_target_result
;
422 target_write_u16(target
, MXC_NF_FADDR
, address
);
424 * start address input operation (set MXC_NF_BIT_OP_DONE==0)
426 target_write_u16(target
, MXC_NF_CFG2
, MXC_NF_BIT_OP_FAI
);
427 poll_result
= poll_for_complete_op(nand
, "address");
428 if (poll_result
!= ERROR_OK
)
434 static int mxc_nand_ready(struct nand_device
*nand
, int tout
)
436 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
437 struct target
*target
= nand
->target
;
438 uint16_t poll_complete_status
;
439 int validate_target_result
;
442 * validate target state
444 validate_target_result
= validate_target_state(nand
);
445 if (validate_target_result
!= ERROR_OK
)
446 return validate_target_result
;
449 target_read_u16(target
, MXC_NF_CFG2
, &poll_complete_status
);
450 if (poll_complete_status
& MXC_NF_BIT_OP_DONE
)
454 } while (tout
-- > 0);
458 static int mxc_write_page(struct nand_device
*nand
, uint32_t page
,
459 uint8_t *data
, uint32_t data_size
,
460 uint8_t *oob
, uint32_t oob_size
)
462 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
463 struct target
*target
= nand
->target
;
465 uint16_t nand_status_content
;
466 uint16_t swap1
, swap2
, new_swap1
;
471 LOG_ERROR(data_block_size_err_msg
, data_size
);
472 return ERROR_NAND_OPERATION_FAILED
;
475 LOG_ERROR(data_block_size_err_msg
, oob_size
);
476 return ERROR_NAND_OPERATION_FAILED
;
479 LOG_ERROR("nothing to program");
480 return ERROR_NAND_OPERATION_FAILED
;
484 * validate target state
486 retval
= validate_target_state(nand
);
487 if (retval
!= ERROR_OK
)
490 in_sram_address
= MXC_NF_MAIN_BUFFER0
;
491 sign_of_sequental_byte_read
= 0;
493 retval
|= mxc_command(nand
, NAND_CMD_SEQIN
);
494 retval
|= mxc_address(nand
, 0); /* col */
495 retval
|= mxc_address(nand
, 0); /* col */
496 retval
|= mxc_address(nand
, page
& 0xff); /* page address */
497 retval
|= mxc_address(nand
, (page
>> 8) & 0xff);/* page address */
498 retval
|= mxc_address(nand
, (page
>> 16) & 0xff); /* page address */
500 target_write_buffer(target
, MXC_NF_MAIN_BUFFER0
, data_size
, data
);
502 if (mxc_nf_info
->flags
.hw_ecc_enabled
) {
504 * part of spare block will be overrided by hardware
507 LOG_DEBUG("part of spare block will be overrided "
508 "by hardware ECC generator");
511 target_write_buffer(target
, MXC_NF_V1_SPARE_BUFFER0
, oob_size
, oob
);
513 uint32_t addr
= MXC_NF_V2_SPARE_BUFFER0
;
514 while (oob_size
> 0) {
515 uint8_t len
= MIN(oob_size
, MXC_NF_SPARE_BUFFER_LEN
);
516 target_write_buffer(target
, addr
, len
, oob
);
517 addr
= align_address_v2(nand
, addr
+ len
);
524 if (nand
->page_size
> 512 && mxc_nf_info
->flags
.biswap_enabled
) {
525 /* BI-swap - work-around of i.MX NFC for NAND device with page == 2kb*/
526 target_read_u16(target
, MXC_NF_MAIN_BUFFER3
+ 464, &swap1
);
528 LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mxc driver");
529 return ERROR_NAND_OPERATION_FAILED
;
531 swap2
= 0xffff; /* Spare buffer unused forced to 0xffff */
532 new_swap1
= (swap1
& 0xFF00) | (swap2
>> 8);
533 swap2
= (swap1
<< 8) | (swap2
& 0xFF);
534 target_write_u16(target
, MXC_NF_MAIN_BUFFER3
+ 464, new_swap1
);
536 target_write_u16(target
, MXC_NF_V1_SPARE_BUFFER3
+ 4, swap2
);
538 target_write_u16(target
, MXC_NF_V2_SPARE_BUFFER3
, swap2
);
542 * start data input operation (set MXC_NF_BIT_OP_DONE==0)
544 if (nfc_is_v1() && nand
->page_size
> 512)
549 for (uint8_t i
= 0; i
< bufs
; ++i
) {
550 target_write_u16(target
, MXC_NF_BUFADDR
, i
);
551 target_write_u16(target
, MXC_NF_CFG2
, MXC_NF_BIT_OP_FDI
);
552 poll_result
= poll_for_complete_op(nand
, "data input");
553 if (poll_result
!= ERROR_OK
)
557 retval
|= mxc_command(nand
, NAND_CMD_PAGEPROG
);
558 if (retval
!= ERROR_OK
)
562 * check status register
565 retval
|= mxc_command(nand
, NAND_CMD_STATUS
);
566 target_write_u16 (target
, MXC_NF_BUFADDR
, 0);
567 mxc_nf_info
->optype
= MXC_NF_DATAOUT_NANDSTATUS
;
568 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
569 retval
|= do_data_output(nand
);
570 if (retval
!= ERROR_OK
) {
571 LOG_ERROR(get_status_register_err_msg
);
574 target_read_u16(target
, MXC_NF_MAIN_BUFFER0
, &nand_status_content
);
575 if (nand_status_content
& 0x0001) {
577 * page not correctly written
579 return ERROR_NAND_OPERATION_FAILED
;
581 #ifdef _MXC_PRINT_STAT
582 LOG_INFO("%d bytes newly written", data_size
);
587 static int mxc_read_page(struct nand_device
*nand
, uint32_t page
,
588 uint8_t *data
, uint32_t data_size
,
589 uint8_t *oob
, uint32_t oob_size
)
591 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
592 struct target
*target
= nand
->target
;
595 uint16_t swap1
, swap2
, new_swap1
;
598 LOG_ERROR(data_block_size_err_msg
, data_size
);
599 return ERROR_NAND_OPERATION_FAILED
;
602 LOG_ERROR(data_block_size_err_msg
, oob_size
);
603 return ERROR_NAND_OPERATION_FAILED
;
607 * validate target state
609 retval
= validate_target_state(nand
);
610 if (retval
!= ERROR_OK
)
612 /* Reset address_cycles before mxc_command ?? */
613 retval
= mxc_command(nand
, NAND_CMD_READ0
);
614 if (retval
!= ERROR_OK
)
616 retval
= mxc_address(nand
, 0); /* col */
617 if (retval
!= ERROR_OK
)
619 retval
= mxc_address(nand
, 0); /* col */
620 if (retval
!= ERROR_OK
)
622 retval
= mxc_address(nand
, page
& 0xff);/* page address */
623 if (retval
!= ERROR_OK
)
625 retval
= mxc_address(nand
, (page
>> 8) & 0xff); /* page address */
626 if (retval
!= ERROR_OK
)
628 retval
= mxc_address(nand
, (page
>> 16) & 0xff);/* page address */
629 if (retval
!= ERROR_OK
)
631 retval
= mxc_command(nand
, NAND_CMD_READSTART
);
632 if (retval
!= ERROR_OK
)
635 if (nfc_is_v1() && nand
->page_size
> 512)
640 for (uint8_t i
= 0; i
< bufs
; ++i
) {
641 target_write_u16(target
, MXC_NF_BUFADDR
, i
);
642 mxc_nf_info
->fin
= MXC_NF_FIN_DATAOUT
;
643 retval
= do_data_output(nand
);
644 if (retval
!= ERROR_OK
) {
645 LOG_ERROR("MXC_NF : Error reading page %d", i
);
650 if (nand
->page_size
> 512 && mxc_nf_info
->flags
.biswap_enabled
) {
651 uint32_t SPARE_BUFFER3
;
652 /* BI-swap - work-around of mxc NFC for NAND device with page == 2k */
653 target_read_u16(target
, MXC_NF_MAIN_BUFFER3
+ 464, &swap1
);
655 SPARE_BUFFER3
= MXC_NF_V1_SPARE_BUFFER3
+ 4;
657 SPARE_BUFFER3
= MXC_NF_V2_SPARE_BUFFER3
;
658 target_read_u16(target
, SPARE_BUFFER3
, &swap2
);
659 new_swap1
= (swap1
& 0xFF00) | (swap2
>> 8);
660 swap2
= (swap1
<< 8) | (swap2
& 0xFF);
661 target_write_u16(target
, MXC_NF_MAIN_BUFFER3
+ 464, new_swap1
);
662 target_write_u16(target
, SPARE_BUFFER3
, swap2
);
666 target_read_buffer(target
, MXC_NF_MAIN_BUFFER0
, data_size
, data
);
669 target_read_buffer(target
, MXC_NF_V1_SPARE_BUFFER0
, oob_size
, oob
);
671 uint32_t addr
= MXC_NF_V2_SPARE_BUFFER0
;
672 while (oob_size
> 0) {
673 uint8_t len
= MIN(oob_size
, MXC_NF_SPARE_BUFFER_LEN
);
674 target_read_buffer(target
, addr
, len
, oob
);
675 addr
= align_address_v2(nand
, addr
+ len
);
682 #ifdef _MXC_PRINT_STAT
684 /* When Operation Status is read (when page is erased),
685 * this function is used but data_size is null.
687 LOG_INFO("%d bytes newly read", data_size
);
693 static uint32_t align_address_v2(struct nand_device
*nand
, uint32_t addr
)
695 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
697 if (addr
> MXC_NF_V2_SPARE_BUFFER0
&&
698 (addr
& 0x1F) == MXC_NF_SPARE_BUFFER_LEN
)
699 ret
+= MXC_NF_SPARE_BUFFER_MAX
- MXC_NF_SPARE_BUFFER_LEN
;
700 else if (addr
>= (mxc_nf_info
->mxc_base_addr
+ (uint32_t)nand
->page_size
))
701 ret
= MXC_NF_V2_SPARE_BUFFER0
;
705 static int initialize_nf_controller(struct nand_device
*nand
)
707 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
708 struct target
*target
= nand
->target
;
709 uint16_t work_mode
= 0;
712 * resets NAND flash controller in zero time ? I dont know.
714 target_write_u16(target
, MXC_NF_CFG1
, MXC_NF_BIT_RESET_EN
);
715 if (mxc_nf_info
->mxc_version
== MXC_VERSION_MX27
)
716 work_mode
= MXC_NF_BIT_INT_DIS
; /* disable interrupt */
718 if (target
->endianness
== TARGET_BIG_ENDIAN
) {
719 LOG_DEBUG("MXC_NF : work in Big Endian mode");
720 work_mode
|= MXC_NF_BIT_BE_EN
;
722 LOG_DEBUG("MXC_NF : work in Little Endian mode");
723 if (mxc_nf_info
->flags
.hw_ecc_enabled
) {
724 LOG_DEBUG("MXC_NF : work with ECC mode");
725 work_mode
|= MXC_NF_BIT_ECC_EN
;
727 LOG_DEBUG("MXC_NF : work without ECC mode");
729 target_write_u16(target
, MXC_NF_V2_SPAS
, OOB_SIZE
/ 2);
730 if (nand
->page_size
) {
731 uint16_t pages_per_block
= nand
->erase_size
/ nand
->page_size
;
732 work_mode
|= MXC_NF_V2_CFG1_PPB(ffs(pages_per_block
) - 6);
734 work_mode
|= MXC_NF_BIT_ECC_4BIT
;
736 target_write_u16(target
, MXC_NF_CFG1
, work_mode
);
739 * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
741 target_write_u16(target
, MXC_NF_BUFCFG
, 2);
742 target_read_u16(target
, MXC_NF_FWP
, &temp
);
743 if ((temp
& 0x0007) == 1) {
744 LOG_ERROR("NAND flash is tight-locked, reset needed");
749 * unlock NAND flash for write
752 target_write_u16(target
, MXC_NF_V1_UNLOCKSTART
, 0x0000);
753 target_write_u16(target
, MXC_NF_V1_UNLOCKEND
, 0xFFFF);
755 target_write_u16(target
, MXC_NF_V2_UNLOCKSTART0
, 0x0000);
756 target_write_u16(target
, MXC_NF_V2_UNLOCKSTART1
, 0x0000);
757 target_write_u16(target
, MXC_NF_V2_UNLOCKSTART2
, 0x0000);
758 target_write_u16(target
, MXC_NF_V2_UNLOCKSTART3
, 0x0000);
759 target_write_u16(target
, MXC_NF_V2_UNLOCKEND0
, 0xFFFF);
760 target_write_u16(target
, MXC_NF_V2_UNLOCKEND1
, 0xFFFF);
761 target_write_u16(target
, MXC_NF_V2_UNLOCKEND2
, 0xFFFF);
762 target_write_u16(target
, MXC_NF_V2_UNLOCKEND3
, 0xFFFF);
764 target_write_u16(target
, MXC_NF_FWP
, 4);
767 * 0x0000 means that first SRAM buffer @base_addr will be used
769 target_write_u16(target
, MXC_NF_BUFADDR
, 0x0000);
771 * address of SRAM buffer
773 in_sram_address
= MXC_NF_MAIN_BUFFER0
;
774 sign_of_sequental_byte_read
= 0;
778 static int get_next_byte_from_sram_buffer(struct nand_device
*nand
, uint8_t *value
)
780 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
781 struct target
*target
= nand
->target
;
782 static uint8_t even_byte
;
787 if (sign_of_sequental_byte_read
== 0)
790 if (in_sram_address
> (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR
: MXC_NF_V2_LAST_BUFFADDR
)) {
791 LOG_ERROR(sram_buffer_bounds_err_msg
, in_sram_address
);
793 sign_of_sequental_byte_read
= 0;
795 return ERROR_NAND_OPERATION_FAILED
;
798 in_sram_address
= align_address_v2(nand
, in_sram_address
);
800 target_read_u16(target
, in_sram_address
, &temp
);
804 in_sram_address
+= 2;
806 *value
= temp
& 0xff;
810 sign_of_sequental_byte_read
= 1;
814 static int get_next_halfword_from_sram_buffer(struct nand_device
*nand
, uint16_t *value
)
816 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
817 struct target
*target
= nand
->target
;
819 if (in_sram_address
> (nfc_is_v1() ? MXC_NF_V1_LAST_BUFFADDR
: MXC_NF_V2_LAST_BUFFADDR
)) {
820 LOG_ERROR(sram_buffer_bounds_err_msg
, in_sram_address
);
822 return ERROR_NAND_OPERATION_FAILED
;
825 in_sram_address
= align_address_v2(nand
, in_sram_address
);
827 target_read_u16(target
, in_sram_address
, value
);
828 in_sram_address
+= 2;
833 static int poll_for_complete_op(struct nand_device
*nand
, const char *text
)
835 if (mxc_nand_ready(nand
, 1000) == -1) {
836 LOG_ERROR("%s sending timeout", text
);
837 return ERROR_NAND_OPERATION_FAILED
;
842 static int validate_target_state(struct nand_device
*nand
)
844 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
845 struct target
*target
= nand
->target
;
847 if (target
->state
!= TARGET_HALTED
) {
848 LOG_ERROR(target_not_halted_err_msg
);
849 return ERROR_NAND_OPERATION_FAILED
;
852 if (mxc_nf_info
->flags
.target_little_endian
!=
853 (target
->endianness
== TARGET_LITTLE_ENDIAN
)) {
855 * endianness changed after NAND controller probed
857 return ERROR_NAND_OPERATION_FAILED
;
862 int ecc_status_v1(struct nand_device
*nand
)
864 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
865 struct target
*target
= nand
->target
;
868 target_read_u16(target
, MXC_NF_ECCSTATUS
, &ecc_status
);
869 switch (ecc_status
& 0x000c) {
871 LOG_INFO("main area read with 1 (correctable) error");
874 LOG_INFO("main area read with more than 1 (incorrectable) error");
875 return ERROR_NAND_OPERATION_FAILED
;
878 switch (ecc_status
& 0x0003) {
880 LOG_INFO("spare area read with 1 (correctable) error");
883 LOG_INFO("main area read with more than 1 (incorrectable) error");
884 return ERROR_NAND_OPERATION_FAILED
;
890 int ecc_status_v2(struct nand_device
*nand
)
892 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
893 struct target
*target
= nand
->target
;
898 no_subpages
= nand
->page_size
>> 9;
900 target_read_u16(target
, MXC_NF_ECCSTATUS
, &ecc_status
);
902 err
= ecc_status
& 0xF;
904 LOG_INFO("UnCorrectable RS-ECC Error");
905 return ERROR_NAND_OPERATION_FAILED
;
907 LOG_INFO("%d Symbol Correctable RS-ECC Error", err
);
909 } while (--no_subpages
);
913 static int do_data_output(struct nand_device
*nand
)
915 struct mxc_nf_controller
*mxc_nf_info
= nand
->controller_priv
;
916 struct target
*target
= nand
->target
;
918 switch (mxc_nf_info
->fin
) {
919 case MXC_NF_FIN_DATAOUT
:
921 * start data output operation (set MXC_NF_BIT_OP_DONE==0)
923 target_write_u16(target
, MXC_NF_CFG2
, MXC_NF_BIT_DATAOUT_TYPE(mxc_nf_info
->optype
));
924 poll_result
= poll_for_complete_op(nand
, "data output");
925 if (poll_result
!= ERROR_OK
)
928 mxc_nf_info
->fin
= MXC_NF_FIN_NONE
;
932 if (mxc_nf_info
->optype
== MXC_NF_DATAOUT_PAGE
&& mxc_nf_info
->flags
.hw_ecc_enabled
) {
935 ecc_status
= ecc_status_v1(nand
);
937 ecc_status
= ecc_status_v2(nand
);
938 if (ecc_status
!= ERROR_OK
)
942 case MXC_NF_FIN_NONE
:
948 struct nand_flash_controller mxc_nand_flash_controller
= {
950 .nand_device_command
= &mxc_nand_device_command
,
951 .commands
= mxc_nand_command_handler
,
954 .command
= &mxc_command
,
955 .address
= &mxc_address
,
956 .write_data
= &mxc_write_data
,
957 .read_data
= &mxc_read_data
,
958 .write_page
= &mxc_write_page
,
959 .read_page
= &mxc_read_page
,
960 .nand_ready
= &mxc_nand_ready
,
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