src/flash/nand/mxc.h

   1
   2 /***************************************************************************
   3  *   Copyright (C) 2009 by Alexei Babich                                   *
   4  *   Rezonans plc., Chelyabinsk, Russia                                    *
   5  *   impatt@mail.ru                                                        *
   6  *                                                                         *
   7  *   Copyright (C) 2011 by Erik Ahlen                                      *
   8  *   Avalon Innovation, Sweden                                             *
   9  *                                                                         *
  10  *   This program is free software; you can redistribute it and/or modify  *
  11  *   it under the terms of the GNU General Public License as published by  *
  12  *   the Free Software Foundation; either version 2 of the License, or     *
  13  *   (at your option) any later version.                                   *
  14  *                                                                         *
  15  *   This program is distributed in the hope that it will be useful,       *
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  18  *   GNU General Public License for more details.                          *
  19  *                                                                         *
  20  *   You should have received a copy of the GNU General Public License     *
  21  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  22  ***************************************************************************/
  23
  24 /*
  25  * Freescale iMX OpenOCD NAND Flash controller support.
  26  * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
  27  *
  28  * Many thanks to Ben Dooks for writing s3c24xx driver.
  29  */
  30
  31 #define         MXC_NF_BUFSIZ                           (mxc_nf_info->mxc_regs_addr + 0x00)
  32 #define         MXC_NF_BUFADDR                          (mxc_nf_info->mxc_regs_addr + 0x04)
  33 #define         MXC_NF_FADDR                            (mxc_nf_info->mxc_regs_addr + 0x06)
  34 #define         MXC_NF_FCMD                                     (mxc_nf_info->mxc_regs_addr + 0x08)
  35 #define         MXC_NF_BUFCFG                           (mxc_nf_info->mxc_regs_addr + 0x0a)
  36 #define         MXC_NF_ECCSTATUS                        (mxc_nf_info->mxc_regs_addr + 0x0c)
  37 #define         MXC_NF_ECCMAINPOS                       (mxc_nf_info->mxc_regs_addr + 0x0e)
  38 #define         MXC_NF_V1_ECCSPAREPOS           (mxc_nf_info->mxc_regs_addr + 0x10)
  39 #define         MXC_NF_V2_SPAS                          (mxc_nf_info->mxc_regs_addr + 0x10)
  40 #define         MXC_NF_FWP                                      (mxc_nf_info->mxc_regs_addr + 0x12)
  41 #define         MXC_NF_V1_UNLOCKSTART           (mxc_nf_info->mxc_regs_addr + 0x14)
  42 #define         MXC_NF_V1_UNLOCKEND                     (mxc_nf_info->mxc_regs_addr + 0x16)
  43 #define         MXC_NF_V2_UNLOCKSTART0          (mxc_nf_info->mxc_regs_addr + 0x20)
  44 #define         MXC_NF_V2_UNLOCKSTART1          (mxc_nf_info->mxc_regs_addr + 0x24)
  45 #define         MXC_NF_V2_UNLOCKSTART2          (mxc_nf_info->mxc_regs_addr + 0x28)
  46 #define         MXC_NF_V2_UNLOCKSTART3          (mxc_nf_info->mxc_regs_addr + 0x2c)
  47 #define         MXC_NF_V2_UNLOCKEND0            (mxc_nf_info->mxc_regs_addr + 0x22)
  48 #define         MXC_NF_V2_UNLOCKEND1            (mxc_nf_info->mxc_regs_addr + 0x26)
  49 #define         MXC_NF_V2_UNLOCKEND2            (mxc_nf_info->mxc_regs_addr + 0x2a)
  50 #define         MXC_NF_V2_UNLOCKEND3            (mxc_nf_info->mxc_regs_addr + 0x2e)
  51 #define         MXC_NF_FWPSTATUS                        (mxc_nf_info->mxc_regs_addr + 0x18)
  52  /*
  53   * all bits not marked as self-clearing bit
  54   */
  55 #define         MXC_NF_CFG1                                     (mxc_nf_info->mxc_regs_addr + 0x1a)
  56 #define         MXC_NF_CFG2                                     (mxc_nf_info->mxc_regs_addr + 0x1c)
  57
  58 #define         MXC_NF_MAIN_BUFFER0                     (mxc_nf_info->mxc_base_addr + 0x0000)
  59 #define         MXC_NF_MAIN_BUFFER1                     (mxc_nf_info->mxc_base_addr + 0x0200)
  60 #define         MXC_NF_MAIN_BUFFER2                     (mxc_nf_info->mxc_base_addr + 0x0400)
  61 #define         MXC_NF_MAIN_BUFFER3                     (mxc_nf_info->mxc_base_addr + 0x0600)
  62 #define         MXC_NF_V1_SPARE_BUFFER0         (mxc_nf_info->mxc_base_addr + 0x0800)
  63 #define         MXC_NF_V1_SPARE_BUFFER1         (mxc_nf_info->mxc_base_addr + 0x0810)
  64 #define         MXC_NF_V1_SPARE_BUFFER2         (mxc_nf_info->mxc_base_addr + 0x0820)
  65 #define         MXC_NF_V1_SPARE_BUFFER3         (mxc_nf_info->mxc_base_addr + 0x0830)
  66 #define         MXC_NF_V2_MAIN_BUFFER4          (mxc_nf_info->mxc_base_addr + 0x0800)
  67 #define         MXC_NF_V2_MAIN_BUFFER5          (mxc_nf_info->mxc_base_addr + 0x0a00)
  68 #define         MXC_NF_V2_MAIN_BUFFER6          (mxc_nf_info->mxc_base_addr + 0x0c00)
  69 #define         MXC_NF_V2_MAIN_BUFFER7          (mxc_nf_info->mxc_base_addr + 0x0e00)
  70 #define         MXC_NF_V2_SPARE_BUFFER0         (mxc_nf_info->mxc_base_addr + 0x1000)
  71 #define         MXC_NF_V2_SPARE_BUFFER1         (mxc_nf_info->mxc_base_addr + 0x1040)
  72 #define         MXC_NF_V2_SPARE_BUFFER2         (mxc_nf_info->mxc_base_addr + 0x1080)
  73 #define         MXC_NF_V2_SPARE_BUFFER3         (mxc_nf_info->mxc_base_addr + 0x10c0)
  74 #define         MXC_NF_V2_SPARE_BUFFER4         (mxc_nf_info->mxc_base_addr + 0x1100)
  75 #define         MXC_NF_V2_SPARE_BUFFER5         (mxc_nf_info->mxc_base_addr + 0x1140)
  76 #define         MXC_NF_V2_SPARE_BUFFER6         (mxc_nf_info->mxc_base_addr + 0x1180)
  77 #define         MXC_NF_V2_SPARE_BUFFER7         (mxc_nf_info->mxc_base_addr + 0x11c0)
  78 #define         MXC_NF_MAIN_BUFFER_LEN          512
  79 #define         MXC_NF_SPARE_BUFFER_LEN         16
  80 #define         MXC_NF_SPARE_BUFFER_MAX         64
  81 #define         MXC_NF_V1_LAST_BUFFADDR         ((MXC_NF_V1_SPARE_BUFFER3) + \
  82         MXC_NF_SPARE_BUFFER_LEN - 2)
  83 #define         MXC_NF_V2_LAST_BUFFADDR         ((MXC_NF_V2_SPARE_BUFFER7) + \
  84         MXC_NF_SPARE_BUFFER_LEN - 2)
  85
  86 /* bits in MXC_NF_CFG1 register */
  87 #define         MXC_NF_BIT_ECC_4BIT                     (1<<0)
  88 #define         MXC_NF_BIT_SPARE_ONLY_EN        (1<<2)
  89 #define         MXC_NF_BIT_ECC_EN                       (1<<3)
  90 #define         MXC_NF_BIT_INT_DIS                      (1<<4)
  91 #define         MXC_NF_BIT_BE_EN                        (1<<5)
  92 #define         MXC_NF_BIT_RESET_EN                     (1<<6)
  93 #define         MXC_NF_BIT_FORCE_CE                     (1<<7)
  94 #define         MXC_NF_V2_CFG1_PPB(x)           (((x) & 0x3) << 9)
  95
  96 /* bits in MXC_NF_CFG2 register */
  97
  98 /*Flash Command Input*/
  99 #define         MXC_NF_BIT_OP_FCI                       (1<<0)
 100  /*
 101   * Flash Address Input
 102   */
 103 #define         MXC_NF_BIT_OP_FAI                       (1<<1)
 104  /*
 105   * Flash Data Input
 106   */
 107 #define         MXC_NF_BIT_OP_FDI                       (1<<2)
 108
 109 /* see "enum mx_dataout_type" below */
 110 #define         MXC_NF_BIT_DATAOUT_TYPE(x)      ((x)<<3)
 111 #define         MXC_NF_BIT_OP_DONE                      (1<<15)
 112
 113 #define         MXC_CCM_CGR2                            0x53f80028
 114 #define         MXC_GPR                                         0x43fac008
 115 #define         MX2_FMCR                                        0x10027814
 116 #define         MX2_FMCR_NF_16BIT_SEL           (1<<4)
 117 #define         MX2_FMCR_NF_FMS                         (1<<5)
 118 #define         MX25_RCSR                                       0x53f80018
 119 #define         MX25_RCSR_NF_16BIT_SEL          (1<<14)
 120 #define         MX25_RCSR_NF_FMS                        (1<<8)
 121 #define         MX25_RCSR_NF_4K                         (1<<9)
 122 #define         MX3_PCSR                                        0x53f8000c
 123 #define         MX3_PCSR_NF_16BIT_SEL           (1<<31)
 124 #define         MX3_PCSR_NF_FMS                         (1<<30)
 125 #define         MX35_RCSR                                       0x53f80018
 126 #define         MX35_RCSR_NF_16BIT_SEL          (1<<14)
 127 #define         MX35_RCSR_NF_FMS                        (1<<8)
 128 #define         MX35_RCSR_NF_4K                         (1<<9)
 129
 130 enum mxc_version {
 131         MXC_VERSION_UKWN = 0,
 132         MXC_VERSION_MX25 = 1,
 133         MXC_VERSION_MX27 = 2,
 134         MXC_VERSION_MX31 = 3,
 135         MXC_VERSION_MX35 = 4
 136 };
 137
 138 enum mxc_dataout_type {
 139         MXC_NF_DATAOUT_PAGE = 1,
 140         MXC_NF_DATAOUT_NANDID = 2,
 141         MXC_NF_DATAOUT_NANDSTATUS = 4,
 142 };
 143
 144 enum mxc_nf_finalize_action {
 145         MXC_NF_FIN_NONE,
 146         MXC_NF_FIN_DATAOUT,
 147 };
 148
 149 struct mxc_nf_flags {
 150         unsigned target_little_endian:1;
 151         unsigned nand_readonly:1;
 152         unsigned one_kb_sram:1;
 153         unsigned hw_ecc_enabled:1;
 154         unsigned biswap_enabled:1;
 155 };
 156
 157 struct mxc_nf_controller {
 158         enum mxc_version mxc_version;
 159         uint32_t mxc_base_addr;
 160         uint32_t mxc_regs_addr;
 161         enum mxc_dataout_type optype;
 162         enum mxc_nf_finalize_action fin;
 163         struct mxc_nf_flags flags;
 164 };