3ab2364d64ff9ad2f06ec98ab23d4f7e8beedd50
[openocd.git] / src / flash / nand / orion.c
1 /***************************************************************************
2 * Copyright (C) 2009 by Marvell Semiconductors, Inc. *
3 * Written by Nicolas Pitre <nico at marvell.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
20
21 /*
22 * NAND controller interface for Marvell Orion/Kirkwood SoCs.
23 */
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include "arm_io.h"
31 #include <target/arm.h>
32
33
34 struct orion_nand_controller
35 {
36 struct target *target;
37
38 struct arm_nand_data io;
39
40 uint32_t cmd;
41 uint32_t addr;
42 uint32_t data;
43 };
44
45 #define CHECK_HALTED \
46 do { \
47 if (target->state != TARGET_HALTED) { \
48 LOG_ERROR("NAND flash access requires halted target"); \
49 return ERROR_NAND_OPERATION_FAILED; \
50 } \
51 } while (0)
52
53 static int orion_nand_command(struct nand_device *nand, uint8_t command)
54 {
55 struct orion_nand_controller *hw = nand->controller_priv;
56 struct target *target = hw->target;
57
58 CHECK_HALTED;
59 target_write_u8(target, hw->cmd, command);
60 return ERROR_OK;
61 }
62
63 static int orion_nand_address(struct nand_device *nand, uint8_t address)
64 {
65 struct orion_nand_controller *hw = nand->controller_priv;
66 struct target *target = hw->target;
67
68 CHECK_HALTED;
69 target_write_u8(target, hw->addr, address);
70 return ERROR_OK;
71 }
72
73 static int orion_nand_read(struct nand_device *nand, void *data)
74 {
75 struct orion_nand_controller *hw = nand->controller_priv;
76 struct target *target = hw->target;
77
78 CHECK_HALTED;
79 target_read_u8(target, hw->data, data);
80 return ERROR_OK;
81 }
82
83 static int orion_nand_write(struct nand_device *nand, uint16_t data)
84 {
85 struct orion_nand_controller *hw = nand->controller_priv;
86 struct target *target = hw->target;
87
88 CHECK_HALTED;
89 target_write_u8(target, hw->data, data);
90 return ERROR_OK;
91 }
92
93 static int orion_nand_slow_block_write(struct nand_device *nand, uint8_t *data, int size)
94 {
95 while (size--)
96 orion_nand_write(nand, *data++);
97 return ERROR_OK;
98 }
99
100 static int orion_nand_fast_block_write(struct nand_device *nand, uint8_t *data, int size)
101 {
102 struct orion_nand_controller *hw = nand->controller_priv;
103 int retval;
104
105 hw->io.chunk_size = nand->page_size;
106
107 retval = arm_nandwrite(&hw->io, data, size);
108 if (retval == ERROR_NAND_NO_BUFFER)
109 retval = orion_nand_slow_block_write(nand, data, size);
110
111 return retval;
112 }
113
114 static int orion_nand_reset(struct nand_device *nand)
115 {
116 return orion_nand_command(nand, NAND_CMD_RESET);
117 }
118
119 NAND_DEVICE_COMMAND_HANDLER(orion_nand_device_command)
120 {
121 struct orion_nand_controller *hw;
122 uint32_t base;
123 uint8_t ale, cle;
124
125 if (CMD_ARGC != 3) {
126 LOG_ERROR("arguments must be: <target_id> <NAND_address>\n");
127 return ERROR_NAND_DEVICE_INVALID;
128 }
129
130 hw = calloc(1, sizeof(*hw));
131 if (!hw) {
132 LOG_ERROR("no memory for nand controller\n");
133 return ERROR_NAND_DEVICE_INVALID;
134 }
135
136 nand->controller_priv = hw;
137 hw->target = get_target(CMD_ARGV[1]);
138 if (!hw->target) {
139 LOG_ERROR("target '%s' not defined", CMD_ARGV[1]);
140 free(hw);
141 return ERROR_NAND_DEVICE_INVALID;
142 }
143
144 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], base);
145 cle = 0;
146 ale = 1;
147
148 hw->data = base;
149 hw->cmd = base + (1 << cle);
150 hw->addr = base + (1 << ale);
151
152 hw->io.target = hw->target;
153 hw->io.data = hw->data;
154 hw->io.op = ARM_NAND_NONE;
155
156 return ERROR_OK;
157 }
158
159 static int orion_nand_init(struct nand_device *nand)
160 {
161 return ERROR_OK;
162 }
163
164 struct nand_flash_controller orion_nand_controller =
165 {
166 .name = "orion",
167 .command = orion_nand_command,
168 .address = orion_nand_address,
169 .read_data = orion_nand_read,
170 .write_data = orion_nand_write,
171 .write_block_data = orion_nand_fast_block_write,
172 .reset = orion_nand_reset,
173 .nand_device_command = orion_nand_device_command,
174 .init = orion_nand_init,
175 };
176

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