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88522458d307eae7cf66bec407a173e7677a5111
[openocd.git] / src / flash / nor / aduc702x.c
1 /***************************************************************************
2 * Copyright (C) 2008 by Kevin McGuire *
3 * Copyright (C) 2008 by Marcel Wijlaars *
4 * Copyright (C) 2009 by Michael Ashton *
5 * *
6 * This program is free software; you can redistribute it and/or modify *
7 * it under the terms of the GNU General Public License as published by *
8 * the Free Software Foundation; either version 2 of the License, or *
9 * (at your option) any later version. *
10 * *
11 * This program is distributed in the hope that it will be useful, *
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
14 * GNU General Public License for more details. *
15 * *
16 * You should have received a copy of the GNU General Public License *
17 * along with this program; if not, write to the *
18 * Free Software Foundation, Inc., *
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
20 ***************************************************************************/
21
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include "imp.h"
27 #include <helper/binarybuffer.h>
28 #include <helper/time_support.h>
29 #include <target/algorithm.h>
30 #include <target/arm.h>
31
32 static int aduc702x_build_sector_list(struct flash_bank *bank);
33 static int aduc702x_check_flash_completion(struct target *target, unsigned int timeout_ms);
34 static int aduc702x_set_write_enable(struct target *target, int enable);
35
36 #define ADUC702x_FLASH 0xfffff800
37 #define ADUC702x_FLASH_FEESTA (0*4)
38 #define ADUC702x_FLASH_FEEMOD (1*4)
39 #define ADUC702x_FLASH_FEECON (2*4)
40 #define ADUC702x_FLASH_FEEDAT (3*4)
41 #define ADUC702x_FLASH_FEEADR (4*4)
42 #define ADUC702x_FLASH_FEESIGN (5*4)
43 #define ADUC702x_FLASH_FEEPRO (6*4)
44 #define ADUC702x_FLASH_FEEHIDE (7*4)
45
46 /* flash bank aduc702x 0 0 0 0 <target#>
47 * The ADC7019-28 devices all have the same flash layout */
48 FLASH_BANK_COMMAND_HANDLER(aduc702x_flash_bank_command)
49 {
50 bank->base = 0x80000;
51 bank->size = 0xF800; /* top 4k not accessible */
52
53 aduc702x_build_sector_list(bank);
54
55 return ERROR_OK;
56 }
57
58 static int aduc702x_build_sector_list(struct flash_bank *bank)
59 {
60 /* aduc7026_struct flash_bank *aduc7026_info = bank->driver_priv; */
61
62 int i = 0;
63 uint32_t offset = 0;
64
65 /* sector size is 512 */
66 bank->num_sectors = bank->size / 512;
67 bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
68 for (i = 0; i < bank->num_sectors; ++i) {
69 bank->sectors[i].offset = offset;
70 bank->sectors[i].size = 512;
71 offset += bank->sectors[i].size;
72 bank->sectors[i].is_erased = -1;
73 bank->sectors[i].is_protected = 0;
74 }
75
76 return ERROR_OK;
77 }
78
79 static int aduc702x_protect_check(struct flash_bank *bank)
80 {
81 printf("aduc702x_protect_check not implemented yet.\n");
82 return ERROR_OK;
83 }
84
85 static int aduc702x_erase(struct flash_bank *bank, int first, int last)
86 {
87 /* int res; */
88 int x;
89 int count;
90 /* uint32_t v; */
91 struct target *target = bank->target;
92
93 aduc702x_set_write_enable(target, 1);
94
95 /* mass erase */
96 if (((first | last) == 0) || ((first == 0) && (last >= bank->num_sectors))) {
97 LOG_DEBUG("performing mass erase.");
98 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEDAT, 0x3cff);
99 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, 0xffc3);
100 target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x06);
101
102 if (aduc702x_check_flash_completion(target, 3500) != ERROR_OK) {
103 LOG_ERROR("mass erase failed");
104 aduc702x_set_write_enable(target, 0);
105 return ERROR_FLASH_OPERATION_FAILED;
106 }
107
108 LOG_DEBUG("mass erase successful.");
109 return ERROR_OK;
110 } else {
111 unsigned long adr;
112
113 count = last - first + 1;
114 for (x = 0; x < count; ++x) {
115 adr = bank->base + ((first + x) * 512);
116
117 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, adr);
118 target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x05);
119
120 if (aduc702x_check_flash_completion(target, 50) != ERROR_OK) {
121 LOG_ERROR("failed to erase sector at address 0x%08lX", adr);
122 aduc702x_set_write_enable(target, 0);
123 return ERROR_FLASH_SECTOR_NOT_ERASED;
124 }
125
126 LOG_DEBUG("erased sector at address 0x%08lX", adr);
127 }
128 }
129
130 aduc702x_set_write_enable(target, 0);
131
132 return ERROR_OK;
133 }
134
135 static int aduc702x_protect(struct flash_bank *bank, int set, int first, int last)
136 {
137 printf("aduc702x_protect not implemented yet.\n");
138 return ERROR_FLASH_OPERATION_FAILED;
139 }
140
141 /* If this fn returns ERROR_TARGET_RESOURCE_NOT_AVAILABLE, then the caller can fall
142 * back to another mechanism that does not require onboard RAM
143 *
144 * Caller should not check for other return values specifically
145 */
146 static int aduc702x_write_block(struct flash_bank *bank,
147 const uint8_t *buffer,
148 uint32_t offset,
149 uint32_t count)
150 {
151 struct target *target = bank->target;
152 uint32_t buffer_size = 7000;
153 struct working_area *write_algorithm;
154 struct working_area *source;
155 uint32_t address = bank->base + offset;
156 struct reg_param reg_params[6];
157 struct arm_algorithm arm_algo;
158 int retval = ERROR_OK;
159
160 if (((count%2) != 0) || ((offset%2) != 0)) {
161 LOG_ERROR("write block must be multiple of two bytes in offset & length");
162 return ERROR_FAIL;
163 }
164
165 /* parameters:
166
167 r0 - address of source data (absolute)
168 r1 - number of halfwords to be copied
169 r2 - start address in flash (offset from beginning of flash memory)
170 r3 - exit code
171 r4 - base address of flash controller (0xFFFFF800)
172
173 registers:
174
175 r5 - scratch
176 r6 - set to 2, used to write flash command
177
178 */
179 static const uint32_t aduc702x_flash_write_code[] = {
180 /* <_start>: */
181 0xe3a05008, /* mov r5, #8 ; 0x8 */
182 0xe5845004, /* str r5, [r4, #4] */
183 0xe3a06002, /* mov r6, #2 ; 0x2 */
184 /* <next>: */
185 0xe1c421b0, /* strh r2, [r4, #16] */
186 0xe0d050b2, /* ldrh r5, [r0], #2 */
187 0xe1c450bc, /* strh r5, [r4, #12] */
188 0xe5c46008, /* strb r6, [r4, #8] */
189 /* <wait_complete>: */
190 0xe1d430b0, /* ldrh r3, [r4] */
191 0xe3130004, /* tst r3, #4 ; 0x4 */
192 0x1afffffc, /* bne 1001c <wait_complete> */
193 0xe2822002, /* add r2, r2, #2 ; 0x2 */
194 0xe2511001, /* subs r1, r1, #1 ; 0x1 */
195 0x0a000001, /* beq 1003c <done> */
196 0xe3130001, /* tst r3, #1 ; 0x1 */
197 0x1afffff3, /* bne 1000c <next> */
198 /* <done>: */
199 0xeafffffe /* b 1003c <done> */
200 };
201
202 /* flash write code */
203 if (target_alloc_working_area(target, sizeof(aduc702x_flash_write_code),
204 &write_algorithm) != ERROR_OK) {
205 LOG_WARNING("no working area available, can't do block memory writes");
206 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
207 }
208
209 uint8_t code[sizeof(aduc702x_flash_write_code)];
210 target_buffer_set_u32_array(target, code, ARRAY_SIZE(aduc702x_flash_write_code),
211 aduc702x_flash_write_code);
212 retval = target_write_buffer(target, write_algorithm->address, sizeof(code), code);
213 if (retval != ERROR_OK)
214 return retval;
215
216 /* memory buffer */
217 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
218 buffer_size /= 2;
219 if (buffer_size <= 256) {
220 /* we already allocated the writing code, but failed to get a buffer,
221 *free the algorithm */
222 target_free_working_area(target, write_algorithm);
223
224 LOG_WARNING("no large enough working area available, can't do block memory writes");
225 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
226 }
227 }
228
229 arm_algo.common_magic = ARM_COMMON_MAGIC;
230 arm_algo.core_mode = ARM_MODE_SVC;
231 arm_algo.core_state = ARM_STATE_ARM;
232
233 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
234 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
235 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
236 init_reg_param(&reg_params[3], "r3", 32, PARAM_IN);
237 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
238
239 while (count > 0) {
240 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
241
242 retval = target_write_buffer(target, source->address, thisrun_count, buffer);
243 if (retval != ERROR_OK)
244 break;
245
246 buf_set_u32(reg_params[0].value, 0, 32, source->address);
247 buf_set_u32(reg_params[1].value, 0, 32, thisrun_count/2);
248 buf_set_u32(reg_params[2].value, 0, 32, address);
249 buf_set_u32(reg_params[4].value, 0, 32, 0xFFFFF800);
250
251 retval = target_run_algorithm(target, 0, NULL, 5,
252 reg_params, write_algorithm->address,
253 write_algorithm->address +
254 sizeof(aduc702x_flash_write_code) - 4,
255 10000, &arm_algo);
256 if (retval != ERROR_OK) {
257 LOG_ERROR("error executing aduc702x flash write algorithm");
258 break;
259 }
260
261 if ((buf_get_u32(reg_params[3].value, 0, 32) & 1) != 1) {
262 /* FIX!!!! what does this mean??? replace w/sensible error message */
263 LOG_ERROR("aduc702x detected error writing flash");
264 retval = ERROR_FAIL;
265 break;
266 }
267
268 buffer += thisrun_count;
269 address += thisrun_count;
270 count -= thisrun_count;
271 }
272
273 target_free_working_area(target, source);
274 target_free_working_area(target, write_algorithm);
275
276 destroy_reg_param(&reg_params[0]);
277 destroy_reg_param(&reg_params[1]);
278 destroy_reg_param(&reg_params[2]);
279 destroy_reg_param(&reg_params[3]);
280 destroy_reg_param(&reg_params[4]);
281
282 return retval;
283 }
284
285 /* All-JTAG, single-access method. Very slow. Used only if there is no
286 * working area available. */
287 static int aduc702x_write_single(struct flash_bank *bank,
288 const uint8_t *buffer,
289 uint32_t offset,
290 uint32_t count)
291 {
292 uint32_t x;
293 uint8_t b;
294 struct target *target = bank->target;
295
296 aduc702x_set_write_enable(target, 1);
297
298 for (x = 0; x < count; x += 2) {
299 /* FEEADR = address */
300 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEADR, offset + x);
301
302 /* set up data */
303 if ((x + 1) == count) {
304 /* last byte */
305 target_read_u8(target, offset + x + 1, &b);
306 } else
307 b = buffer[x + 1];
308
309 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEDAT, buffer[x] | (b << 8));
310
311 /* do single-write command */
312 target_write_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEECON, 0x02);
313
314 if (aduc702x_check_flash_completion(target, 1) != ERROR_OK) {
315 LOG_ERROR("single write failed for address 0x%08lX",
316 (unsigned long)(offset + x));
317 aduc702x_set_write_enable(target, 0);
318 return ERROR_FLASH_OPERATION_FAILED;
319 }
320
321 }
322 LOG_DEBUG("wrote %d bytes at address 0x%08lX", (int)count, (unsigned long)(offset + x));
323
324 aduc702x_set_write_enable(target, 0);
325
326 return ERROR_OK;
327 }
328
329 static int aduc702x_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
330 {
331 int retval;
332
333 /* try using a block write */
334 retval = aduc702x_write_block(bank, buffer, offset, count);
335 if (retval != ERROR_OK) {
336 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
337 /* if block write failed (no sufficient working area),
338 * use normal (slow) JTAG method */
339 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
340
341 retval = aduc702x_write_single(bank, buffer, offset, count);
342 if (retval != ERROR_OK) {
343 LOG_ERROR("slow write failed");
344 return ERROR_FLASH_OPERATION_FAILED;
345 }
346 }
347 }
348
349 return retval;
350 }
351
352 static int aduc702x_probe(struct flash_bank *bank)
353 {
354 return ERROR_OK;
355 }
356
357 /* sets FEEMOD bit 3
358 * enable = 1 enables writes & erases, 0 disables them */
359 static int aduc702x_set_write_enable(struct target *target, int enable)
360 {
361 /* don't bother to preserve int enable bit here */
362 target_write_u16(target, ADUC702x_FLASH + ADUC702x_FLASH_FEEMOD, enable ? 8 : 0);
363
364 return ERROR_OK;
365 }
366
367 /* wait up to timeout_ms for controller to not be busy,
368 * then check whether the command passed or failed.
369 *
370 * this function sleeps 1ms between checks (after the first one),
371 * so in some cases may slow things down without a usleep after the first read */
372 static int aduc702x_check_flash_completion(struct target *target, unsigned int timeout_ms)
373 {
374 uint8_t v = 4;
375
376 long long endtime = timeval_ms() + timeout_ms;
377 while (1) {
378 target_read_u8(target, ADUC702x_FLASH + ADUC702x_FLASH_FEESTA, &v);
379 if ((v & 4) == 0)
380 break;
381 alive_sleep(1);
382 if (timeval_ms() >= endtime)
383 break;
384 }
385
386 if (v & 2)
387 return ERROR_FAIL;
388 /* if a command is ignored, both the success and fail bits may be 0 */
389 else if ((v & 3) == 0)
390 return ERROR_FAIL;
391 else
392 return ERROR_OK;
393 }
394
395 struct flash_driver aduc702x_flash = {
396 .name = "aduc702x",
397 .flash_bank_command = aduc702x_flash_bank_command,
398 .erase = aduc702x_erase,
399 .protect = aduc702x_protect,
400 .write = aduc702x_write,
401 .read = default_flash_read,
402 .probe = aduc702x_probe,
403 .auto_probe = aduc702x_probe,
404 .erase_check = default_flash_blank_check,
405 .protect_check = aduc702x_protect_check,
406 };
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