src/flash/nor/ambiqmicro.c

   1 // SPDX-License-Identifier: BSD-3-Clause
   2
   3 /******************************************************************************
   4  *
   5  * @file ambiqmicro.c
   6  *
   7  * @brief Ambiq Micro flash driver.
   8  *
   9  *****************************************************************************/
  10
  11 /******************************************************************************
  12  * Copyright (c) 2015, David Racine <dracine at ambiqmicro.com>
  13  *
  14  * Copyright (c) 2016, Rick Foos <rfoos at solengtech.com>
  15  *
  16  * Copyright (c) 2015-2016, Ambiq Micro, Inc.
  17  *
  18  * All rights reserved.
  19  *****************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "jtag/interface.h"
  25 #include "imp.h"
  26 #include "target/algorithm.h"
  27 #include "target/armv7m.h"
  28 #include "target/cortex_m.h"
  29
  30 /** Check error, log error. */
  31 #define CHECK_STATUS(rc, msg) { \
  32                 if (rc != ERROR_OK) { \
  33                         LOG_ERROR("status(%d):%s\n", rc, msg); } }
  34
  35 /*
  36  * Address and Key defines.
  37  */
  38 #define PROGRAM_KEY      (0x12344321)
  39 #define OTP_PROGRAM_KEY  (0x87655678)
  40
  41 #define FLASH_PROGRAM_MAIN_FROM_SRAM                0x0800005d
  42 #define FLASH_PROGRAM_OTP_FROM_SRAM                 0x08000061
  43 #define FLASH_ERASE_LIST_MAIN_PAGES_FROM_SRAM       0x08000065
  44 #define FLASH_MASS_ERASE_MAIN_PAGES_FROM_SRAM       0x08000069
  45
  46
  47 static const uint32_t apollo_flash_size[] = {
  48         1 << 15,
  49         1 << 16,
  50         1 << 17,
  51         1 << 18,
  52         1 << 19,
  53         1 << 20,
  54         1 << 21
  55 };
  56
  57 static const uint32_t apollo_sram_size[] = {
  58         1 << 15,
  59         1 << 16,
  60         1 << 17,
  61         1 << 18,
  62         1 << 19,
  63         1 << 20,
  64         1 << 21
  65 };
  66
  67 struct ambiqmicro_flash_bank {
  68         /* chip id register */
  69
  70         bool probed;
  71
  72         const char *target_name;
  73         uint8_t target_class;
  74
  75         uint32_t sramsiz;
  76         uint32_t flshsiz;
  77
  78         /* flash geometry */
  79         uint32_t num_pages;
  80         uint32_t pagesize;
  81         uint32_t pages_in_lockregion;
  82
  83         /* nv memory bits */
  84         uint16_t num_lockbits;
  85
  86         /* main clock status */
  87         uint32_t rcc;
  88         uint32_t rcc2;
  89         uint8_t mck_valid;
  90         uint8_t xtal_mask;
  91         uint32_t iosc_freq;
  92         uint32_t mck_freq;
  93         const char *iosc_desc;
  94         const char *mck_desc;
  95 };
  96
  97 static struct {
  98         uint8_t class;
  99         uint8_t partno;
 100         const char *partname;
 101 } ambiqmicro_parts[6] = {
 102         {0xFF, 0x00, "Unknown"},
 103         {0x01, 0x00, "Apollo"},
 104         {0x02, 0x00, "Apollo2"},
 105         {0x03, 0x00, "Unknown"},
 106         {0x04, 0x00, "Unknown"},
 107         {0x05, 0x00, "Apollo"},
 108 };
 109
 110 static char *ambiqmicro_classname[6] = {
 111         "Unknown", "Apollo", "Apollo2", "Unknown", "Unknown", "Apollo"
 112 };
 113
 114 /***************************************************************************
 115 *       openocd command interface                                              *
 116 ***************************************************************************/
 117
 118 /* flash_bank ambiqmicro <base> <size> 0 0 <target#>
 119  */
 120 FLASH_BANK_COMMAND_HANDLER(ambiqmicro_flash_bank_command)
 121 {
 122         struct ambiqmicro_flash_bank *ambiqmicro_info;
 123
 124         if (CMD_ARGC < 6)
 125                 return ERROR_COMMAND_SYNTAX_ERROR;
 126
 127         ambiqmicro_info = calloc(sizeof(struct ambiqmicro_flash_bank), 1);
 128
 129         bank->driver_priv = ambiqmicro_info;
 130
 131         ambiqmicro_info->target_name = "Unknown target";
 132
 133         /* part wasn't probed yet */
 134         ambiqmicro_info->probed = false;
 135
 136         return ERROR_OK;
 137 }
 138
 139 static int get_ambiqmicro_info(struct flash_bank *bank, struct command_invocation *cmd)
 140 {
 141         struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
 142         char *classname;
 143
 144         if (!ambiqmicro_info->probed) {
 145                 LOG_ERROR("Target not probed");
 146                 return ERROR_FLASH_BANK_NOT_PROBED;
 147         }
 148
 149         /* Check class name in range. */
 150         if (ambiqmicro_info->target_class < sizeof(ambiqmicro_classname))
 151                 classname = ambiqmicro_classname[ambiqmicro_info->target_class];
 152         else
 153                 classname = ambiqmicro_classname[0];
 154
 155         command_print_sameline(cmd, "\nAmbiq Micro information: Chip is "
 156                 "class %d (%s) %s\n",
 157                 ambiqmicro_info->target_class,
 158                 classname,
 159                 ambiqmicro_info->target_name);
 160
 161         return ERROR_OK;
 162 }
 163
 164 /***************************************************************************
 165 *       chip identification and status                                         *
 166 ***************************************************************************/
 167
 168 /* Fill in driver info structure */
 169 static int ambiqmicro_read_part_info(struct flash_bank *bank)
 170 {
 171         struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
 172         struct target *target = bank->target;
 173         uint32_t part_num = 0;
 174         int retval;
 175
 176         /*
 177          * Read Part Number.
 178          */
 179         retval = target_read_u32(target, 0x40020000, &part_num);
 180         if (retval != ERROR_OK) {
 181                 LOG_ERROR("status(0x%x):Could not read part_num.\n", retval);
 182                 /* Set part_num to default device */
 183                 part_num = 0;
 184         }
 185         LOG_DEBUG("Part number: 0x%" PRIx32, part_num);
 186
 187         /*
 188          * Determine device class.
 189          */
 190         ambiqmicro_info->target_class = (part_num & 0xFF000000) >> 24;
 191
 192         switch (ambiqmicro_info->target_class) {
 193                 case 1:         /* 1 - Apollo */
 194                 case 5:         /* 5 - Apollo Bootloader */
 195                         bank->base = bank->bank_number * 0x40000;
 196                         ambiqmicro_info->pagesize = 2048;
 197                         ambiqmicro_info->flshsiz =
 198                         apollo_flash_size[(part_num & 0x00F00000) >> 20];
 199                         ambiqmicro_info->sramsiz =
 200                         apollo_sram_size[(part_num & 0x000F0000) >> 16];
 201                         ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz /
 202                         ambiqmicro_info->pagesize;
 203                         if (ambiqmicro_info->num_pages > 128) {
 204                                 ambiqmicro_info->num_pages = 128;
 205                                 ambiqmicro_info->flshsiz = 1024 * 256;
 206                         }
 207                         break;
 208
 209                 default:
 210                         LOG_INFO("Unknown Class. Using Apollo-64 as default.");
 211
 212                         bank->base = bank->bank_number * 0x40000;
 213                         ambiqmicro_info->pagesize = 2048;
 214                         ambiqmicro_info->flshsiz = apollo_flash_size[1];
 215                         ambiqmicro_info->sramsiz = apollo_sram_size[0];
 216                         ambiqmicro_info->num_pages = ambiqmicro_info->flshsiz /
 217                         ambiqmicro_info->pagesize;
 218                         if (ambiqmicro_info->num_pages > 128) {
 219                                 ambiqmicro_info->num_pages = 128;
 220                                 ambiqmicro_info->flshsiz = 1024 * 256;
 221                         }
 222                         break;
 223
 224         }
 225
 226         if (ambiqmicro_info->target_class < ARRAY_SIZE(ambiqmicro_parts))
 227                 ambiqmicro_info->target_name =
 228                         ambiqmicro_parts[ambiqmicro_info->target_class].partname;
 229         else
 230                 ambiqmicro_info->target_name =
 231                         ambiqmicro_parts[0].partname;
 232
 233         LOG_DEBUG("num_pages: %" PRIu32 ", pagesize: %" PRIu32 ", flash: %" PRIu32 ", sram: %" PRIu32,
 234                 ambiqmicro_info->num_pages,
 235                 ambiqmicro_info->pagesize,
 236                 ambiqmicro_info->flshsiz,
 237                 ambiqmicro_info->sramsiz);
 238
 239         return ERROR_OK;
 240 }
 241
 242 /***************************************************************************
 243 *       flash operations                                                       *
 244 ***************************************************************************/
 245
 246 static int ambiqmicro_protect_check(struct flash_bank *bank)
 247 {
 248         struct ambiqmicro_flash_bank *ambiqmicro = bank->driver_priv;
 249         int status = ERROR_OK;
 250         uint32_t i;
 251
 252
 253         if (!ambiqmicro->probed) {
 254                 LOG_ERROR("Target not probed");
 255                 return ERROR_FLASH_BANK_NOT_PROBED;
 256         }
 257
 258         for (i = 0; i < (unsigned) bank->num_sectors; i++)
 259                 bank->sectors[i].is_protected = -1;
 260
 261         return status;
 262 }
 263 /** Read flash status from bootloader. */
 264 static int check_flash_status(struct target *target, uint32_t address)
 265 {
 266         uint32_t retflash;
 267         int rc;
 268         rc = target_read_u32(target, address, &retflash);
 269         /* target connection failed. */
 270         if (rc != ERROR_OK) {
 271                 LOG_DEBUG("%s:%d:%s(): status(0x%x)\n",
 272                         __FILE__, __LINE__, __func__, rc);
 273                 return rc;
 274         }
 275         /* target flash failed, unknown cause. */
 276         if (retflash != 0) {
 277                 LOG_ERROR("Flash not happy: status(0x%" PRIx32 ")", retflash);
 278                 return ERROR_FLASH_OPERATION_FAILED;
 279         }
 280         return ERROR_OK;
 281 }
 282
 283 static int ambiqmicro_exec_command(struct target *target,
 284         uint32_t command,
 285         uint32_t flash_return_address)
 286 {
 287         int retval, retflash;
 288
 289         retval = target_resume(
 290                 target,
 291                 false,
 292                 command,
 293                 true,
 294                 true);
 295
 296         CHECK_STATUS(retval, "error executing ambiqmicro command");
 297
 298         /*
 299          * Wait for halt.
 300          */
 301         for (;; ) {
 302                 target_poll(target);
 303                 if (target->state == TARGET_HALTED)
 304                         break;
 305                 else if (target->state == TARGET_RUNNING ||
 306                         target->state == TARGET_DEBUG_RUNNING) {
 307                         /*
 308                          * Keep polling until target halts.
 309                          */
 310                         target_poll(target);
 311                         alive_sleep(100);
 312                         LOG_DEBUG("state = %d", target->state);
 313                 } else {
 314                         LOG_ERROR("Target not halted or running %d", target->state);
 315                         break;
 316                 }
 317         }
 318
 319         /*
 320          * Read return value, flash error takes precedence.
 321          */
 322         retflash = check_flash_status(target, flash_return_address);
 323         if (retflash != ERROR_OK)
 324                 retval = retflash;
 325
 326         /* Return code from target_resume OR flash. */
 327         return retval;
 328 }
 329
 330 static int ambiqmicro_mass_erase(struct flash_bank *bank)
 331 {
 332         struct target *target = NULL;
 333         struct ambiqmicro_flash_bank *ambiqmicro_info = NULL;
 334         int retval = ERROR_OK;
 335
 336         ambiqmicro_info = bank->driver_priv;
 337         target = bank->target;
 338
 339         if (target->state != TARGET_HALTED) {
 340                 LOG_ERROR("Target not halted");
 341                 return ERROR_TARGET_NOT_HALTED;
 342         }
 343
 344         if (!ambiqmicro_info->probed) {
 345                 LOG_ERROR("Target not probed");
 346                 return ERROR_FLASH_BANK_NOT_PROBED;
 347         }
 348
 349         /*
 350          * Clear Bootloader bit.
 351          */
 352         retval = target_write_u32(target, 0x400201a0, 0x0);
 353         CHECK_STATUS(retval, "error clearing bootloader bit.");
 354
 355         /*
 356          * Set up the SRAM.
 357          */
 358
 359         /*
 360          * Bank.
 361          */
 362         retval = target_write_u32(target, 0x10000000, bank->bank_number);
 363         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 364
 365         /*
 366          * Write Key.
 367          */
 368         retval = target_write_u32(target, 0x10000004, PROGRAM_KEY);
 369         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 370
 371         /*
 372          * Breakpoint.
 373          */
 374         retval = target_write_u32(target, 0x10000008, 0xfffffffe);
 375         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 376
 377         /*
 378          * Erase the main array.
 379          */
 380         LOG_INFO("Mass erase on bank %d.", bank->bank_number);
 381
 382         /*
 383          * passed pc, addr = ROM function, handle breakpoints, not debugging.
 384          */
 385         retval = ambiqmicro_exec_command(target, FLASH_MASS_ERASE_MAIN_PAGES_FROM_SRAM, 0x10000008);
 386         CHECK_STATUS(retval, "error executing ambiqmicro flash mass erase.");
 387         if (retval != ERROR_OK)
 388                 return retval;
 389
 390         /*
 391          * Set Bootloader bit, regardless of command execution.
 392          */
 393         retval = target_write_u32(target, 0x400201a0, 0x1);
 394         CHECK_STATUS(retval, "error setting bootloader bit.");
 395
 396         return retval;
 397 }
 398
 399
 400 static int ambiqmicro_erase(struct flash_bank *bank, unsigned int first,
 401                 unsigned int last)
 402 {
 403         struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
 404         struct target *target = bank->target;
 405         int retval;
 406
 407         if (bank->target->state != TARGET_HALTED) {
 408                 LOG_ERROR("Target not halted");
 409                 return ERROR_TARGET_NOT_HALTED;
 410         }
 411
 412         if (!ambiqmicro_info->probed) {
 413                 LOG_ERROR("Target not probed");
 414                 return ERROR_FLASH_BANK_NOT_PROBED;
 415         }
 416
 417         /*
 418          * Check pages.
 419          * Fix num_pages for the device.
 420          */
 421         if ((last < first) || (last >= ambiqmicro_info->num_pages))
 422                 return ERROR_FLASH_SECTOR_INVALID;
 423
 424         /*
 425          * Just Mass Erase if all pages are given.
 426          * TODO: Fix num_pages for the device
 427          */
 428         if ((first == 0) && (last == (ambiqmicro_info->num_pages - 1)))
 429                 return ambiqmicro_mass_erase(bank);
 430
 431         /*
 432          * Clear Bootloader bit.
 433          */
 434         retval = target_write_u32(target, 0x400201a0, 0x0);
 435         CHECK_STATUS(retval, "error clearing bootloader bit.");
 436
 437         /*
 438          * Set up the SRAM.
 439          */
 440
 441         /*
 442          * Bank.
 443          */
 444         retval = target_write_u32(target, 0x10000000, bank->bank_number);
 445         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 446
 447         /*
 448          * Number of pages to erase.
 449          */
 450         retval = target_write_u32(target, 0x10000004, 1 + (last-first));
 451         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 452
 453         /*
 454          * Write Key.
 455          */
 456         retval = target_write_u32(target, 0x10000008, PROGRAM_KEY);
 457         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 458
 459         /*
 460          * Breakpoint.
 461          */
 462         retval = target_write_u32(target, 0x1000000c, 0xfffffffe);
 463         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 464
 465         /*
 466          * Pointer to flash address.
 467          */
 468         retval = target_write_u32(target, 0x10000010, first);
 469         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 470         if (retval != ERROR_OK)
 471                 return retval;
 472
 473         /*
 474          * Erase the pages.
 475          */
 476         LOG_INFO("Erasing pages %u to %u on bank %u", first, last, bank->bank_number);
 477
 478         /*
 479          * passed pc, addr = ROM function, handle breakpoints, not debugging.
 480          */
 481         retval = ambiqmicro_exec_command(target, FLASH_ERASE_LIST_MAIN_PAGES_FROM_SRAM, 0x1000000C);
 482         CHECK_STATUS(retval, "error executing flash page erase");
 483         if (retval != ERROR_OK)
 484                 return retval;
 485
 486         LOG_INFO("%u pages erased!", 1+(last-first));
 487
 488         if (first == 0) {
 489                 /*
 490                  * Set Bootloader bit.
 491                  */
 492                 retval = target_write_u32(target, 0x400201a0, 0x1);
 493                 CHECK_STATUS(retval, "error setting bootloader bit.");
 494                 if (retval != ERROR_OK)
 495                         return retval;
 496         }
 497
 498         return retval;
 499 }
 500
 501 static int ambiqmicro_protect(struct flash_bank *bank, int set,
 502                 unsigned int first, unsigned int last)
 503 {
 504         /* struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
 505          * struct target *target = bank->target; */
 506
 507         /*
 508          * TODO
 509          */
 510         LOG_INFO("Not yet implemented");
 511
 512         if (bank->target->state != TARGET_HALTED) {
 513                 LOG_ERROR("Target not halted");
 514                 return ERROR_TARGET_NOT_HALTED;
 515         }
 516
 517         return ERROR_OK;
 518 }
 519
 520 static int ambiqmicro_write_block(struct flash_bank *bank,
 521         const uint8_t *buffer, uint32_t offset, uint32_t count)
 522 {
 523         /* struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv; */
 524         struct target *target = bank->target;
 525         uint32_t address = bank->base + offset;
 526         uint32_t buffer_pointer = 0x10000010;
 527         uint32_t maxbuffer;
 528         uint32_t thisrun_count;
 529         int retval = ERROR_OK;
 530
 531         if (((count%4) != 0) || ((offset%4) != 0)) {
 532                 LOG_ERROR("write block must be multiple of 4 bytes in offset & length");
 533                 return ERROR_FAIL;
 534         }
 535
 536         /*
 537          * Max buffer size for this device.
 538          * Hard code 6kB for the buffer.
 539          */
 540         maxbuffer = 0x1800;
 541
 542         LOG_INFO("Flashing main array");
 543
 544         while (count > 0) {
 545                 if (count > maxbuffer)
 546                         thisrun_count = maxbuffer;
 547                 else
 548                         thisrun_count = count;
 549
 550                 /*
 551                  * Set up the SRAM.
 552                  */
 553
 554                 /*
 555                  * Pointer to flash.
 556                  */
 557                 retval = target_write_u32(target, 0x10000000, address);
 558                 CHECK_STATUS(retval, "error writing target SRAM parameters.");
 559
 560                 /*
 561                  * Number of 32-bit words to program.
 562                  */
 563                 retval = target_write_u32(target, 0x10000004, thisrun_count/4);
 564                 CHECK_STATUS(retval, "error writing target SRAM parameters.");
 565
 566                 /*
 567                  * Write Key.
 568                  */
 569                 retval = target_write_u32(target, 0x10000008, PROGRAM_KEY);
 570                 CHECK_STATUS(retval, "error writing target SRAM parameters.");
 571
 572                 /*
 573                  * Breakpoint.
 574                  */
 575                 retval = target_write_u32(target, 0x1000000c, 0xfffffffe);
 576                 CHECK_STATUS(retval, "error writing target SRAM parameters.");
 577
 578                 /*
 579                  * Write Buffer.
 580                  */
 581                 retval = target_write_buffer(target, buffer_pointer, thisrun_count, buffer);
 582
 583                 if (retval != ERROR_OK) {
 584                         CHECK_STATUS(retval, "error writing target SRAM parameters.");
 585                         break;
 586                 }
 587
 588                 LOG_DEBUG("address = 0x%08" PRIx32, address);
 589
 590                 retval = ambiqmicro_exec_command(target, FLASH_PROGRAM_MAIN_FROM_SRAM, 0x1000000c);
 591                 CHECK_STATUS(retval, "error executing ambiqmicro flash write algorithm");
 592                 if (retval != ERROR_OK)
 593                         break;
 594                 buffer += thisrun_count;
 595                 address += thisrun_count;
 596                 count -= thisrun_count;
 597         }
 598
 599
 600         LOG_INFO("Main array flashed");
 601
 602         /*
 603          * Clear Bootloader bit.
 604          */
 605         retval = target_write_u32(target, 0x400201a0, 0x0);
 606         CHECK_STATUS(retval, "error clearing bootloader bit");
 607
 608         return retval;
 609 }
 610
 611 static int ambiqmicro_write(struct flash_bank *bank, const uint8_t *buffer,
 612         uint32_t offset, uint32_t count)
 613 {
 614         int retval;
 615
 616         /* try using a block write */
 617         retval = ambiqmicro_write_block(bank, buffer, offset, count);
 618         if (retval != ERROR_OK)
 619                 LOG_ERROR("write failed");
 620
 621         return retval;
 622 }
 623
 624 static int ambiqmicro_probe(struct flash_bank *bank)
 625 {
 626         struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
 627         int retval;
 628
 629         /* If this is a ambiqmicro chip, it has flash; probe() is just
 630          * to figure out how much is present.  Only do it once.
 631          */
 632         if (ambiqmicro_info->probed) {
 633                 LOG_INFO("Target already probed");
 634                 return ERROR_OK;
 635         }
 636
 637         /* ambiqmicro_read_part_info() already handled error checking and
 638          * reporting.  Note that it doesn't write, so we don't care about
 639          * whether the target is halted or not.
 640          */
 641         retval = ambiqmicro_read_part_info(bank);
 642         if (retval != ERROR_OK)
 643                 return retval;
 644
 645         free(bank->sectors);
 646
 647         /* provide this for the benefit of the NOR flash framework */
 648         bank->size = ambiqmicro_info->pagesize * ambiqmicro_info->num_pages;
 649         bank->num_sectors = ambiqmicro_info->num_pages;
 650         bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
 651         for (unsigned int i = 0; i < bank->num_sectors; i++) {
 652                 bank->sectors[i].offset = i * ambiqmicro_info->pagesize;
 653                 bank->sectors[i].size = ambiqmicro_info->pagesize;
 654                 bank->sectors[i].is_erased = -1;
 655                 bank->sectors[i].is_protected = -1;
 656         }
 657
 658         /*
 659          * Part has been probed.
 660          */
 661         ambiqmicro_info->probed = true;
 662
 663         return retval;
 664 }
 665
 666 static int ambiqmicro_otp_program(struct flash_bank *bank,
 667         uint32_t offset, uint32_t count)
 668 {
 669         struct target *target = NULL;
 670         struct ambiqmicro_flash_bank *ambiqmicro_info = NULL;
 671         int retval;
 672
 673         ambiqmicro_info = bank->driver_priv;
 674         target = bank->target;
 675
 676         if (target->state != TARGET_HALTED) {
 677                 LOG_ERROR("Target not halted");
 678                 return ERROR_TARGET_NOT_HALTED;
 679         }
 680
 681         if (!ambiqmicro_info->probed) {
 682                 LOG_ERROR("Target not probed");
 683                 return ERROR_FLASH_BANK_NOT_PROBED;
 684         }
 685
 686         if (count > 256) {
 687                 LOG_ERROR("Count must be < 256");
 688                 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 689         }
 690
 691         /*
 692          * Clear Bootloader bit.
 693          */
 694         retval = target_write_u32(target, 0x400201a0, 0x0);
 695         CHECK_STATUS(retval, "error clearing bootloader bit.");
 696
 697         /*
 698          * Set up the SRAM.
 699          */
 700
 701         /*
 702          * Bank.
 703          */
 704         retval = target_write_u32(target, 0x10000000, offset);
 705         CHECK_STATUS(retval, "error setting target SRAM parameters.");
 706
 707         /*
 708          * Num of words to program.
 709          */
 710         retval = target_write_u32(target, 0x10000004, count);
 711         CHECK_STATUS(retval, "error setting target SRAM parameters.");
 712
 713         /*
 714          * Write Key.
 715          */
 716         retval = target_write_u32(target, 0x10000008, OTP_PROGRAM_KEY);
 717         CHECK_STATUS(retval, "error setting target SRAM parameters.");
 718
 719         /*
 720          * Breakpoint.
 721          */
 722         retval = target_write_u32(target, 0x1000000c, 0xfffffffe);
 723         CHECK_STATUS(retval, "error setting target SRAM parameters.");
 724         if (retval != ERROR_OK)
 725                 return retval;
 726
 727         /*
 728          * Program OTP.
 729          */
 730         LOG_INFO("Programming OTP offset 0x%08" PRIx32, offset);
 731
 732         /*
 733          * passed pc, addr = ROM function, handle breakpoints, not debugging.
 734          */
 735         retval = ambiqmicro_exec_command(target, FLASH_PROGRAM_OTP_FROM_SRAM, 0x1000000C);
 736         CHECK_STATUS(retval, "error executing ambiqmicro otp program algorithm");
 737
 738         LOG_INFO("Programming OTP finished.");
 739
 740         return retval;
 741 }
 742
 743
 744
 745 COMMAND_HANDLER(ambiqmicro_handle_mass_erase_command)
 746 {
 747         if (CMD_ARGC < 1)
 748                 return ERROR_COMMAND_SYNTAX_ERROR;
 749
 750         struct flash_bank *bank;
 751         int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 752         if (retval != ERROR_OK)
 753                 return retval;
 754
 755         if (ambiqmicro_mass_erase(bank) == ERROR_OK)
 756                 command_print(CMD, "ambiqmicro mass erase complete");
 757         else
 758                 command_print(CMD, "ambiqmicro mass erase failed");
 759
 760         return ERROR_OK;
 761 }
 762
 763 COMMAND_HANDLER(ambiqmicro_handle_page_erase_command)
 764 {
 765         struct flash_bank *bank;
 766         uint32_t first, last;
 767         int retval;
 768
 769         if (CMD_ARGC < 3)
 770                 return ERROR_COMMAND_SYNTAX_ERROR;
 771
 772         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], first);
 773         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], last);
 774
 775         retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 776         if (retval != ERROR_OK)
 777                 return retval;
 778
 779         if (ambiqmicro_erase(bank, first, last) == ERROR_OK)
 780                 command_print(CMD, "ambiqmicro page erase complete");
 781         else
 782                 command_print(CMD, "ambiqmicro page erase failed");
 783
 784         return ERROR_OK;
 785 }
 786
 787
 788 /**
 789  * Program the otp block.
 790  */
 791 COMMAND_HANDLER(ambiqmicro_handle_program_otp_command)
 792 {
 793         struct flash_bank *bank;
 794         uint32_t offset, count;
 795         int retval;
 796
 797         if (CMD_ARGC < 3)
 798                 return ERROR_COMMAND_SYNTAX_ERROR;
 799
 800         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], offset);
 801         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], count);
 802
 803         command_print(CMD, "offset=0x%08" PRIx32 " count=%" PRIu32, offset, count);
 804
 805         CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 806
 807         retval = ambiqmicro_otp_program(bank, offset, count);
 808
 809         if (retval != ERROR_OK)
 810                 LOG_ERROR("error check log");
 811
 812         return ERROR_OK;
 813 }
 814
 815
 816
 817 static const struct command_registration ambiqmicro_exec_command_handlers[] = {
 818         {
 819                 .name = "mass_erase",
 820                 .usage = "<bank>",
 821                 .handler = ambiqmicro_handle_mass_erase_command,
 822                 .mode = COMMAND_EXEC,
 823                 .help = "Erase entire device",
 824         },
 825         {
 826                 .name = "page_erase",
 827                 .usage = "<bank> <first> <last>",
 828                 .handler = ambiqmicro_handle_page_erase_command,
 829                 .mode = COMMAND_EXEC,
 830                 .help = "Erase device pages",
 831         },
 832         {
 833                 .name = "program_otp",
 834                 .handler = ambiqmicro_handle_program_otp_command,
 835                 .mode = COMMAND_EXEC,
 836                 .usage = "<bank> <offset> <count>",
 837                 .help =
 838                         "Program OTP (assumes you have already written array starting at 0x10000010)",
 839         },
 840         COMMAND_REGISTRATION_DONE
 841 };
 842 static const struct command_registration ambiqmicro_command_handlers[] = {
 843         {
 844                 .name = "ambiqmicro",
 845                 .mode = COMMAND_EXEC,
 846                 .help = "ambiqmicro flash command group",
 847                 .usage = "Support for Ambiq Micro parts.",
 848                 .chain = ambiqmicro_exec_command_handlers,
 849         },
 850         COMMAND_REGISTRATION_DONE
 851 };
 852
 853 const struct flash_driver ambiqmicro_flash = {
 854         .name = "ambiqmicro",
 855         .commands = ambiqmicro_command_handlers,
 856         .flash_bank_command = ambiqmicro_flash_bank_command,
 857         .erase = ambiqmicro_erase,
 858         .protect = ambiqmicro_protect,
 859         .write = ambiqmicro_write,
 860         .read = default_flash_read,
 861         .probe = ambiqmicro_probe,
 862         .auto_probe = ambiqmicro_probe,
 863         .erase_check = default_flash_blank_check,
 864         .protect_check = ambiqmicro_protect_check,
 865         .info = get_ambiqmicro_info,
 866         .free_driver_priv = default_flash_free_driver_priv,
 867 };