flash/nor/at91sam3: remove sam3_page_write_opcodes
[openocd.git] / src / flash / nor / at91sam3.c
1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
4 * *
5 * Copyright (C) 2010 by Olaf L√ľke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
7 * *
8 * Copyright (C) 2011 by Olivier Schonken (at91sam3x* support) * *
9 * and Jim Norris *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
18 * GNU General public License for more details. *
19 * *
20 * You should have received a copy of the GNU General public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
24 ****************************************************************************/
25
26 /* Some of the the lower level code was based on code supplied by
27 * ATMEL under this copyright. */
28
29 /* BEGIN ATMEL COPYRIGHT */
30 /* ----------------------------------------------------------------------------
31 * ATMEL Microcontroller Software Support
32 * ----------------------------------------------------------------------------
33 * Copyright (c) 2009, Atmel Corporation
34 *
35 * All rights reserved.
36 *
37 * Redistribution and use in source and binary forms, with or without
38 * modification, are permitted provided that the following conditions are met:
39 *
40 * - Redistributions of source code must retain the above copyright notice,
41 * this list of conditions and the disclaimer below.
42 *
43 * Atmel's name may not be used to endorse or promote products derived from
44 * this software without specific prior written permission.
45 *
46 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
47 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
48 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
49 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
50 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
51 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
52 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
53 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
54 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
55 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
56 * ----------------------------------------------------------------------------
57 */
58 /* END ATMEL COPYRIGHT */
59
60 #ifdef HAVE_CONFIG_H
61 #include "config.h"
62 #endif
63
64 #include "imp.h"
65 #include <helper/time_support.h>
66
67 #define REG_NAME_WIDTH (12)
68
69 /* at91sam3u series (has one or two flash banks) */
70 #define FLASH_BANK0_BASE_U 0x00080000
71 #define FLASH_BANK1_BASE_U 0x00100000
72
73 /* at91sam3s series (has always one flash bank) */
74 #define FLASH_BANK_BASE_S 0x00400000
75
76 /* at91sam3sd series (has always two flash banks) */
77 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
78 #define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))
79
80
81 /* at91sam3n series (has always one flash bank) */
82 #define FLASH_BANK_BASE_N 0x00400000
83
84 /* at91sam3a/x series has two flash banks*/
85 #define FLASH_BANK0_BASE_AX 0x00080000
86 /*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/
87 #define FLASH_BANK1_BASE_256K_AX 0x000A0000
88 #define FLASH_BANK1_BASE_512K_AX 0x000C0000
89
90 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
91 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
92 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
93 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
94 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
95 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
96 /* cmd6 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
97 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
98 /* cmd7 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
99 /* #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages? */
100 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
101 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
102 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
103 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
104 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
105 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
106 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
107 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
108
109 #define offset_EFC_FMR 0
110 #define offset_EFC_FCR 4
111 #define offset_EFC_FSR 8
112 #define offset_EFC_FRR 12
113
114 extern struct flash_driver at91sam3_flash;
115
116 static float _tomhz(uint32_t freq_hz)
117 {
118 float f;
119
120 f = ((float)(freq_hz)) / 1000000.0;
121 return f;
122 }
123
124 /* How the chip is configured. */
125 struct sam3_cfg {
126 uint32_t unique_id[4];
127
128 uint32_t slow_freq;
129 uint32_t rc_freq;
130 uint32_t mainosc_freq;
131 uint32_t plla_freq;
132 uint32_t mclk_freq;
133 uint32_t cpu_freq;
134 uint32_t fclk_freq;
135 uint32_t pclk0_freq;
136 uint32_t pclk1_freq;
137 uint32_t pclk2_freq;
138
139
140 #define SAM3_CHIPID_CIDR (0x400E0740)
141 uint32_t CHIPID_CIDR;
142 #define SAM3_CHIPID_CIDR2 (0x400E0940) /*SAM3X and SAM3A cidr at this address*/
143 uint32_t CHIPID_CIDR2;
144 #define SAM3_CHIPID_EXID (0x400E0744)
145 uint32_t CHIPID_EXID;
146 #define SAM3_CHIPID_EXID2 (0x400E0944) /*SAM3X and SAM3A cidr at this address*/
147 uint32_t CHIPID_EXID2;
148
149
150 #define SAM3_PMC_BASE (0x400E0400)
151 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
152 uint32_t PMC_SCSR;
153 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
154 uint32_t PMC_PCSR;
155 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
156 uint32_t CKGR_UCKR;
157 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
158 uint32_t CKGR_MOR;
159 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
160 uint32_t CKGR_MCFR;
161 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
162 uint32_t CKGR_PLLAR;
163 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
164 uint32_t PMC_MCKR;
165 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
166 uint32_t PMC_PCK0;
167 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
168 uint32_t PMC_PCK1;
169 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
170 uint32_t PMC_PCK2;
171 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
172 uint32_t PMC_SR;
173 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
174 uint32_t PMC_IMR;
175 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
176 uint32_t PMC_FSMR;
177 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
178 uint32_t PMC_FSPR;
179 };
180
181 /*
182 * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
183 * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
184 * the flash wait state (FWS) should be set to 6. It seems like that the
185 * cause of the problem is not the flash itself, but the flash write
186 * buffer. Ie the wait states have to be set before writing into the
187 * buffer.
188 * Tested and confirmed with SAM3N and SAM3U
189 */
190
191 struct sam3_bank_private {
192 int probed;
193 /* DANGER: THERE ARE DRAGONS HERE.. */
194 /* NOTE: If you add more 'ghost' pointers */
195 /* be aware that you must *manually* update */
196 /* these pointers in the function sam3_GetDetails() */
197 /* See the comment "Here there be dragons" */
198
199 /* so we can find the chip we belong to */
200 struct sam3_chip *pChip;
201 /* so we can find the original bank pointer */
202 struct flash_bank *pBank;
203 unsigned bank_number;
204 uint32_t controller_address;
205 uint32_t base_address;
206 uint32_t flash_wait_states;
207 bool present;
208 unsigned size_bytes;
209 unsigned nsectors;
210 unsigned sector_size;
211 unsigned page_size;
212 };
213
214 struct sam3_chip_details {
215 /* THERE ARE DRAGONS HERE.. */
216 /* note: If you add pointers here */
217 /* be careful about them as they */
218 /* may need to be updated inside */
219 /* the function: "sam3_GetDetails() */
220 /* which copy/overwrites the */
221 /* 'runtime' copy of this structure */
222 uint32_t chipid_cidr;
223 const char *name;
224
225 unsigned n_gpnvms;
226 #define SAM3_N_NVM_BITS 3
227 unsigned gpnvm[SAM3_N_NVM_BITS];
228 unsigned total_flash_size;
229 unsigned total_sram_size;
230 unsigned n_banks;
231 #define SAM3_MAX_FLASH_BANKS 2
232 /* these are "initialized" from the global const data */
233 struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
234 };
235
236 struct sam3_chip {
237 struct sam3_chip *next;
238 int probed;
239
240 /* this is "initialized" from the global const structure */
241 struct sam3_chip_details details;
242 struct target *target;
243 struct sam3_cfg cfg;
244 };
245
246
247 struct sam3_reg_list {
248 uint32_t address; size_t struct_offset; const char *name;
249 void (*explain_func)(struct sam3_chip *pInfo);
250 };
251
252 static struct sam3_chip *all_sam3_chips;
253
254 static struct sam3_chip *get_current_sam3(struct command_context *cmd_ctx)
255 {
256 struct target *t;
257 static struct sam3_chip *p;
258
259 t = get_current_target(cmd_ctx);
260 if (!t) {
261 command_print(cmd_ctx, "No current target?");
262 return NULL;
263 }
264
265 p = all_sam3_chips;
266 if (!p) {
267 /* this should not happen */
268 /* the command is not registered until the chip is created? */
269 command_print(cmd_ctx, "No SAM3 chips exist?");
270 return NULL;
271 }
272
273 while (p) {
274 if (p->target == t)
275 return p;
276 p = p->next;
277 }
278 command_print(cmd_ctx, "Cannot find SAM3 chip?");
279 return NULL;
280 }
281
282 /* these are used to *initialize* the "pChip->details" structure. */
283 static const struct sam3_chip_details all_sam3_details[] = {
284 /* Start at91sam3u* series */
285 {
286 .chipid_cidr = 0x28100960,
287 .name = "at91sam3u4e",
288 .total_flash_size = 256 * 1024,
289 .total_sram_size = 52 * 1024,
290 .n_gpnvms = 3,
291 .n_banks = 2,
292
293 /* System boots at address 0x0 */
294 /* gpnvm[1] = selects boot code */
295 /* if gpnvm[1] == 0 */
296 /* boot is via "SAMBA" (rom) */
297 /* else */
298 /* boot is via FLASH */
299 /* Selection is via gpnvm[2] */
300 /* endif */
301 /* */
302 /* NOTE: banks 0 & 1 switch places */
303 /* if gpnvm[2] == 0 */
304 /* Bank0 is the boot rom */
305 /* else */
306 /* Bank1 is the boot rom */
307 /* endif */
308 /* .bank[0] = { */
309 {
310 {
311 .probed = 0,
312 .pChip = NULL,
313 .pBank = NULL,
314 .bank_number = 0,
315 .base_address = FLASH_BANK0_BASE_U,
316 .controller_address = 0x400e0800,
317 .flash_wait_states = 6, /* workaround silicon bug */
318 .present = 1,
319 .size_bytes = 128 * 1024,
320 .nsectors = 16,
321 .sector_size = 8192,
322 .page_size = 256,
323 },
324
325 /* .bank[1] = { */
326 {
327 .probed = 0,
328 .pChip = NULL,
329 .pBank = NULL,
330 .bank_number = 1,
331 .base_address = FLASH_BANK1_BASE_U,
332 .controller_address = 0x400e0a00,
333 .flash_wait_states = 6, /* workaround silicon bug */
334 .present = 1,
335 .size_bytes = 128 * 1024,
336 .nsectors = 16,
337 .sector_size = 8192,
338 .page_size = 256,
339 },
340 },
341 },
342
343 {
344 .chipid_cidr = 0x281a0760,
345 .name = "at91sam3u2e",
346 .total_flash_size = 128 * 1024,
347 .total_sram_size = 36 * 1024,
348 .n_gpnvms = 2,
349 .n_banks = 1,
350
351 /* System boots at address 0x0 */
352 /* gpnvm[1] = selects boot code */
353 /* if gpnvm[1] == 0 */
354 /* boot is via "SAMBA" (rom) */
355 /* else */
356 /* boot is via FLASH */
357 /* Selection is via gpnvm[2] */
358 /* endif */
359 /* .bank[0] = { */
360 {
361 {
362 .probed = 0,
363 .pChip = NULL,
364 .pBank = NULL,
365 .bank_number = 0,
366 .base_address = FLASH_BANK0_BASE_U,
367 .controller_address = 0x400e0800,
368 .flash_wait_states = 6, /* workaround silicon bug */
369 .present = 1,
370 .size_bytes = 128 * 1024,
371 .nsectors = 16,
372 .sector_size = 8192,
373 .page_size = 256,
374 },
375 /* .bank[1] = { */
376 {
377 .present = 0,
378 .probed = 0,
379 .bank_number = 1,
380 },
381 },
382 },
383 {
384 .chipid_cidr = 0x28190560,
385 .name = "at91sam3u1e",
386 .total_flash_size = 64 * 1024,
387 .total_sram_size = 20 * 1024,
388 .n_gpnvms = 2,
389 .n_banks = 1,
390
391 /* System boots at address 0x0 */
392 /* gpnvm[1] = selects boot code */
393 /* if gpnvm[1] == 0 */
394 /* boot is via "SAMBA" (rom) */
395 /* else */
396 /* boot is via FLASH */
397 /* Selection is via gpnvm[2] */
398 /* endif */
399 /* */
400
401 /* .bank[0] = { */
402 {
403 {
404 .probed = 0,
405 .pChip = NULL,
406 .pBank = NULL,
407 .bank_number = 0,
408 .base_address = FLASH_BANK0_BASE_U,
409 .controller_address = 0x400e0800,
410 .flash_wait_states = 6, /* workaround silicon bug */
411 .present = 1,
412 .size_bytes = 64 * 1024,
413 .nsectors = 8,
414 .sector_size = 8192,
415 .page_size = 256,
416 },
417
418 /* .bank[1] = { */
419 {
420 .present = 0,
421 .probed = 0,
422 .bank_number = 1,
423 },
424 },
425 },
426
427 {
428 .chipid_cidr = 0x28000960,
429 .name = "at91sam3u4c",
430 .total_flash_size = 256 * 1024,
431 .total_sram_size = 52 * 1024,
432 .n_gpnvms = 3,
433 .n_banks = 2,
434
435 /* System boots at address 0x0 */
436 /* gpnvm[1] = selects boot code */
437 /* if gpnvm[1] == 0 */
438 /* boot is via "SAMBA" (rom) */
439 /* else */
440 /* boot is via FLASH */
441 /* Selection is via gpnvm[2] */
442 /* endif */
443 /* */
444 /* NOTE: banks 0 & 1 switch places */
445 /* if gpnvm[2] == 0 */
446 /* Bank0 is the boot rom */
447 /* else */
448 /* Bank1 is the boot rom */
449 /* endif */
450 {
451 {
452 /* .bank[0] = { */
453 .probed = 0,
454 .pChip = NULL,
455 .pBank = NULL,
456 .bank_number = 0,
457 .base_address = FLASH_BANK0_BASE_U,
458 .controller_address = 0x400e0800,
459 .flash_wait_states = 6, /* workaround silicon bug */
460 .present = 1,
461 .size_bytes = 128 * 1024,
462 .nsectors = 16,
463 .sector_size = 8192,
464 .page_size = 256,
465 },
466 /* .bank[1] = { */
467 {
468 .probed = 0,
469 .pChip = NULL,
470 .pBank = NULL,
471 .bank_number = 1,
472 .base_address = FLASH_BANK1_BASE_U,
473 .controller_address = 0x400e0a00,
474 .flash_wait_states = 6, /* workaround silicon bug */
475 .present = 1,
476 .size_bytes = 128 * 1024,
477 .nsectors = 16,
478 .sector_size = 8192,
479 .page_size = 256,
480 },
481 },
482 },
483
484 {
485 .chipid_cidr = 0x280a0760,
486 .name = "at91sam3u2c",
487 .total_flash_size = 128 * 1024,
488 .total_sram_size = 36 * 1024,
489 .n_gpnvms = 2,
490 .n_banks = 1,
491
492 /* System boots at address 0x0 */
493 /* gpnvm[1] = selects boot code */
494 /* if gpnvm[1] == 0 */
495 /* boot is via "SAMBA" (rom) */
496 /* else */
497 /* boot is via FLASH */
498 /* Selection is via gpnvm[2] */
499 /* endif */
500 {
501 /* .bank[0] = { */
502 {
503 .probed = 0,
504 .pChip = NULL,
505 .pBank = NULL,
506 .bank_number = 0,
507 .base_address = FLASH_BANK0_BASE_U,
508 .controller_address = 0x400e0800,
509 .flash_wait_states = 6, /* workaround silicon bug */
510 .present = 1,
511 .size_bytes = 128 * 1024,
512 .nsectors = 16,
513 .sector_size = 8192,
514 .page_size = 256,
515 },
516 /* .bank[1] = { */
517 {
518 .present = 0,
519 .probed = 0,
520 .bank_number = 1,
521 },
522 },
523 },
524 {
525 .chipid_cidr = 0x28090560,
526 .name = "at91sam3u1c",
527 .total_flash_size = 64 * 1024,
528 .total_sram_size = 20 * 1024,
529 .n_gpnvms = 2,
530 .n_banks = 1,
531
532 /* System boots at address 0x0 */
533 /* gpnvm[1] = selects boot code */
534 /* if gpnvm[1] == 0 */
535 /* boot is via "SAMBA" (rom) */
536 /* else */
537 /* boot is via FLASH */
538 /* Selection is via gpnvm[2] */
539 /* endif */
540 /* */
541
542 {
543 /* .bank[0] = { */
544 {
545 .probed = 0,
546 .pChip = NULL,
547 .pBank = NULL,
548 .bank_number = 0,
549 .base_address = FLASH_BANK0_BASE_U,
550 .controller_address = 0x400e0800,
551 .flash_wait_states = 6, /* workaround silicon bug */
552 .present = 1,
553 .size_bytes = 64 * 1024,
554 .nsectors = 8,
555 .sector_size = 8192,
556 .page_size = 256,
557 },
558 /* .bank[1] = { */
559 {
560 .present = 0,
561 .probed = 0,
562 .bank_number = 1,
563
564 },
565 },
566 },
567
568 /* Start at91sam3s* series */
569
570 /* Note: The preliminary at91sam3s datasheet says on page 302 */
571 /* that the flash controller is at address 0x400E0800. */
572 /* This is _not_ the case, the controller resides at address 0x400e0a00. */
573 {
574 .chipid_cidr = 0x28A00960,
575 .name = "at91sam3s4c",
576 .total_flash_size = 256 * 1024,
577 .total_sram_size = 48 * 1024,
578 .n_gpnvms = 2,
579 .n_banks = 1,
580 {
581 /* .bank[0] = { */
582 {
583 .probed = 0,
584 .pChip = NULL,
585 .pBank = NULL,
586 .bank_number = 0,
587 .base_address = FLASH_BANK_BASE_S,
588 .controller_address = 0x400e0a00,
589 .flash_wait_states = 6, /* workaround silicon bug */
590 .present = 1,
591 .size_bytes = 256 * 1024,
592 .nsectors = 16,
593 .sector_size = 16384,
594 .page_size = 256,
595 },
596 /* .bank[1] = { */
597 {
598 .present = 0,
599 .probed = 0,
600 .bank_number = 1,
601
602 },
603 },
604 },
605
606 {
607 .chipid_cidr = 0x28900960,
608 .name = "at91sam3s4b",
609 .total_flash_size = 256 * 1024,
610 .total_sram_size = 48 * 1024,
611 .n_gpnvms = 2,
612 .n_banks = 1,
613 {
614 /* .bank[0] = { */
615 {
616 .probed = 0,
617 .pChip = NULL,
618 .pBank = NULL,
619 .bank_number = 0,
620 .base_address = FLASH_BANK_BASE_S,
621 .controller_address = 0x400e0a00,
622 .flash_wait_states = 6, /* workaround silicon bug */
623 .present = 1,
624 .size_bytes = 256 * 1024,
625 .nsectors = 16,
626 .sector_size = 16384,
627 .page_size = 256,
628 },
629 /* .bank[1] = { */
630 {
631 .present = 0,
632 .probed = 0,
633 .bank_number = 1,
634
635 },
636 },
637 },
638 {
639 .chipid_cidr = 0x28800960,
640 .name = "at91sam3s4a",
641 .total_flash_size = 256 * 1024,
642 .total_sram_size = 48 * 1024,
643 .n_gpnvms = 2,
644 .n_banks = 1,
645 {
646 /* .bank[0] = { */
647 {
648 .probed = 0,
649 .pChip = NULL,
650 .pBank = NULL,
651 .bank_number = 0,
652 .base_address = FLASH_BANK_BASE_S,
653 .controller_address = 0x400e0a00,
654 .flash_wait_states = 6, /* workaround silicon bug */
655 .present = 1,
656 .size_bytes = 256 * 1024,
657 .nsectors = 16,
658 .sector_size = 16384,
659 .page_size = 256,
660 },
661 /* .bank[1] = { */
662 {
663 .present = 0,
664 .probed = 0,
665 .bank_number = 1,
666
667 },
668 },
669 },
670 {
671 .chipid_cidr = 0x28AA0760,
672 .name = "at91sam3s2c",
673 .total_flash_size = 128 * 1024,
674 .total_sram_size = 32 * 1024,
675 .n_gpnvms = 2,
676 .n_banks = 1,
677 {
678 /* .bank[0] = { */
679 {
680 .probed = 0,
681 .pChip = NULL,
682 .pBank = NULL,
683 .bank_number = 0,
684 .base_address = FLASH_BANK_BASE_S,
685 .controller_address = 0x400e0a00,
686 .flash_wait_states = 6, /* workaround silicon bug */
687 .present = 1,
688 .size_bytes = 128 * 1024,
689 .nsectors = 8,
690 .sector_size = 16384,
691 .page_size = 256,
692 },
693 /* .bank[1] = { */
694 {
695 .present = 0,
696 .probed = 0,
697 .bank_number = 1,
698
699 },
700 },
701 },
702 {
703 .chipid_cidr = 0x289A0760,
704 .name = "at91sam3s2b",
705 .total_flash_size = 128 * 1024,
706 .total_sram_size = 32 * 1024,
707 .n_gpnvms = 2,
708 .n_banks = 1,
709 {
710 /* .bank[0] = { */
711 {
712 .probed = 0,
713 .pChip = NULL,
714 .pBank = NULL,
715 .bank_number = 0,
716 .base_address = FLASH_BANK_BASE_S,
717 .controller_address = 0x400e0a00,
718 .flash_wait_states = 6, /* workaround silicon bug */
719 .present = 1,
720 .size_bytes = 128 * 1024,
721 .nsectors = 8,
722 .sector_size = 16384,
723 .page_size = 256,
724 },
725 /* .bank[1] = { */
726 {
727 .present = 0,
728 .probed = 0,
729 .bank_number = 1,
730
731 },
732 },
733 },
734 {
735 .chipid_cidr = 0x298B0A60,
736 .name = "at91sam3sd8a",
737 .total_flash_size = 512 * 1024,
738 .total_sram_size = 64 * 1024,
739 .n_gpnvms = 3,
740 .n_banks = 2,
741 {
742 /* .bank[0] = { */
743 {
744 .probed = 0,
745 .pChip = NULL,
746 .pBank = NULL,
747 .bank_number = 0,
748 .base_address = FLASH_BANK0_BASE_SD,
749 .controller_address = 0x400e0a00,
750 .flash_wait_states = 6, /* workaround silicon bug */
751 .present = 1,
752 .size_bytes = 256 * 1024,
753 .nsectors = 16,
754 .sector_size = 32768,
755 .page_size = 256,
756 },
757 /* .bank[1] = { */
758 {
759 .probed = 0,
760 .pChip = NULL,
761 .pBank = NULL,
762 .bank_number = 1,
763 .base_address = FLASH_BANK1_BASE_512K_SD,
764 .controller_address = 0x400e0a00,
765 .flash_wait_states = 6, /* workaround silicon bug */
766 .present = 1,
767 .size_bytes = 256 * 1024,
768 .nsectors = 16,
769 .sector_size = 32768,
770 .page_size = 256,
771 },
772 },
773 },
774 {
775 .chipid_cidr = 0x299B0A60,
776 .name = "at91sam3sd8b",
777 .total_flash_size = 512 * 1024,
778 .total_sram_size = 64 * 1024,
779 .n_gpnvms = 3,
780 .n_banks = 2,
781 {
782 /* .bank[0] = { */
783 {
784 .probed = 0,
785 .pChip = NULL,
786 .pBank = NULL,
787 .bank_number = 0,
788 .base_address = FLASH_BANK0_BASE_SD,
789 .controller_address = 0x400e0a00,
790 .flash_wait_states = 6, /* workaround silicon bug */
791 .present = 1,
792 .size_bytes = 256 * 1024,
793 .nsectors = 16,
794 .sector_size = 32768,
795 .page_size = 256,
796 },
797 /* .bank[1] = { */
798 {
799 .probed = 0,
800 .pChip = NULL,
801 .pBank = NULL,
802 .bank_number = 1,
803 .base_address = FLASH_BANK1_BASE_512K_SD,
804 .controller_address = 0x400e0a00,
805 .flash_wait_states = 6, /* workaround silicon bug */
806 .present = 1,
807 .size_bytes = 256 * 1024,
808 .nsectors = 16,
809 .sector_size = 32768,
810 .page_size = 256,
811 },
812 },
813 },
814 {
815 .chipid_cidr = 0x29ab0a60,
816 .name = "at91sam3sd8c",
817 .total_flash_size = 512 * 1024,
818 .total_sram_size = 64 * 1024,
819 .n_gpnvms = 3,
820 .n_banks = 2,
821 {
822 /* .bank[0] = { */
823 {
824 .probed = 0,
825 .pChip = NULL,
826 .pBank = NULL,
827 .bank_number = 0,
828 .base_address = FLASH_BANK0_BASE_SD,
829 .controller_address = 0x400e0a00,
830 .flash_wait_states = 6, /* workaround silicon bug */
831 .present = 1,
832 .size_bytes = 256 * 1024,
833 .nsectors = 16,
834 .sector_size = 32768,
835 .page_size = 256,
836 },
837 /* .bank[1] = { */
838 {
839 .probed = 0,
840 .pChip = NULL,
841 .pBank = NULL,
842 .bank_number = 1,
843 .base_address = FLASH_BANK1_BASE_512K_SD,
844 .controller_address = 0x400e0a00,
845 .flash_wait_states = 6, /* workaround silicon bug */
846 .present = 1,
847 .size_bytes = 256 * 1024,
848 .nsectors = 16,
849 .sector_size = 32768,
850 .page_size = 256,
851 },
852 },
853 },
854 {
855 .chipid_cidr = 0x288A0760,
856 .name = "at91sam3s2a",
857 .total_flash_size = 128 * 1024,
858 .total_sram_size = 32 * 1024,
859 .n_gpnvms = 2,
860 .n_banks = 1,
861 {
862 /* .bank[0] = { */
863 {
864 .probed = 0,
865 .pChip = NULL,
866 .pBank = NULL,
867 .bank_number = 0,
868 .base_address = FLASH_BANK_BASE_S,
869 .controller_address = 0x400e0a00,
870 .flash_wait_states = 6, /* workaround silicon bug */
871 .present = 1,
872 .size_bytes = 128 * 1024,
873 .nsectors = 8,
874 .sector_size = 16384,
875 .page_size = 256,
876 },
877 /* .bank[1] = { */
878 {
879 .present = 0,
880 .probed = 0,
881 .bank_number = 1,
882
883 },
884 },
885 },
886 {
887 .chipid_cidr = 0x28A90560,
888 .name = "at91sam3s1c",
889 .total_flash_size = 64 * 1024,
890 .total_sram_size = 16 * 1024,
891 .n_gpnvms = 2,
892 .n_banks = 1,
893 {
894 /* .bank[0] = { */
895 {
896 .probed = 0,
897 .pChip = NULL,
898 .pBank = NULL,
899 .bank_number = 0,
900 .base_address = FLASH_BANK_BASE_S,
901 .controller_address = 0x400e0a00,
902 .flash_wait_states = 6, /* workaround silicon bug */
903 .present = 1,
904 .size_bytes = 64 * 1024,
905 .nsectors = 4,
906 .sector_size = 16384,
907 .page_size = 256,
908 },
909 /* .bank[1] = { */
910 {
911 .present = 0,
912 .probed = 0,
913 .bank_number = 1,
914
915 },
916 },
917 },
918 {
919 .chipid_cidr = 0x28990560,
920 .name = "at91sam3s1b",
921 .total_flash_size = 64 * 1024,
922 .total_sram_size = 16 * 1024,
923 .n_gpnvms = 2,
924 .n_banks = 1,
925 {
926 /* .bank[0] = { */
927 {
928 .probed = 0,
929 .pChip = NULL,
930 .pBank = NULL,
931 .bank_number = 0,
932 .base_address = FLASH_BANK_BASE_S,
933 .controller_address = 0x400e0a00,
934 .flash_wait_states = 6, /* workaround silicon bug */
935 .present = 1,
936 .size_bytes = 64 * 1024,
937 .nsectors = 4,
938 .sector_size = 16384,
939 .page_size = 256,
940 },
941 /* .bank[1] = { */
942 {
943 .present = 0,
944 .probed = 0,
945 .bank_number = 1,
946
947 },
948 },
949 },
950 {
951 .chipid_cidr = 0x28890560,
952 .name = "at91sam3s1a",
953 .total_flash_size = 64 * 1024,
954 .total_sram_size = 16 * 1024,
955 .n_gpnvms = 2,
956 .n_banks = 1,
957 {
958 /* .bank[0] = { */
959 {
960 .probed = 0,
961 .pChip = NULL,
962 .pBank = NULL,
963 .bank_number = 0,
964 .base_address = FLASH_BANK_BASE_S,
965 .controller_address = 0x400e0a00,
966 .flash_wait_states = 6, /* workaround silicon bug */
967 .present = 1,
968 .size_bytes = 64 * 1024,
969 .nsectors = 4,
970 .sector_size = 16384,
971 .page_size = 256,
972 },
973 /* .bank[1] = { */
974 {
975 .present = 0,
976 .probed = 0,
977 .bank_number = 1,
978
979 },
980 },
981 },
982 {
983 .chipid_cidr = 0x288B0A60,
984 .name = "at91sam3s8a",
985 .total_flash_size = 256 * 2048,
986 .total_sram_size = 64 * 1024,
987 .n_gpnvms = 2,
988 .n_banks = 1,
989 {
990 /* .bank[0] = { */
991 {
992 .probed = 0,
993 .pChip = NULL,
994 .pBank = NULL,
995 .bank_number = 0,
996 .base_address = FLASH_BANK_BASE_S,
997 .controller_address = 0x400e0a00,
998 .flash_wait_states = 6, /* workaround silicon bug */
999 .present = 1,
1000 .size_bytes = 256 * 2048,
1001 .nsectors = 16,
1002 .sector_size = 32768,
1003 .page_size = 256,
1004 },
1005 /* .bank[1] = { */
1006 {
1007 .present = 0,
1008 .probed = 0,
1009 .bank_number = 1,
1010
1011 },
1012 },
1013 },
1014 {
1015 .chipid_cidr = 0x289B0A60,
1016 .name = "at91sam3s8b",
1017 .total_flash_size = 256 * 2048,
1018 .total_sram_size = 64 * 1024,
1019 .n_gpnvms = 2,
1020 .n_banks = 1,
1021 {
1022 /* .bank[0] = { */
1023 {
1024 .probed = 0,
1025 .pChip = NULL,
1026 .pBank = NULL,
1027 .bank_number = 0,
1028 .base_address = FLASH_BANK_BASE_S,
1029 .controller_address = 0x400e0a00,
1030 .flash_wait_states = 6, /* workaround silicon bug */
1031 .present = 1,
1032 .size_bytes = 256 * 2048,
1033 .nsectors = 16,
1034 .sector_size = 32768,
1035 .page_size = 256,
1036 },
1037 /* .bank[1] = { */
1038 {
1039 .present = 0,
1040 .probed = 0,
1041 .bank_number = 1,
1042
1043 },
1044 },
1045 },
1046 {
1047 .chipid_cidr = 0x28AB0A60,
1048 .name = "at91sam3s8c",
1049 .total_flash_size = 256 * 2048,
1050 .total_sram_size = 64 * 1024,
1051 .n_gpnvms = 2,
1052 .n_banks = 1,
1053 {
1054 /* .bank[0] = { */
1055 {
1056 .probed = 0,
1057 .pChip = NULL,
1058 .pBank = NULL,
1059 .bank_number = 0,
1060 .base_address = FLASH_BANK_BASE_S,
1061 .controller_address = 0x400e0a00,
1062 .flash_wait_states = 6, /* workaround silicon bug */
1063 .present = 1,
1064 .size_bytes = 256 * 2048,
1065 .nsectors = 16,
1066 .sector_size = 32768,
1067 .page_size = 256,
1068 },
1069 /* .bank[1] = { */
1070 {
1071 .present = 0,
1072 .probed = 0,
1073 .bank_number = 1,
1074
1075 },
1076 },
1077 },
1078
1079 /* Start at91sam3n* series */
1080 {
1081 .chipid_cidr = 0x29540960,
1082 .name = "at91sam3n4c",
1083 .total_flash_size = 256 * 1024,
1084 .total_sram_size = 24 * 1024,
1085 .n_gpnvms = 3,
1086 .n_banks = 1,
1087
1088 /* System boots at address 0x0 */
1089 /* gpnvm[1] = selects boot code */
1090 /* if gpnvm[1] == 0 */
1091 /* boot is via "SAMBA" (rom) */
1092 /* else */
1093 /* boot is via FLASH */
1094 /* Selection is via gpnvm[2] */
1095 /* endif */
1096 /* */
1097 /* NOTE: banks 0 & 1 switch places */
1098 /* if gpnvm[2] == 0 */
1099 /* Bank0 is the boot rom */
1100 /* else */
1101 /* Bank1 is the boot rom */
1102 /* endif */
1103 /* .bank[0] = { */
1104 {
1105 {
1106 .probed = 0,
1107 .pChip = NULL,
1108 .pBank = NULL,
1109 .bank_number = 0,
1110 .base_address = FLASH_BANK_BASE_N,
1111 .controller_address = 0x400e0A00,
1112 .flash_wait_states = 6, /* workaround silicon bug */
1113 .present = 1,
1114 .size_bytes = 256 * 1024,
1115 .nsectors = 16,
1116 .sector_size = 16384,
1117 .page_size = 256,
1118 },
1119
1120 /* .bank[1] = { */
1121 {
1122 .present = 0,
1123 .probed = 0,
1124 .bank_number = 1,
1125 },
1126 },
1127 },
1128
1129 {
1130 .chipid_cidr = 0x29440960,
1131 .name = "at91sam3n4b",
1132 .total_flash_size = 256 * 1024,
1133 .total_sram_size = 24 * 1024,
1134 .n_gpnvms = 3,
1135 .n_banks = 1,
1136
1137 /* System boots at address 0x0 */
1138 /* gpnvm[1] = selects boot code */
1139 /* if gpnvm[1] == 0 */
1140 /* boot is via "SAMBA" (rom) */
1141 /* else */
1142 /* boot is via FLASH */
1143 /* Selection is via gpnvm[2] */
1144 /* endif */
1145 /* */
1146 /* NOTE: banks 0 & 1 switch places */
1147 /* if gpnvm[2] == 0 */
1148 /* Bank0 is the boot rom */
1149 /* else */
1150 /* Bank1 is the boot rom */
1151 /* endif */
1152 /* .bank[0] = { */
1153 {
1154 {
1155 .probed = 0,
1156 .pChip = NULL,
1157 .pBank = NULL,
1158 .bank_number = 0,
1159 .base_address = FLASH_BANK_BASE_N,
1160 .controller_address = 0x400e0A00,
1161 .flash_wait_states = 6, /* workaround silicon bug */
1162 .present = 1,
1163 .size_bytes = 256 * 1024,
1164 .nsectors = 16,
1165 .sector_size = 16384,
1166 .page_size = 256,
1167 },
1168
1169 /* .bank[1] = { */
1170 {
1171 .present = 0,
1172 .probed = 0,
1173 .bank_number = 1,
1174 },
1175 },
1176 },
1177
1178 {
1179 .chipid_cidr = 0x29340960,
1180 .name = "at91sam3n4a",
1181 .total_flash_size = 256 * 1024,
1182 .total_sram_size = 24 * 1024,
1183 .n_gpnvms = 3,
1184 .n_banks = 1,
1185
1186 /* System boots at address 0x0 */
1187 /* gpnvm[1] = selects boot code */
1188 /* if gpnvm[1] == 0 */
1189 /* boot is via "SAMBA" (rom) */
1190 /* else */
1191 /* boot is via FLASH */
1192 /* Selection is via gpnvm[2] */
1193 /* endif */
1194 /* */
1195 /* NOTE: banks 0 & 1 switch places */
1196 /* if gpnvm[2] == 0 */
1197 /* Bank0 is the boot rom */
1198 /* else */
1199 /* Bank1 is the boot rom */
1200 /* endif */
1201 /* .bank[0] = { */
1202 {
1203 {
1204 .probed = 0,
1205 .pChip = NULL,
1206 .pBank = NULL,
1207 .bank_number = 0,
1208 .base_address = FLASH_BANK_BASE_N,
1209 .controller_address = 0x400e0A00,
1210 .flash_wait_states = 6, /* workaround silicon bug */
1211 .present = 1,
1212 .size_bytes = 256 * 1024,
1213 .nsectors = 16,
1214 .sector_size = 16384,
1215 .page_size = 256,
1216 },
1217
1218 /* .bank[1] = { */
1219 {
1220 .present = 0,
1221 .probed = 0,
1222 .bank_number = 1,
1223 },
1224 },
1225 },
1226
1227 {
1228 .chipid_cidr = 0x29590760,
1229 .name = "at91sam3n2c",
1230 .total_flash_size = 128 * 1024,
1231 .total_sram_size = 16 * 1024,
1232 .n_gpnvms = 3,
1233 .n_banks = 1,
1234
1235 /* System boots at address 0x0 */
1236 /* gpnvm[1] = selects boot code */
1237 /* if gpnvm[1] == 0 */
1238 /* boot is via "SAMBA" (rom) */
1239 /* else */
1240 /* boot is via FLASH */
1241 /* Selection is via gpnvm[2] */
1242 /* endif */
1243 /* */
1244 /* NOTE: banks 0 & 1 switch places */
1245 /* if gpnvm[2] == 0 */
1246 /* Bank0 is the boot rom */
1247 /* else */
1248 /* Bank1 is the boot rom */
1249 /* endif */
1250 /* .bank[0] = { */
1251 {
1252 {
1253 .probed = 0,
1254 .pChip = NULL,
1255 .pBank = NULL,
1256 .bank_number = 0,
1257 .base_address = FLASH_BANK_BASE_N,
1258 .controller_address = 0x400e0A00,
1259 .flash_wait_states = 6, /* workaround silicon bug */
1260 .present = 1,
1261 .size_bytes = 128 * 1024,
1262 .nsectors = 8,
1263 .sector_size = 16384,
1264 .page_size = 256,
1265 },
1266
1267 /* .bank[1] = { */
1268 {
1269 .present = 0,
1270 .probed = 0,
1271 .bank_number = 1,
1272 },
1273 },
1274 },
1275
1276 {
1277 .chipid_cidr = 0x29490760,
1278 .name = "at91sam3n2b",
1279 .total_flash_size = 128 * 1024,
1280 .total_sram_size = 16 * 1024,
1281 .n_gpnvms = 3,
1282 .n_banks = 1,
1283
1284 /* System boots at address 0x0 */
1285 /* gpnvm[1] = selects boot code */
1286 /* if gpnvm[1] == 0 */
1287 /* boot is via "SAMBA" (rom) */
1288 /* else */
1289 /* boot is via FLASH */
1290 /* Selection is via gpnvm[2] */
1291 /* endif */
1292 /* */
1293 /* NOTE: banks 0 & 1 switch places */
1294 /* if gpnvm[2] == 0 */
1295 /* Bank0 is the boot rom */
1296 /* else */
1297 /* Bank1 is the boot rom */
1298 /* endif */
1299 /* .bank[0] = { */
1300 {
1301 {
1302 .probed = 0,
1303 .pChip = NULL,
1304 .pBank = NULL,
1305 .bank_number = 0,
1306 .base_address = FLASH_BANK_BASE_N,
1307 .controller_address = 0x400e0A00,
1308 .flash_wait_states = 6, /* workaround silicon bug */
1309 .present = 1,
1310 .size_bytes = 128 * 1024,
1311 .nsectors = 8,
1312 .sector_size = 16384,
1313 .page_size = 256,
1314 },
1315
1316 /* .bank[1] = { */
1317 {
1318 .present = 0,
1319 .probed = 0,
1320 .bank_number = 1,
1321 },
1322 },
1323 },
1324
1325 {
1326 .chipid_cidr = 0x29390760,
1327 .name = "at91sam3n2a",
1328 .total_flash_size = 128 * 1024,
1329 .total_sram_size = 16 * 1024,
1330 .n_gpnvms = 3,
1331 .n_banks = 1,
1332
1333 /* System boots at address 0x0 */
1334 /* gpnvm[1] = selects boot code */
1335 /* if gpnvm[1] == 0 */
1336 /* boot is via "SAMBA" (rom) */
1337 /* else */
1338 /* boot is via FLASH */
1339 /* Selection is via gpnvm[2] */
1340 /* endif */
1341 /* */
1342 /* NOTE: banks 0 & 1 switch places */
1343 /* if gpnvm[2] == 0 */
1344 /* Bank0 is the boot rom */
1345 /* else */
1346 /* Bank1 is the boot rom */
1347 /* endif */
1348 /* .bank[0] = { */
1349 {
1350 {
1351 .probed = 0,
1352 .pChip = NULL,
1353 .pBank = NULL,
1354 .bank_number = 0,
1355 .base_address = FLASH_BANK_BASE_N,
1356 .controller_address = 0x400e0A00,
1357 .flash_wait_states = 6, /* workaround silicon bug */
1358 .present = 1,
1359 .size_bytes = 128 * 1024,
1360 .nsectors = 8,
1361 .sector_size = 16384,
1362 .page_size = 256,
1363 },
1364
1365 /* .bank[1] = { */
1366 {
1367 .present = 0,
1368 .probed = 0,
1369 .bank_number = 1,
1370 },
1371 },
1372 },
1373
1374 {
1375 .chipid_cidr = 0x29580560,
1376 .name = "at91sam3n1c",
1377 .total_flash_size = 64 * 1024,
1378 .total_sram_size = 8 * 1024,
1379 .n_gpnvms = 3,
1380 .n_banks = 1,
1381
1382 /* System boots at address 0x0 */
1383 /* gpnvm[1] = selects boot code */
1384 /* if gpnvm[1] == 0 */
1385 /* boot is via "SAMBA" (rom) */
1386 /* else */
1387 /* boot is via FLASH */
1388 /* Selection is via gpnvm[2] */
1389 /* endif */
1390 /* */
1391 /* NOTE: banks 0 & 1 switch places */
1392 /* if gpnvm[2] == 0 */
1393 /* Bank0 is the boot rom */
1394 /* else */
1395 /* Bank1 is the boot rom */
1396 /* endif */
1397 /* .bank[0] = { */
1398 {
1399 {
1400 .probed = 0,
1401 .pChip = NULL,
1402 .pBank = NULL,
1403 .bank_number = 0,
1404 .base_address = FLASH_BANK_BASE_N,
1405 .controller_address = 0x400e0A00,
1406 .flash_wait_states = 6, /* workaround silicon bug */
1407 .present = 1,
1408 .size_bytes = 64 * 1024,
1409 .nsectors = 4,
1410 .sector_size = 16384,
1411 .page_size = 256,
1412 },
1413
1414 /* .bank[1] = { */
1415 {
1416 .present = 0,
1417 .probed = 0,
1418 .bank_number = 1,
1419 },
1420 },
1421 },
1422
1423 {
1424 .chipid_cidr = 0x29480560,
1425 .name = "at91sam3n1b",
1426 .total_flash_size = 64 * 1024,
1427 .total_sram_size = 8 * 1024,
1428 .n_gpnvms = 3,
1429 .n_banks = 1,
1430
1431 /* System boots at address 0x0 */
1432 /* gpnvm[1] = selects boot code */
1433 /* if gpnvm[1] == 0 */
1434 /* boot is via "SAMBA" (rom) */
1435 /* else */
1436 /* boot is via FLASH */
1437 /* Selection is via gpnvm[2] */
1438 /* endif */
1439 /* */
1440 /* NOTE: banks 0 & 1 switch places */
1441 /* if gpnvm[2] == 0 */
1442 /* Bank0 is the boot rom */
1443 /* else */
1444 /* Bank1 is the boot rom */
1445 /* endif */
1446 /* .bank[0] = { */
1447 {
1448 {
1449 .probed = 0,
1450 .pChip = NULL,
1451 .pBank = NULL,
1452 .bank_number = 0,
1453 .base_address = FLASH_BANK_BASE_N,
1454 .controller_address = 0x400e0A00,
1455 .flash_wait_states = 6, /* workaround silicon bug */
1456 .present = 1,
1457 .size_bytes = 64 * 1024,
1458 .nsectors = 4,
1459 .sector_size = 16384,
1460 .page_size = 256,
1461 },
1462
1463 /* .bank[1] = { */
1464 {
1465 .present = 0,
1466 .probed = 0,
1467 .bank_number = 1,
1468 },
1469 },
1470 },
1471
1472 {
1473 .chipid_cidr = 0x29380560,
1474 .name = "at91sam3n1a",
1475 .total_flash_size = 64 * 1024,
1476 .total_sram_size = 8 * 1024,
1477 .n_gpnvms = 3,
1478 .n_banks = 1,
1479
1480 /* System boots at address 0x0 */
1481 /* gpnvm[1] = selects boot code */
1482 /* if gpnvm[1] == 0 */
1483 /* boot is via "SAMBA" (rom) */
1484 /* else */
1485 /* boot is via FLASH */
1486 /* Selection is via gpnvm[2] */
1487 /* endif */
1488 /* */
1489 /* NOTE: banks 0 & 1 switch places */
1490 /* if gpnvm[2] == 0 */
1491 /* Bank0 is the boot rom */
1492 /* else */
1493 /* Bank1 is the boot rom */
1494 /* endif */
1495 /* .bank[0] = { */
1496 {
1497 {
1498 .probed = 0,
1499 .pChip = NULL,
1500 .pBank = NULL,
1501 .bank_number = 0,
1502 .base_address = FLASH_BANK_BASE_N,
1503 .controller_address = 0x400e0A00,
1504 .flash_wait_states = 6, /* workaround silicon bug */
1505 .present = 1,
1506 .size_bytes = 64 * 1024,
1507 .nsectors = 4,
1508 .sector_size = 16384,
1509 .page_size = 256,
1510 },
1511
1512 /* .bank[1] = { */
1513 {
1514 .present = 0,
1515 .probed = 0,
1516 .bank_number = 1,
1517 },
1518 },
1519 },
1520
1521 {
1522 .chipid_cidr = 0x29480360,
1523 .name = "at91sam3n0b",
1524 .total_flash_size = 32 * 1024,
1525 .total_sram_size = 8 * 1024,
1526 .n_gpnvms = 3,
1527 .n_banks = 1,
1528
1529 /* .bank[0] = { */
1530 {
1531 {
1532 .probed = 0,
1533 .pChip = NULL,
1534 .pBank = NULL,
1535 .bank_number = 0,
1536 .base_address = FLASH_BANK_BASE_N,
1537 .controller_address = 0x400e0A00,
1538 .flash_wait_states = 6, /* workaround silicon bug */
1539 .present = 1,
1540 .size_bytes = 32 * 1024,
1541 .nsectors = 2,
1542 .sector_size = 16384,
1543 .page_size = 256,
1544 },
1545
1546 /* .bank[1] = { */
1547 {
1548 .present = 0,
1549 .probed = 0,
1550 .bank_number = 1,
1551 },
1552 },
1553 },
1554
1555 {
1556 .chipid_cidr = 0x29380360,
1557 .name = "at91sam3n0a",
1558 .total_flash_size = 32 * 1024,
1559 .total_sram_size = 8 * 1024,
1560 .n_gpnvms = 3,
1561 .n_banks = 1,
1562
1563 /* .bank[0] = { */
1564 {
1565 {
1566 .probed = 0,
1567 .pChip = NULL,
1568 .pBank = NULL,
1569 .bank_number = 0,
1570 .base_address = FLASH_BANK_BASE_N,
1571 .controller_address = 0x400e0A00,
1572 .flash_wait_states = 6, /* workaround silicon bug */
1573 .present = 1,
1574 .size_bytes = 32 * 1024,
1575 .nsectors = 2,
1576 .sector_size = 16384,
1577 .page_size = 256,
1578 },
1579
1580 /* .bank[1] = { */
1581 {
1582 .present = 0,
1583 .probed = 0,
1584 .bank_number = 1,
1585 },
1586 },
1587 },
1588
1589 {
1590 .chipid_cidr = 0x29450260,
1591 .name = "at91sam3n00b",
1592 .total_flash_size = 16 * 1024,
1593 .total_sram_size = 4 * 1024,
1594 .n_gpnvms = 3,
1595 .n_banks = 1,
1596
1597 /* .bank[0] = { */
1598 {
1599 {
1600 .probed = 0,
1601 .pChip = NULL,
1602 .pBank = NULL,
1603 .bank_number = 0,
1604 .base_address = FLASH_BANK_BASE_N,
1605 .controller_address = 0x400e0A00,
1606 .flash_wait_states = 6, /* workaround silicon bug */
1607 .present = 1,
1608 .size_bytes = 16 * 1024,
1609 .nsectors = 1,
1610 .sector_size = 16384,
1611 .page_size = 256,
1612 },
1613
1614 /* .bank[1] = { */
1615 {
1616 .present = 0,
1617 .probed = 0,
1618 .bank_number = 1,
1619 },
1620 },
1621 },
1622
1623 {
1624 .chipid_cidr = 0x29350260,
1625 .name = "at91sam3n00a",
1626 .total_flash_size = 16 * 1024,
1627 .total_sram_size = 4 * 1024,
1628 .n_gpnvms = 3,
1629 .n_banks = 1,
1630
1631 /* .bank[0] = { */
1632 {
1633 {
1634 .probed = 0,
1635 .pChip = NULL,
1636 .pBank = NULL,
1637 .bank_number = 0,
1638 .base_address = FLASH_BANK_BASE_N,
1639 .controller_address = 0x400e0A00,
1640 .flash_wait_states = 6, /* workaround silicon bug */
1641 .present = 1,
1642 .size_bytes = 16 * 1024,
1643 .nsectors = 1,
1644 .sector_size = 16384,
1645 .page_size = 256,
1646 },
1647
1648 /* .bank[1] = { */
1649 {
1650 .present = 0,
1651 .probed = 0,
1652 .bank_number = 1,
1653 },
1654 },
1655 },
1656
1657
1658 /* Start at91sam3a series*/
1659 /* System boots at address 0x0 */
1660 /* gpnvm[1] = selects boot code */
1661 /* if gpnvm[1] == 0 */
1662 /* boot is via "SAMBA" (rom) */
1663 /* else */
1664 /* boot is via FLASH */
1665 /* Selection is via gpnvm[2] */
1666 /* endif */
1667 /* */
1668 /* NOTE: banks 0 & 1 switch places */
1669 /* if gpnvm[2] == 0 */
1670 /* Bank0 is the boot rom */
1671 /* else */
1672 /* Bank1 is the boot rom */
1673 /* endif */
1674
1675 {
1676 .chipid_cidr = 0x283E0A60,
1677 .name = "at91sam3a8c",
1678 .total_flash_size = 512 * 1024,
1679 .total_sram_size = 96 * 1024,
1680 .n_gpnvms = 3,
1681 .n_banks = 2,
1682 {
1683 /* .bank[0] = { */
1684 {
1685 .probed = 0,
1686 .pChip = NULL,
1687 .pBank = NULL,
1688 .bank_number = 0,
1689 .base_address = FLASH_BANK0_BASE_AX,
1690 .controller_address = 0x400e0a00,
1691 .flash_wait_states = 6, /* workaround silicon bug */
1692 .present = 1,
1693 .size_bytes = 256 * 1024,
1694 .nsectors = 16,
1695 .sector_size = 16384,
1696 .page_size = 256,
1697 },
1698 /* .bank[1] = { */
1699 {
1700 .probed = 0,
1701 .pChip = NULL,
1702 .pBank = NULL,
1703 .bank_number = 1,
1704 .base_address = FLASH_BANK1_BASE_512K_AX,
1705 .controller_address = 0x400e0c00,
1706 .flash_wait_states = 6, /* workaround silicon bug */
1707 .present = 1,
1708 .size_bytes = 256 * 1024,
1709 .nsectors = 16,
1710 .sector_size = 16384,
1711 .page_size = 256,
1712
1713 },
1714 },
1715 },
1716 {
1717 .chipid_cidr = 0x283B0960,
1718 .name = "at91sam3a4c",
1719 .total_flash_size = 256 * 1024,
1720 .total_sram_size = 64 * 1024,
1721 .n_gpnvms = 3,
1722 .n_banks = 2,
1723 {
1724 /* .bank[0] = { */
1725 {
1726 .probed = 0,
1727 .pChip = NULL,
1728 .pBank = NULL,
1729 .bank_number = 0,
1730 .base_address = FLASH_BANK0_BASE_AX,
1731 .controller_address = 0x400e0a00,
1732 .flash_wait_states = 6, /* workaround silicon bug */
1733 .present = 1,
1734 .size_bytes = 128 * 1024,
1735 .nsectors = 8,
1736 .sector_size = 16384,
1737 .page_size = 256,
1738 },
1739 /* .bank[1] = { */
1740 {
1741 .probed = 0,
1742 .pChip = NULL,
1743 .pBank = NULL,
1744 .bank_number = 1,
1745 .base_address = FLASH_BANK1_BASE_256K_AX,
1746 .controller_address = 0x400e0c00,
1747 .flash_wait_states = 6, /* workaround silicon bug */
1748 .present = 1,
1749 .size_bytes = 128 * 1024,
1750 .nsectors = 8,
1751 .sector_size = 16384,
1752 .page_size = 256,
1753
1754 },
1755 },
1756 },
1757
1758 /* Start at91sam3x* series */
1759 /* System boots at address 0x0 */
1760 /* gpnvm[1] = selects boot code */
1761 /* if gpnvm[1] == 0 */
1762 /* boot is via "SAMBA" (rom) */
1763 /* else */
1764 /* boot is via FLASH */
1765 /* Selection is via gpnvm[2] */
1766 /* endif */
1767 /* */
1768 /* NOTE: banks 0 & 1 switch places */
1769 /* if gpnvm[2] == 0 */
1770 /* Bank0 is the boot rom */
1771 /* else */
1772 /* Bank1 is the boot rom */
1773 /* endif */
1774 /*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/
1775 {
1776 .chipid_cidr = 0x286E0A20,
1777 .name = "at91sam3x8h - ES",
1778 .total_flash_size = 512 * 1024,
1779 .total_sram_size = 96 * 1024,
1780 .n_gpnvms = 3,
1781 .n_banks = 2,
1782 {
1783 /* .bank[0] = { */
1784 {
1785 .probed = 0,
1786 .pChip = NULL,
1787 .pBank = NULL,
1788 .bank_number = 0,
1789 .base_address = FLASH_BANK0_BASE_AX,
1790 .controller_address = 0x400e0a00,
1791 .flash_wait_states = 6, /* workaround silicon bug */
1792 .present = 1,
1793 .size_bytes = 256 * 1024,
1794 .nsectors = 16,
1795 .sector_size = 16384,
1796 .page_size = 256,
1797 },
1798 /* .bank[1] = { */
1799 {
1800 .probed = 0,
1801 .pChip = NULL,
1802 .pBank = NULL,
1803 .bank_number = 1,
1804 .base_address = FLASH_BANK1_BASE_512K_AX,
1805 .controller_address = 0x400e0c00,
1806 .flash_wait_states = 6, /* workaround silicon bug */
1807 .present = 1,
1808 .size_bytes = 256 * 1024,
1809 .nsectors = 16,
1810 .sector_size = 16384,
1811 .page_size = 256,
1812
1813 },
1814 },
1815 },
1816 /*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/
1817 {
1818 .chipid_cidr = 0x286E0A60,
1819 .name = "at91sam3x8h",
1820 .total_flash_size = 512 * 1024,
1821 .total_sram_size = 96 * 1024,
1822 .n_gpnvms = 3,
1823 .n_banks = 2,
1824 {
1825 /* .bank[0] = { */
1826 {
1827 .probed = 0,
1828 .pChip = NULL,
1829 .pBank = NULL,
1830 .bank_number = 0,
1831 .base_address = FLASH_BANK0_BASE_AX,
1832 .controller_address = 0x400e0a00,
1833 .flash_wait_states = 6, /* workaround silicon bug */
1834 .present = 1,
1835 .size_bytes = 256 * 1024,
1836 .nsectors = 16,
1837 .sector_size = 16384,
1838 .page_size = 256,
1839 },
1840 /* .bank[1] = { */
1841 {
1842 .probed = 0,
1843 .pChip = NULL,
1844 .pBank = NULL,
1845 .bank_number = 1,
1846 .base_address = FLASH_BANK1_BASE_512K_AX,
1847 .controller_address = 0x400e0c00,
1848 .flash_wait_states = 6, /* workaround silicon bug */
1849 .present = 1,
1850 .size_bytes = 256 * 1024,
1851 .nsectors = 16,
1852 .sector_size = 16384,
1853 .page_size = 256,
1854
1855 },
1856 },
1857 },
1858 {
1859 .chipid_cidr = 0x285E0A60,
1860 .name = "at91sam3x8e",
1861 .total_flash_size = 512 * 1024,
1862 .total_sram_size = 96 * 1024,
1863 .n_gpnvms = 3,
1864 .n_banks = 2,
1865 {
1866 /* .bank[0] = { */
1867 {
1868 .probed = 0,
1869 .pChip = NULL,
1870 .pBank = NULL,
1871 .bank_number = 0,
1872 .base_address = FLASH_BANK0_BASE_AX,
1873 .controller_address = 0x400e0a00,
1874 .flash_wait_states = 6, /* workaround silicon bug */
1875 .present = 1,
1876 .size_bytes = 256 * 1024,
1877 .nsectors = 16,
1878 .sector_size = 16384,
1879 .page_size = 256,
1880 },
1881 /* .bank[1] = { */
1882 {
1883 .probed = 0,
1884 .pChip = NULL,
1885 .pBank = NULL,
1886 .bank_number = 1,
1887 .base_address = FLASH_BANK1_BASE_512K_AX,
1888 .controller_address = 0x400e0c00,
1889 .flash_wait_states = 6, /* workaround silicon bug */
1890 .present = 1,
1891 .size_bytes = 256 * 1024,
1892 .nsectors = 16,
1893 .sector_size = 16384,
1894 .page_size = 256,
1895
1896 },
1897 },
1898 },
1899 {
1900 .chipid_cidr = 0x284E0A60,
1901 .name = "at91sam3x8c",
1902 .total_flash_size = 512 * 1024,
1903 .total_sram_size = 96 * 1024,
1904 .n_gpnvms = 3,
1905 .n_banks = 2,
1906 {
1907 /* .bank[0] = { */
1908 {
1909 .probed = 0,
1910 .pChip = NULL,
1911 .pBank = NULL,
1912 .bank_number = 0,
1913 .base_address = FLASH_BANK0_BASE_AX,
1914 .controller_address = 0x400e0a00,
1915 .flash_wait_states = 6, /* workaround silicon bug */
1916 .present = 1,
1917 .size_bytes = 256 * 1024,
1918 .nsectors = 16,
1919 .sector_size = 16384,
1920 .page_size = 256,
1921 },
1922 /* .bank[1] = { */
1923 {
1924 .probed = 0,
1925 .pChip = NULL,
1926 .pBank = NULL,
1927 .bank_number = 1,
1928 .base_address = FLASH_BANK1_BASE_512K_AX ,
1929 .controller_address = 0x400e0c00,
1930 .flash_wait_states = 6, /* workaround silicon bug */
1931 .present = 1,
1932 .size_bytes = 256 * 1024,
1933 .nsectors = 16,
1934 .sector_size = 16384,
1935 .page_size = 256,
1936
1937 },
1938 },
1939 },
1940 {
1941 .chipid_cidr = 0x285B0960,
1942 .name = "at91sam3x4e",
1943 .total_flash_size = 256 * 1024,
1944 .total_sram_size = 64 * 1024,
1945 .n_gpnvms = 3,
1946 .n_banks = 2,
1947 {
1948 /* .bank[0] = { */
1949 {
1950 .probed = 0,
1951 .pChip = NULL,
1952 .pBank = NULL,
1953 .bank_number = 0,
1954 .base_address = FLASH_BANK0_BASE_AX,
1955 .controller_address = 0x400e0a00,
1956 .flash_wait_states = 6, /* workaround silicon bug */
1957 .present = 1,
1958 .size_bytes = 128 * 1024,
1959 .nsectors = 8,
1960 .sector_size = 16384,
1961 .page_size = 256,
1962 },
1963 /* .bank[1] = { */
1964 {
1965 .probed = 0,
1966 .pChip = NULL,
1967 .pBank = NULL,
1968 .bank_number = 1,
1969 .base_address = FLASH_BANK1_BASE_256K_AX,
1970 .controller_address = 0x400e0c00,
1971 .flash_wait_states = 6, /* workaround silicon bug */
1972 .present = 1,
1973 .size_bytes = 128 * 1024,
1974 .nsectors = 8,
1975 .sector_size = 16384,
1976 .page_size = 256,
1977
1978 },
1979 },
1980 },
1981 {
1982 .chipid_cidr = 0x284B0960,
1983 .name = "at91sam3x4c",
1984 .total_flash_size = 256 * 1024,
1985 .total_sram_size = 64 * 1024,
1986 .n_gpnvms = 3,
1987 .n_banks = 2,
1988 {
1989 /* .bank[0] = { */
1990 {
1991 .probed = 0,
1992 .pChip = NULL,
1993 .pBank = NULL,
1994 .bank_number = 0,
1995 .base_address = FLASH_BANK0_BASE_AX,
1996 .controller_address = 0x400e0a00,
1997 .flash_wait_states = 6, /* workaround silicon bug */
1998 .present = 1,
1999 .size_bytes = 128 * 1024,
2000 .nsectors = 8,
2001 .sector_size = 16384,
2002 .page_size = 256,
2003 },
2004 /* .bank[1] = { */
2005 {
2006 .probed = 0,
2007 .pChip = NULL,
2008 .pBank = NULL,
2009 .bank_number = 1,
2010 .base_address = FLASH_BANK1_BASE_256K_AX,
2011 .controller_address = 0x400e0c00,
2012 .flash_wait_states = 6, /* workaround silicon bug */
2013 .present = 1,
2014 .size_bytes = 128 * 1024,
2015 .nsectors = 8,
2016 .sector_size = 16384,
2017 .page_size = 256,
2018
2019 },
2020 },
2021 },
2022 /* terminate */
2023 {
2024 .chipid_cidr = 0,
2025 .name = NULL,
2026 }
2027 };
2028
2029 /* Globals above */
2030 /***********************************************************************
2031 **********************************************************************
2032 **********************************************************************
2033 **********************************************************************
2034 **********************************************************************
2035 **********************************************************************/
2036 /* *ATMEL* style code - from the SAM3 driver code */
2037
2038 /**
2039 * Get the current status of the EEFC and
2040 * the value of some status bits (LOCKE, PROGE).
2041 * @param pPrivate - info about the bank
2042 * @param v - result goes here
2043 */
2044 static int EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
2045 {
2046 int r;
2047 r = target_read_u32(pPrivate->pChip->target,
2048 pPrivate->controller_address + offset_EFC_FSR,
2049 v);
2050 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
2051 (unsigned int)(*v),
2052 ((unsigned int)((*v >> 2) & 1)),
2053 ((unsigned int)((*v >> 1) & 1)),
2054 ((unsigned int)((*v >> 0) & 1)));
2055
2056 return r;
2057 }
2058
2059 /**
2060 * Get the result of the last executed command.
2061 * @param pPrivate - info about the bank
2062 * @param v - result goes here
2063 */
2064 static int EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
2065 {
2066 int r;
2067 uint32_t rv;
2068 r = target_read_u32(pPrivate->pChip->target,
2069 pPrivate->controller_address + offset_EFC_FRR,
2070 &rv);
2071 if (v)
2072 *v = rv;
2073 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
2074 return r;
2075 }
2076
2077 static int EFC_StartCommand(struct sam3_bank_private *pPrivate,
2078 unsigned command, unsigned argument)
2079 {
2080 uint32_t n, v;
2081 int r;
2082 int retry;
2083
2084 retry = 0;
2085 do_retry:
2086
2087 /* Check command & argument */
2088 switch (command) {
2089
2090 case AT91C_EFC_FCMD_WP:
2091 case AT91C_EFC_FCMD_WPL:
2092 case AT91C_EFC_FCMD_EWP:
2093 case AT91C_EFC_FCMD_EWPL:
2094 /* case AT91C_EFC_FCMD_EPL: */
2095 /* case AT91C_EFC_FCMD_EPA: */
2096 case AT91C_EFC_FCMD_SLB:
2097 case AT91C_EFC_FCMD_CLB:
2098 n = (pPrivate->size_bytes / pPrivate->page_size);
2099 if (argument >= n)
2100 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
2101 break;
2102
2103 case AT91C_EFC_FCMD_SFB:
2104 case AT91C_EFC_FCMD_CFB:
2105 if (argument >= pPrivate->pChip->details.n_gpnvms) {
2106 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
2107 pPrivate->pChip->details.n_gpnvms);
2108 }
2109 break;
2110
2111 case AT91C_EFC_FCMD_GETD:
2112 case AT91C_EFC_FCMD_EA:
2113 case AT91C_EFC_FCMD_GLB:
2114 case AT91C_EFC_FCMD_GFB:
2115 case AT91C_EFC_FCMD_STUI:
2116 case AT91C_EFC_FCMD_SPUI:
2117 if (argument != 0)
2118 LOG_ERROR("Argument is meaningless for cmd: %d", command);
2119 break;
2120 default:
2121 LOG_ERROR("Unknown command %d", command);
2122 break;
2123 }
2124
2125 if (command == AT91C_EFC_FCMD_SPUI) {
2126 /* this is a very special situation. */
2127 /* Situation (1) - error/retry - see below */
2128 /* And we are being called recursively */
2129 /* Situation (2) - normal, finished reading unique id */
2130 } else {
2131 /* it should be "ready" */
2132 EFC_GetStatus(pPrivate, &v);
2133 if (v & 1) {
2134 /* then it is ready */
2135 /* we go on */
2136 } else {
2137 if (retry) {
2138 /* we have done this before */
2139 /* the controller is not responding. */
2140 LOG_ERROR("flash controller(%d) is not ready! Error",
2141 pPrivate->bank_number);
2142 return ERROR_FAIL;
2143 } else {
2144 retry++;
2145 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
2146 pPrivate->bank_number);
2147 /* we do that by issuing the *STOP* command */
2148 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
2149 /* above is recursive, and further recursion is blocked by */
2150 /* if (command == AT91C_EFC_FCMD_SPUI) above */
2151 goto do_retry;
2152 }
2153 }
2154 }
2155
2156 v = (0x5A << 24) | (argument << 8) | command;
2157 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
2158 r = target_write_u32(pPrivate->pBank->target,
2159 pPrivate->controller_address + offset_EFC_FCR, v);
2160 if (r != ERROR_OK)
2161 LOG_DEBUG("Error Write failed");
2162 return r;
2163 }
2164
2165 /**
2166 * Performs the given command and wait until its completion (or an error).
2167 * @param pPrivate - info about the bank
2168 * @param command - Command to perform.
2169 * @param argument - Optional command argument.
2170 * @param status - put command status bits here
2171 */
2172 static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,
2173 unsigned command,
2174 unsigned argument,
2175 uint32_t *status)
2176 {
2177
2178 int r;
2179 uint32_t v;
2180 long long ms_now, ms_end;
2181
2182 /* default */
2183 if (status)
2184 *status = 0;
2185
2186 r = EFC_StartCommand(pPrivate, command, argument);
2187 if (r != ERROR_OK)
2188 return r;
2189
2190 ms_end = 500 + timeval_ms();
2191
2192 do {
2193 r = EFC_GetStatus(pPrivate, &v);
2194 if (r != ERROR_OK)
2195 return r;
2196 ms_now = timeval_ms();
2197 if (ms_now > ms_end) {
2198 /* error */
2199 LOG_ERROR("Command timeout");
2200 return ERROR_FAIL;
2201 }
2202 } while ((v & 1) == 0);
2203
2204 /* error bits.. */
2205 if (status)
2206 *status = (v & 0x6);
2207 return ERROR_OK;
2208
2209 }
2210
2211 /**
2212 * Read the unique ID.
2213 * @param pPrivate - info about the bank
2214 * The unique ID is stored in the 'pPrivate' structure.
2215 */
2216 static int FLASHD_ReadUniqueID(struct sam3_bank_private *pPrivate)
2217 {
2218 int r;
2219 uint32_t v;
2220 int x;
2221 /* assume 0 */
2222 pPrivate->pChip->cfg.unique_id[0] = 0;
2223 pPrivate->pChip->cfg.unique_id[1] = 0;
2224 pPrivate->pChip->cfg.unique_id[2] = 0;
2225 pPrivate->pChip->cfg.unique_id[3] = 0;
2226
2227 LOG_DEBUG("Begin");
2228 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
2229 if (r < 0)
2230 return r;
2231
2232 for (x = 0; x < 4; x++) {
2233 r = target_read_u32(pPrivate->pChip->target,
2234 pPrivate->pBank->base + (x * 4),
2235 &v);
2236 if (r < 0)
2237 return r;
2238 pPrivate->pChip->cfg.unique_id[x] = v;
2239 }
2240
2241 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
2242 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
2243 r,
2244 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
2245 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
2246 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
2247 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
2248 return r;
2249
2250 }
2251
2252 /**
2253 * Erases the entire flash.
2254 * @param pPrivate - the info about the bank.
2255 */
2256 static int FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
2257 {
2258 LOG_DEBUG("Here");
2259 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
2260 }
2261
2262 /**
2263 * Gets current GPNVM state.
2264 * @param pPrivate - info about the bank.
2265 * @param gpnvm - GPNVM bit index.
2266 * @param puthere - result stored here.
2267 */
2268 /* ------------------------------------------------------------------------------ */
2269 static int FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
2270 {
2271 uint32_t v;
2272 int r;
2273
2274 LOG_DEBUG("Here");
2275 if (pPrivate->bank_number != 0) {
2276 LOG_ERROR("GPNVM only works with Bank0");
2277 return ERROR_FAIL;
2278 }
2279
2280 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
2281 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2282 gpnvm, pPrivate->pChip->details.n_gpnvms);
2283 return ERROR_FAIL;
2284 }
2285
2286 /* Get GPNVMs status */
2287 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
2288 if (r != ERROR_OK) {
2289 LOG_ERROR("Failed");
2290 return r;
2291 }
2292
2293 r = EFC_GetResult(pPrivate, &v);
2294
2295 if (puthere) {
2296 /* Check if GPNVM is set */
2297 /* get the bit and make it a 0/1 */
2298 *puthere = (v >> gpnvm) & 1;
2299 }
2300
2301 return r;
2302 }
2303
2304 /**
2305 * Clears the selected GPNVM bit.
2306 * @param pPrivate info about the bank
2307 * @param gpnvm GPNVM index.
2308 * @returns 0 if successful; otherwise returns an error code.
2309 */
2310 static int FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
2311 {
2312 int r;
2313 unsigned v;
2314
2315 LOG_DEBUG("Here");
2316 if (pPrivate->bank_number != 0) {
2317 LOG_ERROR("GPNVM only works with Bank0");
2318 return ERROR_FAIL;
2319 }
2320
2321 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
2322 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2323 gpnvm, pPrivate->pChip->details.n_gpnvms);
2324 return ERROR_FAIL;
2325 }
2326
2327 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
2328 if (r != ERROR_OK) {
2329 LOG_DEBUG("Failed: %d", r);
2330 return r;
2331 }
2332 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
2333 LOG_DEBUG("End: %d", r);
2334 return r;
2335 }
2336
2337 /**
2338 * Sets the selected GPNVM bit.
2339 * @param pPrivate info about the bank
2340 * @param gpnvm GPNVM index.
2341 */
2342 static int FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
2343 {
2344 int r;
2345 unsigned v;
2346
2347 if (pPrivate->bank_number != 0) {
2348 LOG_ERROR("GPNVM only works with Bank0");
2349 return ERROR_FAIL;
2350 }
2351
2352 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
2353 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2354 gpnvm, pPrivate->pChip->details.n_gpnvms);
2355 return ERROR_FAIL;
2356 }
2357
2358 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
2359 if (r != ERROR_OK)
2360 return r;
2361 if (v) {
2362 /* already set */
2363 r = ERROR_OK;
2364 } else {
2365 /* set it */
2366 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
2367 }
2368 return r;
2369 }
2370
2371 /**
2372 * Returns a bit field (at most 64) of locked regions within a page.
2373 * @param pPrivate info about the bank
2374 * @param v where to store locked bits
2375 */
2376 static int FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
2377 {
2378 int r;
2379 LOG_DEBUG("Here");
2380 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
2381 if (r == ERROR_OK)
2382 r = EFC_GetResult(pPrivate, v);
2383 LOG_DEBUG("End: %d", r);
2384 return r;
2385 }
2386
2387 /**
2388 * Unlocks all the regions in the given address range.
2389 * @param pPrivate info about the bank
2390 * @param start_sector first sector to unlock
2391 * @param end_sector last (inclusive) to unlock
2392 */
2393
2394 static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,
2395 unsigned start_sector,
2396 unsigned end_sector)
2397 {
2398 int r;
2399 uint32_t status;
2400 uint32_t pg;
2401 uint32_t pages_per_sector;
2402
2403 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
2404
2405 /* Unlock all pages */
2406 while (start_sector <= end_sector) {
2407 pg = start_sector * pages_per_sector;
2408
2409 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
2410 if (r != ERROR_OK)
2411 return r;
2412 start_sector++;
2413 }
2414
2415 return ERROR_OK;
2416 }
2417
2418 /**
2419 * Locks regions
2420 * @param pPrivate - info about the bank
2421 * @param start_sector - first sector to lock
2422 * @param end_sector - last sector (inclusive) to lock
2423 */
2424 static int FLASHD_Lock(struct sam3_bank_private *pPrivate,
2425 unsigned start_sector,
2426 unsigned end_sector)
2427 {
2428 uint32_t status;
2429 uint32_t pg;
2430 uint32_t pages_per_sector;
2431 int r;
2432
2433 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
2434
2435 /* Lock all pages */
2436 while (start_sector <= end_sector) {
2437 pg = start_sector * pages_per_sector;
2438
2439 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
2440 if (r != ERROR_OK)
2441 return r;
2442 start_sector++;
2443 }
2444 return ERROR_OK;
2445 }
2446
2447 /****** END SAM3 CODE ********/
2448
2449 /* begin helpful debug code */
2450 /* print the fieldname, the field value, in dec & hex, and return field value */
2451 static uint32_t sam3_reg_fieldname(struct sam3_chip *pChip,
2452 const char *regname,
2453 uint32_t value,
2454 unsigned shift,
2455 unsigned width)
2456 {
2457 uint32_t v;
2458 int hwidth, dwidth;
2459
2460
2461 /* extract the field */
2462 v = value >> shift;
2463 v = v & ((1 << width)-1);
2464 if (width <= 16) {
2465 hwidth = 4;
2466 dwidth = 5;
2467 } else {
2468 hwidth = 8;
2469 dwidth = 12;
2470 }
2471
2472 /* show the basics */
2473 LOG_USER_N("\t%*s: %*" PRIu32 " [0x%0*" PRIx32 "] ",
2474 REG_NAME_WIDTH, regname,
2475 dwidth, v,
2476 hwidth, v);
2477 return v;
2478 }
2479
2480 static const char _unknown[] = "unknown";
2481 static const char *const eproc_names[] = {
2482 _unknown, /* 0 */
2483 "arm946es", /* 1 */
2484 "arm7tdmi", /* 2 */
2485 "cortex-m3", /* 3 */
2486 "arm920t", /* 4 */
2487 "arm926ejs", /* 5 */
2488 _unknown, /* 6 */
2489 _unknown, /* 7 */
2490 _unknown, /* 8 */
2491 _unknown, /* 9 */
2492 _unknown, /* 10 */
2493 _unknown, /* 11 */
2494 _unknown, /* 12 */
2495 _unknown, /* 13 */
2496 _unknown, /* 14 */
2497 _unknown, /* 15 */
2498 };
2499
2500 #define nvpsize2 nvpsize /* these two tables are identical */
2501 static const char *const nvpsize[] = {
2502 "none", /* 0 */
2503 "8K bytes", /* 1 */
2504 "16K bytes", /* 2 */
2505 "32K bytes", /* 3 */
2506 _unknown, /* 4 */
2507 "64K bytes", /* 5 */
2508 _unknown, /* 6 */
2509 "128K bytes", /* 7 */
2510 _unknown, /* 8 */
2511 "256K bytes", /* 9 */
2512 "512K bytes", /* 10 */
2513 _unknown, /* 11 */
2514 "1024K bytes", /* 12 */
2515 _unknown, /* 13 */
2516 "2048K bytes", /* 14 */
2517 _unknown, /* 15 */
2518 };
2519
2520 static const char *const sramsize[] = {
2521 "48K Bytes", /* 0 */
2522 "1K Bytes", /* 1 */
2523 "2K Bytes", /* 2 */
2524 "6K Bytes", /* 3 */
2525 "112K Bytes", /* 4 */
2526 "4K Bytes", /* 5 */
2527 "80K Bytes", /* 6 */
2528 "160K Bytes", /* 7 */
2529 "8K Bytes", /* 8 */
2530 "16K Bytes", /* 9 */
2531 "32K Bytes", /* 10 */
2532 "64K Bytes", /* 11 */
2533 "128K Bytes", /* 12 */
2534 "256K Bytes", /* 13 */
2535 "96K Bytes", /* 14 */
2536 "512K Bytes", /* 15 */
2537
2538 };
2539
2540 static const struct archnames { unsigned value; const char *name; } archnames[] = {
2541 { 0x19, "AT91SAM9xx Series" },
2542 { 0x29, "AT91SAM9XExx Series" },
2543 { 0x34, "AT91x34 Series" },
2544 { 0x37, "CAP7 Series" },
2545 { 0x39, "CAP9 Series" },
2546 { 0x3B, "CAP11 Series" },
2547 { 0x40, "AT91x40 Series" },
2548 { 0x42, "AT91x42 Series" },
2549 { 0x55, "AT91x55 Series" },
2550 { 0x60, "AT91SAM7Axx Series" },
2551 { 0x61, "AT91SAM7AQxx Series" },
2552 { 0x63, "AT91x63 Series" },
2553 { 0x70, "AT91SAM7Sxx Series" },
2554 { 0x71, "AT91SAM7XCxx Series" },
2555 { 0x72, "AT91SAM7SExx Series" },
2556 { 0x73, "AT91SAM7Lxx Series" },
2557 { 0x75, "AT91SAM7Xxx Series" },
2558 { 0x76, "AT91SAM7SLxx Series" },
2559 { 0x80, "ATSAM3UxC Series (100-pin version)" },
2560 { 0x81, "ATSAM3UxE Series (144-pin version)" },
2561 { 0x83, "ATSAM3AxC Series (100-pin version)" },
2562 { 0x84, "ATSAM3XxC Series (100-pin version)" },
2563 { 0x85, "ATSAM3XxE Series (144-pin version)" },
2564 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
2565 { 0x88, "ATSAM3SxA Series (48-pin version)" },
2566 { 0x89, "ATSAM3SxB Series (64-pin version)" },
2567 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
2568 { 0x92, "AT91x92 Series" },
2569 { 0x93, "ATSAM3NxA Series (48-pin version)" },
2570 { 0x94, "ATSAM3NxB Series (64-pin version)" },
2571 { 0x95, "ATSAM3NxC Series (100-pin version)" },
2572 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2573 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2574 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2575 { 0xA5, "ATSAM5A" },
2576 { 0xF0, "AT75Cxx Series" },
2577 { -1, NULL },
2578 };
2579
2580 static const char *const nvptype[] = {
2581 "rom", /* 0 */
2582 "romless or onchip flash", /* 1 */
2583 "embedded flash memory",/* 2 */
2584 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2585 "sram emulating flash", /* 4 */
2586 _unknown, /* 5 */
2587 _unknown, /* 6 */
2588 _unknown, /* 7 */
2589 };
2590
2591 static const char *_yes_or_no(uint32_t v)
2592 {
2593 if (v)
2594 return "YES";
2595 else
2596 return "NO";
2597 }
2598
2599 static const char *const _rc_freq[] = {
2600 "4 MHz", "8 MHz", "12 MHz", "reserved"
2601 };
2602
2603 static void sam3_explain_ckgr_mor(struct sam3_chip *pChip)
2604 {
2605 uint32_t v;
2606 uint32_t rcen;
2607
2608 v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
2609 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2610 v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
2611 LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2612 rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
2613 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2614 v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
2615 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2616
2617 pChip->cfg.rc_freq = 0;
2618 if (rcen) {
2619 switch (v) {
2620 default:
2621 pChip->cfg.rc_freq = 0;
2622 break;
2623 case 0:
2624 pChip->cfg.rc_freq = 4 * 1000 * 1000;
2625 break;
2626 case 1:
2627 pChip->cfg.rc_freq = 8 * 1000 * 1000;
2628 break;
2629 case 2:
2630 pChip->cfg.rc_freq = 12 * 1000 * 1000;
2631 break;
2632 }
2633 }
2634
2635 v = sam3_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
2636 LOG_USER("(startup clks, time= %f uSecs)",
2637 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
2638 v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
2639 LOG_USER("(mainosc source: %s)",
2640 v ? "external xtal" : "internal RC");
2641
2642 v = sam3_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
2643 LOG_USER("(clock failure enabled: %s)",
2644 _yes_or_no(v));
2645 }
2646
2647 static void sam3_explain_chipid_cidr(struct sam3_chip *pChip)
2648 {
2649 int x;
2650 uint32_t v;
2651 const char *cp;
2652
2653 sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
2654 LOG_USER_N("\n");
2655
2656 v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
2657 LOG_USER("%s", eproc_names[v]);
2658
2659 v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
2660 LOG_USER("%s", nvpsize[v]);
2661
2662 v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
2663 LOG_USER("%s", nvpsize2[v]);
2664
2665 v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
2666 LOG_USER("%s", sramsize[v]);
2667
2668 v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
2669 cp = _unknown;
2670 for (x = 0; archnames[x].name; x++) {
2671 if (v == archnames[x].value) {
2672 cp = archnames[x].name;
2673 break;
2674 }
2675 }
2676
2677 LOG_USER("%s", cp);
2678
2679 v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
2680 LOG_USER("%s", nvptype[v]);
2681
2682 v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
2683 LOG_USER("(exists: %s)", _yes_or_no(v));
2684 }
2685
2686 static void sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
2687 {
2688 uint32_t v;
2689
2690 v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
2691 LOG_USER("(main ready: %s)", _yes_or_no(v));
2692
2693 v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
2694
2695 v = (v * pChip->cfg.slow_freq) / 16;
2696 pChip->cfg.mainosc_freq = v;
2697
2698 LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
2699 _tomhz(v),
2700 (uint32_t)(pChip->cfg.slow_freq / 1000),
2701 (uint32_t)(pChip->cfg.slow_freq % 1000));
2702 }
2703
2704 static void sam3_explain_ckgr_plla(struct sam3_chip *pChip)
2705 {
2706 uint32_t mula, diva;
2707
2708 diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
2709 LOG_USER_N("\n");
2710 mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
2711 LOG_USER_N("\n");
2712 pChip->cfg.plla_freq = 0;
2713 if (mula == 0)
2714 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2715 else if (diva == 0)
2716 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2717 else if (diva >= 1) {
2718 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
2719 LOG_USER("\tPLLA Freq: %3.03f MHz",
2720 _tomhz(pChip->cfg.plla_freq));
2721 }
2722 }
2723
2724 static void sam3_explain_mckr(struct sam3_chip *pChip)
2725 {
2726 uint32_t css, pres, fin = 0;
2727 int pdiv = 0;
2728 const char *cp = NULL;
2729
2730 css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
2731 switch (css & 3) {
2732 case 0:
2733 fin = pChip->cfg.slow_freq;
2734 cp = "slowclk";
2735 break;
2736 case 1:
2737 fin = pChip->cfg.mainosc_freq;
2738 cp = "mainosc";
2739 break;
2740 case 2:
2741 fin = pChip->cfg.plla_freq;
2742 cp = "plla";
2743 break;
2744 case 3:
2745 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
2746 fin = 480 * 1000 * 1000;
2747 cp = "upll";
2748 } else {
2749 fin = 0;
2750 cp = "upll (*ERROR* UPLL is disabled)";
2751 }
2752 break;
2753 default:
2754 assert(0);
2755 break;
2756 }
2757
2758 LOG_USER("%s (%3.03f Mhz)",
2759 cp,
2760 _tomhz(fin));
2761 pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
2762 switch (pres & 0x07) {
2763 case 0:
2764 pdiv = 1;
2765 cp = "selected clock";
2766 break;
2767 case 1:
2768 pdiv = 2;
2769 cp = "clock/2";
2770 break;
2771 case 2:
2772 pdiv = 4;
2773 cp = "clock/4";
2774 break;
2775 case 3:
2776 pdiv = 8;
2777 cp = "clock/8";
2778 break;
2779 case 4:
2780 pdiv = 16;
2781 cp = "clock/16";
2782 break;
2783 case 5:
2784 pdiv = 32;
2785 cp = "clock/32";
2786 break;
2787 case 6:
2788 pdiv = 64;
2789 cp = "clock/64";
2790 break;
2791 case 7:
2792 pdiv = 6;
2793 cp = "clock/6";
2794 break;
2795 default:
2796 assert(0);
2797 break;
2798 }
2799 LOG_USER("(%s)", cp);
2800 fin = fin / pdiv;
2801 /* sam3 has a *SINGLE* clock - */
2802 /* other at91 series parts have divisors for these. */
2803 pChip->cfg.cpu_freq = fin;
2804 pChip->cfg.mclk_freq = fin;
2805 pChip->cfg.fclk_freq = fin;
2806 LOG_USER("\t\tResult CPU Freq: %3.03f",
2807 _tomhz(fin));
2808 }
2809
2810 #if 0
2811 static struct sam3_chip *target2sam3(struct target *pTarget)
2812 {
2813 struct sam3_chip *pChip;
2814
2815 if (pTarget == NULL)
2816 return NULL;
2817
2818 pChip = all_sam3_chips;
2819 while (pChip) {
2820 if (pChip->target == pTarget)
2821 break; /* return below */
2822 else
2823 pChip = pChip->next;
2824 }
2825 return pChip;
2826 }
2827 #endif
2828
2829 static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
2830 {
2831 /* this function exists to help */
2832 /* keep funky offsetof() errors */
2833 /* and casting from causing bugs */
2834
2835 /* By using prototypes - we can detect what would */
2836 /* be casting errors. */
2837
2838 return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
2839 }
2840
2841
2842 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
2843 struct sam3_cfg, \
2844 NAME), # NAME, FUNC }
2845 static const struct sam3_reg_list sam3_all_regs[] = {
2846 SAM3_ENTRY(CKGR_MOR, sam3_explain_ckgr_mor),
2847 SAM3_ENTRY(CKGR_MCFR, sam3_explain_ckgr_mcfr),
2848 SAM3_ENTRY(CKGR_PLLAR, sam3_explain_ckgr_plla),
2849 SAM3_ENTRY(CKGR_UCKR, NULL),
2850 SAM3_ENTRY(PMC_FSMR, NULL),
2851 SAM3_ENTRY(PMC_FSPR, NULL),
2852 SAM3_ENTRY(PMC_IMR, NULL),
2853 SAM3_ENTRY(PMC_MCKR, sam3_explain_mckr),
2854 SAM3_ENTRY(PMC_PCK0, NULL),
2855 SAM3_ENTRY(PMC_PCK1, NULL),
2856 SAM3_ENTRY(PMC_PCK2, NULL),
2857 SAM3_ENTRY(PMC_PCSR, NULL),
2858 SAM3_ENTRY(PMC_SCSR, NULL),
2859 SAM3_ENTRY(PMC_SR, NULL),
2860 SAM3_ENTRY(CHIPID_CIDR, sam3_explain_chipid_cidr),
2861 SAM3_ENTRY(CHIPID_CIDR2, sam3_explain_chipid_cidr),
2862 SAM3_ENTRY(CHIPID_EXID, NULL),
2863 SAM3_ENTRY(CHIPID_EXID2, NULL),
2864 /* TERMINATE THE LIST */
2865 { .name = NULL }
2866 };
2867 #undef SAM3_ENTRY
2868
2869 static struct sam3_bank_private *get_sam3_bank_private(struct flash_bank *bank)
2870 {
2871 return bank->driver_priv;
2872 }
2873
2874 /**
2875 * Given a pointer to where it goes in the structure,
2876 * determine the register name, address from the all registers table.
2877 */
2878 static const struct sam3_reg_list *sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
2879 {
2880 const struct sam3_reg_list *pReg;
2881
2882 pReg = &(sam3_all_regs[0]);
2883 while (pReg->name) {
2884 uint32_t *pPossible;
2885
2886 /* calculate where this one go.. */
2887 /* it is "possibly" this register. */
2888
2889 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
2890
2891 /* well? Is it this register */
2892 if (pPossible == goes_here) {
2893 /* Jump for joy! */
2894 return pReg;
2895 }
2896
2897 /* next... */
2898 pReg++;
2899 }
2900 /* This is *TOTAL*PANIC* - we are totally screwed. */
2901 LOG_ERROR("INVALID SAM3 REGISTER");
2902 return NULL;
2903 }
2904
2905 static int sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
2906 {
2907 const struct sam3_reg_list *pReg;
2908 int r;
2909
2910 pReg = sam3_GetReg(pChip, goes_here);
2911 if (!pReg)
2912 return ERROR_FAIL;
2913
2914 r = target_read_u32(pChip->target, pReg->address, goes_here);
2915 if (r != ERROR_OK) {
2916 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
2917 pReg->name, (unsigned)(pReg->address), r);
2918 }
2919 return r;
2920 }
2921
2922 static int sam3_ReadAllRegs(struct sam3_chip *pChip)
2923 {
2924 int r;
2925 const struct sam3_reg_list *pReg;
2926
2927 pReg = &(sam3_all_regs[0]);
2928 while (pReg->name) {
2929 r = sam3_ReadThisReg(pChip,
2930 sam3_get_reg_ptr(&(pChip->cfg), pReg));
2931 if (r != ERROR_OK) {
2932 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Error: %d",
2933 pReg->name, ((unsigned)(pReg->address)), r);
2934 return r;
2935 }
2936 pReg++;
2937 }
2938
2939 /* Chip identification register
2940 *
2941 * Unfortunately, the chip identification register is not at
2942 * a constant address across all of the SAM3 series'. As a
2943 * consequence, a simple heuristic is used to find where it's
2944 * at...
2945 *
2946 * If the contents at the first address is zero, then we know
2947 * that the second address is where the chip id register is.
2948 * We can deduce this because for those SAM's that have the
2949 * chip id @ 0x400e0940, the first address, 0x400e0740, is
2950 * located in the memory map of the Power Management Controller
2951 * (PMC). Furthermore, the address is not used by the PMC.
2952 * So when read, the memory controller returns zero.*/
2953 if (pChip->cfg.CHIPID_CIDR == 0) {
2954 /*Put the correct CIDR and EXID values in the pChip structure */
2955 pChip->cfg.CHIPID_CIDR = pChip->cfg.CHIPID_CIDR2;
2956 pChip->cfg.CHIPID_EXID = pChip->cfg.CHIPID_EXID2;
2957 }
2958 return ERROR_OK;
2959 }
2960
2961 static int sam3_GetInfo(struct sam3_chip *pChip)
2962 {
2963 const struct sam3_reg_list *pReg;
2964 uint32_t regval;
2965
2966 pReg = &(sam3_all_regs[0]);
2967 while (pReg->name) {
2968 /* display all regs */
2969 LOG_DEBUG("Start: %s", pReg->name);
2970 regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
2971 LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
2972 REG_NAME_WIDTH,
2973 pReg->name,
2974 pReg->address,
2975 regval);
2976 if (pReg->explain_func)
2977 (*(pReg->explain_func))(pChip);
2978 LOG_DEBUG("End: %s", pReg->name);
2979 pReg++;
2980 }
2981 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
2982 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
2983 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
2984 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
2985 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
2986
2987 LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32,
2988 pChip->cfg.unique_id[0],
2989 pChip->cfg.unique_id[1],
2990 pChip->cfg.unique_id[2],
2991 pChip->cfg.unique_id[3]);
2992
2993 return ERROR_OK;
2994 }
2995
2996 static int sam3_erase_check(struct flash_bank *bank)
2997 {
2998 int x;
2999
3000 LOG_DEBUG("Here");
3001 if (bank->target->state != TARGET_HALTED) {
3002 LOG_ERROR("Target not halted");
3003 return ERROR_TARGET_NOT_HALTED;
3004 }
3005 if (0 == bank->num_sectors) {
3006 LOG_ERROR("Target: not supported/not probed");
3007 return ERROR_FAIL;
3008 }
3009
3010 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
3011 for (x = 0; x < bank->num_sectors; x++)
3012 bank->sectors[x].is_erased = 1;
3013
3014 LOG_DEBUG("Done");
3015 return ERROR_OK;
3016 }
3017
3018 static int sam3_protect_check(struct flash_bank *bank)
3019 {
3020 int r;
3021 uint32_t v = 0;
3022 unsigned x;
3023 struct sam3_bank_private *pPrivate;
3024
3025 LOG_DEBUG("Begin");
3026 if (bank->target->state != TARGET_HALTED) {
3027 LOG_ERROR("Target not halted");
3028 return ERROR_TARGET_NOT_HALTED;
3029 }
3030
3031 pPrivate = get_sam3_bank_private(bank);
3032 if (!pPrivate) {
3033 LOG_ERROR("no private for this bank?");
3034 return ERROR_FAIL;
3035 }
3036 if (!(pPrivate->probed))
3037 return ERROR_FLASH_BANK_NOT_PROBED;
3038
3039 r = FLASHD_GetLockBits(pPrivate, &v);
3040 if (r != ERROR_OK) {
3041 LOG_DEBUG("Failed: %d", r);
3042 return r;
3043 }
3044
3045 for (x = 0; x < pPrivate->nsectors; x++)
3046 bank->sectors[x].is_protected = (!!(v & (1 << x)));
3047 LOG_DEBUG("Done");
3048 return ERROR_OK;
3049 }
3050
3051 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
3052 {
3053 struct sam3_chip *pChip;
3054
3055 pChip = all_sam3_chips;
3056
3057 /* is this an existing chip? */
3058 while (pChip) {
3059 if (pChip->target == bank->target)
3060 break;
3061 pChip = pChip->next;
3062 }
3063
3064 if (!pChip) {
3065 /* this is a *NEW* chip */
3066 pChip = calloc(1, sizeof(struct sam3_chip));
3067 if (!pChip) {
3068 LOG_ERROR("NO RAM!");
3069 return ERROR_FAIL;
3070 }
3071 pChip->target = bank->target;
3072 /* insert at head */
3073 pChip->next = all_sam3_chips;
3074 all_sam3_chips = pChip;
3075 pChip->target = bank->target;
3076 /* assumption is this runs at 32khz */
3077 pChip->cfg.slow_freq = 32768;
3078 pChip->probed = 0;
3079 }
3080
3081 switch (bank->base) {
3082 default:
3083 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x "
3084 "[at91sam3u series] or 0x%08x [at91sam3s series] or "
3085 "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )",
3086 ((unsigned int)(bank->base)),
3087 ((unsigned int)(FLASH_BANK0_BASE_U)),
3088 ((unsigned int)(FLASH_BANK1_BASE_U)),
3089 ((unsigned int)(FLASH_BANK_BASE_S)),
3090 ((unsigned int)(FLASH_BANK_BASE_N)),
3091 ((unsigned int)(FLASH_BANK0_BASE_AX)),
3092 ((unsigned int)(FLASH_BANK1_BASE_256K_AX)),
3093 ((unsigned int)(FLASH_BANK1_BASE_512K_AX)));
3094 return ERROR_FAIL;
3095 break;
3096
3097 /* at91sam3s and at91sam3n series only has bank 0*/
3098 /* at91sam3u and at91sam3ax series has the same address for bank 0*/
3099 case FLASH_BANK_BASE_S:
3100 case FLASH_BANK0_BASE_U:
3101 bank->driver_priv = &(pChip->details.bank[0]);
3102 bank->bank_number = 0;
3103 pChip->details.bank[0].pChip = pChip;
3104 pChip->details.bank[0].pBank = bank;
3105 break;
3106
3107 /* Bank 1 of at91sam3u or at91sam3ax series */
3108 case FLASH_BANK1_BASE_U:
3109 case FLASH_BANK1_BASE_256K_AX:
3110 case FLASH_BANK1_BASE_512K_AX:
3111 bank->driver_priv = &(pChip->details.bank[1]);
3112 bank->bank_number = 1;
3113 pChip->details.bank[1].pChip = pChip;
3114 pChip->details.bank[1].pBank = bank;
3115 break;
3116 }
3117
3118 /* we initialize after probing. */
3119 return ERROR_OK;
3120 }
3121
3122 static int sam3_GetDetails(struct sam3_bank_private *pPrivate)
3123 {
3124 const struct sam3_chip_details *pDetails;
3125 struct sam3_chip *pChip;
3126 struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
3127 unsigned x;
3128
3129 LOG_DEBUG("Begin");
3130 pDetails = all_sam3_details;
3131 while (pDetails->name) {
3132 /* Compare cidr without version bits */
3133 if (((pDetails->chipid_cidr ^ pPrivate->pChip->cfg.CHIPID_CIDR) & 0xFFFFFFE0) == 0)
3134 break;
3135 else
3136 pDetails++;