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flash/nor/at91sam: implement flash bank deallocation for SAM series
[openocd.git] / src / flash / nor / at91sam3.c
1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
4 * *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
7 * *
8 * Copyright (C) 2011 by Olivier Schonken (at91sam3x* support) * *
9 * and Jim Norris *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
19 * *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
22 ****************************************************************************/
23
24 /* Some of the the lower level code was based on code supplied by
25 * ATMEL under this copyright. */
26
27 /* BEGIN ATMEL COPYRIGHT */
28 /* ----------------------------------------------------------------------------
29 * ATMEL Microcontroller Software Support
30 * ----------------------------------------------------------------------------
31 * Copyright (c) 2009, Atmel Corporation
32 *
33 * All rights reserved.
34 *
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions are met:
37 *
38 * - Redistributions of source code must retain the above copyright notice,
39 * this list of conditions and the disclaimer below.
40 *
41 * Atmel's name may not be used to endorse or promote products derived from
42 * this software without specific prior written permission.
43 *
44 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
46 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
47 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
50 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
51 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
52 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
53 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 * ----------------------------------------------------------------------------
55 */
56 /* END ATMEL COPYRIGHT */
57
58 #ifdef HAVE_CONFIG_H
59 #include "config.h"
60 #endif
61
62 #include "imp.h"
63 #include <helper/time_support.h>
64
65 #define REG_NAME_WIDTH (12)
66
67 /* at91sam3u series (has one or two flash banks) */
68 #define FLASH_BANK0_BASE_U 0x00080000
69 #define FLASH_BANK1_BASE_U 0x00100000
70
71 /* at91sam3s series (has always one flash bank) */
72 #define FLASH_BANK_BASE_S 0x00400000
73
74 /* at91sam3sd series (has always two flash banks) */
75 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
76 #define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))
77
78
79 /* at91sam3n series (has always one flash bank) */
80 #define FLASH_BANK_BASE_N 0x00400000
81
82 /* at91sam3a/x series has two flash banks*/
83 #define FLASH_BANK0_BASE_AX 0x00080000
84 /*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/
85 #define FLASH_BANK1_BASE_256K_AX 0x000A0000
86 #define FLASH_BANK1_BASE_512K_AX 0x000C0000
87
88 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
89 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
90 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
91 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
92 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
93 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
94 /* cmd6 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
95 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
96 /* cmd7 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
97 /* #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages? */
98 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
99 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
100 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
101 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
102 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
103 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
104 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
105 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
106
107 #define offset_EFC_FMR 0
108 #define offset_EFC_FCR 4
109 #define offset_EFC_FSR 8
110 #define offset_EFC_FRR 12
111
112 extern struct flash_driver at91sam3_flash;
113
114 static float _tomhz(uint32_t freq_hz)
115 {
116 float f;
117
118 f = ((float)(freq_hz)) / 1000000.0;
119 return f;
120 }
121
122 /* How the chip is configured. */
123 struct sam3_cfg {
124 uint32_t unique_id[4];
125
126 uint32_t slow_freq;
127 uint32_t rc_freq;
128 uint32_t mainosc_freq;
129 uint32_t plla_freq;
130 uint32_t mclk_freq;
131 uint32_t cpu_freq;
132 uint32_t fclk_freq;
133 uint32_t pclk0_freq;
134 uint32_t pclk1_freq;
135 uint32_t pclk2_freq;
136
137
138 #define SAM3_CHIPID_CIDR (0x400E0740)
139 uint32_t CHIPID_CIDR;
140 #define SAM3_CHIPID_CIDR2 (0x400E0940) /*SAM3X and SAM3A cidr at this address*/
141 uint32_t CHIPID_CIDR2;
142 #define SAM3_CHIPID_EXID (0x400E0744)
143 uint32_t CHIPID_EXID;
144 #define SAM3_CHIPID_EXID2 (0x400E0944) /*SAM3X and SAM3A cidr at this address*/
145 uint32_t CHIPID_EXID2;
146
147
148 #define SAM3_PMC_BASE (0x400E0400)
149 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
150 uint32_t PMC_SCSR;
151 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
152 uint32_t PMC_PCSR;
153 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
154 uint32_t CKGR_UCKR;
155 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
156 uint32_t CKGR_MOR;
157 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
158 uint32_t CKGR_MCFR;
159 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
160 uint32_t CKGR_PLLAR;
161 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
162 uint32_t PMC_MCKR;
163 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
164 uint32_t PMC_PCK0;
165 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
166 uint32_t PMC_PCK1;
167 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
168 uint32_t PMC_PCK2;
169 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
170 uint32_t PMC_SR;
171 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
172 uint32_t PMC_IMR;
173 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
174 uint32_t PMC_FSMR;
175 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
176 uint32_t PMC_FSPR;
177 };
178
179 /*
180 * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
181 * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
182 * the flash wait state (FWS) should be set to 6. It seems like that the
183 * cause of the problem is not the flash itself, but the flash write
184 * buffer. Ie the wait states have to be set before writing into the
185 * buffer.
186 * Tested and confirmed with SAM3N and SAM3U
187 */
188
189 struct sam3_bank_private {
190 int probed;
191 /* DANGER: THERE ARE DRAGONS HERE.. */
192 /* NOTE: If you add more 'ghost' pointers */
193 /* be aware that you must *manually* update */
194 /* these pointers in the function sam3_GetDetails() */
195 /* See the comment "Here there be dragons" */
196
197 /* so we can find the chip we belong to */
198 struct sam3_chip *pChip;
199 /* so we can find the original bank pointer */
200 struct flash_bank *pBank;
201 unsigned bank_number;
202 uint32_t controller_address;
203 uint32_t base_address;
204 uint32_t flash_wait_states;
205 bool present;
206 unsigned size_bytes;
207 unsigned nsectors;
208 unsigned sector_size;
209 unsigned page_size;
210 };
211
212 struct sam3_chip_details {
213 /* THERE ARE DRAGONS HERE.. */
214 /* note: If you add pointers here */
215 /* be careful about them as they */
216 /* may need to be updated inside */
217 /* the function: "sam3_GetDetails() */
218 /* which copy/overwrites the */
219 /* 'runtime' copy of this structure */
220 uint32_t chipid_cidr;
221 const char *name;
222
223 unsigned n_gpnvms;
224 #define SAM3_N_NVM_BITS 3
225 unsigned gpnvm[SAM3_N_NVM_BITS];
226 unsigned total_flash_size;
227 unsigned total_sram_size;
228 unsigned n_banks;
229 #define SAM3_MAX_FLASH_BANKS 2
230 /* these are "initialized" from the global const data */
231 struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
232 };
233
234 struct sam3_chip {
235 struct sam3_chip *next;
236 int probed;
237
238 /* this is "initialized" from the global const structure */
239 struct sam3_chip_details details;
240 struct target *target;
241 struct sam3_cfg cfg;
242 };
243
244
245 struct sam3_reg_list {
246 uint32_t address; size_t struct_offset; const char *name;
247 void (*explain_func)(struct sam3_chip *pInfo);
248 };
249
250 static struct sam3_chip *all_sam3_chips;
251
252 static struct sam3_chip *get_current_sam3(struct command_context *cmd_ctx)
253 {
254 struct target *t;
255 static struct sam3_chip *p;
256
257 t = get_current_target(cmd_ctx);
258 if (!t) {
259 command_print(cmd_ctx, "No current target?");
260 return NULL;
261 }
262
263 p = all_sam3_chips;
264 if (!p) {
265 /* this should not happen */
266 /* the command is not registered until the chip is created? */
267 command_print(cmd_ctx, "No SAM3 chips exist?");
268 return NULL;
269 }
270
271 while (p) {
272 if (p->target == t)
273 return p;
274 p = p->next;
275 }
276 command_print(cmd_ctx, "Cannot find SAM3 chip?");
277 return NULL;
278 }
279
280 /* these are used to *initialize* the "pChip->details" structure. */
281 static const struct sam3_chip_details all_sam3_details[] = {
282 /* Start at91sam3u* series */
283 {
284 .chipid_cidr = 0x28100960,
285 .name = "at91sam3u4e",
286 .total_flash_size = 256 * 1024,
287 .total_sram_size = 52 * 1024,
288 .n_gpnvms = 3,
289 .n_banks = 2,
290
291 /* System boots at address 0x0 */
292 /* gpnvm[1] = selects boot code */
293 /* if gpnvm[1] == 0 */
294 /* boot is via "SAMBA" (rom) */
295 /* else */
296 /* boot is via FLASH */
297 /* Selection is via gpnvm[2] */
298 /* endif */
299 /* */
300 /* NOTE: banks 0 & 1 switch places */
301 /* if gpnvm[2] == 0 */
302 /* Bank0 is the boot rom */
303 /* else */
304 /* Bank1 is the boot rom */
305 /* endif */
306 /* .bank[0] = { */
307 {
308 {
309 .probed = 0,
310 .pChip = NULL,
311 .pBank = NULL,
312 .bank_number = 0,
313 .base_address = FLASH_BANK0_BASE_U,
314 .controller_address = 0x400e0800,
315 .flash_wait_states = 6, /* workaround silicon bug */
316 .present = 1,
317 .size_bytes = 128 * 1024,
318 .nsectors = 16,
319 .sector_size = 8192,
320 .page_size = 256,
321 },
322
323 /* .bank[1] = { */
324 {
325 .probed = 0,
326 .pChip = NULL,
327 .pBank = NULL,
328 .bank_number = 1,
329 .base_address = FLASH_BANK1_BASE_U,
330 .controller_address = 0x400e0a00,
331 .flash_wait_states = 6, /* workaround silicon bug */
332 .present = 1,
333 .size_bytes = 128 * 1024,
334 .nsectors = 16,
335 .sector_size = 8192,
336 .page_size = 256,
337 },
338 },
339 },
340
341 {
342 .chipid_cidr = 0x281a0760,
343 .name = "at91sam3u2e",
344 .total_flash_size = 128 * 1024,
345 .total_sram_size = 36 * 1024,
346 .n_gpnvms = 2,
347 .n_banks = 1,
348
349 /* System boots at address 0x0 */
350 /* gpnvm[1] = selects boot code */
351 /* if gpnvm[1] == 0 */
352 /* boot is via "SAMBA" (rom) */
353 /* else */
354 /* boot is via FLASH */
355 /* Selection is via gpnvm[2] */
356 /* endif */
357 /* .bank[0] = { */
358 {
359 {
360 .probed = 0,
361 .pChip = NULL,
362 .pBank = NULL,
363 .bank_number = 0,
364 .base_address = FLASH_BANK0_BASE_U,
365 .controller_address = 0x400e0800,
366 .flash_wait_states = 6, /* workaround silicon bug */
367 .present = 1,
368 .size_bytes = 128 * 1024,
369 .nsectors = 16,
370 .sector_size = 8192,
371 .page_size = 256,
372 },
373 /* .bank[1] = { */
374 {
375 .present = 0,
376 .probed = 0,
377 .bank_number = 1,
378 },
379 },
380 },
381 {
382 .chipid_cidr = 0x28190560,
383 .name = "at91sam3u1e",
384 .total_flash_size = 64 * 1024,
385 .total_sram_size = 20 * 1024,
386 .n_gpnvms = 2,
387 .n_banks = 1,
388
389 /* System boots at address 0x0 */
390 /* gpnvm[1] = selects boot code */
391 /* if gpnvm[1] == 0 */
392 /* boot is via "SAMBA" (rom) */
393 /* else */
394 /* boot is via FLASH */
395 /* Selection is via gpnvm[2] */
396 /* endif */
397 /* */
398
399 /* .bank[0] = { */
400 {
401 {
402 .probed = 0,
403 .pChip = NULL,
404 .pBank = NULL,
405 .bank_number = 0,
406 .base_address = FLASH_BANK0_BASE_U,
407 .controller_address = 0x400e0800,
408 .flash_wait_states = 6, /* workaround silicon bug */
409 .present = 1,
410 .size_bytes = 64 * 1024,
411 .nsectors = 8,
412 .sector_size = 8192,
413 .page_size = 256,
414 },
415
416 /* .bank[1] = { */
417 {
418 .present = 0,
419 .probed = 0,
420 .bank_number = 1,
421 },
422 },
423 },
424
425 {
426 .chipid_cidr = 0x28000960,
427 .name = "at91sam3u4c",
428 .total_flash_size = 256 * 1024,
429 .total_sram_size = 52 * 1024,
430 .n_gpnvms = 3,
431 .n_banks = 2,
432
433 /* System boots at address 0x0 */
434 /* gpnvm[1] = selects boot code */
435 /* if gpnvm[1] == 0 */
436 /* boot is via "SAMBA" (rom) */
437 /* else */
438 /* boot is via FLASH */
439 /* Selection is via gpnvm[2] */
440 /* endif */
441 /* */
442 /* NOTE: banks 0 & 1 switch places */
443 /* if gpnvm[2] == 0 */
444 /* Bank0 is the boot rom */
445 /* else */
446 /* Bank1 is the boot rom */
447 /* endif */
448 {
449 {
450 /* .bank[0] = { */
451 .probed = 0,
452 .pChip = NULL,
453 .pBank = NULL,
454 .bank_number = 0,
455 .base_address = FLASH_BANK0_BASE_U,
456 .controller_address = 0x400e0800,
457 .flash_wait_states = 6, /* workaround silicon bug */
458 .present = 1,
459 .size_bytes = 128 * 1024,
460 .nsectors = 16,
461 .sector_size = 8192,
462 .page_size = 256,
463 },
464 /* .bank[1] = { */
465 {
466 .probed = 0,
467 .pChip = NULL,
468 .pBank = NULL,
469 .bank_number = 1,
470 .base_address = FLASH_BANK1_BASE_U,
471 .controller_address = 0x400e0a00,
472 .flash_wait_states = 6, /* workaround silicon bug */
473 .present = 1,
474 .size_bytes = 128 * 1024,
475 .nsectors = 16,
476 .sector_size = 8192,
477 .page_size = 256,
478 },
479 },
480 },
481
482 {
483 .chipid_cidr = 0x280a0760,
484 .name = "at91sam3u2c",
485 .total_flash_size = 128 * 1024,
486 .total_sram_size = 36 * 1024,
487 .n_gpnvms = 2,
488 .n_banks = 1,
489
490 /* System boots at address 0x0 */
491 /* gpnvm[1] = selects boot code */
492 /* if gpnvm[1] == 0 */
493 /* boot is via "SAMBA" (rom) */
494 /* else */
495 /* boot is via FLASH */
496 /* Selection is via gpnvm[2] */
497 /* endif */
498 {
499 /* .bank[0] = { */
500 {
501 .probed = 0,
502 .pChip = NULL,
503 .pBank = NULL,
504 .bank_number = 0,
505 .base_address = FLASH_BANK0_BASE_U,
506 .controller_address = 0x400e0800,
507 .flash_wait_states = 6, /* workaround silicon bug */
508 .present = 1,
509 .size_bytes = 128 * 1024,
510 .nsectors = 16,
511 .sector_size = 8192,
512 .page_size = 256,
513 },
514 /* .bank[1] = { */
515 {
516 .present = 0,
517 .probed = 0,
518 .bank_number = 1,
519 },
520 },
521 },
522 {
523 .chipid_cidr = 0x28090560,
524 .name = "at91sam3u1c",
525 .total_flash_size = 64 * 1024,
526 .total_sram_size = 20 * 1024,
527 .n_gpnvms = 2,
528 .n_banks = 1,
529
530 /* System boots at address 0x0 */
531 /* gpnvm[1] = selects boot code */
532 /* if gpnvm[1] == 0 */
533 /* boot is via "SAMBA" (rom) */
534 /* else */
535 /* boot is via FLASH */
536 /* Selection is via gpnvm[2] */
537 /* endif */
538 /* */
539
540 {
541 /* .bank[0] = { */
542 {
543 .probed = 0,
544 .pChip = NULL,
545 .pBank = NULL,
546 .bank_number = 0,
547 .base_address = FLASH_BANK0_BASE_U,
548 .controller_address = 0x400e0800,
549 .flash_wait_states = 6, /* workaround silicon bug */
550 .present = 1,
551 .size_bytes = 64 * 1024,
552 .nsectors = 8,
553 .sector_size = 8192,
554 .page_size = 256,
555 },
556 /* .bank[1] = { */
557 {
558 .present = 0,
559 .probed = 0,
560 .bank_number = 1,
561
562 },
563 },
564 },
565
566 /* Start at91sam3s* series */
567
568 /* Note: The preliminary at91sam3s datasheet says on page 302 */
569 /* that the flash controller is at address 0x400E0800. */
570 /* This is _not_ the case, the controller resides at address 0x400e0a00. */
571 {
572 .chipid_cidr = 0x28A00960,
573 .name = "at91sam3s4c",
574 .total_flash_size = 256 * 1024,
575 .total_sram_size = 48 * 1024,
576 .n_gpnvms = 2,
577 .n_banks = 1,
578 {
579 /* .bank[0] = { */
580 {
581 .probed = 0,
582 .pChip = NULL,
583 .pBank = NULL,
584 .bank_number = 0,
585 .base_address = FLASH_BANK_BASE_S,
586 .controller_address = 0x400e0a00,
587 .flash_wait_states = 6, /* workaround silicon bug */
588 .present = 1,
589 .size_bytes = 256 * 1024,
590 .nsectors = 16,
591 .sector_size = 16384,
592 .page_size = 256,
593 },
594 /* .bank[1] = { */
595 {
596 .present = 0,
597 .probed = 0,
598 .bank_number = 1,
599
600 },
601 },
602 },
603
604 {
605 .chipid_cidr = 0x28900960,
606 .name = "at91sam3s4b",
607 .total_flash_size = 256 * 1024,
608 .total_sram_size = 48 * 1024,
609 .n_gpnvms = 2,
610 .n_banks = 1,
611 {
612 /* .bank[0] = { */
613 {
614 .probed = 0,
615 .pChip = NULL,
616 .pBank = NULL,
617 .bank_number = 0,
618 .base_address = FLASH_BANK_BASE_S,
619 .controller_address = 0x400e0a00,
620 .flash_wait_states = 6, /* workaround silicon bug */
621 .present = 1,
622 .size_bytes = 256 * 1024,
623 .nsectors = 16,
624 .sector_size = 16384,
625 .page_size = 256,
626 },
627 /* .bank[1] = { */
628 {
629 .present = 0,
630 .probed = 0,
631 .bank_number = 1,
632
633 },
634 },
635 },
636 {
637 .chipid_cidr = 0x28800960,
638 .name = "at91sam3s4a",
639 .total_flash_size = 256 * 1024,
640 .total_sram_size = 48 * 1024,
641 .n_gpnvms = 2,
642 .n_banks = 1,
643 {
644 /* .bank[0] = { */
645 {
646 .probed = 0,
647 .pChip = NULL,
648 .pBank = NULL,
649 .bank_number = 0,
650 .base_address = FLASH_BANK_BASE_S,
651 .controller_address = 0x400e0a00,
652 .flash_wait_states = 6, /* workaround silicon bug */
653 .present = 1,
654 .size_bytes = 256 * 1024,
655 .nsectors = 16,
656 .sector_size = 16384,
657 .page_size = 256,
658 },
659 /* .bank[1] = { */
660 {
661 .present = 0,
662 .probed = 0,
663 .bank_number = 1,
664
665 },
666 },
667 },
668 {
669 .chipid_cidr = 0x28AA0760,
670 .name = "at91sam3s2c",
671 .total_flash_size = 128 * 1024,
672 .total_sram_size = 32 * 1024,
673 .n_gpnvms = 2,
674 .n_banks = 1,
675 {
676 /* .bank[0] = { */
677 {
678 .probed = 0,
679 .pChip = NULL,
680 .pBank = NULL,
681 .bank_number = 0,
682 .base_address = FLASH_BANK_BASE_S,
683 .controller_address = 0x400e0a00,
684 .flash_wait_states = 6, /* workaround silicon bug */
685 .present = 1,
686 .size_bytes = 128 * 1024,
687 .nsectors = 8,
688 .sector_size = 16384,
689 .page_size = 256,
690 },
691 /* .bank[1] = { */
692 {
693 .present = 0,
694 .probed = 0,
695 .bank_number = 1,
696
697 },
698 },
699 },
700 {
701 .chipid_cidr = 0x289A0760,
702 .name = "at91sam3s2b",
703 .total_flash_size = 128 * 1024,
704 .total_sram_size = 32 * 1024,
705 .n_gpnvms = 2,
706 .n_banks = 1,
707 {
708 /* .bank[0] = { */
709 {
710 .probed = 0,
711 .pChip = NULL,
712 .pBank = NULL,
713 .bank_number = 0,
714 .base_address = FLASH_BANK_BASE_S,
715 .controller_address = 0x400e0a00,
716 .flash_wait_states = 6, /* workaround silicon bug */
717 .present = 1,
718 .size_bytes = 128 * 1024,
719 .nsectors = 8,
720 .sector_size = 16384,
721 .page_size = 256,
722 },
723 /* .bank[1] = { */
724 {
725 .present = 0,
726 .probed = 0,
727 .bank_number = 1,
728
729 },
730 },
731 },
732 {
733 .chipid_cidr = 0x298B0A60,
734 .name = "at91sam3sd8a",
735 .total_flash_size = 512 * 1024,
736 .total_sram_size = 64 * 1024,
737 .n_gpnvms = 3,
738 .n_banks = 2,
739 {
740 /* .bank[0] = { */
741 {
742 .probed = 0,
743 .pChip = NULL,
744 .pBank = NULL,
745 .bank_number = 0,
746 .base_address = FLASH_BANK0_BASE_SD,
747 .controller_address = 0x400e0a00,
748 .flash_wait_states = 6, /* workaround silicon bug */
749 .present = 1,
750 .size_bytes = 256 * 1024,
751 .nsectors = 16,
752 .sector_size = 32768,
753 .page_size = 256,
754 },
755 /* .bank[1] = { */
756 {
757 .probed = 0,
758 .pChip = NULL,
759 .pBank = NULL,
760 .bank_number = 1,
761 .base_address = FLASH_BANK1_BASE_512K_SD,
762 .controller_address = 0x400e0a00,
763 .flash_wait_states = 6, /* workaround silicon bug */
764 .present = 1,
765 .size_bytes = 256 * 1024,
766 .nsectors = 16,
767 .sector_size = 32768,
768 .page_size = 256,
769 },
770 },
771 },
772 {
773 .chipid_cidr = 0x299B0A60,
774 .name = "at91sam3sd8b",
775 .total_flash_size = 512 * 1024,
776 .total_sram_size = 64 * 1024,
777 .n_gpnvms = 3,
778 .n_banks = 2,
779 {
780 /* .bank[0] = { */
781 {
782 .probed = 0,
783 .pChip = NULL,
784 .pBank = NULL,
785 .bank_number = 0,
786 .base_address = FLASH_BANK0_BASE_SD,
787 .controller_address = 0x400e0a00,
788 .flash_wait_states = 6, /* workaround silicon bug */
789 .present = 1,
790 .size_bytes = 256 * 1024,
791 .nsectors = 16,
792 .sector_size = 32768,
793 .page_size = 256,
794 },
795 /* .bank[1] = { */
796 {
797 .probed = 0,
798 .pChip = NULL,
799 .pBank = NULL,
800 .bank_number = 1,
801 .base_address = FLASH_BANK1_BASE_512K_SD,
802 .controller_address = 0x400e0a00,
803 .flash_wait_states = 6, /* workaround silicon bug */
804 .present = 1,
805 .size_bytes = 256 * 1024,
806 .nsectors = 16,
807 .sector_size = 32768,
808 .page_size = 256,
809 },
810 },
811 },
812 {
813 .chipid_cidr = 0x29ab0a60,
814 .name = "at91sam3sd8c",
815 .total_flash_size = 512 * 1024,
816 .total_sram_size = 64 * 1024,
817 .n_gpnvms = 3,
818 .n_banks = 2,
819 {
820 /* .bank[0] = { */
821 {
822 .probed = 0,
823 .pChip = NULL,
824 .pBank = NULL,
825 .bank_number = 0,
826 .base_address = FLASH_BANK0_BASE_SD,
827 .controller_address = 0x400e0a00,
828 .flash_wait_states = 6, /* workaround silicon bug */
829 .present = 1,
830 .size_bytes = 256 * 1024,
831 .nsectors = 16,
832 .sector_size = 32768,
833 .page_size = 256,
834 },
835 /* .bank[1] = { */
836 {
837 .probed = 0,
838 .pChip = NULL,
839 .pBank = NULL,
840 .bank_number = 1,
841 .base_address = FLASH_BANK1_BASE_512K_SD,
842 .controller_address = 0x400e0a00,
843 .flash_wait_states = 6, /* workaround silicon bug */
844 .present = 1,
845 .size_bytes = 256 * 1024,
846 .nsectors = 16,
847 .sector_size = 32768,
848 .page_size = 256,
849 },
850 },
851 },
852 {
853 .chipid_cidr = 0x288A0760,
854 .name = "at91sam3s2a",
855 .total_flash_size = 128 * 1024,
856 .total_sram_size = 32 * 1024,
857 .n_gpnvms = 2,
858 .n_banks = 1,
859 {
860 /* .bank[0] = { */
861 {
862 .probed = 0,
863 .pChip = NULL,
864 .pBank = NULL,
865 .bank_number = 0,
866 .base_address = FLASH_BANK_BASE_S,
867 .controller_address = 0x400e0a00,
868 .flash_wait_states = 6, /* workaround silicon bug */
869 .present = 1,
870 .size_bytes = 128 * 1024,
871 .nsectors = 8,
872 .sector_size = 16384,
873 .page_size = 256,
874 },
875 /* .bank[1] = { */
876 {
877 .present = 0,
878 .probed = 0,
879 .bank_number = 1,
880
881 },
882 },
883 },
884 {
885 .chipid_cidr = 0x28A90560,
886 .name = "at91sam3s1c",
887 .total_flash_size = 64 * 1024,
888 .total_sram_size = 16 * 1024,
889 .n_gpnvms = 2,
890 .n_banks = 1,
891 {
892 /* .bank[0] = { */
893 {
894 .probed = 0,
895 .pChip = NULL,
896 .pBank = NULL,
897 .bank_number = 0,
898 .base_address = FLASH_BANK_BASE_S,
899 .controller_address = 0x400e0a00,
900 .flash_wait_states = 6, /* workaround silicon bug */
901 .present = 1,
902 .size_bytes = 64 * 1024,
903 .nsectors = 4,
904 .sector_size = 16384,
905 .page_size = 256,
906 },
907 /* .bank[1] = { */
908 {
909 .present = 0,
910 .probed = 0,
911 .bank_number = 1,
912
913 },
914 },
915 },
916 {
917 .chipid_cidr = 0x28990560,
918 .name = "at91sam3s1b",
919 .total_flash_size = 64 * 1024,
920 .total_sram_size = 16 * 1024,
921 .n_gpnvms = 2,
922 .n_banks = 1,
923 {
924 /* .bank[0] = { */
925 {
926 .probed = 0,
927 .pChip = NULL,
928 .pBank = NULL,
929 .bank_number = 0,
930 .base_address = FLASH_BANK_BASE_S,
931 .controller_address = 0x400e0a00,
932 .flash_wait_states = 6, /* workaround silicon bug */
933 .present = 1,
934 .size_bytes = 64 * 1024,
935 .nsectors = 4,
936 .sector_size = 16384,
937 .page_size = 256,
938 },
939 /* .bank[1] = { */
940 {
941 .present = 0,
942 .probed = 0,
943 .bank_number = 1,
944
945 },
946 },
947 },
948 {
949 .chipid_cidr = 0x28890560,
950 .name = "at91sam3s1a",
951 .total_flash_size = 64 * 1024,
952 .total_sram_size = 16 * 1024,
953 .n_gpnvms = 2,
954 .n_banks = 1,
955 {
956 /* .bank[0] = { */
957 {
958 .probed = 0,
959 .pChip = NULL,
960 .pBank = NULL,
961 .bank_number = 0,
962 .base_address = FLASH_BANK_BASE_S,
963 .controller_address = 0x400e0a00,
964 .flash_wait_states = 6, /* workaround silicon bug */
965 .present = 1,
966 .size_bytes = 64 * 1024,
967 .nsectors = 4,
968 .sector_size = 16384,
969 .page_size = 256,
970 },
971 /* .bank[1] = { */
972 {
973 .present = 0,
974 .probed = 0,
975 .bank_number = 1,
976
977 },
978 },
979 },
980 {
981 .chipid_cidr = 0x288B0A60,
982 .name = "at91sam3s8a",
983 .total_flash_size = 256 * 2048,
984 .total_sram_size = 64 * 1024,
985 .n_gpnvms = 2,
986 .n_banks = 1,
987 {
988 /* .bank[0] = { */
989 {
990 .probed = 0,
991 .pChip = NULL,
992 .pBank = NULL,
993 .bank_number = 0,
994 .base_address = FLASH_BANK_BASE_S,
995 .controller_address = 0x400e0a00,
996 .flash_wait_states = 6, /* workaround silicon bug */
997 .present = 1,
998 .size_bytes = 256 * 2048,
999 .nsectors = 16,
1000 .sector_size = 32768,
1001 .page_size = 256,
1002 },
1003 /* .bank[1] = { */
1004 {
1005 .present = 0,
1006 .probed = 0,
1007 .bank_number = 1,
1008
1009 },
1010 },
1011 },
1012 {
1013 .chipid_cidr = 0x289B0A60,
1014 .name = "at91sam3s8b",
1015 .total_flash_size = 256 * 2048,
1016 .total_sram_size = 64 * 1024,
1017 .n_gpnvms = 2,
1018 .n_banks = 1,
1019 {
1020 /* .bank[0] = { */
1021 {
1022 .probed = 0,
1023 .pChip = NULL,
1024 .pBank = NULL,
1025 .bank_number = 0,
1026 .base_address = FLASH_BANK_BASE_S,
1027 .controller_address = 0x400e0a00,
1028 .flash_wait_states = 6, /* workaround silicon bug */
1029 .present = 1,
1030 .size_bytes = 256 * 2048,
1031 .nsectors = 16,
1032 .sector_size = 32768,
1033 .page_size = 256,
1034 },
1035 /* .bank[1] = { */
1036 {
1037 .present = 0,
1038 .probed = 0,
1039 .bank_number = 1,
1040
1041 },
1042 },
1043 },
1044 {
1045 .chipid_cidr = 0x28AB0A60,
1046 .name = "at91sam3s8c",
1047 .total_flash_size = 256 * 2048,
1048 .total_sram_size = 64 * 1024,
1049 .n_gpnvms = 2,
1050 .n_banks = 1,
1051 {
1052 /* .bank[0] = { */
1053 {
1054 .probed = 0,
1055 .pChip = NULL,
1056 .pBank = NULL,
1057 .bank_number = 0,
1058 .base_address = FLASH_BANK_BASE_S,
1059 .controller_address = 0x400e0a00,
1060 .flash_wait_states = 6, /* workaround silicon bug */
1061 .present = 1,
1062 .size_bytes = 256 * 2048,
1063 .nsectors = 16,
1064 .sector_size = 32768,
1065 .page_size = 256,
1066 },
1067 /* .bank[1] = { */
1068 {
1069 .present = 0,
1070 .probed = 0,
1071 .bank_number = 1,
1072
1073 },
1074 },
1075 },
1076
1077 /* Start at91sam3n* series */
1078 {
1079 .chipid_cidr = 0x29540960,
1080 .name = "at91sam3n4c",
1081 .total_flash_size = 256 * 1024,
1082 .total_sram_size = 24 * 1024,
1083 .n_gpnvms = 3,
1084 .n_banks = 1,
1085
1086 /* System boots at address 0x0 */
1087 /* gpnvm[1] = selects boot code */
1088 /* if gpnvm[1] == 0 */
1089 /* boot is via "SAMBA" (rom) */
1090 /* else */
1091 /* boot is via FLASH */
1092 /* Selection is via gpnvm[2] */
1093 /* endif */
1094 /* */
1095 /* NOTE: banks 0 & 1 switch places */
1096 /* if gpnvm[2] == 0 */
1097 /* Bank0 is the boot rom */
1098 /* else */
1099 /* Bank1 is the boot rom */
1100 /* endif */
1101 /* .bank[0] = { */
1102 {
1103 {
1104 .probed = 0,
1105 .pChip = NULL,
1106 .pBank = NULL,
1107 .bank_number = 0,
1108 .base_address = FLASH_BANK_BASE_N,
1109 .controller_address = 0x400e0A00,
1110 .flash_wait_states = 6, /* workaround silicon bug */
1111 .present = 1,
1112 .size_bytes = 256 * 1024,
1113 .nsectors = 16,
1114 .sector_size = 16384,
1115 .page_size = 256,
1116 },
1117
1118 /* .bank[1] = { */
1119 {
1120 .present = 0,
1121 .probed = 0,
1122 .bank_number = 1,
1123 },
1124 },
1125 },
1126
1127 {
1128 .chipid_cidr = 0x29440960,
1129 .name = "at91sam3n4b",
1130 .total_flash_size = 256 * 1024,
1131 .total_sram_size = 24 * 1024,
1132 .n_gpnvms = 3,
1133 .n_banks = 1,
1134
1135 /* System boots at address 0x0 */
1136 /* gpnvm[1] = selects boot code */
1137 /* if gpnvm[1] == 0 */
1138 /* boot is via "SAMBA" (rom) */
1139 /* else */
1140 /* boot is via FLASH */
1141 /* Selection is via gpnvm[2] */
1142 /* endif */
1143 /* */
1144 /* NOTE: banks 0 & 1 switch places */
1145 /* if gpnvm[2] == 0 */
1146 /* Bank0 is the boot rom */
1147 /* else */
1148 /* Bank1 is the boot rom */
1149 /* endif */
1150 /* .bank[0] = { */
1151 {
1152 {
1153 .probed = 0,
1154 .pChip = NULL,
1155 .pBank = NULL,
1156 .bank_number = 0,
1157 .base_address = FLASH_BANK_BASE_N,
1158 .controller_address = 0x400e0A00,
1159 .flash_wait_states = 6, /* workaround silicon bug */
1160 .present = 1,
1161 .size_bytes = 256 * 1024,
1162 .nsectors = 16,
1163 .sector_size = 16384,
1164 .page_size = 256,
1165 },
1166
1167 /* .bank[1] = { */
1168 {
1169 .present = 0,
1170 .probed = 0,
1171 .bank_number = 1,
1172 },
1173 },
1174 },
1175
1176 {
1177 .chipid_cidr = 0x29340960,
1178 .name = "at91sam3n4a",
1179 .total_flash_size = 256 * 1024,
1180 .total_sram_size = 24 * 1024,
1181 .n_gpnvms = 3,
1182 .n_banks = 1,
1183
1184 /* System boots at address 0x0 */
1185 /* gpnvm[1] = selects boot code */
1186 /* if gpnvm[1] == 0 */
1187 /* boot is via "SAMBA" (rom) */
1188 /* else */
1189 /* boot is via FLASH */
1190 /* Selection is via gpnvm[2] */
1191 /* endif */
1192 /* */
1193 /* NOTE: banks 0 & 1 switch places */
1194 /* if gpnvm[2] == 0 */
1195 /* Bank0 is the boot rom */
1196 /* else */
1197 /* Bank1 is the boot rom */
1198 /* endif */
1199 /* .bank[0] = { */
1200 {
1201 {
1202 .probed = 0,
1203 .pChip = NULL,
1204 .pBank = NULL,
1205 .bank_number = 0,
1206 .base_address = FLASH_BANK_BASE_N,
1207 .controller_address = 0x400e0A00,
1208 .flash_wait_states = 6, /* workaround silicon bug */
1209 .present = 1,
1210 .size_bytes = 256 * 1024,
1211 .nsectors = 16,
1212 .sector_size = 16384,
1213 .page_size = 256,
1214 },
1215
1216 /* .bank[1] = { */
1217 {
1218 .present = 0,
1219 .probed = 0,
1220 .bank_number = 1,
1221 },
1222 },
1223 },
1224
1225 {
1226 .chipid_cidr = 0x29590760,
1227 .name = "at91sam3n2c",
1228 .total_flash_size = 128 * 1024,
1229 .total_sram_size = 16 * 1024,
1230 .n_gpnvms = 3,
1231 .n_banks = 1,
1232
1233 /* System boots at address 0x0 */
1234 /* gpnvm[1] = selects boot code */
1235 /* if gpnvm[1] == 0 */
1236 /* boot is via "SAMBA" (rom) */
1237 /* else */
1238 /* boot is via FLASH */
1239 /* Selection is via gpnvm[2] */
1240 /* endif */
1241 /* */
1242 /* NOTE: banks 0 & 1 switch places */
1243 /* if gpnvm[2] == 0 */
1244 /* Bank0 is the boot rom */
1245 /* else */
1246 /* Bank1 is the boot rom */
1247 /* endif */
1248 /* .bank[0] = { */
1249 {
1250 {
1251 .probed = 0,
1252 .pChip = NULL,
1253 .pBank = NULL,
1254 .bank_number = 0,
1255 .base_address = FLASH_BANK_BASE_N,
1256 .controller_address = 0x400e0A00,
1257 .flash_wait_states = 6, /* workaround silicon bug */
1258 .present = 1,
1259 .size_bytes = 128 * 1024,
1260 .nsectors = 8,
1261 .sector_size = 16384,
1262 .page_size = 256,
1263 },
1264
1265 /* .bank[1] = { */
1266 {
1267 .present = 0,
1268 .probed = 0,
1269 .bank_number = 1,
1270 },
1271 },
1272 },
1273
1274 {
1275 .chipid_cidr = 0x29490760,
1276 .name = "at91sam3n2b",
1277 .total_flash_size = 128 * 1024,
1278 .total_sram_size = 16 * 1024,
1279 .n_gpnvms = 3,
1280 .n_banks = 1,
1281
1282 /* System boots at address 0x0 */
1283 /* gpnvm[1] = selects boot code */
1284 /* if gpnvm[1] == 0 */
1285 /* boot is via "SAMBA" (rom) */
1286 /* else */
1287 /* boot is via FLASH */
1288 /* Selection is via gpnvm[2] */
1289 /* endif */
1290 /* */
1291 /* NOTE: banks 0 & 1 switch places */
1292 /* if gpnvm[2] == 0 */
1293 /* Bank0 is the boot rom */
1294 /* else */
1295 /* Bank1 is the boot rom */
1296 /* endif */
1297 /* .bank[0] = { */
1298 {
1299 {
1300 .probed = 0,
1301 .pChip = NULL,
1302 .pBank = NULL,
1303 .bank_number = 0,
1304 .base_address = FLASH_BANK_BASE_N,
1305 .controller_address = 0x400e0A00,
1306 .flash_wait_states = 6, /* workaround silicon bug */
1307 .present = 1,
1308 .size_bytes = 128 * 1024,
1309 .nsectors = 8,
1310 .sector_size = 16384,
1311 .page_size = 256,
1312 },
1313
1314 /* .bank[1] = { */
1315 {
1316 .present = 0,
1317 .probed = 0,
1318 .bank_number = 1,
1319 },
1320 },
1321 },
1322
1323 {
1324 .chipid_cidr = 0x29390760,
1325 .name = "at91sam3n2a",
1326 .total_flash_size = 128 * 1024,
1327 .total_sram_size = 16 * 1024,
1328 .n_gpnvms = 3,
1329 .n_banks = 1,
1330
1331 /* System boots at address 0x0 */
1332 /* gpnvm[1] = selects boot code */
1333 /* if gpnvm[1] == 0 */
1334 /* boot is via "SAMBA" (rom) */
1335 /* else */
1336 /* boot is via FLASH */
1337 /* Selection is via gpnvm[2] */
1338 /* endif */
1339 /* */
1340 /* NOTE: banks 0 & 1 switch places */
1341 /* if gpnvm[2] == 0 */
1342 /* Bank0 is the boot rom */
1343 /* else */
1344 /* Bank1 is the boot rom */
1345 /* endif */
1346 /* .bank[0] = { */
1347 {
1348 {
1349 .probed = 0,
1350 .pChip = NULL,
1351 .pBank = NULL,
1352 .bank_number = 0,
1353 .base_address = FLASH_BANK_BASE_N,
1354 .controller_address = 0x400e0A00,
1355 .flash_wait_states = 6, /* workaround silicon bug */
1356 .present = 1,
1357 .size_bytes = 128 * 1024,
1358 .nsectors = 8,
1359 .sector_size = 16384,
1360 .page_size = 256,
1361 },
1362
1363 /* .bank[1] = { */
1364 {
1365 .present = 0,
1366 .probed = 0,
1367 .bank_number = 1,
1368 },
1369 },
1370 },
1371
1372 {
1373 .chipid_cidr = 0x29580560,
1374 .name = "at91sam3n1c",
1375 .total_flash_size = 64 * 1024,
1376 .total_sram_size = 8 * 1024,
1377 .n_gpnvms = 3,
1378 .n_banks = 1,
1379
1380 /* System boots at address 0x0 */
1381 /* gpnvm[1] = selects boot code */
1382 /* if gpnvm[1] == 0 */
1383 /* boot is via "SAMBA" (rom) */
1384 /* else */
1385 /* boot is via FLASH */
1386 /* Selection is via gpnvm[2] */
1387 /* endif */
1388 /* */
1389 /* NOTE: banks 0 & 1 switch places */
1390 /* if gpnvm[2] == 0 */
1391 /* Bank0 is the boot rom */
1392 /* else */
1393 /* Bank1 is the boot rom */
1394 /* endif */
1395 /* .bank[0] = { */
1396 {
1397 {
1398 .probed = 0,
1399 .pChip = NULL,
1400 .pBank = NULL,
1401 .bank_number = 0,
1402 .base_address = FLASH_BANK_BASE_N,
1403 .controller_address = 0x400e0A00,
1404 .flash_wait_states = 6, /* workaround silicon bug */
1405 .present = 1,
1406 .size_bytes = 64 * 1024,
1407 .nsectors = 4,
1408 .sector_size = 16384,
1409 .page_size = 256,
1410 },
1411
1412 /* .bank[1] = { */
1413 {
1414 .present = 0,
1415 .probed = 0,
1416 .bank_number = 1,
1417 },
1418 },
1419 },
1420
1421 {
1422 .chipid_cidr = 0x29480560,
1423 .name = "at91sam3n1b",
1424 .total_flash_size = 64 * 1024,
1425 .total_sram_size = 8 * 1024,
1426 .n_gpnvms = 3,
1427 .n_banks = 1,
1428
1429 /* System boots at address 0x0 */
1430 /* gpnvm[1] = selects boot code */
1431 /* if gpnvm[1] == 0 */
1432 /* boot is via "SAMBA" (rom) */
1433 /* else */
1434 /* boot is via FLASH */
1435 /* Selection is via gpnvm[2] */
1436 /* endif */
1437 /* */
1438 /* NOTE: banks 0 & 1 switch places */
1439 /* if gpnvm[2] == 0 */
1440 /* Bank0 is the boot rom */
1441 /* else */
1442 /* Bank1 is the boot rom */
1443 /* endif */
1444 /* .bank[0] = { */
1445 {
1446 {
1447 .probed = 0,
1448 .pChip = NULL,
1449 .pBank = NULL,
1450 .bank_number = 0,
1451 .base_address = FLASH_BANK_BASE_N,
1452 .controller_address = 0x400e0A00,
1453 .flash_wait_states = 6, /* workaround silicon bug */
1454 .present = 1,
1455 .size_bytes = 64 * 1024,
1456 .nsectors = 4,
1457 .sector_size = 16384,
1458 .page_size = 256,
1459 },
1460
1461 /* .bank[1] = { */
1462 {
1463 .present = 0,
1464 .probed = 0,
1465 .bank_number = 1,
1466 },
1467 },
1468 },
1469
1470 {
1471 .chipid_cidr = 0x29380560,
1472 .name = "at91sam3n1a",
1473 .total_flash_size = 64 * 1024,
1474 .total_sram_size = 8 * 1024,
1475 .n_gpnvms = 3,
1476 .n_banks = 1,
1477
1478 /* System boots at address 0x0 */
1479 /* gpnvm[1] = selects boot code */
1480 /* if gpnvm[1] == 0 */
1481 /* boot is via "SAMBA" (rom) */
1482 /* else */
1483 /* boot is via FLASH */
1484 /* Selection is via gpnvm[2] */
1485 /* endif */
1486 /* */
1487 /* NOTE: banks 0 & 1 switch places */
1488 /* if gpnvm[2] == 0 */
1489 /* Bank0 is the boot rom */
1490 /* else */
1491 /* Bank1 is the boot rom */
1492 /* endif */
1493 /* .bank[0] = { */
1494 {
1495 {
1496 .probed = 0,
1497 .pChip = NULL,
1498 .pBank = NULL,
1499 .bank_number = 0,
1500 .base_address = FLASH_BANK_BASE_N,
1501 .controller_address = 0x400e0A00,
1502 .flash_wait_states = 6, /* workaround silicon bug */
1503 .present = 1,
1504 .size_bytes = 64 * 1024,
1505 .nsectors = 4,
1506 .sector_size = 16384,
1507 .page_size = 256,
1508 },
1509
1510 /* .bank[1] = { */
1511 {
1512 .present = 0,
1513 .probed = 0,
1514 .bank_number = 1,
1515 },
1516 },
1517 },
1518
1519 {
1520 .chipid_cidr = 0x29480360,
1521 .name = "at91sam3n0b",
1522 .total_flash_size = 32 * 1024,
1523 .total_sram_size = 8 * 1024,
1524 .n_gpnvms = 3,
1525 .n_banks = 1,
1526
1527 /* .bank[0] = { */
1528 {
1529 {
1530 .probed = 0,
1531 .pChip = NULL,
1532 .pBank = NULL,
1533 .bank_number = 0,
1534 .base_address = FLASH_BANK_BASE_N,
1535 .controller_address = 0x400e0A00,
1536 .flash_wait_states = 6, /* workaround silicon bug */
1537 .present = 1,
1538 .size_bytes = 32 * 1024,
1539 .nsectors = 2,
1540 .sector_size = 16384,
1541 .page_size = 256,
1542 },
1543
1544 /* .bank[1] = { */
1545 {
1546 .present = 0,
1547 .probed = 0,
1548 .bank_number = 1,
1549 },
1550 },
1551 },
1552
1553 {
1554 .chipid_cidr = 0x29380360,
1555 .name = "at91sam3n0a",
1556 .total_flash_size = 32 * 1024,
1557 .total_sram_size = 8 * 1024,
1558 .n_gpnvms = 3,
1559 .n_banks = 1,
1560
1561 /* .bank[0] = { */
1562 {
1563 {
1564 .probed = 0,
1565 .pChip = NULL,
1566 .pBank = NULL,
1567 .bank_number = 0,
1568 .base_address = FLASH_BANK_BASE_N,
1569 .controller_address = 0x400e0A00,
1570 .flash_wait_states = 6, /* workaround silicon bug */
1571 .present = 1,
1572 .size_bytes = 32 * 1024,
1573 .nsectors = 2,
1574 .sector_size = 16384,
1575 .page_size = 256,
1576 },
1577
1578 /* .bank[1] = { */
1579 {
1580 .present = 0,
1581 .probed = 0,
1582 .bank_number = 1,
1583 },
1584 },
1585 },
1586
1587 {
1588 .chipid_cidr = 0x29450260,
1589 .name = "at91sam3n00b",
1590 .total_flash_size = 16 * 1024,
1591 .total_sram_size = 4 * 1024,
1592 .n_gpnvms = 3,
1593 .n_banks = 1,
1594
1595 /* .bank[0] = { */
1596 {
1597 {
1598 .probed = 0,
1599 .pChip = NULL,
1600 .pBank = NULL,
1601 .bank_number = 0,
1602 .base_address = FLASH_BANK_BASE_N,
1603 .controller_address = 0x400e0A00,
1604 .flash_wait_states = 6, /* workaround silicon bug */
1605 .present = 1,
1606 .size_bytes = 16 * 1024,
1607 .nsectors = 1,
1608 .sector_size = 16384,
1609 .page_size = 256,
1610 },
1611
1612 /* .bank[1] = { */
1613 {
1614 .present = 0,
1615 .probed = 0,
1616 .bank_number = 1,
1617 },
1618 },
1619 },
1620
1621 {
1622 .chipid_cidr = 0x29350260,
1623 .name = "at91sam3n00a",
1624 .total_flash_size = 16 * 1024,
1625 .total_sram_size = 4 * 1024,
1626 .n_gpnvms = 3,
1627 .n_banks = 1,
1628
1629 /* .bank[0] = { */
1630 {
1631 {
1632 .probed = 0,
1633 .pChip = NULL,
1634 .pBank = NULL,
1635 .bank_number = 0,
1636 .base_address = FLASH_BANK_BASE_N,
1637 .controller_address = 0x400e0A00,
1638 .flash_wait_states = 6, /* workaround silicon bug */
1639 .present = 1,
1640 .size_bytes = 16 * 1024,
1641 .nsectors = 1,
1642 .sector_size = 16384,
1643 .page_size = 256,
1644 },
1645
1646 /* .bank[1] = { */
1647 {
1648 .present = 0,
1649 .probed = 0,
1650 .bank_number = 1,
1651 },
1652 },
1653 },
1654
1655
1656 /* Start at91sam3a series*/
1657 /* System boots at address 0x0 */
1658 /* gpnvm[1] = selects boot code */
1659 /* if gpnvm[1] == 0 */
1660 /* boot is via "SAMBA" (rom) */
1661 /* else */
1662 /* boot is via FLASH */
1663 /* Selection is via gpnvm[2] */
1664 /* endif */
1665 /* */
1666 /* NOTE: banks 0 & 1 switch places */
1667 /* if gpnvm[2] == 0 */
1668 /* Bank0 is the boot rom */
1669 /* else */
1670 /* Bank1 is the boot rom */
1671 /* endif */
1672
1673 {
1674 .chipid_cidr = 0x283E0A60,
1675 .name = "at91sam3a8c",
1676 .total_flash_size = 512 * 1024,
1677 .total_sram_size = 96 * 1024,
1678 .n_gpnvms = 3,
1679 .n_banks = 2,
1680 {
1681 /* .bank[0] = { */
1682 {
1683 .probed = 0,
1684 .pChip = NULL,
1685 .pBank = NULL,
1686 .bank_number = 0,
1687 .base_address = FLASH_BANK0_BASE_AX,
1688 .controller_address = 0x400e0a00,
1689 .flash_wait_states = 6, /* workaround silicon bug */
1690 .present = 1,
1691 .size_bytes = 256 * 1024,
1692 .nsectors = 16,
1693 .sector_size = 16384,
1694 .page_size = 256,
1695 },
1696 /* .bank[1] = { */
1697 {
1698 .probed = 0,
1699 .pChip = NULL,
1700 .pBank = NULL,
1701 .bank_number = 1,
1702 .base_address = FLASH_BANK1_BASE_512K_AX,
1703 .controller_address = 0x400e0c00,
1704 .flash_wait_states = 6, /* workaround silicon bug */
1705 .present = 1,
1706 .size_bytes = 256 * 1024,
1707 .nsectors = 16,
1708 .sector_size = 16384,
1709 .page_size = 256,
1710
1711 },
1712 },
1713 },
1714 {
1715 .chipid_cidr = 0x283B0960,
1716 .name = "at91sam3a4c",
1717 .total_flash_size = 256 * 1024,
1718 .total_sram_size = 64 * 1024,
1719 .n_gpnvms = 3,
1720 .n_banks = 2,
1721 {
1722 /* .bank[0] = { */
1723 {
1724 .probed = 0,
1725 .pChip = NULL,
1726 .pBank = NULL,
1727 .bank_number = 0,
1728 .base_address = FLASH_BANK0_BASE_AX,
1729 .controller_address = 0x400e0a00,
1730 .flash_wait_states = 6, /* workaround silicon bug */
1731 .present = 1,
1732 .size_bytes = 128 * 1024,
1733 .nsectors = 8,
1734 .sector_size = 16384,
1735 .page_size = 256,
1736 },
1737 /* .bank[1] = { */
1738 {
1739 .probed = 0,
1740 .pChip = NULL,
1741 .pBank = NULL,
1742 .bank_number = 1,
1743 .base_address = FLASH_BANK1_BASE_256K_AX,
1744 .controller_address = 0x400e0c00,
1745 .flash_wait_states = 6, /* workaround silicon bug */
1746 .present = 1,
1747 .size_bytes = 128 * 1024,
1748 .nsectors = 8,
1749 .sector_size = 16384,
1750 .page_size = 256,
1751
1752 },
1753 },
1754 },
1755
1756 /* Start at91sam3x* series */
1757 /* System boots at address 0x0 */
1758 /* gpnvm[1] = selects boot code */
1759 /* if gpnvm[1] == 0 */
1760 /* boot is via "SAMBA" (rom) */
1761 /* else */
1762 /* boot is via FLASH */
1763 /* Selection is via gpnvm[2] */
1764 /* endif */
1765 /* */
1766 /* NOTE: banks 0 & 1 switch places */
1767 /* if gpnvm[2] == 0 */
1768 /* Bank0 is the boot rom */
1769 /* else */
1770 /* Bank1 is the boot rom */
1771 /* endif */
1772 /*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/
1773 {
1774 .chipid_cidr = 0x286E0A20,
1775 .name = "at91sam3x8h - ES",
1776 .total_flash_size = 512 * 1024,
1777 .total_sram_size = 96 * 1024,
1778 .n_gpnvms = 3,
1779 .n_banks = 2,
1780 {
1781 /* .bank[0] = { */
1782 {
1783 .probed = 0,
1784 .pChip = NULL,
1785 .pBank = NULL,
1786 .bank_number = 0,
1787 .base_address = FLASH_BANK0_BASE_AX,
1788 .controller_address = 0x400e0a00,
1789 .flash_wait_states = 6, /* workaround silicon bug */
1790 .present = 1,
1791 .size_bytes = 256 * 1024,
1792 .nsectors = 16,
1793 .sector_size = 16384,
1794 .page_size = 256,
1795 },
1796 /* .bank[1] = { */
1797 {
1798 .probed = 0,
1799 .pChip = NULL,
1800 .pBank = NULL,
1801 .bank_number = 1,
1802 .base_address = FLASH_BANK1_BASE_512K_AX,
1803 .controller_address = 0x400e0c00,
1804 .flash_wait_states = 6, /* workaround silicon bug */
1805 .present = 1,
1806 .size_bytes = 256 * 1024,
1807 .nsectors = 16,
1808 .sector_size = 16384,
1809 .page_size = 256,
1810
1811 },
1812 },
1813 },
1814 /*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/
1815 {
1816 .chipid_cidr = 0x286E0A60,
1817 .name = "at91sam3x8h",
1818 .total_flash_size = 512 * 1024,
1819 .total_sram_size = 96 * 1024,
1820 .n_gpnvms = 3,
1821 .n_banks = 2,
1822 {
1823 /* .bank[0] = { */
1824 {
1825 .probed = 0,
1826 .pChip = NULL,
1827 .pBank = NULL,
1828 .bank_number = 0,
1829 .base_address = FLASH_BANK0_BASE_AX,
1830 .controller_address = 0x400e0a00,
1831 .flash_wait_states = 6, /* workaround silicon bug */
1832 .present = 1,
1833 .size_bytes = 256 * 1024,
1834 .nsectors = 16,
1835 .sector_size = 16384,
1836 .page_size = 256,
1837 },
1838 /* .bank[1] = { */
1839 {
1840 .probed = 0,
1841 .pChip = NULL,
1842 .pBank = NULL,
1843 .bank_number = 1,
1844 .base_address = FLASH_BANK1_BASE_512K_AX,
1845 .controller_address = 0x400e0c00,
1846 .flash_wait_states = 6, /* workaround silicon bug */
1847 .present = 1,
1848 .size_bytes = 256 * 1024,
1849 .nsectors = 16,
1850 .sector_size = 16384,
1851 .page_size = 256,
1852
1853 },
1854 },
1855 },
1856 {
1857 .chipid_cidr = 0x285E0A60,
1858 .name = "at91sam3x8e",
1859 .total_flash_size = 512 * 1024,
1860 .total_sram_size = 96 * 1024,
1861 .n_gpnvms = 3,
1862 .n_banks = 2,
1863 {
1864 /* .bank[0] = { */
1865 {
1866 .probed = 0,
1867 .pChip = NULL,
1868 .pBank = NULL,
1869 .bank_number = 0,
1870 .base_address = FLASH_BANK0_BASE_AX,
1871 .controller_address = 0x400e0a00,
1872 .flash_wait_states = 6, /* workaround silicon bug */
1873 .present = 1,
1874 .size_bytes = 256 * 1024,
1875 .nsectors = 16,
1876 .sector_size = 16384,
1877 .page_size = 256,
1878 },
1879 /* .bank[1] = { */
1880 {
1881 .probed = 0,
1882 .pChip = NULL,
1883 .pBank = NULL,
1884 .bank_number = 1,
1885 .base_address = FLASH_BANK1_BASE_512K_AX,
1886 .controller_address = 0x400e0c00,
1887 .flash_wait_states = 6, /* workaround silicon bug */
1888 .present = 1,
1889 .size_bytes = 256 * 1024,
1890 .nsectors = 16,
1891 .sector_size = 16384,
1892 .page_size = 256,
1893
1894 },
1895 },
1896 },
1897 {
1898 .chipid_cidr = 0x284E0A60,
1899 .name = "at91sam3x8c",
1900 .total_flash_size = 512 * 1024,
1901 .total_sram_size = 96 * 1024,
1902 .n_gpnvms = 3,
1903 .n_banks = 2,
1904 {
1905 /* .bank[0] = { */
1906 {
1907 .probed = 0,
1908 .pChip = NULL,
1909 .pBank = NULL,
1910 .bank_number = 0,
1911 .base_address = FLASH_BANK0_BASE_AX,
1912 .controller_address = 0x400e0a00,
1913 .flash_wait_states = 6, /* workaround silicon bug */
1914 .present = 1,
1915 .size_bytes = 256 * 1024,
1916 .nsectors = 16,
1917 .sector_size = 16384,
1918 .page_size = 256,
1919 },
1920 /* .bank[1] = { */
1921 {
1922 .probed = 0,
1923 .pChip = NULL,
1924 .pBank = NULL,
1925 .bank_number = 1,
1926 .base_address = FLASH_BANK1_BASE_512K_AX ,
1927 .controller_address = 0x400e0c00,
1928 .flash_wait_states = 6, /* workaround silicon bug */
1929 .present = 1,
1930 .size_bytes = 256 * 1024,
1931 .nsectors = 16,
1932 .sector_size = 16384,
1933 .page_size = 256,
1934
1935 },
1936 },
1937 },
1938 {
1939 .chipid_cidr = 0x285B0960,
1940 .name = "at91sam3x4e",
1941 .total_flash_size = 256 * 1024,
1942 .total_sram_size = 64 * 1024,
1943 .n_gpnvms = 3,
1944 .n_banks = 2,
1945 {
1946 /* .bank[0] = { */
1947 {
1948 .probed = 0,
1949 .pChip = NULL,
1950 .pBank = NULL,
1951 .bank_number = 0,
1952 .base_address = FLASH_BANK0_BASE_AX,
1953 .controller_address = 0x400e0a00,
1954 .flash_wait_states = 6, /* workaround silicon bug */
1955 .present = 1,
1956 .size_bytes = 128 * 1024,
1957 .nsectors = 8,
1958 .sector_size = 16384,
1959 .page_size = 256,
1960 },
1961 /* .bank[1] = { */
1962 {
1963 .probed = 0,
1964 .pChip = NULL,
1965 .pBank = NULL,
1966 .bank_number = 1,
1967 .base_address = FLASH_BANK1_BASE_256K_AX,
1968 .controller_address = 0x400e0c00,
1969 .flash_wait_states = 6, /* workaround silicon bug */
1970 .present = 1,
1971 .size_bytes = 128 * 1024,
1972 .nsectors = 8,
1973 .sector_size = 16384,
1974 .page_size = 256,
1975
1976 },
1977 },
1978 },
1979 {
1980 .chipid_cidr = 0x284B0960,
1981 .name = "at91sam3x4c",
1982 .total_flash_size = 256 * 1024,
1983 .total_sram_size = 64 * 1024,
1984 .n_gpnvms = 3,
1985 .n_banks = 2,
1986 {
1987 /* .bank[0] = { */
1988 {
1989 .probed = 0,
1990 .pChip = NULL,
1991 .pBank = NULL,
1992 .bank_number = 0,
1993 .base_address = FLASH_BANK0_BASE_AX,
1994 .controller_address = 0x400e0a00,
1995 .flash_wait_states = 6, /* workaround silicon bug */
1996 .present = 1,
1997 .size_bytes = 128 * 1024,
1998 .nsectors = 8,
1999 .sector_size = 16384,
2000 .page_size = 256,
2001 },
2002 /* .bank[1] = { */
2003 {
2004 .probed = 0,
2005 .pChip = NULL,
2006 .pBank = NULL,
2007 .bank_number = 1,
2008 .base_address = FLASH_BANK1_BASE_256K_AX,
2009 .controller_address = 0x400e0c00,
2010 .flash_wait_states = 6, /* workaround silicon bug */
2011 .present = 1,
2012 .size_bytes = 128 * 1024,
2013 .nsectors = 8,
2014 .sector_size = 16384,
2015 .page_size = 256,
2016
2017 },
2018 },
2019 },
2020 /* terminate */
2021 {
2022 .chipid_cidr = 0,
2023 .name = NULL,
2024 }
2025 };
2026
2027 /* Globals above */
2028 /***********************************************************************
2029 **********************************************************************
2030 **********************************************************************
2031 **********************************************************************
2032 **********************************************************************
2033 **********************************************************************/
2034 /* *ATMEL* style code - from the SAM3 driver code */
2035
2036 /**
2037 * Get the current status of the EEFC and
2038 * the value of some status bits (LOCKE, PROGE).
2039 * @param pPrivate - info about the bank
2040 * @param v - result goes here
2041 */
2042 static int EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
2043 {
2044 int r;
2045 r = target_read_u32(pPrivate->pChip->target,
2046 pPrivate->controller_address + offset_EFC_FSR,
2047 v);
2048 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
2049 (unsigned int)(*v),
2050 ((unsigned int)((*v >> 2) & 1)),
2051 ((unsigned int)((*v >> 1) & 1)),
2052 ((unsigned int)((*v >> 0) & 1)));
2053
2054 return r;
2055 }
2056
2057 /**
2058 * Get the result of the last executed command.
2059 * @param pPrivate - info about the bank
2060 * @param v - result goes here
2061 */
2062 static int EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
2063 {
2064 int r;
2065 uint32_t rv;
2066 r = target_read_u32(pPrivate->pChip->target,
2067 pPrivate->controller_address + offset_EFC_FRR,
2068 &rv);
2069 if (v)
2070 *v = rv;
2071 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
2072 return r;
2073 }
2074
2075 static int EFC_StartCommand(struct sam3_bank_private *pPrivate,
2076 unsigned command, unsigned argument)
2077 {
2078 uint32_t n, v;
2079 int r;
2080 int retry;
2081
2082 retry = 0;
2083 do_retry:
2084
2085 /* Check command & argument */
2086 switch (command) {
2087
2088 case AT91C_EFC_FCMD_WP:
2089 case AT91C_EFC_FCMD_WPL:
2090 case AT91C_EFC_FCMD_EWP:
2091 case AT91C_EFC_FCMD_EWPL:
2092 /* case AT91C_EFC_FCMD_EPL: */
2093 /* case AT91C_EFC_FCMD_EPA: */
2094 case AT91C_EFC_FCMD_SLB:
2095 case AT91C_EFC_FCMD_CLB:
2096 n = (pPrivate->size_bytes / pPrivate->page_size);
2097 if (argument >= n)
2098 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
2099 break;
2100
2101 case AT91C_EFC_FCMD_SFB:
2102 case AT91C_EFC_FCMD_CFB:
2103 if (argument >= pPrivate->pChip->details.n_gpnvms) {
2104 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
2105 pPrivate->pChip->details.n_gpnvms);
2106 }
2107 break;
2108
2109 case AT91C_EFC_FCMD_GETD:
2110 case AT91C_EFC_FCMD_EA:
2111 case AT91C_EFC_FCMD_GLB:
2112 case AT91C_EFC_FCMD_GFB:
2113 case AT91C_EFC_FCMD_STUI:
2114 case AT91C_EFC_FCMD_SPUI:
2115 if (argument != 0)
2116 LOG_ERROR("Argument is meaningless for cmd: %d", command);
2117 break;
2118 default:
2119 LOG_ERROR("Unknown command %d", command);
2120 break;
2121 }
2122
2123 if (command == AT91C_EFC_FCMD_SPUI) {
2124 /* this is a very special situation. */
2125 /* Situation (1) - error/retry - see below */
2126 /* And we are being called recursively */
2127 /* Situation (2) - normal, finished reading unique id */
2128 } else {
2129 /* it should be "ready" */
2130 EFC_GetStatus(pPrivate, &v);
2131 if (v & 1) {
2132 /* then it is ready */
2133 /* we go on */
2134 } else {
2135 if (retry) {
2136 /* we have done this before */
2137 /* the controller is not responding. */
2138 LOG_ERROR("flash controller(%d) is not ready! Error",
2139 pPrivate->bank_number);
2140 return ERROR_FAIL;
2141 } else {
2142 retry++;
2143 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
2144 pPrivate->bank_number);
2145 /* we do that by issuing the *STOP* command */
2146 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
2147 /* above is recursive, and further recursion is blocked by */
2148 /* if (command == AT91C_EFC_FCMD_SPUI) above */
2149 goto do_retry;
2150 }
2151 }
2152 }
2153
2154 v = (0x5A << 24) | (argument << 8) | command;
2155 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
2156 r = target_write_u32(pPrivate->pBank->target,
2157 pPrivate->controller_address + offset_EFC_FCR, v);
2158 if (r != ERROR_OK)
2159 LOG_DEBUG("Error Write failed");
2160 return r;
2161 }
2162
2163 /**
2164 * Performs the given command and wait until its completion (or an error).
2165 * @param pPrivate - info about the bank
2166 * @param command - Command to perform.
2167 * @param argument - Optional command argument.
2168 * @param status - put command status bits here
2169 */
2170 static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,
2171 unsigned command,
2172 unsigned argument,
2173 uint32_t *status)
2174 {
2175
2176 int r;
2177 uint32_t v;
2178 int64_t ms_now, ms_end;
2179
2180 /* default */
2181 if (status)
2182 *status = 0;
2183
2184 r = EFC_StartCommand(pPrivate, command, argument);
2185 if (r != ERROR_OK)
2186 return r;
2187
2188 ms_end = 500 + timeval_ms();
2189
2190 do {
2191 r = EFC_GetStatus(pPrivate, &v);
2192 if (r != ERROR_OK)
2193 return r;
2194 ms_now = timeval_ms();
2195 if (ms_now > ms_end) {
2196 /* error */
2197 LOG_ERROR("Command timeout");
2198 return ERROR_FAIL;
2199 }
2200 } while ((v & 1) == 0);
2201
2202 /* error bits.. */
2203 if (status)
2204 *status = (v & 0x6);
2205 return ERROR_OK;
2206
2207 }
2208
2209 /**
2210 * Read the unique ID.
2211 * @param pPrivate - info about the bank
2212 * The unique ID is stored in the 'pPrivate' structure.
2213 */
2214 static int FLASHD_ReadUniqueID(struct sam3_bank_private *pPrivate)
2215 {
2216 int r;
2217 uint32_t v;
2218 int x;
2219 /* assume 0 */
2220 pPrivate->pChip->cfg.unique_id[0] = 0;
2221 pPrivate->pChip->cfg.unique_id[1] = 0;
2222 pPrivate->pChip->cfg.unique_id[2] = 0;
2223 pPrivate->pChip->cfg.unique_id[3] = 0;
2224
2225 LOG_DEBUG("Begin");
2226 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
2227 if (r < 0)
2228 return r;
2229
2230 for (x = 0; x < 4; x++) {
2231 r = target_read_u32(pPrivate->pChip->target,
2232 pPrivate->pBank->base + (x * 4),
2233 &v);
2234 if (r < 0)
2235 return r;
2236 pPrivate->pChip->cfg.unique_id[x] = v;
2237 }
2238
2239 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
2240 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
2241 r,
2242 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
2243 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
2244 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
2245 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
2246 return r;
2247
2248 }
2249
2250 /**
2251 * Erases the entire flash.
2252 * @param pPrivate - the info about the bank.
2253 */
2254 static int FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
2255 {
2256 LOG_DEBUG("Here");
2257 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
2258 }
2259
2260 /**
2261 * Gets current GPNVM state.
2262 * @param pPrivate - info about the bank.
2263 * @param gpnvm - GPNVM bit index.
2264 * @param puthere - result stored here.
2265 */
2266 /* ------------------------------------------------------------------------------ */
2267 static int FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
2268 {
2269 uint32_t v;
2270 int r;
2271
2272 LOG_DEBUG("Here");
2273 if (pPrivate->bank_number != 0) {
2274 LOG_ERROR("GPNVM only works with Bank0");
2275 return ERROR_FAIL;
2276 }
2277
2278 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
2279 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2280 gpnvm, pPrivate->pChip->details.n_gpnvms);
2281 return ERROR_FAIL;
2282 }
2283
2284 /* Get GPNVMs status */
2285 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
2286 if (r != ERROR_OK) {
2287 LOG_ERROR("Failed");
2288 return r;
2289 }
2290
2291 r = EFC_GetResult(pPrivate, &v);
2292
2293 if (puthere) {
2294 /* Check if GPNVM is set */
2295 /* get the bit and make it a 0/1 */
2296 *puthere = (v >> gpnvm) & 1;
2297 }
2298
2299 return r;
2300 }
2301
2302 /**
2303 * Clears the selected GPNVM bit.
2304 * @param pPrivate info about the bank
2305 * @param gpnvm GPNVM index.
2306 * @returns 0 if successful; otherwise returns an error code.
2307 */
2308 static int FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
2309 {
2310 int r;
2311 unsigned v;
2312
2313 LOG_DEBUG("Here");
2314 if (pPrivate->bank_number != 0) {
2315 LOG_ERROR("GPNVM only works with Bank0");
2316 return ERROR_FAIL;
2317 }
2318
2319 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
2320 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2321 gpnvm, pPrivate->pChip->details.n_gpnvms);
2322 return ERROR_FAIL;
2323 }
2324
2325 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
2326 if (r != ERROR_OK) {
2327 LOG_DEBUG("Failed: %d", r);
2328 return r;
2329 }
2330 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
2331 LOG_DEBUG("End: %d", r);
2332 return r;
2333 }
2334
2335 /**
2336 * Sets the selected GPNVM bit.
2337 * @param pPrivate info about the bank
2338 * @param gpnvm GPNVM index.
2339 */
2340 static int FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
2341 {
2342 int r;
2343 unsigned v;
2344
2345 if (pPrivate->bank_number != 0) {
2346 LOG_ERROR("GPNVM only works with Bank0");
2347 return ERROR_FAIL;
2348 }
2349
2350 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
2351 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2352 gpnvm, pPrivate->pChip->details.n_gpnvms);
2353 return ERROR_FAIL;
2354 }
2355
2356 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
2357 if (r != ERROR_OK)
2358 return r;
2359 if (v) {
2360 /* already set */
2361 r = ERROR_OK;
2362 } else {
2363 /* set it */
2364 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
2365 }
2366 return r;
2367 }
2368
2369 /**
2370 * Returns a bit field (at most 64) of locked regions within a page.
2371 * @param pPrivate info about the bank
2372 * @param v where to store locked bits
2373 */
2374 static int FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
2375 {
2376 int r;
2377 LOG_DEBUG("Here");
2378 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
2379 if (r == ERROR_OK)
2380 r = EFC_GetResult(pPrivate, v);
2381 LOG_DEBUG("End: %d", r);
2382 return r;
2383 }
2384
2385 /**
2386 * Unlocks all the regions in the given address range.
2387 * @param pPrivate info about the bank
2388 * @param start_sector first sector to unlock
2389 * @param end_sector last (inclusive) to unlock
2390 */
2391
2392 static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,
2393 unsigned start_sector,
2394 unsigned end_sector)
2395 {
2396 int r;
2397 uint32_t status;
2398 uint32_t pg;
2399 uint32_t pages_per_sector;
2400
2401 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
2402
2403 /* Unlock all pages */
2404 while (start_sector <= end_sector) {
2405 pg = start_sector * pages_per_sector;
2406
2407 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
2408 if (r != ERROR_OK)
2409 return r;
2410 start_sector++;
2411 }
2412
2413 return ERROR_OK;
2414 }
2415
2416 /**
2417 * Locks regions
2418 * @param pPrivate - info about the bank
2419 * @param start_sector - first sector to lock
2420 * @param end_sector - last sector (inclusive) to lock
2421 */
2422 static int FLASHD_Lock(struct sam3_bank_private *pPrivate,
2423 unsigned start_sector,
2424 unsigned end_sector)
2425 {
2426 uint32_t status;
2427 uint32_t pg;
2428 uint32_t pages_per_sector;
2429 int r;
2430
2431 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
2432
2433 /* Lock all pages */
2434 while (start_sector <= end_sector) {
2435 pg = start_sector * pages_per_sector;
2436
2437 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
2438 if (r != ERROR_OK)
2439 return r;
2440 start_sector++;
2441 }
2442 return ERROR_OK;
2443 }
2444
2445 /****** END SAM3 CODE ********/
2446
2447 /* begin helpful debug code */
2448 /* print the fieldname, the field value, in dec & hex, and return field value */
2449 static uint32_t sam3_reg_fieldname(struct sam3_chip *pChip,
2450 const char *regname,
2451 uint32_t value,
2452 unsigned shift,
2453 unsigned width)
2454 {
2455 uint32_t v;
2456 int hwidth, dwidth;
2457
2458
2459 /* extract the field */
2460 v = value >> shift;
2461 v = v & ((1 << width)-1);
2462 if (width <= 16) {
2463 hwidth = 4;
2464 dwidth = 5;
2465 } else {
2466 hwidth = 8;
2467 dwidth = 12;
2468 }
2469
2470 /* show the basics */
2471 LOG_USER_N("\t%*s: %*" PRIu32 " [0x%0*" PRIx32 "] ",
2472 REG_NAME_WIDTH, regname,
2473 dwidth, v,
2474 hwidth, v);
2475 return v;
2476 }
2477
2478 static const char _unknown[] = "unknown";
2479 static const char *const eproc_names[] = {
2480 _unknown, /* 0 */
2481 "arm946es", /* 1 */
2482 "arm7tdmi", /* 2 */
2483 "Cortex-M3", /* 3 */
2484 "arm920t", /* 4 */
2485 "arm926ejs", /* 5 */
2486 _unknown, /* 6 */
2487 _unknown, /* 7 */
2488 _unknown, /* 8 */
2489 _unknown, /* 9 */
2490 _unknown, /* 10 */
2491 _unknown, /* 11 */
2492 _unknown, /* 12 */
2493 _unknown, /* 13 */
2494 _unknown, /* 14 */
2495 _unknown, /* 15 */
2496 };
2497
2498 #define nvpsize2 nvpsize /* these two tables are identical */
2499 static const char *const nvpsize[] = {
2500 "none", /* 0 */
2501 "8K bytes", /* 1 */
2502 "16K bytes", /* 2 */
2503 "32K bytes", /* 3 */
2504 _unknown, /* 4 */
2505 "64K bytes", /* 5 */
2506 _unknown, /* 6 */
2507 "128K bytes", /* 7 */
2508 _unknown, /* 8 */
2509 "256K bytes", /* 9 */
2510 "512K bytes", /* 10 */
2511 _unknown, /* 11 */
2512 "1024K bytes", /* 12 */
2513 _unknown, /* 13 */
2514 "2048K bytes", /* 14 */
2515 _unknown, /* 15 */
2516 };
2517
2518 static const char *const sramsize[] = {
2519 "48K Bytes", /* 0 */
2520 "1K Bytes", /* 1 */
2521 "2K Bytes", /* 2 */
2522 "6K Bytes", /* 3 */
2523 "112K Bytes", /* 4 */
2524 "4K Bytes", /* 5 */
2525 "80K Bytes", /* 6 */
2526 "160K Bytes", /* 7 */
2527 "8K Bytes", /* 8 */
2528 "16K Bytes", /* 9 */
2529 "32K Bytes", /* 10 */
2530 "64K Bytes", /* 11 */
2531 "128K Bytes", /* 12 */
2532 "256K Bytes", /* 13 */
2533 "96K Bytes", /* 14 */
2534 "512K Bytes", /* 15 */
2535
2536 };
2537
2538 static const struct archnames { unsigned value; const char *name; } archnames[] = {
2539 { 0x19, "AT91SAM9xx Series" },
2540 { 0x29, "AT91SAM9XExx Series" },
2541 { 0x34, "AT91x34 Series" },
2542 { 0x37, "CAP7 Series" },
2543 { 0x39, "CAP9 Series" },
2544 { 0x3B, "CAP11 Series" },
2545 { 0x40, "AT91x40 Series" },
2546 { 0x42, "AT91x42 Series" },
2547 { 0x55, "AT91x55 Series" },
2548 { 0x60, "AT91SAM7Axx Series" },
2549 { 0x61, "AT91SAM7AQxx Series" },
2550 { 0x63, "AT91x63 Series" },
2551 { 0x70, "AT91SAM7Sxx Series" },
2552 { 0x71, "AT91SAM7XCxx Series" },
2553 { 0x72, "AT91SAM7SExx Series" },
2554 { 0x73, "AT91SAM7Lxx Series" },
2555 { 0x75, "AT91SAM7Xxx Series" },
2556 { 0x76, "AT91SAM7SLxx Series" },
2557 { 0x80, "ATSAM3UxC Series (100-pin version)" },
2558 { 0x81, "ATSAM3UxE Series (144-pin version)" },
2559 { 0x83, "ATSAM3AxC Series (100-pin version)" },
2560 { 0x84, "ATSAM3XxC Series (100-pin version)" },
2561 { 0x85, "ATSAM3XxE Series (144-pin version)" },
2562 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
2563 { 0x88, "ATSAM3SxA Series (48-pin version)" },
2564 { 0x89, "ATSAM3SxB Series (64-pin version)" },
2565 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
2566 { 0x92, "AT91x92 Series" },
2567 { 0x93, "ATSAM3NxA Series (48-pin version)" },
2568 { 0x94, "ATSAM3NxB Series (64-pin version)" },
2569 { 0x95, "ATSAM3NxC Series (100-pin version)" },
2570 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2571 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2572 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2573 { 0xA5, "ATSAM5A" },
2574 { 0xF0, "AT75Cxx Series" },
2575 { -1, NULL },
2576 };
2577
2578 static const char *const nvptype[] = {
2579 "rom", /* 0 */
2580 "romless or onchip flash", /* 1 */
2581 "embedded flash memory",/* 2 */
2582 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2583 "sram emulating flash", /* 4 */
2584 _unknown, /* 5 */
2585 _unknown, /* 6 */
2586 _unknown, /* 7 */
2587 };
2588
2589 static const char *_yes_or_no(uint32_t v)
2590 {
2591 if (v)
2592 return "YES";
2593 else
2594 return "NO";
2595 }
2596
2597 static const char *const _rc_freq[] = {
2598 "4 MHz", "8 MHz", "12 MHz", "reserved"
2599 };
2600
2601 static void sam3_explain_ckgr_mor(struct sam3_chip *pChip)
2602 {
2603 uint32_t v;
2604 uint32_t rcen;
2605
2606 v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
2607 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2608 v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
2609 LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2610 rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
2611 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2612 v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
2613 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2614
2615 pChip->cfg.rc_freq = 0;
2616 if (rcen) {
2617 switch (v) {
2618 default:
2619 pChip->cfg.rc_freq = 0;
2620 break;
2621 case 0:
2622 pChip->cfg.rc_freq = 4 * 1000 * 1000;
2623 break;
2624 case 1:
2625 pChip->cfg.rc_freq = 8 * 1000 * 1000;
2626 break;
2627 case 2:
2628 pChip->cfg.rc_freq = 12 * 1000 * 1000;
2629 break;
2630 }
2631 }
2632
2633 v = sam3_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
2634 LOG_USER("(startup clks, time= %f uSecs)",
2635 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
2636 v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
2637 LOG_USER("(mainosc source: %s)",
2638 v ? "external xtal" : "internal RC");
2639
2640 v = sam3_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
2641 LOG_USER("(clock failure enabled: %s)",
2642 _yes_or_no(v));
2643 }
2644
2645 static void sam3_explain_chipid_cidr(struct sam3_chip *pChip)
2646 {
2647 int x;
2648 uint32_t v;
2649 const char *cp;
2650
2651 sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
2652 LOG_USER_N("\n");
2653
2654 v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
2655 LOG_USER("%s", eproc_names[v]);
2656
2657 v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
2658 LOG_USER("%s", nvpsize[v]);
2659
2660 v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
2661 LOG_USER("%s", nvpsize2[v]);
2662
2663 v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
2664 LOG_USER("%s", sramsize[v]);
2665
2666 v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
2667 cp = _unknown;
2668 for (x = 0; archnames[x].name; x++) {
2669 if (v == archnames[x].value) {
2670 cp = archnames[x].name;
2671 break;
2672 }
2673 }
2674
2675 LOG_USER("%s", cp);
2676
2677 v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
2678 LOG_USER("%s", nvptype[v]);
2679
2680 v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
2681 LOG_USER("(exists: %s)", _yes_or_no(v));
2682 }
2683
2684 static void sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
2685 {
2686 uint32_t v;
2687
2688 v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
2689 LOG_USER("(main ready: %s)", _yes_or_no(v));
2690
2691 v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
2692
2693 v = (v * pChip->cfg.slow_freq) / 16;
2694 pChip->cfg.mainosc_freq = v;
2695
2696 LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
2697 _tomhz(v),
2698 (uint32_t)(pChip->cfg.slow_freq / 1000),
2699 (uint32_t)(pChip->cfg.slow_freq % 1000));
2700 }
2701
2702 static void sam3_explain_ckgr_plla(struct sam3_chip *pChip)
2703 {
2704 uint32_t mula, diva;
2705
2706 diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
2707 LOG_USER_N("\n");
2708 mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
2709 LOG_USER_N("\n");
2710 pChip->cfg.plla_freq = 0;
2711 if (mula == 0)
2712 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2713 else if (diva == 0)
2714 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2715 else if (diva >= 1) {
2716 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
2717 LOG_USER("\tPLLA Freq: %3.03f MHz",
2718 _tomhz(pChip->cfg.plla_freq));
2719 }
2720 }
2721
2722 static void sam3_explain_mckr(struct sam3_chip *pChip)
2723 {
2724 uint32_t css, pres, fin = 0;
2725 int pdiv = 0;
2726 const char *cp = NULL;
2727
2728 css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
2729 switch (css & 3) {
2730 case 0:
2731 fin = pChip->cfg.slow_freq;
2732 cp = "slowclk";
2733 break;
2734 case 1:
2735 fin = pChip->cfg.mainosc_freq;
2736 cp = "mainosc";
2737 break;
2738 case 2:
2739 fin = pChip->cfg.plla_freq;
2740 cp = "plla";
2741 break;
2742 case 3:
2743 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
2744 fin = 480 * 1000 * 1000;
2745 cp = "upll";
2746 } else {
2747 fin = 0;
2748 cp = "upll (*ERROR* UPLL is disabled)";
2749 }
2750 break;
2751 default:
2752 assert(0);
2753 break;
2754 }
2755
2756 LOG_USER("%s (%3.03f Mhz)",
2757 cp,
2758 _tomhz(fin));
2759 pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
2760 switch (pres & 0x07) {
2761 case 0:
2762 pdiv = 1;
2763 cp = "selected clock";
2764 break;
2765 case 1:
2766 pdiv = 2;
2767 cp = "clock/2";
2768 break;
2769 case 2:
2770 pdiv = 4;
2771 cp = "clock/4";
2772 break;
2773 case 3:
2774 pdiv = 8;
2775 cp = "clock/8";
2776 break;
2777 case 4:
2778 pdiv = 16;
2779 cp = "clock/16";
2780 break;
2781 case 5:
2782 pdiv = 32;
2783 cp = "clock/32";
2784 break;
2785 case 6:
2786 pdiv = 64;
2787 cp = "clock/64";
2788 break;
2789 case 7:
2790 pdiv = 6;
2791 cp = "clock/6";
2792 break;
2793 default:
2794 assert(0);
2795 break;
2796 }
2797 LOG_USER("(%s)", cp);
2798 fin = fin / pdiv;
2799 /* sam3 has a *SINGLE* clock - */
2800 /* other at91 series parts have divisors for these. */
2801 pChip->cfg.cpu_freq = fin;
2802 pChip->cfg.mclk_freq = fin;
2803 pChip->cfg.fclk_freq = fin;
2804 LOG_USER("\t\tResult CPU Freq: %3.03f",
2805 _tomhz(fin));
2806 }
2807
2808 #if 0
2809 static struct sam3_chip *target2sam3(struct target *pTarget)
2810 {
2811 struct sam3_chip *pChip;
2812
2813 if (pTarget == NULL)
2814 return NULL;
2815
2816 pChip = all_sam3_chips;
2817 while (pChip) {
2818 if (pChip->target == pTarget)
2819 break; /* return below */
2820 else
2821 pChip = pChip->next;
2822 }
2823 return pChip;
2824 }
2825 #endif
2826
2827 static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
2828 {
2829 /* this function exists to help */
2830 /* keep funky offsetof() errors */
2831 /* and casting from causing bugs */
2832
2833 /* By using prototypes - we can detect what would */
2834 /* be casting errors. */
2835
2836 return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
2837 }
2838
2839
2840 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
2841 struct sam3_cfg, \
2842 NAME), # NAME, FUNC }
2843 static const struct sam3_reg_list sam3_all_regs[] = {
2844 SAM3_ENTRY(CKGR_MOR, sam3_explain_ckgr_mor),
2845 SAM3_ENTRY(CKGR_MCFR, sam3_explain_ckgr_mcfr),
2846 SAM3_ENTRY(CKGR_PLLAR, sam3_explain_ckgr_plla),
2847 SAM3_ENTRY(CKGR_UCKR, NULL),
2848 SAM3_ENTRY(PMC_FSMR, NULL),
2849 SAM3_ENTRY(PMC_FSPR, NULL),
2850 SAM3_ENTRY(PMC_IMR, NULL),
2851 SAM3_ENTRY(PMC_MCKR, sam3_explain_mckr),
2852 SAM3_ENTRY(PMC_PCK0, NULL),
2853 SAM3_ENTRY(PMC_PCK1, NULL),
2854 SAM3_ENTRY(PMC_PCK2, NULL),
2855 SAM3_ENTRY(PMC_PCSR, NULL),
2856 SAM3_ENTRY(PMC_SCSR, NULL),
2857 SAM3_ENTRY(PMC_SR, NULL),
2858 SAM3_ENTRY(CHIPID_CIDR, sam3_explain_chipid_cidr),
2859 SAM3_ENTRY(CHIPID_CIDR2, sam3_explain_chipid_cidr),
2860 SAM3_ENTRY(CHIPID_EXID, NULL),
2861 SAM3_ENTRY(CHIPID_EXID2, NULL),
2862 /* TERMINATE THE LIST */
2863 { .name = NULL }
2864 };
2865 #undef SAM3_ENTRY
2866
2867 static struct sam3_bank_private *get_sam3_bank_private(struct flash_bank *bank)
2868 {
2869 return bank->driver_priv;
2870 }
2871
2872 /**
2873 * Given a pointer to where it goes in the structure,
2874 * determine the register name, address from the all registers table.
2875 */
2876 static const struct sam3_reg_list *sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
2877 {
2878 const struct sam3_reg_list *pReg;
2879
2880 pReg = &(sam3_all_regs[0]);
2881 while (pReg->name) {
2882 uint32_t *pPossible;
2883
2884 /* calculate where this one go.. */
2885 /* it is "possibly" this register. */
2886
2887 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
2888
2889 /* well? Is it this register */
2890 if (pPossible == goes_here) {
2891 /* Jump for joy! */
2892 return pReg;
2893 }
2894
2895 /* next... */
2896 pReg++;
2897 }
2898 /* This is *TOTAL*PANIC* - we are totally screwed. */
2899 LOG_ERROR("INVALID SAM3 REGISTER");
2900 return NULL;
2901 }
2902
2903 static int sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
2904 {
2905 const struct sam3_reg_list *pReg;
2906 int r;
2907
2908 pReg = sam3_GetReg(pChip, goes_here);
2909 if (!pReg)
2910 return ERROR_FAIL;
2911
2912 r = target_read_u32(pChip->target, pReg->address, goes_here);
2913 if (r != ERROR_OK) {
2914 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
2915 pReg->name, (unsigned)(pReg->address), r);
2916 }
2917 return r;
2918 }
2919
2920 static int sam3_ReadAllRegs(struct sam3_chip *pChip)
2921 {
2922 int r;
2923 const struct sam3_reg_list *pReg;
2924
2925 pReg = &(sam3_all_regs[0]);
2926 while (pReg->name) {
2927 r = sam3_ReadThisReg(pChip,
2928 sam3_get_reg_ptr(&(pChip->cfg), pReg));
2929 if (r != ERROR_OK) {
2930 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Error: %d",
2931 pReg->name, ((unsigned)(pReg->address)), r);
2932 return r;
2933 }
2934 pReg++;
2935 }
2936
2937 /* Chip identification register
2938 *
2939 * Unfortunately, the chip identification register is not at
2940 * a constant address across all of the SAM3 series'. As a
2941 * consequence, a simple heuristic is used to find where it's
2942 * at...
2943 *
2944 * If the contents at the first address is zero, then we know
2945 * that the second address is where the chip id register is.
2946 * We can deduce this because for those SAM's that have the
2947 * chip id @ 0x400e0940, the first address, 0x400e0740, is
2948 * located in the memory map of the Power Management Controller
2949 * (PMC). Furthermore, the address is not used by the PMC.
2950 * So when read, the memory controller returns zero.*/
2951 if (pChip->cfg.CHIPID_CIDR == 0) {
2952 /*Put the correct CIDR and EXID values in the pChip structure */
2953 pChip->cfg.CHIPID_CIDR = pChip->cfg.CHIPID_CIDR2;
2954 pChip->cfg.CHIPID_EXID = pChip->cfg.CHIPID_EXID2;
2955 }
2956 return ERROR_OK;
2957 }
2958
2959 static int sam3_GetInfo(struct sam3_chip *pChip)
2960 {
2961 const struct sam3_reg_list *pReg;
2962 uint32_t regval;
2963
2964 pReg = &(sam3_all_regs[0]);
2965 while (pReg->name) {
2966 /* display all regs */
2967 LOG_DEBUG("Start: %s", pReg->name);
2968 regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
2969 LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
2970 REG_NAME_WIDTH,
2971 pReg->name,
2972 pReg->address,
2973 regval);
2974 if (pReg->explain_func)
2975 (*(pReg->explain_func))(pChip);
2976 LOG_DEBUG("End: %s", pReg->name);
2977 pReg++;
2978 }
2979 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
2980 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
2981 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
2982 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
2983 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
2984
2985 LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32,
2986 pChip->cfg.unique_id[0],
2987 pChip->cfg.unique_id[1],
2988 pChip->cfg.unique_id[2],
2989 pChip->cfg.unique_id[3]);
2990
2991 return ERROR_OK;
2992 }
2993
2994 static int sam3_erase_check(struct flash_bank *bank)
2995 {
2996 int x;
2997
2998 LOG_DEBUG("Here");
2999 if (bank->target->state != TARGET_HALTED) {
3000 LOG_ERROR("Target not halted");
3001 return ERROR_TARGET_NOT_HALTED;
3002 }
3003 if (0 == bank->num_sectors) {
3004 LOG_ERROR("Target: not supported/not probed");
3005 return ERROR_FAIL;
3006 }
3007
3008 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
3009 for (x = 0; x < bank->num_sectors; x++)
3010 bank->sectors[x].is_erased = 1;
3011
3012 LOG_DEBUG("Done");
3013 return ERROR_OK;
3014 }
3015
3016 static int sam3_protect_check(struct flash_bank *bank)
3017 {
3018 int r;
3019 uint32_t v = 0;
3020 unsigned x;
3021 struct sam3_bank_private *pPrivate;
3022
3023 LOG_DEBUG("Begin");
3024 if (bank->target->state != TARGET_HALTED) {
3025 LOG_ERROR("Target not halted");
3026 return ERROR_TARGET_NOT_HALTED;
3027 }
3028
3029 pPrivate = get_sam3_bank_private(bank);
3030 if (!pPrivate) {
3031 LOG_ERROR("no private for this bank?");
3032 return ERROR_FAIL;
3033 }
3034 if (!(pPrivate->probed))
3035 return ERROR_FLASH_BANK_NOT_PROBED;
3036
3037 r = FLASHD_GetLockBits(pPrivate, &v);
3038 if (r != ERROR_OK) {
3039 LOG_DEBUG("Failed: %d", r);
3040 return r;
3041 }
3042
3043 for (x = 0; x < pPrivate->nsectors; x++)
3044 bank->sectors[x].is_protected = (!!(v & (1 << x)));
3045 LOG_DEBUG("Done");
3046 return ERROR_OK;
3047 }
3048
3049 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
3050 {
3051 struct sam3_chip *pChip;
3052
3053 pChip = all_sam3_chips;
3054
3055 /* is this an existing chip? */
3056 while (pChip) {
3057 if (pChip->target == bank->target)
3058 break;
3059 pChip = pChip->next;
3060 }
3061
3062 if (!pChip) {
3063 /* this is a *NEW* chip */
3064 pChip = calloc(1, sizeof(struct sam3_chip));
3065 if (!pChip) {
3066 LOG_ERROR("NO RAM!");
3067 return ERROR_FAIL;
3068 }
3069 pChip->target = bank->target;
3070 /* insert at head */
3071 pChip->next = all_sam3_chips;
3072 all_sam3_chips = pChip;
3073 pChip->target = bank->target;
3074 /* assumption is this runs at 32khz */
3075 pChip->cfg.slow_freq = 32768;
3076 pChip->probed = 0;
3077 }
3078
3079 switch (bank->base) {
3080 default:
3081 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x "
3082 "[at91sam3u series] or 0x%08x [at91sam3s series] or "
3083 "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )",
3084 ((unsigned int)(bank->base)),
3085 ((unsigned int)(FLASH_BANK0_BASE_U)),
3086 ((unsigned int)(FLASH_BANK1_BASE_U)),
3087 ((unsigned int)(FLASH_BANK_BASE_S)),
3088 ((unsigned int)(FLASH_BANK_BASE_N)),
3089 ((unsigned int)(FLASH_BANK0_BASE_AX)),
3090 ((unsigned int)(FLASH_BANK1_BASE_256K_AX)),
3091 ((unsigned int)(FLASH_BANK1_BASE_512K_AX)));
3092 return ERROR_FAIL;
3093 break;
3094
3095 /* at91sam3s and at91sam3n series only has bank 0*/
3096 /* at91sam3u and at91sam3ax series has the same address for bank 0*/
3097 case FLASH_BANK_BASE_S:
3098 case FLASH_BANK0_BASE_U:
3099 bank->driver_priv = &(pChip->details.bank[0]);
3100 bank->bank_number = 0;
3101 pChip->details.bank[0].pChip = pChip;
3102 pChip->details.bank[0].pBank = bank;
3103 break;
3104
3105 /* Bank 1 of at91sam3u or at91sam3ax series */
3106 case FLASH_BANK1_BASE_U:
3107 case FLASH_BANK1_BASE_256K_AX:
3108 case FLASH_BANK1_BASE_512K_AX:
3109 bank->driver_priv = &(pChip->details.bank[1]);
3110 bank->bank_number = 1;
3111 pChip->details.bank[1].pChip = pChip;
3112 pChip->details.bank[1].pBank = bank;
3113 break;
3114 }
3115
3116 /* we initialize after probing. */
3117 return ERROR_OK;
3118 }
3119
3120 /**
3121 * Remove all chips from the internal list without distingushing which one
3122 * is owned by this bank. This simplification works only for one shot
3123 * deallocation like current flash_free_all_banks()
3124 */
3125 void sam3_free_driver_priv(struct flash_bank *bank)
3126 {
3127 struct sam3_chip *chip = all_sam3_chips;
3128 while (chip) {
3129 struct sam3_chip *next = chip->next;
3130 free(chip);
3131 chip = next;
3132 }
3133 all_sam3_chips = NULL;
3134 }
3135
3136 static int sam3_GetDetails(struct sam3_bank_private *pPrivate)
3137 {
3138 const struct sam3_chip_details *pDetails;