1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
17 * GNU General public License for more details. *
19 * You should have received a copy of the GNU General public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ****************************************************************************/
25 /* Some of the the lower level code was based on code supplied by
26 * ATMEL under this copyright. */
28 /* BEGIN ATMEL COPYRIGHT */
29 /* ----------------------------------------------------------------------------
30 * ATMEL Microcontroller Software Support
31 * ----------------------------------------------------------------------------
32 * Copyright (c) 2009, Atmel Corporation
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions are met:
39 * - Redistributions of source code must retain the above copyright notice,
40 * this list of conditions and the disclaimer below.
42 * Atmel's name may not be used to endorse or promote products derived from
43 * this software without specific prior written permission.
45 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
47 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
48 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
50 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
51 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
52 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
53 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
54 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 * ----------------------------------------------------------------------------
57 /* END ATMEL COPYRIGHT */
65 #include <helper/time_support.h>
67 #define REG_NAME_WIDTH (12)
69 // at91sam3u series (has one or two flash banks)
70 #define FLASH_BANK0_BASE_U 0x00080000
71 #define FLASH_BANK1_BASE_U 0x00100000
73 // at91sam3s series (has always one flash bank)
74 #define FLASH_BANK_BASE_S 0x00400000
76 // at91sam3n series (has always one flash bank)
77 #define FLASH_BANK_BASE_N 0x00400000
79 #define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor
80 #define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page
81 #define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock
82 #define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page
83 #define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock
84 #define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All
85 // cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2
86 // #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane?
87 // cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2
88 // #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages?
89 #define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit
90 #define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit
91 #define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit
92 #define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit
93 #define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit
94 #define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit
95 #define AT91C_EFC_FCMD_STUI (0xE) // (EFC) Start Read Unique ID
96 #define AT91C_EFC_FCMD_SPUI (0xF) // (EFC) Stop Read Unique ID
98 #define offset_EFC_FMR 0
99 #define offset_EFC_FCR 4
100 #define offset_EFC_FSR 8
101 #define offset_EFC_FRR 12
104 extern struct flash_driver at91sam3_flash
;
107 _tomhz(uint32_t freq_hz
)
111 f
= ((float)(freq_hz
)) / 1000000.0;
115 // How the chip is configured.
117 uint32_t unique_id
[4];
121 uint32_t mainosc_freq
;
131 #define SAM3_CHIPID_CIDR (0x400E0740)
132 uint32_t CHIPID_CIDR
;
133 #define SAM3_CHIPID_EXID (0x400E0744)
134 uint32_t CHIPID_EXID
;
136 #define SAM3_SUPC_CR (0x400E1210)
139 #define SAM3_PMC_BASE (0x400E0400)
140 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
142 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
144 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
146 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
148 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
150 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
152 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
154 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
156 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
158 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
160 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
162 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
164 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
166 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
171 struct sam3_bank_private
{
173 // DANGER: THERE ARE DRAGONS HERE..
174 // NOTE: If you add more 'ghost' pointers
175 // be aware that you must *manually* update
176 // these pointers in the function sam3_GetDetails()
177 // See the comment "Here there be dragons"
179 // so we can find the chip we belong to
180 struct sam3_chip
*pChip
;
181 // so we can find the orginal bank pointer
182 struct flash_bank
*pBank
;
183 unsigned bank_number
;
184 uint32_t controller_address
;
185 uint32_t base_address
;
189 unsigned sector_size
;
193 struct sam3_chip_details
{
194 // THERE ARE DRAGONS HERE..
195 // note: If you add pointers here
196 // becareful about them as they
197 // may need to be updated inside
198 // the function: "sam3_GetDetails()
199 // which copy/overwrites the
200 // 'runtime' copy of this structure
201 uint32_t chipid_cidr
;
205 #define SAM3_N_NVM_BITS 3
206 unsigned gpnvm
[SAM3_N_NVM_BITS
];
207 unsigned total_flash_size
;
208 unsigned total_sram_size
;
210 #define SAM3_MAX_FLASH_BANKS 2
211 // these are "initialized" from the global const data
212 struct sam3_bank_private bank
[SAM3_MAX_FLASH_BANKS
];
217 struct sam3_chip
*next
;
220 // this is "initialized" from the global const structure
221 struct sam3_chip_details details
;
222 struct target
*target
;
227 struct sam3_reg_list
{
228 uint32_t address
; size_t struct_offset
; const char *name
;
229 void (*explain_func
)(struct sam3_chip
*pInfo
);
233 static struct sam3_chip
*all_sam3_chips
;
235 static struct sam3_chip
*
236 get_current_sam3(struct command_context
*cmd_ctx
)
239 static struct sam3_chip
*p
;
241 t
= get_current_target(cmd_ctx
);
243 command_print(cmd_ctx
, "No current target?");
249 // this should not happen
250 // the command is not registered until the chip is created?
251 command_print(cmd_ctx
, "No SAM3 chips exist?");
256 if (p
->target
== t
) {
261 command_print(cmd_ctx
, "Cannot find SAM3 chip?");
266 // these are used to *initialize* the "pChip->details" structure.
267 static const struct sam3_chip_details all_sam3_details
[] = {
268 // Start at91sam3u* series
270 .chipid_cidr
= 0x28100960,
271 .name
= "at91sam3u4e",
272 .total_flash_size
= 256 * 1024,
273 .total_sram_size
= 52 * 1024,
277 // System boots at address 0x0
278 // gpnvm[1] = selects boot code
280 // boot is via "SAMBA" (rom)
283 // Selection is via gpnvm[2]
286 // NOTE: banks 0 & 1 switch places
288 // Bank0 is the boot rom
290 // Bank1 is the boot rom
299 .base_address
= FLASH_BANK0_BASE_U
,
300 .controller_address
= 0x400e0800,
302 .size_bytes
= 128 * 1024,
314 .base_address
= FLASH_BANK1_BASE_U
,
315 .controller_address
= 0x400e0a00,
317 .size_bytes
= 128 * 1024,
326 .chipid_cidr
= 0x281a0760,
327 .name
= "at91sam3u2e",
328 .total_flash_size
= 128 * 1024,
329 .total_sram_size
= 36 * 1024,
333 // System boots at address 0x0
334 // gpnvm[1] = selects boot code
336 // boot is via "SAMBA" (rom)
339 // Selection is via gpnvm[2]
348 .base_address
= FLASH_BANK0_BASE_U
,
349 .controller_address
= 0x400e0800,
351 .size_bytes
= 128 * 1024,
365 .chipid_cidr
= 0x28190560,
366 .name
= "at91sam3u1e",
367 .total_flash_size
= 64 * 1024,
368 .total_sram_size
= 20 * 1024,
372 // System boots at address 0x0
373 // gpnvm[1] = selects boot code
375 // boot is via "SAMBA" (rom)
378 // Selection is via gpnvm[2]
389 .base_address
= FLASH_BANK0_BASE_U
,
390 .controller_address
= 0x400e0800,
392 .size_bytes
= 64 * 1024,
408 .chipid_cidr
= 0x28000960,
409 .name
= "at91sam3u4c",
410 .total_flash_size
= 256 * 1024,
411 .total_sram_size
= 52 * 1024,
415 // System boots at address 0x0
416 // gpnvm[1] = selects boot code
418 // boot is via "SAMBA" (rom)
421 // Selection is via gpnvm[2]
424 // NOTE: banks 0 & 1 switch places
426 // Bank0 is the boot rom
428 // Bank1 is the boot rom
437 .base_address
= FLASH_BANK0_BASE_U
,
438 .controller_address
= 0x400e0800,
440 .size_bytes
= 128 * 1024,
451 .base_address
= FLASH_BANK1_BASE_U
,
452 .controller_address
= 0x400e0a00,
454 .size_bytes
= 128 * 1024,
463 .chipid_cidr
= 0x280a0760,
464 .name
= "at91sam3u2c",
465 .total_flash_size
= 128 * 1024,
466 .total_sram_size
= 36 * 1024,
470 // System boots at address 0x0
471 // gpnvm[1] = selects boot code
473 // boot is via "SAMBA" (rom)
476 // Selection is via gpnvm[2]
485 .base_address
= FLASH_BANK0_BASE_U
,
486 .controller_address
= 0x400e0800,
488 .size_bytes
= 128 * 1024,
502 .chipid_cidr
= 0x28090560,
503 .name
= "at91sam3u1c",
504 .total_flash_size
= 64 * 1024,
505 .total_sram_size
= 20 * 1024,
509 // System boots at address 0x0
510 // gpnvm[1] = selects boot code
512 // boot is via "SAMBA" (rom)
515 // Selection is via gpnvm[2]
526 .base_address
= FLASH_BANK0_BASE_U
,
527 .controller_address
= 0x400e0800,
529 .size_bytes
= 64 * 1024,
544 // Start at91sam3s* series
546 // Note: The preliminary at91sam3s datasheet says on page 302
547 // that the flash controller is at address 0x400E0800.
548 // This is _not_ the case, the controller resides at address 0x400e0a0.
550 .chipid_cidr
= 0x28A00960,
551 .name
= "at91sam3s4c",
552 .total_flash_size
= 256 * 1024,
553 .total_sram_size
= 48 * 1024,
563 .base_address
= FLASH_BANK_BASE_S
,
565 .controller_address
= 0x400e0a00,
567 .size_bytes
= 256 * 1024,
583 .chipid_cidr
= 0x28900960,
584 .name
= "at91sam3s4b",
585 .total_flash_size
= 256 * 1024,
586 .total_sram_size
= 48 * 1024,
596 .base_address
= FLASH_BANK_BASE_S
,
598 .controller_address
= 0x400e0a00,
600 .size_bytes
= 256 * 1024,
615 .chipid_cidr
= 0x28800960,
616 .name
= "at91sam3s4a",
617 .total_flash_size
= 256 * 1024,
618 .total_sram_size
= 48 * 1024,
628 .base_address
= FLASH_BANK_BASE_S
,
630 .controller_address
= 0x400e0a00,
632 .size_bytes
= 256 * 1024,
647 .chipid_cidr
= 0x28AA0760,
648 .name
= "at91sam3s2c",
649 .total_flash_size
= 128 * 1024,
650 .total_sram_size
= 32 * 1024,
660 .base_address
= FLASH_BANK_BASE_S
,
662 .controller_address
= 0x400e0a00,
664 .size_bytes
= 128 * 1024,
679 .chipid_cidr
= 0x289A0760,
680 .name
= "at91sam3s2b",
681 .total_flash_size
= 128 * 1024,
682 .total_sram_size
= 32 * 1024,
692 .base_address
= FLASH_BANK_BASE_S
,
694 .controller_address
= 0x400e0a00,
696 .size_bytes
= 128 * 1024,
711 .chipid_cidr
= 0x288A0760,
712 .name
= "at91sam3s2a",
713 .total_flash_size
= 128 * 1024,
714 .total_sram_size
= 32 * 1024,
724 .base_address
= FLASH_BANK_BASE_S
,
726 .controller_address
= 0x400e0a00,
728 .size_bytes
= 128 * 1024,
743 .chipid_cidr
= 0x28A90560,
744 .name
= "at91sam3s1c",
745 .total_flash_size
= 64 * 1024,
746 .total_sram_size
= 16 * 1024,
756 .base_address
= FLASH_BANK_BASE_S
,
758 .controller_address
= 0x400e0a00,
760 .size_bytes
= 64 * 1024,
775 .chipid_cidr
= 0x28990560,
776 .name
= "at91sam3s1b",
777 .total_flash_size
= 64 * 1024,
778 .total_sram_size
= 16 * 1024,
788 .base_address
= FLASH_BANK_BASE_S
,
790 .controller_address
= 0x400e0a00,
792 .size_bytes
= 64 * 1024,
807 .chipid_cidr
= 0x28890560,
808 .name
= "at91sam3s1a",
809 .total_flash_size
= 64 * 1024,
810 .total_sram_size
= 16 * 1024,
820 .base_address
= FLASH_BANK_BASE_S
,
822 .controller_address
= 0x400e0a00,
824 .size_bytes
= 64 * 1024,
839 // Start at91sam3n* series
841 .chipid_cidr
= 0x29540960,
842 .name
= "at91sam3n4c",
843 .total_flash_size
= 256 * 1024,
844 .total_sram_size
= 24 * 1024,
848 // System boots at address 0x0
849 // gpnvm[1] = selects boot code
851 // boot is via "SAMBA" (rom)
854 // Selection is via gpnvm[2]
857 // NOTE: banks 0 & 1 switch places
859 // Bank0 is the boot rom
861 // Bank1 is the boot rom
870 .base_address
= FLASH_BANK_BASE_N
,
871 .controller_address
= 0x400e0A00,
873 .size_bytes
= 256 * 1024,
875 .sector_size
= 16384,
889 .chipid_cidr
= 0x29440960,
890 .name
= "at91sam3n4b",
891 .total_flash_size
= 256 * 1024,
892 .total_sram_size
= 24 * 1024,
896 // System boots at address 0x0
897 // gpnvm[1] = selects boot code
899 // boot is via "SAMBA" (rom)
902 // Selection is via gpnvm[2]
905 // NOTE: banks 0 & 1 switch places
907 // Bank0 is the boot rom
909 // Bank1 is the boot rom
918 .base_address
= FLASH_BANK_BASE_N
,
919 .controller_address
= 0x400e0A00,
921 .size_bytes
= 256 * 1024,
923 .sector_size
= 16384,
937 .chipid_cidr
= 0x29340960,
938 .name
= "at91sam3n4a",
939 .total_flash_size
= 256 * 1024,
940 .total_sram_size
= 24 * 1024,
944 // System boots at address 0x0
945 // gpnvm[1] = selects boot code
947 // boot is via "SAMBA" (rom)
950 // Selection is via gpnvm[2]
953 // NOTE: banks 0 & 1 switch places
955 // Bank0 is the boot rom
957 // Bank1 is the boot rom
966 .base_address
= FLASH_BANK_BASE_N
,
967 .controller_address
= 0x400e0A00,
969 .size_bytes
= 256 * 1024,
971 .sector_size
= 16384,
985 .chipid_cidr
= 0x29590760,
986 .name
= "at91sam3n2c",
987 .total_flash_size
= 128 * 1024,
988 .total_sram_size
= 16 * 1024,
992 // System boots at address 0x0
993 // gpnvm[1] = selects boot code
995 // boot is via "SAMBA" (rom)
998 // Selection is via gpnvm[2]
1001 // NOTE: banks 0 & 1 switch places
1003 // Bank0 is the boot rom
1005 // Bank1 is the boot rom
1014 .base_address
= FLASH_BANK_BASE_N
,
1015 .controller_address
= 0x400e0A00,
1017 .size_bytes
= 128 * 1024,
1019 .sector_size
= 16384,
1033 .chipid_cidr
= 0x29490760,
1034 .name
= "at91sam3n2b",
1035 .total_flash_size
= 128 * 1024,
1036 .total_sram_size
= 16 * 1024,
1040 // System boots at address 0x0
1041 // gpnvm[1] = selects boot code
1043 // boot is via "SAMBA" (rom)
1045 // boot is via FLASH
1046 // Selection is via gpnvm[2]
1049 // NOTE: banks 0 & 1 switch places
1051 // Bank0 is the boot rom
1053 // Bank1 is the boot rom
1062 .base_address
= FLASH_BANK_BASE_N
,
1063 .controller_address
= 0x400e0A00,
1065 .size_bytes
= 128 * 1024,
1067 .sector_size
= 16384,
1081 .chipid_cidr
= 0x29390760,
1082 .name
= "at91sam3n2a",
1083 .total_flash_size
= 128 * 1024,
1084 .total_sram_size
= 16 * 1024,
1088 // System boots at address 0x0
1089 // gpnvm[1] = selects boot code
1091 // boot is via "SAMBA" (rom)
1093 // boot is via FLASH
1094 // Selection is via gpnvm[2]
1097 // NOTE: banks 0 & 1 switch places
1099 // Bank0 is the boot rom
1101 // Bank1 is the boot rom
1110 .base_address
= FLASH_BANK_BASE_N
,
1111 .controller_address
= 0x400e0A00,
1113 .size_bytes
= 128 * 1024,
1115 .sector_size
= 16384,
1129 .chipid_cidr
= 0x29580560,
1130 .name
= "at91sam3n1c",
1131 .total_flash_size
= 64 * 1024,
1132 .total_sram_size
= 8 * 1024,
1136 // System boots at address 0x0
1137 // gpnvm[1] = selects boot code
1139 // boot is via "SAMBA" (rom)
1141 // boot is via FLASH
1142 // Selection is via gpnvm[2]
1145 // NOTE: banks 0 & 1 switch places
1147 // Bank0 is the boot rom
1149 // Bank1 is the boot rom
1158 .base_address
= FLASH_BANK_BASE_N
,
1159 .controller_address
= 0x400e0A00,
1161 .size_bytes
= 64 * 1024,
1163 .sector_size
= 16384,
1177 .chipid_cidr
= 0x29480560,
1178 .name
= "at91sam3n1b",
1179 .total_flash_size
= 64 * 1024,
1180 .total_sram_size
= 8 * 1024,
1184 // System boots at address 0x0
1185 // gpnvm[1] = selects boot code
1187 // boot is via "SAMBA" (rom)
1189 // boot is via FLASH
1190 // Selection is via gpnvm[2]
1193 // NOTE: banks 0 & 1 switch places
1195 // Bank0 is the boot rom
1197 // Bank1 is the boot rom
1206 .base_address
= FLASH_BANK_BASE_N
,
1207 .controller_address
= 0x400e0A00,
1209 .size_bytes
= 64 * 1024,
1211 .sector_size
= 16384,
1225 .chipid_cidr
= 0x29380560,
1226 .name
= "at91sam3n1a",
1227 .total_flash_size
= 64 * 1024,
1228 .total_sram_size
= 8 * 1024,
1232 // System boots at address 0x0
1233 // gpnvm[1] = selects boot code
1235 // boot is via "SAMBA" (rom)
1237 // boot is via FLASH
1238 // Selection is via gpnvm[2]
1241 // NOTE: banks 0 & 1 switch places
1243 // Bank0 is the boot rom
1245 // Bank1 is the boot rom
1254 .base_address
= FLASH_BANK_BASE_N
,
1255 .controller_address
= 0x400e0A00,
1257 .size_bytes
= 64 * 1024,
1259 .sector_size
= 16384,
1280 /***********************************************************************
1281 **********************************************************************
1282 **********************************************************************
1283 **********************************************************************
1284 **********************************************************************
1285 **********************************************************************/
1286 /* *ATMEL* style code - from the SAM3 driver code */
1289 * Get the current status of the EEFC and
1290 * the value of some status bits (LOCKE, PROGE).
1291 * @param pPrivate - info about the bank
1292 * @param v - result goes here
1295 EFC_GetStatus(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
1298 r
= target_read_u32(pPrivate
->pChip
->target
, pPrivate
->controller_address
+ offset_EFC_FSR
, v
);
1299 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1301 ((unsigned int)((*v
>> 2) & 1)),
1302 ((unsigned int)((*v
>> 1) & 1)),
1303 ((unsigned int)((*v
>> 0) & 1)));
1309 * Get the result of the last executed command.
1310 * @param pPrivate - info about the bank
1311 * @param v - result goes here
1314 EFC_GetResult(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
1318 r
= target_read_u32(pPrivate
->pChip
->target
, pPrivate
->controller_address
+ offset_EFC_FRR
, &rv
);
1322 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv
)));
1327 EFC_StartCommand(struct sam3_bank_private
*pPrivate
,
1328 unsigned command
, unsigned argument
)
1337 // Check command & argument
1340 case AT91C_EFC_FCMD_WP
:
1341 case AT91C_EFC_FCMD_WPL
:
1342 case AT91C_EFC_FCMD_EWP
:
1343 case AT91C_EFC_FCMD_EWPL
:
1344 // case AT91C_EFC_FCMD_EPL:
1345 // case AT91C_EFC_FCMD_EPA:
1346 case AT91C_EFC_FCMD_SLB
:
1347 case AT91C_EFC_FCMD_CLB
:
1348 n
= (pPrivate
->size_bytes
/ pPrivate
->page_size
);
1349 if (argument
>= n
) {
1350 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n
));
1354 case AT91C_EFC_FCMD_SFB
:
1355 case AT91C_EFC_FCMD_CFB
:
1356 if (argument
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1357 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1358 pPrivate
->pChip
->details
.n_gpnvms
);
1362 case AT91C_EFC_FCMD_GETD
:
1363 case AT91C_EFC_FCMD_EA
:
1364 case AT91C_EFC_FCMD_GLB
:
1365 case AT91C_EFC_FCMD_GFB
:
1366 case AT91C_EFC_FCMD_STUI
:
1367 case AT91C_EFC_FCMD_SPUI
:
1368 if (argument
!= 0) {
1369 LOG_ERROR("Argument is meaningless for cmd: %d", command
);
1373 LOG_ERROR("Unknown command %d", command
);
1377 if (command
== AT91C_EFC_FCMD_SPUI
) {
1378 // this is a very special situation.
1379 // Situation (1) - error/retry - see below
1380 // And we are being called recursively
1381 // Situation (2) - normal, finished reading unique id
1383 // it should be "ready"
1384 EFC_GetStatus(pPrivate
, &v
);
1390 // we have done this before
1391 // the controller is not responding.
1392 LOG_ERROR("flash controller(%d) is not ready! Error", pPrivate
->bank_number
);
1396 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1397 pPrivate
->bank_number
);
1398 // we do that by issuing the *STOP* command
1399 EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0);
1400 // above is recursive, and further recursion is blocked by
1401 // if (command == AT91C_EFC_FCMD_SPUI) above
1407 v
= (0x5A << 24) | (argument
<< 8) | command
;
1408 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v
)));
1409 r
= target_write_u32(pPrivate
->pBank
->target
,
1410 pPrivate
->controller_address
+ offset_EFC_FCR
,
1412 if (r
!= ERROR_OK
) {
1413 LOG_DEBUG("Error Write failed");
1419 * Performs the given command and wait until its completion (or an error).
1420 * @param pPrivate - info about the bank
1421 * @param command - Command to perform.
1422 * @param argument - Optional command argument.
1423 * @param status - put command status bits here
1426 EFC_PerformCommand(struct sam3_bank_private
*pPrivate
,
1434 long long ms_now
, ms_end
;
1441 r
= EFC_StartCommand(pPrivate
, command
, argument
);
1442 if (r
!= ERROR_OK
) {
1446 ms_end
= 500 + timeval_ms();
1450 r
= EFC_GetStatus(pPrivate
, &v
);
1451 if (r
!= ERROR_OK
) {
1454 ms_now
= timeval_ms();
1455 if (ms_now
> ms_end
) {
1457 LOG_ERROR("Command timeout");
1461 while ((v
& 1) == 0)
1466 *status
= (v
& 0x6);
1477 * Read the unique ID.
1478 * @param pPrivate - info about the bank
1479 * The unique ID is stored in the 'pPrivate' structure.
1482 FLASHD_ReadUniqueID (struct sam3_bank_private
*pPrivate
)
1488 pPrivate
->pChip
->cfg
.unique_id
[0] = 0;
1489 pPrivate
->pChip
->cfg
.unique_id
[1] = 0;
1490 pPrivate
->pChip
->cfg
.unique_id
[2] = 0;
1491 pPrivate
->pChip
->cfg
.unique_id
[3] = 0;
1494 r
= EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_STUI
, 0);
1499 for (x
= 0 ; x
< 4 ; x
++) {
1500 r
= target_read_u32(pPrivate
->pChip
->target
,
1501 pPrivate
->pBank
->base
+ (x
* 4),
1506 pPrivate
->pChip
->cfg
.unique_id
[x
] = v
;
1509 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0, NULL
);
1510 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1512 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[0]),
1513 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[1]),
1514 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[2]),
1515 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[3]));
1521 * Erases the entire flash.
1522 * @param pPrivate - the info about the bank.
1525 FLASHD_EraseEntireBank(struct sam3_bank_private
*pPrivate
)
1528 return EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_EA
, 0, NULL
);
1534 * Gets current GPNVM state.
1535 * @param pPrivate - info about the bank.
1536 * @param gpnvm - GPNVM bit index.
1537 * @param puthere - result stored here.
1539 //------------------------------------------------------------------------------
1541 FLASHD_GetGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
, unsigned *puthere
)
1547 if (pPrivate
->bank_number
!= 0) {
1548 LOG_ERROR("GPNVM only works with Bank0");
1552 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1553 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1554 gpnvm
,pPrivate
->pChip
->details
.n_gpnvms
);
1558 // Get GPNVMs status
1559 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GFB
, 0, NULL
);
1560 if (r
!= ERROR_OK
) {
1561 LOG_ERROR("Failed");
1565 r
= EFC_GetResult(pPrivate
, &v
);
1568 // Check if GPNVM is set
1569 // get the bit and make it a 0/1
1570 *puthere
= (v
>> gpnvm
) & 1;
1580 * Clears the selected GPNVM bit.
1581 * @param pPrivate info about the bank
1582 * @param gpnvm GPNVM index.
1583 * @returns 0 if successful; otherwise returns an error code.
1586 FLASHD_ClrGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
)
1592 if (pPrivate
->bank_number
!= 0) {
1593 LOG_ERROR("GPNVM only works with Bank0");
1597 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1598 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1599 gpnvm
,pPrivate
->pChip
->details
.n_gpnvms
);
1603 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
1604 if (r
!= ERROR_OK
) {
1605 LOG_DEBUG("Failed: %d",r
);
1608 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CFB
, gpnvm
, NULL
);
1609 LOG_DEBUG("End: %d",r
);
1616 * Sets the selected GPNVM bit.
1617 * @param pPrivate info about the bank
1618 * @param gpnvm GPNVM index.
1621 FLASHD_SetGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
)
1626 if (pPrivate
->bank_number
!= 0) {
1627 LOG_ERROR("GPNVM only works with Bank0");
1631 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1632 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1633 gpnvm
,pPrivate
->pChip
->details
.n_gpnvms
);
1637 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
1638 if (r
!= ERROR_OK
) {
1646 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SFB
, gpnvm
, NULL
);
1653 * Returns a bit field (at most 64) of locked regions within a page.
1654 * @param pPrivate info about the bank
1655 * @param v where to store locked bits
1658 FLASHD_GetLockBits(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
1662 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GLB
, 0, NULL
);
1663 if (r
== ERROR_OK
) {
1664 r
= EFC_GetResult(pPrivate
, v
);
1666 LOG_DEBUG("End: %d",r
);
1672 * Unlocks all the regions in the given address range.
1673 * @param pPrivate info about the bank
1674 * @param start_sector first sector to unlock
1675 * @param end_sector last (inclusive) to unlock
1679 FLASHD_Unlock(struct sam3_bank_private
*pPrivate
,
1680 unsigned start_sector
,
1681 unsigned end_sector
)
1686 uint32_t pages_per_sector
;
1688 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
1690 /* Unlock all pages */
1691 while (start_sector
<= end_sector
) {
1692 pg
= start_sector
* pages_per_sector
;
1694 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CLB
, pg
, &status
);
1695 if (r
!= ERROR_OK
) {
1707 * @param pPrivate - info about the bank
1708 * @param start_sector - first sector to lock
1709 * @param end_sector - last sector (inclusive) to lock
1712 FLASHD_Lock(struct sam3_bank_private
*pPrivate
,
1713 unsigned start_sector
,
1714 unsigned end_sector
)
1718 uint32_t pages_per_sector
;
1721 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
1723 /* Lock all pages */
1724 while (start_sector
<= end_sector
) {
1725 pg
= start_sector
* pages_per_sector
;
1727 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SLB
, pg
, &status
);
1728 if (r
!= ERROR_OK
) {
1737 /****** END SAM3 CODE ********/
1739 /* begin helpful debug code */
1740 // print the fieldname, the field value, in dec & hex, and return field value
1742 sam3_reg_fieldname(struct sam3_chip
*pChip
,
1743 const char *regname
,
1752 // extract the field
1754 v
= v
& ((1 << width
)-1);
1764 LOG_USER_N("\t%*s: %*d [0x%0*x] ",
1765 REG_NAME_WIDTH
, regname
,
1772 static const char _unknown
[] = "unknown";
1773 static const char * const eproc_names
[] = {
1792 #define nvpsize2 nvpsize // these two tables are identical
1793 static const char * const nvpsize
[] = {
1806 "1024K bytes", // 12
1808 "2048K bytes", // 14
1813 static const char * const sramsize
[] = {
1833 static const struct archnames
{ unsigned value
; const char *name
; } archnames
[] = {
1834 { 0x19, "AT91SAM9xx Series" },
1835 { 0x29, "AT91SAM9XExx Series" },
1836 { 0x34, "AT91x34 Series" },
1837 { 0x37, "CAP7 Series" },
1838 { 0x39, "CAP9 Series" },
1839 { 0x3B, "CAP11 Series" },
1840 { 0x40, "AT91x40 Series" },
1841 { 0x42, "AT91x42 Series" },
1842 { 0x55, "AT91x55 Series" },
1843 { 0x60, "AT91SAM7Axx Series" },
1844 { 0x61, "AT91SAM7AQxx Series" },
1845 { 0x63, "AT91x63 Series" },
1846 { 0x70, "AT91SAM7Sxx Series" },
1847 { 0x71, "AT91SAM7XCxx Series" },
1848 { 0x72, "AT91SAM7SExx Series" },
1849 { 0x73, "AT91SAM7Lxx Series" },
1850 { 0x75, "AT91SAM7Xxx Series" },
1851 { 0x76, "AT91SAM7SLxx Series" },
1852 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1853 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1854 { 0x83, "ATSAM3AxC Series (100-pin version)" },
1855 { 0x84, "ATSAM3XxC Series (100-pin version)" },
1856 { 0x85, "ATSAM3XxE Series (144-pin version)" },
1857 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
1858 { 0x88, "ATSAM3SxA Series (48-pin version)" },
1859 { 0x89, "ATSAM3SxB Series (64-pin version)" },
1860 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
1861 { 0x92, "AT91x92 Series" },
1862 { 0xF0, "AT75Cxx Series" },
1867 static const char * const nvptype
[] = {
1869 "romless or onchip flash", // 1
1870 "embedded flash memory", // 2
1871 "rom(nvpsiz) + embedded flash (nvpsiz2)", //3
1872 "sram emulating flash", // 4
1879 static const char *_yes_or_no(uint32_t v
)
1888 static const char * const _rc_freq
[] = {
1889 "4 MHz", "8 MHz", "12 MHz", "reserved"
1893 sam3_explain_ckgr_mor(struct sam3_chip
*pChip
)
1898 v
= sam3_reg_fieldname(pChip
, "MOSCXTEN", pChip
->cfg
.CKGR_MOR
, 0, 1);
1899 LOG_USER("(main xtal enabled: %s)",
1901 v
= sam3_reg_fieldname(pChip
, "MOSCXTBY", pChip
->cfg
.CKGR_MOR
, 1, 1);
1902 LOG_USER("(main osc bypass: %s)",
1904 rcen
= sam3_reg_fieldname(pChip
, "MOSCRCEN", pChip
->cfg
.CKGR_MOR
, 3, 1);
1905 LOG_USER("(onchip RC-OSC enabled: %s)",
1907 v
= sam3_reg_fieldname(pChip
, "MOSCRCF", pChip
->cfg
.CKGR_MOR
, 4, 3);
1908 LOG_USER("(onchip RC-OSC freq: %s)",
1911 pChip
->cfg
.rc_freq
= 0;
1915 pChip
->cfg
.rc_freq
= 0;
1918 pChip
->cfg
.rc_freq
= 4 * 1000 * 1000;
1921 pChip
->cfg
.rc_freq
= 8 * 1000 * 1000;
1924 pChip
->cfg
.rc_freq
= 12* 1000 * 1000;
1929 v
= sam3_reg_fieldname(pChip
,"MOSCXTST", pChip
->cfg
.CKGR_MOR
, 8, 8);
1930 LOG_USER("(startup clks, time= %f uSecs)",
1931 ((float)(v
* 1000000)) / ((float)(pChip
->cfg
.slow_freq
)));
1932 v
= sam3_reg_fieldname(pChip
, "MOSCSEL", pChip
->cfg
.CKGR_MOR
, 24, 1);
1933 LOG_USER("(mainosc source: %s)",
1934 v
? "external xtal" : "internal RC");
1936 v
= sam3_reg_fieldname(pChip
,"CFDEN", pChip
->cfg
.CKGR_MOR
, 25, 1);
1937 LOG_USER("(clock failure enabled: %s)",
1944 sam3_explain_chipid_cidr(struct sam3_chip
*pChip
)
1950 sam3_reg_fieldname(pChip
, "Version", pChip
->cfg
.CHIPID_CIDR
, 0, 5);
1953 v
= sam3_reg_fieldname(pChip
, "EPROC", pChip
->cfg
.CHIPID_CIDR
, 5, 3);
1954 LOG_USER("%s", eproc_names
[v
]);
1956 v
= sam3_reg_fieldname(pChip
, "NVPSIZE", pChip
->cfg
.CHIPID_CIDR
, 8, 4);
1957 LOG_USER("%s", nvpsize
[v
]);
1959 v
= sam3_reg_fieldname(pChip
, "NVPSIZE2", pChip
->cfg
.CHIPID_CIDR
, 12, 4);
1960 LOG_USER("%s", nvpsize2
[v
]);
1962 v
= sam3_reg_fieldname(pChip
, "SRAMSIZE", pChip
->cfg
.CHIPID_CIDR
, 16,4);
1963 LOG_USER("%s", sramsize
[ v
]);
1965 v
= sam3_reg_fieldname(pChip
, "ARCH", pChip
->cfg
.CHIPID_CIDR
, 20, 8);
1967 for (x
= 0 ; archnames
[x
].name
; x
++) {
1968 if (v
== archnames
[x
].value
) {
1969 cp
= archnames
[x
].name
;
1976 v
= sam3_reg_fieldname(pChip
, "NVPTYP", pChip
->cfg
.CHIPID_CIDR
, 28, 3);
1977 LOG_USER("%s", nvptype
[ v
]);
1979 v
= sam3_reg_fieldname(pChip
, "EXTID", pChip
->cfg
.CHIPID_CIDR
, 31, 1);
1980 LOG_USER("(exists: %s)", _yes_or_no(v
));
1984 sam3_explain_ckgr_mcfr(struct sam3_chip
*pChip
)
1989 v
= sam3_reg_fieldname(pChip
, "MAINFRDY", pChip
->cfg
.CKGR_MCFR
, 16, 1);
1990 LOG_USER("(main ready: %s)", _yes_or_no(v
));
1992 v
= sam3_reg_fieldname(pChip
, "MAINF", pChip
->cfg
.CKGR_MCFR
, 0, 16);
1994 v
= (v
* pChip
->cfg
.slow_freq
) / 16;
1995 pChip
->cfg
.mainosc_freq
= v
;
1997 LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
1999 pChip
->cfg
.slow_freq
/ 1000,
2000 pChip
->cfg
.slow_freq
% 1000);
2005 sam3_explain_ckgr_plla(struct sam3_chip
*pChip
)
2009 diva
= sam3_reg_fieldname(pChip
, "DIVA", pChip
->cfg
.CKGR_PLLAR
, 0, 8);
2011 mula
= sam3_reg_fieldname(pChip
, "MULA", pChip
->cfg
.CKGR_PLLAR
, 16, 11);
2013 pChip
->cfg
.plla_freq
= 0;
2015 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2016 } else if (diva
== 0) {
2017 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2018 } else if (diva
== 1) {
2019 pChip
->cfg
.plla_freq
= (pChip
->cfg
.mainosc_freq
* (mula
+ 1));
2020 LOG_USER("\tPLLA Freq: %3.03f MHz",
2021 _tomhz(pChip
->cfg
.plla_freq
));
2027 sam3_explain_mckr(struct sam3_chip
*pChip
)
2029 uint32_t css
, pres
, fin
= 0;
2031 const char *cp
= NULL
;
2033 css
= sam3_reg_fieldname(pChip
, "CSS", pChip
->cfg
.PMC_MCKR
, 0, 2);
2036 fin
= pChip
->cfg
.slow_freq
;
2040 fin
= pChip
->cfg
.mainosc_freq
;
2044 fin
= pChip
->cfg
.plla_freq
;
2048 if (pChip
->cfg
.CKGR_UCKR
& (1 << 16)) {
2049 fin
= 480 * 1000 * 1000;
2053 cp
= "upll (*ERROR* UPLL is disabled)";
2061 LOG_USER("%s (%3.03f Mhz)",
2064 pres
= sam3_reg_fieldname(pChip
, "PRES", pChip
->cfg
.PMC_MCKR
, 4, 3);
2065 switch (pres
& 0x07) {
2068 cp
= "selected clock";
2102 LOG_USER("(%s)", cp
);
2104 // sam3 has a *SINGLE* clock -
2105 // other at91 series parts have divisors for these.
2106 pChip
->cfg
.cpu_freq
= fin
;
2107 pChip
->cfg
.mclk_freq
= fin
;
2108 pChip
->cfg
.fclk_freq
= fin
;
2109 LOG_USER("\t\tResult CPU Freq: %3.03f",
2114 static struct sam3_chip
*
2115 target2sam3(struct target
*pTarget
)
2117 struct sam3_chip
*pChip
;
2119 if (pTarget
== NULL
) {
2123 pChip
= all_sam3_chips
;
2125 if (pChip
->target
== pTarget
) {
2126 break; // return below
2128 pChip
= pChip
->next
;
2136 sam3_get_reg_ptr(struct sam3_cfg
*pCfg
, const struct sam3_reg_list
*pList
)
2138 // this function exists to help
2139 // keep funky offsetof() errors
2140 // and casting from causing bugs
2142 // By using prototypes - we can detect what would
2143 // be casting errors.
2145 return ((uint32_t *)(void *)(((char *)(pCfg
)) + pList
->struct_offset
));
2149 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof(struct sam3_cfg, NAME), #NAME, FUNC }
2150 static const struct sam3_reg_list sam3_all_regs
[] = {
2151 SAM3_ENTRY(CKGR_MOR
, sam3_explain_ckgr_mor
),
2152 SAM3_ENTRY(CKGR_MCFR
, sam3_explain_ckgr_mcfr
),
2153 SAM3_ENTRY(CKGR_PLLAR
, sam3_explain_ckgr_plla
),
2154 SAM3_ENTRY(CKGR_UCKR
, NULL
),
2155 SAM3_ENTRY(PMC_FSMR
, NULL
),
2156 SAM3_ENTRY(PMC_FSPR
, NULL
),
2157 SAM3_ENTRY(PMC_IMR
, NULL
),
2158 SAM3_ENTRY(PMC_MCKR
, sam3_explain_mckr
),
2159 SAM3_ENTRY(PMC_PCK0
, NULL
),
2160 SAM3_ENTRY(PMC_PCK1
, NULL
),
2161 SAM3_ENTRY(PMC_PCK2
, NULL
),
2162 SAM3_ENTRY(PMC_PCSR
, NULL
),
2163 SAM3_ENTRY(PMC_SCSR
, NULL
),
2164 SAM3_ENTRY(PMC_SR
, NULL
),
2165 SAM3_ENTRY(CHIPID_CIDR
, sam3_explain_chipid_cidr
),
2166 SAM3_ENTRY(CHIPID_EXID
, NULL
),
2167 SAM3_ENTRY(SUPC_CR
, NULL
),
2169 // TERMINATE THE LIST
2177 static struct sam3_bank_private
*
2178 get_sam3_bank_private(struct flash_bank
*bank
)
2180 return (struct sam3_bank_private
*)(bank
->driver_priv
);
2184 * Given a pointer to where it goes in the structure,
2185 * determine the register name, address from the all registers table.
2187 static const struct sam3_reg_list
*
2188 sam3_GetReg(struct sam3_chip
*pChip
, uint32_t *goes_here
)
2190 const struct sam3_reg_list
*pReg
;
2192 pReg
= &(sam3_all_regs
[0]);
2193 while (pReg
->name
) {
2194 uint32_t *pPossible
;
2196 // calculate where this one go..
2197 // it is "possibly" this register.
2199 pPossible
= ((uint32_t *)(void *)(((char *)(&(pChip
->cfg
))) + pReg
->struct_offset
));
2201 // well? Is it this register
2202 if (pPossible
== goes_here
) {
2210 // This is *TOTAL*PANIC* - we are totally screwed.
2211 LOG_ERROR("INVALID SAM3 REGISTER");
2217 sam3_ReadThisReg(struct sam3_chip
*pChip
, uint32_t *goes_here
)
2219 const struct sam3_reg_list
*pReg
;
2222 pReg
= sam3_GetReg(pChip
, goes_here
);
2227 r
= target_read_u32(pChip
->target
, pReg
->address
, goes_here
);
2228 if (r
!= ERROR_OK
) {
2229 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
2230 pReg
->name
, (unsigned)(pReg
->address
), r
);
2238 sam3_ReadAllRegs(struct sam3_chip
*pChip
)
2241 const struct sam3_reg_list
*pReg
;
2243 pReg
= &(sam3_all_regs
[0]);
2244 while (pReg
->name
) {
2245 r
= sam3_ReadThisReg(pChip
,
2246 sam3_get_reg_ptr(&(pChip
->cfg
), pReg
));
2247 if (r
!= ERROR_OK
) {
2248 LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d",
2249 pReg
->name
, ((unsigned)(pReg
->address
)), r
);
2261 sam3_GetInfo(struct sam3_chip
*pChip
)
2263 const struct sam3_reg_list
*pReg
;
2266 pReg
= &(sam3_all_regs
[0]);
2267 while (pReg
->name
) {
2269 LOG_DEBUG("Start: %s", pReg
->name
);
2270 regval
= *sam3_get_reg_ptr(&(pChip
->cfg
), pReg
);
2271 LOG_USER("%*s: [0x%08x] -> 0x%08x",
2276 if (pReg
->explain_func
) {
2277 (*(pReg
->explain_func
))(pChip
);
2279 LOG_DEBUG("End: %s", pReg
->name
);
2282 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip
->cfg
.rc_freq
));
2283 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip
->cfg
.mainosc_freq
));
2284 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip
->cfg
.plla_freq
));
2285 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip
->cfg
.cpu_freq
));
2286 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip
->cfg
.mclk_freq
));
2289 LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
2290 pChip
->cfg
.unique_id
[0],
2291 pChip
->cfg
.unique_id
[1],
2292 pChip
->cfg
.unique_id
[2],
2293 pChip
->cfg
.unique_id
[3]);
2301 sam3_erase_check(struct flash_bank
*bank
)
2306 if (bank
->target
->state
!= TARGET_HALTED
) {
2307 LOG_ERROR("Target not halted");
2308 return ERROR_TARGET_NOT_HALTED
;
2310 if (0 == bank
->num_sectors
) {
2311 LOG_ERROR("Target: not supported/not probed");
2315 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
2316 for (x
= 0 ; x
< bank
->num_sectors
; x
++) {
2317 bank
->sectors
[x
].is_erased
= 1;
2325 sam3_protect_check(struct flash_bank
*bank
)
2330 struct sam3_bank_private
*pPrivate
;
2333 if (bank
->target
->state
!= TARGET_HALTED
) {
2334 LOG_ERROR("Target not halted");
2335 return ERROR_TARGET_NOT_HALTED
;
2338 pPrivate
= get_sam3_bank_private(bank
);
2340 LOG_ERROR("no private for this bank?");
2343 if (!(pPrivate
->probed
)) {
2344 return ERROR_FLASH_BANK_NOT_PROBED
;
2347 r
= FLASHD_GetLockBits(pPrivate
, &v
);
2348 if (r
!= ERROR_OK
) {
2349 LOG_DEBUG("Failed: %d",r
);
2353 for (x
= 0 ; x
< pPrivate
->nsectors
; x
++) {
2354 bank
->sectors
[x
].is_protected
= (!!(v
& (1 << x
)));
2360 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command
)
2362 struct sam3_chip
*pChip
;
2364 pChip
= all_sam3_chips
;
2366 // is this an existing chip?
2368 if (pChip
->target
== bank
->target
) {
2371 pChip
= pChip
->next
;
2375 // this is a *NEW* chip
2376 pChip
= calloc(1, sizeof(struct sam3_chip
));
2378 LOG_ERROR("NO RAM!");
2381 pChip
->target
= bank
->target
;
2383 pChip
->next
= all_sam3_chips
;
2384 all_sam3_chips
= pChip
;
2385 pChip
->target
= bank
->target
;
2386 // assumption is this runs at 32khz
2387 pChip
->cfg
.slow_freq
= 32768;
2391 switch (bank
->base
) {
2393 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x \
2394 [at91sam3u series] or 0x%08x [at91sam3s series])",
2395 ((unsigned int)(bank
->base
)),
2396 ((unsigned int)(FLASH_BANK0_BASE_U
)),
2397 ((unsigned int)(FLASH_BANK1_BASE_U
)),
2398 ((unsigned int)(FLASH_BANK_BASE_S
)));
2403 case FLASH_BANK0_BASE_U
:
2404 bank
->driver_priv
= &(pChip
->details
.bank
[0]);
2405 bank
->bank_number
= 0;
2406 pChip
->details
.bank
[0].pChip
= pChip
;
2407 pChip
->details
.bank
[0].pBank
= bank
;
2409 case FLASH_BANK1_BASE_U
:
2410 bank
->driver_priv
= &(pChip
->details
.bank
[1]);
2411 bank
->bank_number
= 1;
2412 pChip
->details
.bank
[1].pChip
= pChip
;
2413 pChip
->details
.bank
[1].pBank
= bank
;
2417 case FLASH_BANK_BASE_S
:
2418 bank
->driver_priv
= &(pChip
->details
.bank
[0]);
2419 bank
->bank_number
= 0;
2420 pChip
->details
.bank
[0].pChip
= pChip
;
2421 pChip
->details
.bank
[0].pBank
= bank
;
2425 // we initialize after probing.
2430 sam3_GetDetails(struct sam3_bank_private
*pPrivate
)
2432 const struct sam3_chip_details
*pDetails
;
2433 struct sam3_chip
*pChip
;
2434 struct flash_bank
*saved_banks
[SAM3_MAX_FLASH_BANKS
];
2438 pDetails
= all_sam3_details
;
2439 while (pDetails
->name
) {
2440 // Compare cidr without version bits
2441 if (pDetails
->chipid_cidr
== (pPrivate
->pChip
->cfg
.CHIPID_CIDR
& 0xFFFFFFE0)) {
2447 if (pDetails
->name
== NULL
) {
2448 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)",
2449 (unsigned int)(pPrivate
->pChip
->cfg
.CHIPID_CIDR
));
2450 // Help the victim, print details about the chip
2451 LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows",
2452 pPrivate
->pChip
->cfg
.CHIPID_CIDR
);
2453 sam3_explain_chipid_cidr(pPrivate
->pChip
);
2457 // DANGER: THERE ARE DRAGONS HERE
2459 // get our pChip - it is going
2460 // to be over-written shortly
2461 pChip
= pPrivate
->pChip
;
2463 // Note that, in reality:
2465 // pPrivate = &(pChip->details.bank[0])
2466 // or pPrivate = &(pChip->details.bank[1])
2469 // save the "bank" pointers
2470 for (x
= 0 ; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
2471 saved_banks
[ x
] = pChip
->details
.bank
[x
].pBank
;
2474 // Overwrite the "details" structure.
2475 memcpy(&(pPrivate
->pChip
->details
),
2477 sizeof(pPrivate
->pChip
->details
));
2479 // now fix the ghosted pointers
2480 for (x
= 0 ; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
2481 pChip
->details
.bank
[x
].pChip
= pChip
;
2482 pChip
->details
.bank
[x
].pBank
= saved_banks
[x
];
2485 // update the *BANK*SIZE*
2494 _sam3_probe(struct flash_bank
*bank
, int noise
)
2498 struct sam3_bank_private
*pPrivate
;
2501 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank
->bank_number
, noise
);
2502 if (bank
->target
->state
!= TARGET_HALTED
)
2504 LOG_ERROR("Target not halted");
2505 return ERROR_TARGET_NOT_HALTED
;
2508 pPrivate
= get_sam3_bank_private(bank
);
2510 LOG_ERROR("Invalid/unknown bank number");
2514 r
= sam3_ReadAllRegs(pPrivate
->pChip
);
2515 if (r
!= ERROR_OK
) {
2521 if (pPrivate
->pChip
->probed
) {
2522 r
= sam3_GetInfo(pPrivate
->pChip
);
2524 r
= sam3_GetDetails(pPrivate
);
2526 if (r
!= ERROR_OK
) {
2530 // update the flash bank size
2531 for (x
= 0 ; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
2532 if (bank
->base
== pPrivate
->pChip
->details
.bank
[x
].base_address
) {
2533 bank
->size
= pPrivate
->pChip
->details
.bank
[x
].size_bytes
;
2538 if (bank
->sectors
== NULL
) {
2539 bank
->sectors
= calloc(pPrivate
->nsectors
, (sizeof((bank
->sectors
)[0])));
2540 if (bank
->sectors
== NULL
) {
2541 LOG_ERROR("No memory!");
2544 bank
->num_sectors
= pPrivate
->nsectors
;
2546 for (x
= 0 ; ((int)(x
)) < bank
->num_sectors
; x
++) {
2547 bank
->sectors
[x
].size
= pPrivate
->sector_size
;
2548 bank
->sectors
[x
].offset
= x
* (pPrivate
->sector_size
);
2550 bank
->sectors
[x
].is_erased
= -1;
2551 bank
->sectors
[x
].is_protected
= -1;
2555 pPrivate
->probed
= 1;
2557 r
= sam3_protect_check(bank
);
2558 if (r
!= ERROR_OK
) {
2562 LOG_DEBUG("Bank = %d, nbanks = %d",
2563 pPrivate
->bank_number
, pPrivate
->pChip
->details
.n_banks
);
2564 if ((pPrivate
->bank_number
+ 1) == pPrivate
->pChip
->details
.n_banks
) {
2566 // it appears to be associated with the *last* flash bank.
2567 FLASHD_ReadUniqueID(pPrivate
);
2574 sam3_probe(struct flash_bank
*bank
)
2576 return _sam3_probe(bank
, 1);
2580 sam3_auto_probe(struct flash_bank
*bank
)
2582 return _sam3_probe(bank
, 0);
2588 sam3_erase(struct flash_bank
*bank
, int first
, int last
)
2590 struct sam3_bank_private
*pPrivate
;
2594 if (bank
->target
->state
!= TARGET_HALTED
) {
2595 LOG_ERROR("Target not halted");
2596 return ERROR_TARGET_NOT_HALTED
;
2599 r
= sam3_auto_probe(bank
);
2600 if (r
!= ERROR_OK
) {
2601 LOG_DEBUG("Here,r=%d",r
);
2605 pPrivate
= get_sam3_bank_private(bank
);
2606 if (!(pPrivate
->probed
)) {
2607 return ERROR_FLASH_BANK_NOT_PROBED
;
2610 if ((first
== 0) && ((last
+ 1)== ((int)(pPrivate
->nsectors
)))) {
2613 return FLASHD_EraseEntireBank(pPrivate
);
2615 LOG_INFO("sam3 auto-erases while programing (request ignored)");
2620 sam3_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
2622 struct sam3_bank_private
*pPrivate
;
2626 if (bank
->target
->state
!= TARGET_HALTED
) {
2627 LOG_ERROR("Target not halted");
2628 return ERROR_TARGET_NOT_HALTED
;
2631 pPrivate
= get_sam3_bank_private(bank
);
2632 if (!(pPrivate
->probed
)) {
2633 return ERROR_FLASH_BANK_NOT_PROBED
;
2637 r
= FLASHD_Lock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
2639 r
= FLASHD_Unlock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
2641 LOG_DEBUG("End: r=%d",r
);
2649 sam3_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
2651 if (bank
->target
->state
!= TARGET_HALTED
) {
2652 LOG_ERROR("Target not halted");
2653 return ERROR_TARGET_NOT_HALTED
;
2660 sam3_page_read(struct sam3_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
2665 adr
= pagenum
* pPrivate
->page_size
;
2666 adr
+= adr
+ pPrivate
->base_address
;
2668 r
= target_read_memory(pPrivate
->pChip
->target
,
2670 4, /* THIS*MUST*BE* in 32bit values */
2671 pPrivate
->page_size
/ 4,
2673 if (r
!= ERROR_OK
) {
2674 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x", (unsigned int)(adr
));
2679 // The code below is basically this:
2681 // arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s
2683 // Only the *CPU* can write to the flash buffer.
2684 // the DAP cannot... so - we download this 28byte thing
2685 // Run the algorithm - (below)
2686 // to program the device
2688 // ========================================
2689 // #include <stdint.h>
2693 // const uint32_t *src;
2695 // volatile uint32_t *base;
2700 // uint32_t sam3_function(struct foo *p)
2702 // volatile uint32_t *v;
2704 // const uint32_t *s;
2726 // ========================================
2730 static const uint8_t
2731 sam3_page_write_opcodes
[] = {
2732 // 24 0000 0446 mov r4, r0
2734 // 25 0002 6168 ldr r1, [r4, #4]
2736 // 26 0004 0068 ldr r0, [r0, #0]
2738 // 27 0006 A268 ldr r2, [r4, #8]
2740 // 28 @ lr needed for prologue
2742 // 30 0008 51F8043B ldr r3, [r1], #4
2743 0x51,0xf8,0x04,0x3b,
2744 // 31 000c 12F1FF32 adds r2, r2, #-1
2745 0x12,0xf1,0xff,0x32,
2746 // 32 0010 40F8043B str r3, [r0], #4
2747 0x40,0xf8,0x04,0x3b,
2748 // 33 0014 F8D1 bne .L2
2750 // 34 0016 E268 ldr r2, [r4, #12]
2752 // 35 0018 2369 ldr r3, [r4, #16]
2754 // 36 001a 5360 str r3, [r2, #4]
2756 // 37 001c 0832 adds r2, r2, #8
2759 // 39 001e 1068 ldr r0, [r2, #0]
2761 // 40 0020 10F0010F tst r0, #1
2762 0x10,0xf0,0x01,0x0f,
2763 // 41 0024 FBD0 beq .L4
2765 0x00,0xBE /* bkpt #0 */
2770 sam3_page_write(struct sam3_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
2776 adr
= pagenum
* pPrivate
->page_size
;
2777 adr
+= (adr
+ pPrivate
->base_address
);
2779 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum
, (unsigned int)(adr
));
2780 r
= target_write_memory(pPrivate
->pChip
->target
,
2782 4, /* THIS*MUST*BE* in 32bit values */
2783 pPrivate
->page_size
/ 4,
2785 if (r
!= ERROR_OK
) {
2786 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x", (unsigned int)(adr
));
2790 r
= EFC_PerformCommand(pPrivate
,
2791 // send Erase & Write Page
2796 if (r
!= ERROR_OK
) {
2797 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x", (unsigned int)(adr
));
2799 if (status
& (1 << 2)) {
2800 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr
));
2803 if (status
& (1 << 1)) {
2804 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr
));
2815 sam3_write(struct flash_bank
*bank
,
2824 unsigned page_offset
;
2825 struct sam3_bank_private
*pPrivate
;
2826 uint8_t *pagebuffer
;
2828 // incase we bail further below, set this to null
2831 // ignore dumb requests
2837 if (bank
->target
->state
!= TARGET_HALTED
) {
2838 LOG_ERROR("Target not halted");
2839 r
= ERROR_TARGET_NOT_HALTED
;
2843 pPrivate
= get_sam3_bank_private(bank
);
2844 if (!(pPrivate
->probed
)) {
2845 r
= ERROR_FLASH_BANK_NOT_PROBED
;
2850 if ((offset
+ count
) > pPrivate
->size_bytes
) {
2851 LOG_ERROR("Flash write error - past end of bank");
2852 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2853 (unsigned int)(offset
),
2854 (unsigned int)(count
),
2855 (unsigned int)(pPrivate
->size_bytes
));
2860 pagebuffer
= malloc(pPrivate
->page_size
);
2862 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate
->page_size
));
2867 // what page do we start & end in?
2868 page_cur
= offset
/ pPrivate
->page_size
;
2869 page_end
= (offset
+ count
- 1) / pPrivate
->page_size
;
2871 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset
), (unsigned int)(count
));
2872 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur
), (int)(page_end
));
2874 // Special case: all one page
2877 // (1) non-aligned start
2879 // (3) non-aligned end.
2881 // Handle special case - all one page.
2882 if (page_cur
== page_end
) {
2883 LOG_DEBUG("Special case, all in one page");
2884 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
2885 if (r
!= ERROR_OK
) {
2889 page_offset
= (offset
& (pPrivate
->page_size
-1));
2890 memcpy(pagebuffer
+ page_offset
,
2894 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
2895 if (r
!= ERROR_OK
) {
2902 // non-aligned start
2903 page_offset
= offset
& (pPrivate
->page_size
- 1);
2905 LOG_DEBUG("Not-Aligned start");
2907 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
2908 if (r
!= ERROR_OK
) {
2912 // over-write with new data
2913 n
= (pPrivate
->page_size
- page_offset
);
2914 memcpy(pagebuffer
+ page_offset
,
2918 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
2919 if (r
!= ERROR_OK
) {
2929 // intermediate large pages
2930 // also - the final *terminal*
2931 // if that terminal page is a full page
2932 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2933 (int)page_cur
, (int)page_end
, (unsigned int)(count
));
2935 while ((page_cur
< page_end
) &&
2936 (count
>= pPrivate
->page_size
)) {
2937 r
= sam3_page_write(pPrivate
, page_cur
, buffer
);
2938 if (r
!= ERROR_OK
) {
2941 count
-= pPrivate
->page_size
;
2942 buffer
+= pPrivate
->page_size
;
2946 // terminal partial page?
2948 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count
));
2949 // we have a partial page
2950 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
2951 if (r
!= ERROR_OK
) {
2954 // data goes at start
2955 memcpy(pagebuffer
, buffer
, count
);
2956 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
2957 if (r
!= ERROR_OK
) {
2972 COMMAND_HANDLER(sam3_handle_info_command
)
2974 struct sam3_chip
*pChip
;
2978 pChip
= get_current_sam3(CMD_CTX
);
2985 // bank0 must exist before we can do anything
2986 if (pChip
->details
.bank
[0].pBank
== NULL
) {
2989 command_print(CMD_CTX
,
2990 "Please define bank %d via command: flash bank %s ... ",
2992 at91sam3_flash
.name
);
2996 // if bank 0 is not probed, then probe it
2997 if (!(pChip
->details
.bank
[0].probed
)) {
2998 r
= sam3_auto_probe(pChip
->details
.bank
[0].pBank
);
2999 if (r
!= ERROR_OK
) {
3003 // above guarantees the "chip details" structure is valid
3004 // and thus, bank private areas are valid
3005 // and we have a SAM3 chip, what a concept!
3008 // auto-probe other banks, 0 done above
3009 for (x
= 1 ; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
3010 // skip banks not present
3011 if (!(pChip
->details
.bank
[x
].present
)) {
3015 if (pChip
->details
.bank
[x
].pBank
== NULL
) {
3019 if (pChip
->details
.bank
[x
].probed
) {
3023 r
= sam3_auto_probe(pChip
->details
.bank
[x
].pBank
);
3024 if (r
!= ERROR_OK
) {
3030 r
= sam3_GetInfo(pChip
);
3031 if (r
!= ERROR_OK
) {
3032 LOG_DEBUG("Sam3Info, Failed %d",r
);
3039 COMMAND_HANDLER(sam3_handle_gpnvm_command
)
3043 struct sam3_chip
*pChip
;
3045 pChip
= get_current_sam3(CMD_CTX
);
3050 if (pChip
->target
->state
!= TARGET_HALTED
) {
3051 LOG_ERROR("sam3 - target not halted");
3052 return ERROR_TARGET_NOT_HALTED
;
3056 if (pChip
->details
.bank
[0].pBank
== NULL
) {
3057 command_print(CMD_CTX
, "Bank0 must be defined first via: flash bank %s ...",
3058 at91sam3_flash
.name
);
3061 if (!pChip
->details
.bank
[0].probed
) {
3062 r
= sam3_auto_probe(pChip
->details
.bank
[0].pBank
);
3063 if (r
!= ERROR_OK
) {
3071 command_print(CMD_CTX
,"Too many parameters\n");
3072 return ERROR_COMMAND_SYNTAX_ERROR
;
3082 if ((0 == strcmp(CMD_ARGV
[0], "show")) && (0 == strcmp(CMD_ARGV
[1], "all"))) {
3086 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], v32
);
3092 if (0 == strcmp("show", CMD_ARGV
[0])) {
3096 for (x
= 0 ; x
< pChip
->details
.n_gpnvms
; x
++) {
3097 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), x
, &v
);
3098 if (r
!= ERROR_OK
) {
3101 command_print(CMD_CTX
, "sam3-gpnvm%u: %u", x
, v
);
3105 if ((who
>= 0) && (((unsigned)(who
)) < pChip
->details
.n_gpnvms
)) {
3106 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), who
, &v
);
3107 command_print(CMD_CTX
, "sam3-gpnvm%u: %u", who
, v
);
3110 command_print(CMD_CTX
, "sam3-gpnvm invalid GPNVM: %u", who
);
3111 return ERROR_COMMAND_SYNTAX_ERROR
;
3116 command_print(CMD_CTX
, "Missing GPNVM number");
3117 return ERROR_COMMAND_SYNTAX_ERROR
;
3120 if (0 == strcmp("set", CMD_ARGV
[0])) {
3121 r
= FLASHD_SetGPNVM(&(pChip
->details
.bank
[0]), who
);
3122 } else if ((0 == strcmp("clr", CMD_ARGV
[0])) ||
3123 (0 == strcmp("clear", CMD_ARGV
[0]))) { // quietly accept both
3124 r
= FLASHD_ClrGPNVM(&(pChip
->details
.bank
[0]), who
);
3126 command_print(CMD_CTX
, "Unknown command: %s", CMD_ARGV
[0]);
3127 r
= ERROR_COMMAND_SYNTAX_ERROR
;
3132 COMMAND_HANDLER(sam3_handle_slowclk_command
)
3134 struct sam3_chip
*pChip
;
3136 pChip
= get_current_sam3(CMD_CTX
);
3150 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], v
);
3152 // absurd slow clock of 200Khz?
3153 command_print(CMD_CTX
,"Absurd/illegal slow clock freq: %d\n", (int)(v
));
3154 return ERROR_COMMAND_SYNTAX_ERROR
;
3156 pChip
->cfg
.slow_freq
= v
;
3161 command_print(CMD_CTX
,"Too many parameters");
3162 return ERROR_COMMAND_SYNTAX_ERROR
;
3165 command_print(CMD_CTX
, "Slowclk freq: %d.%03dkhz",
3166 (int)(pChip
->cfg
.slow_freq
/ 1000),
3167 (int)(pChip
->cfg
.slow_freq
% 1000));
3171 static const struct command_registration at91sam3_exec_command_handlers
[] = {
3174 .handler
= sam3_handle_gpnvm_command
,
3175 .mode
= COMMAND_EXEC
,
3176 .usage
= "[('clr'|'set'|'show') bitnum]",
3177 .help
= "Without arguments, shows all bits in the gpnvm "
3178 "register. Otherwise, clears, sets, or shows one "
3179 "General Purpose Non-Volatile Memory (gpnvm) bit.",
3183 .handler
= sam3_handle_info_command
,
3184 .mode
= COMMAND_EXEC
,
3185 .help
= "Print information about the current at91sam3 chip"
3186 "and its flash configuration.",
3190 .handler
= sam3_handle_slowclk_command
,
3191 .mode
= COMMAND_EXEC
,
3192 .usage
= "[clock_hz]",
3193 .help
= "Display or set the slowclock frequency "
3194 "(default 32768 Hz).",
3196 COMMAND_REGISTRATION_DONE
3198 static const struct command_registration at91sam3_command_handlers
[] = {
3201 .mode
= COMMAND_ANY
,
3202 .help
= "at91sam3 flash command group",
3203 .chain
= at91sam3_exec_command_handlers
,
3205 COMMAND_REGISTRATION_DONE
3208 struct flash_driver at91sam3_flash
= {
3210 .commands
= at91sam3_command_handlers
,
3211 .flash_bank_command
= sam3_flash_bank_command
,
3212 .erase
= sam3_erase
,
3213 .protect
= sam3_protect
,
3214 .write
= sam3_write
,
3215 .read
= default_flash_read
,
3216 .probe
= sam3_probe
,
3217 .auto_probe
= sam3_auto_probe
,
3218 .erase_check
= sam3_erase_check
,
3219 .protect_check
= sam3_protect_check
,
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