1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
8 * Copyright (C) 2011 by Olivier Schonken, Jim Norris *
9 * (at91sam3x* & at91sam4 support)* *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
19 * GNU General public License for more details. *
21 * You should have received a copy of the GNU General public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
25 ****************************************************************************/
27 /* Some of the the lower level code was based on code supplied by
28 * ATMEL under this copyright. */
30 /* BEGIN ATMEL COPYRIGHT */
31 /* ----------------------------------------------------------------------------
32 * ATMEL Microcontroller Software Support
33 * ----------------------------------------------------------------------------
34 * Copyright (c) 2009, Atmel Corporation
36 * All rights reserved.
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions are met:
41 * - Redistributions of source code must retain the above copyright notice,
42 * this list of conditions and the disclaimer below.
44 * Atmel's name may not be used to endorse or promote products derived from
45 * this software without specific prior written permission.
47 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
49 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
50 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
52 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
53 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
54 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
55 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
56 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 * ----------------------------------------------------------------------------
59 /* END ATMEL COPYRIGHT */
66 #include <helper/time_support.h>
68 #define REG_NAME_WIDTH (12)
70 /* at91sam4s/at91sam4e series (has always one flash bank)*/
71 #define FLASH_BANK_BASE_S 0x00400000
73 /* at91sam4sd series (two one flash banks), first bank address */
74 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
75 /* at91sam4sd16x, second bank address */
76 #define FLASH_BANK1_BASE_1024K_SD (FLASH_BANK0_BASE_SD+(1024*1024/2))
77 /* at91sam4sd32x, second bank address */
78 #define FLASH_BANK1_BASE_2048K_SD (FLASH_BANK0_BASE_SD+(2048*1024/2))
80 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
81 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
82 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
83 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
84 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
85 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
86 /* cmd6 is not present in the at91sam4u4/2/1 data sheet table 19-2 */
87 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
88 #define AT91C_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
89 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
90 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
91 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
92 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
93 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
94 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
95 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
96 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
98 #define offset_EFC_FMR 0
99 #define offset_EFC_FCR 4
100 #define offset_EFC_FSR 8
101 #define offset_EFC_FRR 12
103 extern struct flash_driver at91sam4_flash
;
105 static float _tomhz(uint32_t freq_hz
)
109 f
= ((float)(freq_hz
)) / 1000000.0;
113 /* How the chip is configured. */
115 uint32_t unique_id
[4];
119 uint32_t mainosc_freq
;
129 #define SAM4_CHIPID_CIDR (0x400E0740)
130 uint32_t CHIPID_CIDR
;
131 #define SAM4_CHIPID_EXID (0x400E0744)
132 uint32_t CHIPID_EXID
;
134 #define SAM4_PMC_BASE (0x400E0400)
135 #define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
137 #define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
139 #define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
141 #define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
143 #define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
145 #define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
147 #define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
149 #define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
151 #define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
153 #define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
155 #define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
157 #define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
159 #define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
161 #define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
165 struct sam4_bank_private
{
167 /* DANGER: THERE ARE DRAGONS HERE.. */
168 /* NOTE: If you add more 'ghost' pointers */
169 /* be aware that you must *manually* update */
170 /* these pointers in the function sam4_GetDetails() */
171 /* See the comment "Here there be dragons" */
173 /* so we can find the chip we belong to */
174 struct sam4_chip
*pChip
;
175 /* so we can find the original bank pointer */
176 struct flash_bank
*pBank
;
177 unsigned bank_number
;
178 uint32_t controller_address
;
179 uint32_t base_address
;
180 uint32_t flash_wait_states
;
184 unsigned sector_size
;
188 struct sam4_chip_details
{
189 /* THERE ARE DRAGONS HERE.. */
190 /* note: If you add pointers here */
191 /* be careful about them as they */
192 /* may need to be updated inside */
193 /* the function: "sam4_GetDetails() */
194 /* which copy/overwrites the */
195 /* 'runtime' copy of this structure */
196 uint32_t chipid_cidr
;
200 #define SAM4_N_NVM_BITS 3
201 unsigned gpnvm
[SAM4_N_NVM_BITS
];
202 unsigned total_flash_size
;
203 unsigned total_sram_size
;
205 #define SAM4_MAX_FLASH_BANKS 2
206 /* these are "initialized" from the global const data */
207 struct sam4_bank_private bank
[SAM4_MAX_FLASH_BANKS
];
211 struct sam4_chip
*next
;
214 /* this is "initialized" from the global const structure */
215 struct sam4_chip_details details
;
216 struct target
*target
;
221 struct sam4_reg_list
{
222 uint32_t address
; size_t struct_offset
; const char *name
;
223 void (*explain_func
)(struct sam4_chip
*pInfo
);
226 static struct sam4_chip
*all_sam4_chips
;
228 static struct sam4_chip
*get_current_sam4(struct command_context
*cmd_ctx
)
231 static struct sam4_chip
*p
;
233 t
= get_current_target(cmd_ctx
);
235 command_print(cmd_ctx
, "No current target?");
241 /* this should not happen */
242 /* the command is not registered until the chip is created? */
243 command_print(cmd_ctx
, "No SAM4 chips exist?");
252 command_print(cmd_ctx
, "Cannot find SAM4 chip?");
256 /*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
257 /*The lockregions are 8KB per lock region, with a 1024KB device having 128 lock regions. */
258 /*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
259 /*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
261 /* these are used to *initialize* the "pChip->details" structure. */
262 static const struct sam4_chip_details all_sam4_details
[] = {
264 /* Start at91sam4e* series */
265 /*atsam4e16e - LQFP144/LFBGA144*/
267 .chipid_cidr
= 0xA3CC0CE0,
268 .name
= "at91sam4e16e",
269 .total_flash_size
= 1024 * 1024,
270 .total_sram_size
= 128 * 1024,
280 .base_address
= FLASH_BANK_BASE_S
,
281 .controller_address
= 0x400e0a00,
282 .flash_wait_states
= 6, /* workaround silicon bug */
284 .size_bytes
= 1024 * 1024,
299 /* Start at91sam4s* series */
300 /*atsam4s16c - LQFP100/BGA100*/
302 .chipid_cidr
= 0x28AC0CE0,
303 .name
= "at91sam4s16c",
304 .total_flash_size
= 1024 * 1024,
305 .total_sram_size
= 128 * 1024,
315 .base_address
= FLASH_BANK_BASE_S
,
316 .controller_address
= 0x400e0a00,
317 .flash_wait_states
= 6, /* workaround silicon bug */
319 .size_bytes
= 1024 * 1024,
333 /*atsam4s16b - LQFP64/QFN64*/
335 .chipid_cidr
= 0x289C0CE0,
336 .name
= "at91sam4s16b",
337 .total_flash_size
= 1024 * 1024,
338 .total_sram_size
= 128 * 1024,
348 .base_address
= FLASH_BANK_BASE_S
,
349 .controller_address
= 0x400e0a00,
350 .flash_wait_states
= 6, /* workaround silicon bug */
352 .size_bytes
= 1024 * 1024,
366 /*atsam4s16a - LQFP48/QFN48*/
368 .chipid_cidr
= 0x288C0CE0,
369 .name
= "at91sam4s16a",
370 .total_flash_size
= 1024 * 1024,
371 .total_sram_size
= 128 * 1024,
381 .base_address
= FLASH_BANK_BASE_S
,
382 .controller_address
= 0x400e0a00,
383 .flash_wait_states
= 6, /* workaround silicon bug */
385 .size_bytes
= 1024 * 1024,
399 /*atsam4s8c - LQFP100/BGA100*/
401 .chipid_cidr
= 0x28AC0AE0,
402 .name
= "at91sam4s8c",
403 .total_flash_size
= 512 * 1024,
404 .total_sram_size
= 128 * 1024,
414 .base_address
= FLASH_BANK_BASE_S
,
415 .controller_address
= 0x400e0a00,
416 .flash_wait_states
= 6, /* workaround silicon bug */
418 .size_bytes
= 512 * 1024,
432 /*atsam4s8b - LQFP64/BGA64*/
434 .chipid_cidr
= 0x289C0AE0,
435 .name
= "at91sam4s8b",
436 .total_flash_size
= 512 * 1024,
437 .total_sram_size
= 128 * 1024,
447 .base_address
= FLASH_BANK_BASE_S
,
448 .controller_address
= 0x400e0a00,
449 .flash_wait_states
= 6, /* workaround silicon bug */
451 .size_bytes
= 512 * 1024,
465 /*atsam4s8a - LQFP48/BGA48*/
467 .chipid_cidr
= 0x288C0AE0,
468 .name
= "at91sam4s8a",
469 .total_flash_size
= 512 * 1024,
470 .total_sram_size
= 128 * 1024,
480 .base_address
= FLASH_BANK_BASE_S
,
481 .controller_address
= 0x400e0a00,
482 .flash_wait_states
= 6, /* workaround silicon bug */
484 .size_bytes
= 512 * 1024,
501 .chipid_cidr
= 0x29a70ee0,
502 .name
= "at91sam4sd32c",
503 .total_flash_size
= 2048 * 1024,
504 .total_sram_size
= 160 * 1024,
515 .base_address
= FLASH_BANK0_BASE_SD
,
516 .controller_address
= 0x400e0a00,
517 .flash_wait_states
= 6, /* workaround silicon bug */
519 .size_bytes
= 1024 * 1024,
531 .base_address
= FLASH_BANK1_BASE_2048K_SD
,
532 .controller_address
= 0x400e0c00,
533 .flash_wait_states
= 6, /* workaround silicon bug */
535 .size_bytes
= 1024 * 1024,
545 .chipid_cidr
= 0x247e0ae0,
546 .name
= "at91samg53n19",
547 .total_flash_size
= 512 * 1024,
548 .total_sram_size
= 96 * 1024,
559 .base_address
= FLASH_BANK_BASE_S
,
560 .controller_address
= 0x400e0a00,
561 .flash_wait_states
= 6, /* workaround silicon bug */
563 .size_bytes
= 512 * 1024,
586 /***********************************************************************
587 **********************************************************************
588 **********************************************************************
589 **********************************************************************
590 **********************************************************************
591 **********************************************************************/
592 /* *ATMEL* style code - from the SAM4 driver code */
595 * Get the current status of the EEFC and
596 * the value of some status bits (LOCKE, PROGE).
597 * @param pPrivate - info about the bank
598 * @param v - result goes here
600 static int EFC_GetStatus(struct sam4_bank_private
*pPrivate
, uint32_t *v
)
603 r
= target_read_u32(pPrivate
->pChip
->target
,
604 pPrivate
->controller_address
+ offset_EFC_FSR
,
606 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
608 ((unsigned int)((*v
>> 2) & 1)),
609 ((unsigned int)((*v
>> 1) & 1)),
610 ((unsigned int)((*v
>> 0) & 1)));
616 * Get the result of the last executed command.
617 * @param pPrivate - info about the bank
618 * @param v - result goes here
620 static int EFC_GetResult(struct sam4_bank_private
*pPrivate
, uint32_t *v
)
624 r
= target_read_u32(pPrivate
->pChip
->target
,
625 pPrivate
->controller_address
+ offset_EFC_FRR
,
629 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv
)));
633 static int EFC_StartCommand(struct sam4_bank_private
*pPrivate
,
634 unsigned command
, unsigned argument
)
643 /* Check command & argument */
646 case AT91C_EFC_FCMD_WP
:
647 case AT91C_EFC_FCMD_WPL
:
648 case AT91C_EFC_FCMD_EWP
:
649 case AT91C_EFC_FCMD_EWPL
:
650 /* case AT91C_EFC_FCMD_EPL: */
651 case AT91C_EFC_FCMD_EPA
:
652 case AT91C_EFC_FCMD_SLB
:
653 case AT91C_EFC_FCMD_CLB
:
654 n
= (pPrivate
->size_bytes
/ pPrivate
->page_size
);
656 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n
));
659 case AT91C_EFC_FCMD_SFB
:
660 case AT91C_EFC_FCMD_CFB
:
661 if (argument
>= pPrivate
->pChip
->details
.n_gpnvms
) {
662 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
663 pPrivate
->pChip
->details
.n_gpnvms
);
667 case AT91C_EFC_FCMD_GETD
:
668 case AT91C_EFC_FCMD_EA
:
669 case AT91C_EFC_FCMD_GLB
:
670 case AT91C_EFC_FCMD_GFB
:
671 case AT91C_EFC_FCMD_STUI
:
672 case AT91C_EFC_FCMD_SPUI
:
674 LOG_ERROR("Argument is meaningless for cmd: %d", command
);
677 LOG_ERROR("Unknown command %d", command
);
681 if (command
== AT91C_EFC_FCMD_SPUI
) {
682 /* this is a very special situation. */
683 /* Situation (1) - error/retry - see below */
684 /* And we are being called recursively */
685 /* Situation (2) - normal, finished reading unique id */
687 /* it should be "ready" */
688 EFC_GetStatus(pPrivate
, &v
);
690 /* then it is ready */
694 /* we have done this before */
695 /* the controller is not responding. */
696 LOG_ERROR("flash controller(%d) is not ready! Error",
697 pPrivate
->bank_number
);
701 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
702 pPrivate
->bank_number
);
703 /* we do that by issuing the *STOP* command */
704 EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0);
705 /* above is recursive, and further recursion is blocked by */
706 /* if (command == AT91C_EFC_FCMD_SPUI) above */
712 v
= (0x5A << 24) | (argument
<< 8) | command
;
713 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v
)));
714 r
= target_write_u32(pPrivate
->pBank
->target
,
715 pPrivate
->controller_address
+ offset_EFC_FCR
, v
);
717 LOG_DEBUG("Error Write failed");
722 * Performs the given command and wait until its completion (or an error).
723 * @param pPrivate - info about the bank
724 * @param command - Command to perform.
725 * @param argument - Optional command argument.
726 * @param status - put command status bits here
728 static int EFC_PerformCommand(struct sam4_bank_private
*pPrivate
,
736 long long ms_now
, ms_end
;
742 r
= EFC_StartCommand(pPrivate
, command
, argument
);
746 ms_end
= 10000 + timeval_ms();
749 r
= EFC_GetStatus(pPrivate
, &v
);
752 ms_now
= timeval_ms();
753 if (ms_now
> ms_end
) {
755 LOG_ERROR("Command timeout");
758 } while ((v
& 1) == 0);
768 * Read the unique ID.
769 * @param pPrivate - info about the bank
770 * The unique ID is stored in the 'pPrivate' structure.
772 static int FLASHD_ReadUniqueID(struct sam4_bank_private
*pPrivate
)
778 pPrivate
->pChip
->cfg
.unique_id
[0] = 0;
779 pPrivate
->pChip
->cfg
.unique_id
[1] = 0;
780 pPrivate
->pChip
->cfg
.unique_id
[2] = 0;
781 pPrivate
->pChip
->cfg
.unique_id
[3] = 0;
784 r
= EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_STUI
, 0);
788 for (x
= 0; x
< 4; x
++) {
789 r
= target_read_u32(pPrivate
->pChip
->target
,
790 pPrivate
->pBank
->base
+ (x
* 4),
794 pPrivate
->pChip
->cfg
.unique_id
[x
] = v
;
797 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0, NULL
);
798 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
800 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[0]),
801 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[1]),
802 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[2]),
803 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[3]));
809 * Erases the entire flash.
810 * @param pPrivate - the info about the bank.
812 static int FLASHD_EraseEntireBank(struct sam4_bank_private
*pPrivate
)
815 return EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_EA
, 0, NULL
);
819 * Erases the entire flash.
820 * @param pPrivate - the info about the bank.
822 static int FLASHD_ErasePages(struct sam4_bank_private
*pPrivate
,
847 /* AT91C_EFC_FCMD_EPA
848 * According to the datasheet FARG[15:2] defines the page from which
849 * the erase will start.This page must be modulo 4, 8, 16 or 32
850 * according to the number of pages to erase. FARG[1:0] defines the
851 * number of pages to be erased. Previously (firstpage << 2) was used
852 * to conform to this, seems it should not be shifted...
854 return EFC_PerformCommand(pPrivate
,
855 /* send Erase Page */
857 (firstPage
) | erasePages
,
862 * Gets current GPNVM state.
863 * @param pPrivate - info about the bank.
864 * @param gpnvm - GPNVM bit index.
865 * @param puthere - result stored here.
867 /* ------------------------------------------------------------------------------ */
868 static int FLASHD_GetGPNVM(struct sam4_bank_private
*pPrivate
, unsigned gpnvm
, unsigned *puthere
)
874 if (pPrivate
->bank_number
!= 0) {
875 LOG_ERROR("GPNVM only works with Bank0");
879 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
880 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
881 gpnvm
, pPrivate
->pChip
->details
.n_gpnvms
);
885 /* Get GPNVMs status */
886 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GFB
, 0, NULL
);
892 r
= EFC_GetResult(pPrivate
, &v
);
895 /* Check if GPNVM is set */
896 /* get the bit and make it a 0/1 */
897 *puthere
= (v
>> gpnvm
) & 1;
904 * Clears the selected GPNVM bit.
905 * @param pPrivate info about the bank
906 * @param gpnvm GPNVM index.
907 * @returns 0 if successful; otherwise returns an error code.
909 static int FLASHD_ClrGPNVM(struct sam4_bank_private
*pPrivate
, unsigned gpnvm
)
915 if (pPrivate
->bank_number
!= 0) {
916 LOG_ERROR("GPNVM only works with Bank0");
920 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
921 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
922 gpnvm
, pPrivate
->pChip
->details
.n_gpnvms
);
926 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
928 LOG_DEBUG("Failed: %d", r
);
931 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CFB
, gpnvm
, NULL
);
932 LOG_DEBUG("End: %d", r
);
937 * Sets the selected GPNVM bit.
938 * @param pPrivate info about the bank
939 * @param gpnvm GPNVM index.
941 static int FLASHD_SetGPNVM(struct sam4_bank_private
*pPrivate
, unsigned gpnvm
)
946 if (pPrivate
->bank_number
!= 0) {
947 LOG_ERROR("GPNVM only works with Bank0");
951 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
952 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
953 gpnvm
, pPrivate
->pChip
->details
.n_gpnvms
);
957 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
965 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SFB
, gpnvm
, NULL
);
971 * Returns a bit field (at most 64) of locked regions within a page.
972 * @param pPrivate info about the bank
973 * @param v where to store locked bits
975 static int FLASHD_GetLockBits(struct sam4_bank_private
*pPrivate
, uint32_t *v
)
979 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GLB
, 0, NULL
);
981 EFC_GetResult(pPrivate
, v
);
982 EFC_GetResult(pPrivate
, v
);
983 EFC_GetResult(pPrivate
, v
);
984 r
= EFC_GetResult(pPrivate
, v
);
986 LOG_DEBUG("End: %d", r
);
991 * Unlocks all the regions in the given address range.
992 * @param pPrivate info about the bank
993 * @param start_sector first sector to unlock
994 * @param end_sector last (inclusive) to unlock
997 static int FLASHD_Unlock(struct sam4_bank_private
*pPrivate
,
998 unsigned start_sector
,
1004 uint32_t pages_per_sector
;
1006 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
1008 /* Unlock all pages */
1009 while (start_sector
<= end_sector
) {
1010 pg
= start_sector
* pages_per_sector
;
1012 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CLB
, pg
, &status
);
1023 * @param pPrivate - info about the bank
1024 * @param start_sector - first sector to lock
1025 * @param end_sector - last sector (inclusive) to lock
1027 static int FLASHD_Lock(struct sam4_bank_private
*pPrivate
,
1028 unsigned start_sector
,
1029 unsigned end_sector
)
1033 uint32_t pages_per_sector
;
1036 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
1038 /* Lock all pages */
1039 while (start_sector
<= end_sector
) {
1040 pg
= start_sector
* pages_per_sector
;
1042 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SLB
, pg
, &status
);
1050 /****** END SAM4 CODE ********/
1052 /* begin helpful debug code */
1053 /* print the fieldname, the field value, in dec & hex, and return field value */
1054 static uint32_t sam4_reg_fieldname(struct sam4_chip
*pChip
,
1055 const char *regname
,
1064 /* extract the field */
1066 v
= v
& ((1 << width
)-1);
1075 /* show the basics */
1076 LOG_USER_N("\t%*s: %*" PRId32
" [0x%0*" PRIx32
"] ",
1077 REG_NAME_WIDTH
, regname
,
1083 static const char _unknown
[] = "unknown";
1084 static const char *const eproc_names
[] = {
1088 "cortex-m3", /* 3 */
1090 "arm926ejs", /* 5 */
1091 "cortex-a5", /* 6 */
1092 "cortex-m4", /* 7 */
1103 #define nvpsize2 nvpsize /* these two tables are identical */
1104 static const char *const nvpsize
[] = {
1107 "16K bytes", /* 2 */
1108 "32K bytes", /* 3 */
1110 "64K bytes", /* 5 */
1112 "128K bytes", /* 7 */
1114 "256K bytes", /* 9 */
1115 "512K bytes", /* 10 */
1117 "1024K bytes", /* 12 */
1119 "2048K bytes", /* 14 */
1123 static const char *const sramsize
[] = {
1124 "48K Bytes", /* 0 */
1128 "112K Bytes", /* 4 */
1130 "80K Bytes", /* 6 */
1131 "160K Bytes", /* 7 */
1133 "16K Bytes", /* 9 */
1134 "32K Bytes", /* 10 */
1135 "64K Bytes", /* 11 */
1136 "128K Bytes", /* 12 */
1137 "256K Bytes", /* 13 */
1138 "96K Bytes", /* 14 */
1139 "512K Bytes", /* 15 */
1143 static const struct archnames
{ unsigned value
; const char *name
; } archnames
[] = {
1144 { 0x19, "AT91SAM9xx Series" },
1145 { 0x29, "AT91SAM9XExx Series" },
1146 { 0x34, "AT91x34 Series" },
1147 { 0x37, "CAP7 Series" },
1148 { 0x39, "CAP9 Series" },
1149 { 0x3B, "CAP11 Series" },
1150 { 0x3C, "ATSAM4E" },
1151 { 0x40, "AT91x40 Series" },
1152 { 0x42, "AT91x42 Series" },
1153 { 0x43, "SAMG51 Series"
1155 { 0x47, "SAMG53 Series"
1157 { 0x55, "AT91x55 Series" },
1158 { 0x60, "AT91SAM7Axx Series" },
1159 { 0x61, "AT91SAM7AQxx Series" },
1160 { 0x63, "AT91x63 Series" },
1161 { 0x70, "AT91SAM7Sxx Series" },
1162 { 0x71, "AT91SAM7XCxx Series" },
1163 { 0x72, "AT91SAM7SExx Series" },
1164 { 0x73, "AT91SAM7Lxx Series" },
1165 { 0x75, "AT91SAM7Xxx Series" },
1166 { 0x76, "AT91SAM7SLxx Series" },
1167 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1168 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1169 { 0x83, "ATSAM3A/SAM4A xC Series (100-pin version)"},
1170 { 0x84, "ATSAM3X/SAM4X xC Series (100-pin version)"},
1171 { 0x85, "ATSAM3X/SAM4X xE Series (144-pin version)"},
1172 { 0x86, "ATSAM3X/SAM4X xG Series (208/217-pin version)" },
1173 { 0x88, "ATSAM3S/SAM4S xA Series (48-pin version)" },
1174 { 0x89, "ATSAM3S/SAM4S xB Series (64-pin version)" },
1175 { 0x8A, "ATSAM3S/SAM4S xC Series (100-pin version)"},
1176 { 0x92, "AT91x92 Series" },
1177 { 0x93, "ATSAM3NxA Series (48-pin version)" },
1178 { 0x94, "ATSAM3NxB Series (64-pin version)" },
1179 { 0x95, "ATSAM3NxC Series (100-pin version)" },
1180 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
1181 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
1182 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
1183 { 0xA5, "ATSAM5A" },
1184 { 0xF0, "AT75Cxx Series" },
1188 static const char *const nvptype
[] = {
1190 "romless or onchip flash", /* 1 */
1191 "embedded flash memory",/* 2 */
1192 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
1193 "sram emulating flash", /* 4 */
1199 static const char *_yes_or_no(uint32_t v
)
1207 static const char *const _rc_freq
[] = {
1208 "4 MHz", "8 MHz", "12 MHz", "reserved"
1211 static void sam4_explain_ckgr_mor(struct sam4_chip
*pChip
)
1216 v
= sam4_reg_fieldname(pChip
, "MOSCXTEN", pChip
->cfg
.CKGR_MOR
, 0, 1);
1217 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v
));
1218 v
= sam4_reg_fieldname(pChip
, "MOSCXTBY", pChip
->cfg
.CKGR_MOR
, 1, 1);
1219 LOG_USER("(main osc bypass: %s)", _yes_or_no(v
));
1220 rcen
= sam4_reg_fieldname(pChip
, "MOSCRCEN", pChip
->cfg
.CKGR_MOR
, 3, 1);
1221 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen
));
1222 v
= sam4_reg_fieldname(pChip
, "MOSCRCF", pChip
->cfg
.CKGR_MOR
, 4, 3);
1223 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq
[v
]);
1225 pChip
->cfg
.rc_freq
= 0;
1229 pChip
->cfg
.rc_freq
= 0;
1232 pChip
->cfg
.rc_freq
= 4 * 1000 * 1000;
1235 pChip
->cfg
.rc_freq
= 8 * 1000 * 1000;
1238 pChip
->cfg
.rc_freq
= 12 * 1000 * 1000;
1243 v
= sam4_reg_fieldname(pChip
, "MOSCXTST", pChip
->cfg
.CKGR_MOR
, 8, 8);
1244 LOG_USER("(startup clks, time= %f uSecs)",
1245 ((float)(v
* 1000000)) / ((float)(pChip
->cfg
.slow_freq
)));
1246 v
= sam4_reg_fieldname(pChip
, "MOSCSEL", pChip
->cfg
.CKGR_MOR
, 24, 1);
1247 LOG_USER("(mainosc source: %s)",
1248 v
? "external xtal" : "internal RC");
1250 v
= sam4_reg_fieldname(pChip
, "CFDEN", pChip
->cfg
.CKGR_MOR
, 25, 1);
1251 LOG_USER("(clock failure enabled: %s)",
1255 static void sam4_explain_chipid_cidr(struct sam4_chip
*pChip
)
1261 sam4_reg_fieldname(pChip
, "Version", pChip
->cfg
.CHIPID_CIDR
, 0, 5);
1264 v
= sam4_reg_fieldname(pChip
, "EPROC", pChip
->cfg
.CHIPID_CIDR
, 5, 3);
1265 LOG_USER("%s", eproc_names
[v
]);
1267 v
= sam4_reg_fieldname(pChip
, "NVPSIZE", pChip
->cfg
.CHIPID_CIDR
, 8, 4);
1268 LOG_USER("%s", nvpsize
[v
]);
1270 v
= sam4_reg_fieldname(pChip
, "NVPSIZE2", pChip
->cfg
.CHIPID_CIDR
, 12, 4);
1271 LOG_USER("%s", nvpsize2
[v
]);
1273 v
= sam4_reg_fieldname(pChip
, "SRAMSIZE", pChip
->cfg
.CHIPID_CIDR
, 16, 4);
1274 LOG_USER("%s", sramsize
[v
]);
1276 v
= sam4_reg_fieldname(pChip
, "ARCH", pChip
->cfg
.CHIPID_CIDR
, 20, 8);
1278 for (x
= 0; archnames
[x
].name
; x
++) {
1279 if (v
== archnames
[x
].value
) {
1280 cp
= archnames
[x
].name
;
1287 v
= sam4_reg_fieldname(pChip
, "NVPTYP", pChip
->cfg
.CHIPID_CIDR
, 28, 3);
1288 LOG_USER("%s", nvptype
[v
]);
1290 v
= sam4_reg_fieldname(pChip
, "EXTID", pChip
->cfg
.CHIPID_CIDR
, 31, 1);
1291 LOG_USER("(exists: %s)", _yes_or_no(v
));
1294 static void sam4_explain_ckgr_mcfr(struct sam4_chip
*pChip
)
1298 v
= sam4_reg_fieldname(pChip
, "MAINFRDY", pChip
->cfg
.CKGR_MCFR
, 16, 1);
1299 LOG_USER("(main ready: %s)", _yes_or_no(v
));
1301 v
= sam4_reg_fieldname(pChip
, "MAINF", pChip
->cfg
.CKGR_MCFR
, 0, 16);
1303 v
= (v
* pChip
->cfg
.slow_freq
) / 16;
1304 pChip
->cfg
.mainosc_freq
= v
;
1306 LOG_USER("(%3.03f Mhz (%" PRIu32
".%03" PRIu32
"khz slowclk)",
1308 (uint32_t)(pChip
->cfg
.slow_freq
/ 1000),
1309 (uint32_t)(pChip
->cfg
.slow_freq
% 1000));
1312 static void sam4_explain_ckgr_plla(struct sam4_chip
*pChip
)
1314 uint32_t mula
, diva
;
1316 diva
= sam4_reg_fieldname(pChip
, "DIVA", pChip
->cfg
.CKGR_PLLAR
, 0, 8);
1318 mula
= sam4_reg_fieldname(pChip
, "MULA", pChip
->cfg
.CKGR_PLLAR
, 16, 11);
1320 pChip
->cfg
.plla_freq
= 0;
1322 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
1324 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
1325 else if (diva
>= 1) {
1326 pChip
->cfg
.plla_freq
= (pChip
->cfg
.mainosc_freq
* (mula
+ 1) / diva
);
1327 LOG_USER("\tPLLA Freq: %3.03f MHz",
1328 _tomhz(pChip
->cfg
.plla_freq
));
1332 static void sam4_explain_mckr(struct sam4_chip
*pChip
)
1334 uint32_t css
, pres
, fin
= 0;
1336 const char *cp
= NULL
;
1338 css
= sam4_reg_fieldname(pChip
, "CSS", pChip
->cfg
.PMC_MCKR
, 0, 2);
1341 fin
= pChip
->cfg
.slow_freq
;
1345 fin
= pChip
->cfg
.mainosc_freq
;
1349 fin
= pChip
->cfg
.plla_freq
;
1353 if (pChip
->cfg
.CKGR_UCKR
& (1 << 16)) {
1354 fin
= 480 * 1000 * 1000;
1358 cp
= "upll (*ERROR* UPLL is disabled)";
1366 LOG_USER("%s (%3.03f Mhz)",
1369 pres
= sam4_reg_fieldname(pChip
, "PRES", pChip
->cfg
.PMC_MCKR
, 4, 3);
1370 switch (pres
& 0x07) {
1373 cp
= "selected clock";
1407 LOG_USER("(%s)", cp
);
1409 /* sam4 has a *SINGLE* clock - */
1410 /* other at91 series parts have divisors for these. */
1411 pChip
->cfg
.cpu_freq
= fin
;
1412 pChip
->cfg
.mclk_freq
= fin
;
1413 pChip
->cfg
.fclk_freq
= fin
;
1414 LOG_USER("\t\tResult CPU Freq: %3.03f",
1419 static struct sam4_chip
*target2sam4(struct target
*pTarget
)
1421 struct sam4_chip
*pChip
;
1423 if (pTarget
== NULL
)
1426 pChip
= all_sam4_chips
;
1428 if (pChip
->target
== pTarget
)
1429 break; /* return below */
1431 pChip
= pChip
->next
;
1437 static uint32_t *sam4_get_reg_ptr(struct sam4_cfg
*pCfg
, const struct sam4_reg_list
*pList
)
1439 /* this function exists to help */
1440 /* keep funky offsetof() errors */
1441 /* and casting from causing bugs */
1443 /* By using prototypes - we can detect what would */
1444 /* be casting errors. */
1446 return (uint32_t *)(void *)(((char *)(pCfg
)) + pList
->struct_offset
);
1450 #define SAM4_ENTRY(NAME, FUNC) { .address = SAM4_ ## NAME, .struct_offset = offsetof( \
1452 NAME), # NAME, FUNC }
1453 static const struct sam4_reg_list sam4_all_regs
[] = {
1454 SAM4_ENTRY(CKGR_MOR
, sam4_explain_ckgr_mor
),
1455 SAM4_ENTRY(CKGR_MCFR
, sam4_explain_ckgr_mcfr
),
1456 SAM4_ENTRY(CKGR_PLLAR
, sam4_explain_ckgr_plla
),
1457 SAM4_ENTRY(CKGR_UCKR
, NULL
),
1458 SAM4_ENTRY(PMC_FSMR
, NULL
),
1459 SAM4_ENTRY(PMC_FSPR
, NULL
),
1460 SAM4_ENTRY(PMC_IMR
, NULL
),
1461 SAM4_ENTRY(PMC_MCKR
, sam4_explain_mckr
),
1462 SAM4_ENTRY(PMC_PCK0
, NULL
),
1463 SAM4_ENTRY(PMC_PCK1
, NULL
),
1464 SAM4_ENTRY(PMC_PCK2
, NULL
),
1465 SAM4_ENTRY(PMC_PCSR
, NULL
),
1466 SAM4_ENTRY(PMC_SCSR
, NULL
),
1467 SAM4_ENTRY(PMC_SR
, NULL
),
1468 SAM4_ENTRY(CHIPID_CIDR
, sam4_explain_chipid_cidr
),
1469 SAM4_ENTRY(CHIPID_EXID
, NULL
),
1470 /* TERMINATE THE LIST */
1475 static struct sam4_bank_private
*get_sam4_bank_private(struct flash_bank
*bank
)
1477 return bank
->driver_priv
;
1481 * Given a pointer to where it goes in the structure,
1482 * determine the register name, address from the all registers table.
1484 static const struct sam4_reg_list
*sam4_GetReg(struct sam4_chip
*pChip
, uint32_t *goes_here
)
1486 const struct sam4_reg_list
*pReg
;
1488 pReg
= &(sam4_all_regs
[0]);
1489 while (pReg
->name
) {
1490 uint32_t *pPossible
;
1492 /* calculate where this one go.. */
1493 /* it is "possibly" this register. */
1495 pPossible
= ((uint32_t *)(void *)(((char *)(&(pChip
->cfg
))) + pReg
->struct_offset
));
1497 /* well? Is it this register */
1498 if (pPossible
== goes_here
) {
1506 /* This is *TOTAL*PANIC* - we are totally screwed. */
1507 LOG_ERROR("INVALID SAM4 REGISTER");
1511 static int sam4_ReadThisReg(struct sam4_chip
*pChip
, uint32_t *goes_here
)
1513 const struct sam4_reg_list
*pReg
;
1516 pReg
= sam4_GetReg(pChip
, goes_here
);
1520 r
= target_read_u32(pChip
->target
, pReg
->address
, goes_here
);
1521 if (r
!= ERROR_OK
) {
1522 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d",
1523 pReg
->name
, (unsigned)(pReg
->address
), r
);
1528 static int sam4_ReadAllRegs(struct sam4_chip
*pChip
)
1531 const struct sam4_reg_list
*pReg
;
1533 pReg
= &(sam4_all_regs
[0]);
1534 while (pReg
->name
) {
1535 r
= sam4_ReadThisReg(pChip
,
1536 sam4_get_reg_ptr(&(pChip
->cfg
), pReg
));
1537 if (r
!= ERROR_OK
) {
1538 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Error: %d",
1539 pReg
->name
, ((unsigned)(pReg
->address
)), r
);
1548 static int sam4_GetInfo(struct sam4_chip
*pChip
)
1550 const struct sam4_reg_list
*pReg
;
1553 pReg
= &(sam4_all_regs
[0]);
1554 while (pReg
->name
) {
1555 /* display all regs */
1556 LOG_DEBUG("Start: %s", pReg
->name
);
1557 regval
= *sam4_get_reg_ptr(&(pChip
->cfg
), pReg
);
1558 LOG_USER("%*s: [0x%08" PRIx32
"] -> 0x%08" PRIx32
,
1563 if (pReg
->explain_func
)
1564 (*(pReg
->explain_func
))(pChip
);
1565 LOG_DEBUG("End: %s", pReg
->name
);
1568 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip
->cfg
.rc_freq
));
1569 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip
->cfg
.mainosc_freq
));
1570 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip
->cfg
.plla_freq
));
1571 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip
->cfg
.cpu_freq
));
1572 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip
->cfg
.mclk_freq
));
1574 LOG_USER(" UniqueId: 0x%08" PRIx32
" 0x%08" PRIx32
" 0x%08" PRIx32
" 0x%08"PRIx32
,
1575 pChip
->cfg
.unique_id
[0],
1576 pChip
->cfg
.unique_id
[1],
1577 pChip
->cfg
.unique_id
[2],
1578 pChip
->cfg
.unique_id
[3]);
1583 static int sam4_protect_check(struct flash_bank
*bank
)
1586 uint32_t v
[4] = {0};
1588 struct sam4_bank_private
*pPrivate
;
1591 if (bank
->target
->state
!= TARGET_HALTED
) {
1592 LOG_ERROR("Target not halted");
1593 return ERROR_TARGET_NOT_HALTED
;
1596 pPrivate
= get_sam4_bank_private(bank
);
1598 LOG_ERROR("no private for this bank?");
1601 if (!(pPrivate
->probed
))
1602 return ERROR_FLASH_BANK_NOT_PROBED
;
1604 r
= FLASHD_GetLockBits(pPrivate
, v
);
1605 if (r
!= ERROR_OK
) {
1606 LOG_DEBUG("Failed: %d", r
);
1610 for (x
= 0; x
< pPrivate
->nsectors
; x
++)
1611 bank
->sectors
[x
].is_protected
= (!!(v
[x
>> 5] & (1 << (x
% 32))));
1616 FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command
)
1618 struct sam4_chip
*pChip
;
1620 pChip
= all_sam4_chips
;
1622 /* is this an existing chip? */
1624 if (pChip
->target
== bank
->target
)
1626 pChip
= pChip
->next
;
1630 /* this is a *NEW* chip */
1631 pChip
= calloc(1, sizeof(struct sam4_chip
));
1633 LOG_ERROR("NO RAM!");
1636 pChip
->target
= bank
->target
;
1637 /* insert at head */
1638 pChip
->next
= all_sam4_chips
;
1639 all_sam4_chips
= pChip
;
1640 pChip
->target
= bank
->target
;
1641 /* assumption is this runs at 32khz */
1642 pChip
->cfg
.slow_freq
= 32768;
1646 switch (bank
->base
) {
1648 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x"
1649 "[at91sam4s series] )",
1650 ((unsigned int)(bank
->base
)),
1651 ((unsigned int)(FLASH_BANK_BASE_S
)));
1655 /* at91sam4s series only has bank 0*/
1656 /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/
1657 case FLASH_BANK_BASE_S
:
1658 bank
->driver_priv
= &(pChip
->details
.bank
[0]);
1659 bank
->bank_number
= 0;
1660 pChip
->details
.bank
[0].pChip
= pChip
;
1661 pChip
->details
.bank
[0].pBank
= bank
;
1664 /* Bank 1 of at91sam4sd series */
1665 case FLASH_BANK1_BASE_1024K_SD
:
1666 case FLASH_BANK1_BASE_2048K_SD
:
1667 bank
->driver_priv
= &(pChip
->details
.bank
[1]);
1668 bank
->bank_number
= 1;
1669 pChip
->details
.bank
[1].pChip
= pChip
;
1670 pChip
->details
.bank
[1].pBank
= bank
;
1674 /* we initialize after probing. */
1678 static int sam4_GetDetails(struct sam4_bank_private
*pPrivate
)
1680 const struct sam4_chip_details
*pDetails
;
1681 struct sam4_chip
*pChip
;
1682 struct flash_bank
*saved_banks
[SAM4_MAX_FLASH_BANKS
];
1686 pDetails
= all_sam4_details
;
1687 while (pDetails
->name
) {
1688 /* Compare cidr without version bits */
1689 if (pDetails
->chipid_cidr
== (pPrivate
->pChip
->cfg
.CHIPID_CIDR
& 0xFFFFFFE0))
1694 if (pDetails
->name
== NULL
) {
1695 LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
1696 (unsigned int)(pPrivate
->pChip
->cfg
.CHIPID_CIDR
));
1697 /* Help the victim, print details about the chip */
1698 LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32
" decodes as follows",
1699 pPrivate
->pChip
->cfg
.CHIPID_CIDR
);
1700 sam4_explain_chipid_cidr(pPrivate
->pChip
);
1704 /* DANGER: THERE ARE DRAGONS HERE */
1706 /* get our pChip - it is going */
1707 /* to be over-written shortly */
1708 pChip
= pPrivate
->pChip
;
1710 /* Note that, in reality: */
1712 /* pPrivate = &(pChip->details.bank[0]) */
1713 /* or pPrivate = &(pChip->details.bank[1]) */
1716 /* save the "bank" pointers */
1717 for (x
= 0; x
< SAM4_MAX_FLASH_BANKS
; x
++)
1718 saved_banks
[x
] = pChip
->details
.bank
[x
].pBank
;
1720 /* Overwrite the "details" structure. */
1721 memcpy(&(pPrivate
->pChip
->details
),
1723 sizeof(pPrivate
->pChip
->details
));
1725 /* now fix the ghosted pointers */
1726 for (x
= 0; x
< SAM4_MAX_FLASH_BANKS
; x
++) {
1727 pChip
->details
.bank
[x
].pChip
= pChip
;
1728 pChip
->details
.bank
[x
].pBank
= saved_banks
[x
];
1731 /* update the *BANK*SIZE* */
1737 static int _sam4_probe(struct flash_bank
*bank
, int noise
)
1741 struct sam4_bank_private
*pPrivate
;
1744 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank
->bank_number
, noise
);
1745 if (bank
->target
->state
!= TARGET_HALTED
) {
1746 LOG_ERROR("Target not halted");
1747 return ERROR_TARGET_NOT_HALTED
;
1750 pPrivate
= get_sam4_bank_private(bank
);
1752 LOG_ERROR("Invalid/unknown bank number");
1756 r
= sam4_ReadAllRegs(pPrivate
->pChip
);
1761 if (pPrivate
->pChip
->probed
)
1762 r
= sam4_GetInfo(pPrivate
->pChip
);
1764 r
= sam4_GetDetails(pPrivate
);
1768 /* update the flash bank size */
1769 for (x
= 0; x
< SAM4_MAX_FLASH_BANKS
; x
++) {
1770 if (bank
->base
== pPrivate
->pChip
->details
.bank
[x
].base_address
) {
1771 bank
->size
= pPrivate
->pChip
->details
.bank
[x
].size_bytes
;
1776 if (bank
->sectors
== NULL
) {
1777 bank
->sectors
= calloc(pPrivate
->nsectors
, (sizeof((bank
->sectors
)[0])));
1778 if (bank
->sectors
== NULL
) {
1779 LOG_ERROR("No memory!");
1782 bank
->num_sectors
= pPrivate
->nsectors
;
1784 for (x
= 0; ((int)(x
)) < bank
->num_sectors
; x
++) {
1785 bank
->sectors
[x
].size
= pPrivate
->sector_size
;
1786 bank
->sectors
[x
].offset
= x
* (pPrivate
->sector_size
);
1787 /* mark as unknown */
1788 bank
->sectors
[x
].is_erased
= -1;
1789 bank
->sectors
[x
].is_protected
= -1;
1793 pPrivate
->probed
= 1;
1795 r
= sam4_protect_check(bank
);
1799 LOG_DEBUG("Bank = %d, nbanks = %d",
1800 pPrivate
->bank_number
, pPrivate
->pChip
->details
.n_banks
);
1801 if ((pPrivate
->bank_number
+ 1) == pPrivate
->pChip
->details
.n_banks
) {
1802 /* read unique id, */
1803 /* it appears to be associated with the *last* flash bank. */
1804 FLASHD_ReadUniqueID(pPrivate
);
1810 static int sam4_probe(struct flash_bank
*bank
)
1812 return _sam4_probe(bank
, 1);
1815 static int sam4_auto_probe(struct flash_bank
*bank
)
1817 return _sam4_probe(bank
, 0);
1820 static int sam4_erase(struct flash_bank
*bank
, int first
, int last
)
1822 struct sam4_bank_private
*pPrivate
;
1826 /*16 pages equals 8KB - Same size as a lock region*/
1831 if (bank
->target
->state
!= TARGET_HALTED
) {
1832 LOG_ERROR("Target not halted");
1833 return ERROR_TARGET_NOT_HALTED
;
1836 r
= sam4_auto_probe(bank
);
1837 if (r
!= ERROR_OK
) {
1838 LOG_DEBUG("Here,r=%d", r
);
1842 pPrivate
= get_sam4_bank_private(bank
);
1843 if (!(pPrivate
->probed
))
1844 return ERROR_FLASH_BANK_NOT_PROBED
;
1846 if ((first
== 0) && ((last
+ 1) == ((int)(pPrivate
->nsectors
)))) {
1849 return FLASHD_EraseEntireBank(pPrivate
);
1851 LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
1852 LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", (unsigned int)(first
), (unsigned int)(last
));
1853 for (i
= first
; i
<= last
; i
++) {
1854 /*16 pages equals 8KB - Same size as a lock region*/
1855 r
= FLASHD_ErasePages(pPrivate
, (i
* pageCount
), pageCount
, &status
);
1856 LOG_INFO("Erasing sector: 0x%08x", (unsigned int)(i
));
1858 LOG_ERROR("SAM4: Error performing Erase page @ lock region number %d",
1860 if (status
& (1 << 2)) {
1861 LOG_ERROR("SAM4: Lock Region %d is locked", (unsigned int)(i
));
1864 if (status
& (1 << 1)) {
1865 LOG_ERROR("SAM4: Flash Command error @lock region %d", (unsigned int)(i
));
1873 static int sam4_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
1875 struct sam4_bank_private
*pPrivate
;
1879 if (bank
->target
->state
!= TARGET_HALTED
) {
1880 LOG_ERROR("Target not halted");
1881 return ERROR_TARGET_NOT_HALTED
;
1884 pPrivate
= get_sam4_bank_private(bank
);
1885 if (!(pPrivate
->probed
))
1886 return ERROR_FLASH_BANK_NOT_PROBED
;
1889 r
= FLASHD_Lock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
1891 r
= FLASHD_Unlock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
1892 LOG_DEBUG("End: r=%d", r
);
1898 static int sam4_page_read(struct sam4_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
1903 adr
= pagenum
* pPrivate
->page_size
;
1904 adr
= adr
+ pPrivate
->base_address
;
1906 r
= target_read_memory(pPrivate
->pChip
->target
,
1908 4, /* THIS*MUST*BE* in 32bit values */
1909 pPrivate
->page_size
/ 4,
1912 LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
1913 (unsigned int)(adr
));
1917 static int sam4_page_write(struct sam4_bank_private
*pPrivate
, unsigned pagenum
, const uint8_t *buf
)
1921 uint32_t fmr
; /* EEFC Flash Mode Register */
1924 adr
= pagenum
* pPrivate
->page_size
;
1925 adr
= (adr
+ pPrivate
->base_address
);
1927 /* Get flash mode register value */
1928 r
= target_read_u32(pPrivate
->pChip
->target
, pPrivate
->controller_address
, &fmr
);
1930 LOG_DEBUG("Error Read failed: read flash mode register");
1932 /* Clear flash wait state field */
1935 /* set FWS (flash wait states) field in the FMR (flash mode register) */
1936 fmr
|= (pPrivate
->flash_wait_states
<< 8);
1938 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr
)));
1939 r
= target_write_u32(pPrivate
->pBank
->target
, pPrivate
->controller_address
, fmr
);
1941 LOG_DEBUG("Error Write failed: set flash mode register");
1943 /* 1st sector 8kBytes - page 0 - 15*/
1944 /* 2nd sector 8kBytes - page 16 - 30*/
1945 /* 3rd sector 48kBytes - page 31 - 127*/
1946 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum
, (unsigned int)(adr
));
1947 r
= target_write_memory(pPrivate
->pChip
->target
,
1949 4, /* THIS*MUST*BE* in 32bit values */
1950 pPrivate
->page_size
/ 4,
1952 if (r
!= ERROR_OK
) {
1953 LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
1954 (unsigned int)(adr
));
1958 r
= EFC_PerformCommand(pPrivate
,
1959 /* send Erase & Write Page */
1960 AT91C_EFC_FCMD_WP
, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
1965 LOG_ERROR("SAM4: Error performing Write page @ phys address 0x%08x",
1966 (unsigned int)(adr
));
1967 if (status
& (1 << 2)) {
1968 LOG_ERROR("SAM4: Page @ Phys address 0x%08x is locked", (unsigned int)(adr
));
1971 if (status
& (1 << 1)) {
1972 LOG_ERROR("SAM4: Flash Command error @phys address 0x%08x", (unsigned int)(adr
));
1978 static int sam4_write(struct flash_bank
*bank
,
1979 const uint8_t *buffer
,
1987 unsigned page_offset
;
1988 struct sam4_bank_private
*pPrivate
;
1989 uint8_t *pagebuffer
;
1991 /* incase we bail further below, set this to null */
1994 /* ignore dumb requests */
2000 if (bank
->target
->state
!= TARGET_HALTED
) {
2001 LOG_ERROR("Target not halted");
2002 r
= ERROR_TARGET_NOT_HALTED
;
2006 pPrivate
= get_sam4_bank_private(bank
);
2007 if (!(pPrivate
->probed
)) {
2008 r
= ERROR_FLASH_BANK_NOT_PROBED
;
2012 if ((offset
+ count
) > pPrivate
->size_bytes
) {
2013 LOG_ERROR("Flash write error - past end of bank");
2014 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2015 (unsigned int)(offset
),
2016 (unsigned int)(count
),
2017 (unsigned int)(pPrivate
->size_bytes
));
2022 pagebuffer
= malloc(pPrivate
->page_size
);
2024 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate
->page_size
));
2029 /* what page do we start & end in? */
2030 page_cur
= offset
/ pPrivate
->page_size
;
2031 page_end
= (offset
+ count
- 1) / pPrivate
->page_size
;
2033 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset
), (unsigned int)(count
));
2034 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur
), (int)(page_end
));
2036 /* Special case: all one page */
2039 /* (1) non-aligned start */
2040 /* (2) body pages */
2041 /* (3) non-aligned end. */
2043 /* Handle special case - all one page. */
2044 if (page_cur
== page_end
) {
2045 LOG_DEBUG("Special case, all in one page");
2046 r
= sam4_page_read(pPrivate
, page_cur
, pagebuffer
);
2050 page_offset
= (offset
& (pPrivate
->page_size
-1));
2051 memcpy(pagebuffer
+ page_offset
,
2055 r
= sam4_page_write(pPrivate
, page_cur
, pagebuffer
);
2062 /* non-aligned start */
2063 page_offset
= offset
& (pPrivate
->page_size
- 1);
2065 LOG_DEBUG("Not-Aligned start");
2066 /* read the partial */
2067 r
= sam4_page_read(pPrivate
, page_cur
, pagebuffer
);
2071 /* over-write with new data */
2072 n
= (pPrivate
->page_size
- page_offset
);
2073 memcpy(pagebuffer
+ page_offset
,
2077 r
= sam4_page_write(pPrivate
, page_cur
, pagebuffer
);
2087 /* By checking that offset is correct here, we also
2088 fix a clang warning */
2089 assert(offset
% pPrivate
->page_size
== 0);
2091 /* intermediate large pages */
2092 /* also - the final *terminal* */
2093 /* if that terminal page is a full page */
2094 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2095 (int)page_cur
, (int)page_end
, (unsigned int)(count
));
2097 while ((page_cur
< page_end
) &&
2098 (count
>= pPrivate
->page_size
)) {
2099 r
= sam4_page_write(pPrivate
, page_cur
, buffer
);
2102 count
-= pPrivate
->page_size
;
2103 buffer
+= pPrivate
->page_size
;
2107 /* terminal partial page? */
2109 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count
));
2110 /* we have a partial page */
2111 r
= sam4_page_read(pPrivate
, page_cur
, pagebuffer
);
2114 /* data goes at start */
2115 memcpy(pagebuffer
, buffer
, count
);
2116 r
= sam4_page_write(pPrivate
, page_cur
, pagebuffer
);
2128 COMMAND_HANDLER(sam4_handle_info_command
)
2130 struct sam4_chip
*pChip
;
2131 pChip
= get_current_sam4(CMD_CTX
);
2138 /* bank0 must exist before we can do anything */
2139 if (pChip
->details
.bank
[0].pBank
== NULL
) {
2142 command_print(CMD_CTX
,
2143 "Please define bank %d via command: flash bank %s ... ",
2145 at91sam4_flash
.name
);
2149 /* if bank 0 is not probed, then probe it */
2150 if (!(pChip
->details
.bank
[0].probed
)) {
2151 r
= sam4_auto_probe(pChip
->details
.bank
[0].pBank
);
2155 /* above guarantees the "chip details" structure is valid */
2156 /* and thus, bank private areas are valid */
2157 /* and we have a SAM4 chip, what a concept! */
2159 /* auto-probe other banks, 0 done above */
2160 for (x
= 1; x
< SAM4_MAX_FLASH_BANKS
; x
++) {
2161 /* skip banks not present */
2162 if (!(pChip
->details
.bank
[x
].present
))
2165 if (pChip
->details
.bank
[x
].pBank
== NULL
)
2168 if (pChip
->details
.bank
[x
].probed
)
2171 r
= sam4_auto_probe(pChip
->details
.bank
[x
].pBank
);
2176 r
= sam4_GetInfo(pChip
);
2177 if (r
!= ERROR_OK
) {
2178 LOG_DEBUG("Sam4Info, Failed %d", r
);
2185 COMMAND_HANDLER(sam4_handle_gpnvm_command
)
2189 struct sam4_chip
*pChip
;
2191 pChip
= get_current_sam4(CMD_CTX
);
2195 if (pChip
->target
->state
!= TARGET_HALTED
) {
2196 LOG_ERROR("sam4 - target not halted");
2197 return ERROR_TARGET_NOT_HALTED
;
2200 if (pChip
->details
.bank
[0].pBank
== NULL
) {
2201 command_print(CMD_CTX
, "Bank0 must be defined first via: flash bank %s ...",
2202 at91sam4_flash
.name
);
2205 if (!pChip
->details
.bank
[0].probed
) {
2206 r
= sam4_auto_probe(pChip
->details
.bank
[0].pBank
);
2213 return ERROR_COMMAND_SYNTAX_ERROR
;
2222 if ((0 == strcmp(CMD_ARGV
[0], "show")) && (0 == strcmp(CMD_ARGV
[1], "all")))
2226 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], v32
);
2232 if (0 == strcmp("show", CMD_ARGV
[0])) {
2236 for (x
= 0; x
< pChip
->details
.n_gpnvms
; x
++) {
2237 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), x
, &v
);
2240 command_print(CMD_CTX
, "sam4-gpnvm%u: %u", x
, v
);
2244 if ((who
>= 0) && (((unsigned)(who
)) < pChip
->details
.n_gpnvms
)) {
2245 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), who
, &v
);
2246 command_print(CMD_CTX
, "sam4-gpnvm%u: %u", who
, v
);
2249 command_print(CMD_CTX
, "sam4-gpnvm invalid GPNVM: %u", who
);
2250 return ERROR_COMMAND_SYNTAX_ERROR
;
2255 command_print(CMD_CTX
, "Missing GPNVM number");
2256 return ERROR_COMMAND_SYNTAX_ERROR
;
2259 if (0 == strcmp("set", CMD_ARGV
[0]))
2260 r
= FLASHD_SetGPNVM(&(pChip
->details
.bank
[0]), who
);
2261 else if ((0 == strcmp("clr", CMD_ARGV
[0])) ||
2262 (0 == strcmp("clear", CMD_ARGV
[0]))) /* quietly accept both */
2263 r
= FLASHD_ClrGPNVM(&(pChip
->details
.bank
[0]), who
);
2265 command_print(CMD_CTX
, "Unknown command: %s", CMD_ARGV
[0]);
2266 r
= ERROR_COMMAND_SYNTAX_ERROR
;
2271 COMMAND_HANDLER(sam4_handle_slowclk_command
)
2273 struct sam4_chip
*pChip
;
2275 pChip
= get_current_sam4(CMD_CTX
);
2287 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], v
);
2289 /* absurd slow clock of 200Khz? */
2290 command_print(CMD_CTX
, "Absurd/illegal slow clock freq: %d\n", (int)(v
));
2291 return ERROR_COMMAND_SYNTAX_ERROR
;
2293 pChip
->cfg
.slow_freq
= v
;
2298 command_print(CMD_CTX
, "Too many parameters");
2299 return ERROR_COMMAND_SYNTAX_ERROR
;
2302 command_print(CMD_CTX
, "Slowclk freq: %d.%03dkhz",
2303 (int)(pChip
->cfg
.slow_freq
/ 1000),
2304 (int)(pChip
->cfg
.slow_freq
% 1000));
2308 static const struct command_registration at91sam4_exec_command_handlers
[] = {
2311 .handler
= sam4_handle_gpnvm_command
,
2312 .mode
= COMMAND_EXEC
,
2313 .usage
= "[('clr'|'set'|'show') bitnum]",
2314 .help
= "Without arguments, shows all bits in the gpnvm "
2315 "register. Otherwise, clears, sets, or shows one "
2316 "General Purpose Non-Volatile Memory (gpnvm) bit.",
2320 .handler
= sam4_handle_info_command
,
2321 .mode
= COMMAND_EXEC
,
2322 .help
= "Print information about the current at91sam4 chip"
2323 "and its flash configuration.",
2327 .handler
= sam4_handle_slowclk_command
,
2328 .mode
= COMMAND_EXEC
,
2329 .usage
= "[clock_hz]",
2330 .help
= "Display or set the slowclock frequency "
2331 "(default 32768 Hz).",
2333 COMMAND_REGISTRATION_DONE
2335 static const struct command_registration at91sam4_command_handlers
[] = {
2338 .mode
= COMMAND_ANY
,
2339 .help
= "at91sam4 flash command group",
2341 .chain
= at91sam4_exec_command_handlers
,
2343 COMMAND_REGISTRATION_DONE
2346 struct flash_driver at91sam4_flash
= {
2348 .commands
= at91sam4_command_handlers
,
2349 .flash_bank_command
= sam4_flash_bank_command
,
2350 .erase
= sam4_erase
,
2351 .protect
= sam4_protect
,
2352 .write
= sam4_write
,
2353 .read
= default_flash_read
,
2354 .probe
= sam4_probe
,
2355 .auto_probe
= sam4_auto_probe
,
2356 .erase_check
= default_flash_blank_check
,
2357 .protect_check
= sam4_protect_check
,
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