cda74f9b22f4d5c58a862efc7dee75dd83a59bdb
[openocd.git] / src / flash / nor / at91sam4.c
1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
4 * *
5 * Copyright (C) 2010 by Olaf L√ľke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
7 * *
8 * Copyright (C) 2011 by Olivier Schonken, Jim Norris *
9 * (at91sam3x* & at91sam4 support)* *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
19 * GNU General public License for more details. *
20 * *
21 * You should have received a copy of the GNU General public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
25 ****************************************************************************/
26
27 /* Some of the the lower level code was based on code supplied by
28 * ATMEL under this copyright. */
29
30 /* BEGIN ATMEL COPYRIGHT */
31 /* ----------------------------------------------------------------------------
32 * ATMEL Microcontroller Software Support
33 * ----------------------------------------------------------------------------
34 * Copyright (c) 2009, Atmel Corporation
35 *
36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions are met:
40 *
41 * - Redistributions of source code must retain the above copyright notice,
42 * this list of conditions and the disclaimer below.
43 *
44 * Atmel's name may not be used to endorse or promote products derived from
45 * this software without specific prior written permission.
46 *
47 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
49 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
50 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
52 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
53 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
54 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
55 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
56 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 * ----------------------------------------------------------------------------
58 */
59 /* END ATMEL COPYRIGHT */
60
61 #ifdef HAVE_CONFIG_H
62 #include "config.h"
63 #endif
64
65 #include "imp.h"
66 #include <helper/time_support.h>
67
68 #define REG_NAME_WIDTH (12)
69
70 /* at91sam4s series (has always one flash bank)*/
71 #define FLASH_BANK_BASE_S 0x00400000
72
73 /* at91sam4sd series (two one flash banks), first bank address */
74 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
75 /* at91sam4sd16x, second bank address */
76 #define FLASH_BANK1_BASE_1024K_SD (FLASH_BANK0_BASE_SD+(1024*1024/2))
77 /* at91sam4sd32x, second bank address */
78 #define FLASH_BANK1_BASE_2048K_SD (FLASH_BANK0_BASE_SD+(2048*1024/2))
79
80 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
81 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
82 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
83 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
84 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
85 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
86 /* cmd6 is not present in the at91sam4u4/2/1 data sheet table 19-2 */
87 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
88 #define AT91C_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
89 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
90 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
91 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
92 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
93 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
94 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
95 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
96 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
97
98 #define offset_EFC_FMR 0
99 #define offset_EFC_FCR 4
100 #define offset_EFC_FSR 8
101 #define offset_EFC_FRR 12
102
103 extern struct flash_driver at91sam4_flash;
104
105 static float _tomhz(uint32_t freq_hz)
106 {
107 float f;
108
109 f = ((float)(freq_hz)) / 1000000.0;
110 return f;
111 }
112
113 /* How the chip is configured. */
114 struct sam4_cfg {
115 uint32_t unique_id[4];
116
117 uint32_t slow_freq;
118 uint32_t rc_freq;
119 uint32_t mainosc_freq;
120 uint32_t plla_freq;
121 uint32_t mclk_freq;
122 uint32_t cpu_freq;
123 uint32_t fclk_freq;
124 uint32_t pclk0_freq;
125 uint32_t pclk1_freq;
126 uint32_t pclk2_freq;
127
128
129 #define SAM4_CHIPID_CIDR (0x400E0740)
130 uint32_t CHIPID_CIDR;
131 #define SAM4_CHIPID_EXID (0x400E0744)
132 uint32_t CHIPID_EXID;
133
134 #define SAM4_PMC_BASE (0x400E0400)
135 #define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
136 uint32_t PMC_SCSR;
137 #define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
138 uint32_t PMC_PCSR;
139 #define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
140 uint32_t CKGR_UCKR;
141 #define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
142 uint32_t CKGR_MOR;
143 #define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
144 uint32_t CKGR_MCFR;
145 #define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
146 uint32_t CKGR_PLLAR;
147 #define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
148 uint32_t PMC_MCKR;
149 #define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
150 uint32_t PMC_PCK0;
151 #define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
152 uint32_t PMC_PCK1;
153 #define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
154 uint32_t PMC_PCK2;
155 #define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
156 uint32_t PMC_SR;
157 #define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
158 uint32_t PMC_IMR;
159 #define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
160 uint32_t PMC_FSMR;
161 #define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
162 uint32_t PMC_FSPR;
163 };
164
165 struct sam4_bank_private {
166 int probed;
167 /* DANGER: THERE ARE DRAGONS HERE.. */
168 /* NOTE: If you add more 'ghost' pointers */
169 /* be aware that you must *manually* update */
170 /* these pointers in the function sam4_GetDetails() */
171 /* See the comment "Here there be dragons" */
172
173 /* so we can find the chip we belong to */
174 struct sam4_chip *pChip;
175 /* so we can find the original bank pointer */
176 struct flash_bank *pBank;
177 unsigned bank_number;
178 uint32_t controller_address;
179 uint32_t base_address;
180 uint32_t flash_wait_states;
181 bool present;
182 unsigned size_bytes;
183 unsigned nsectors;
184 unsigned sector_size;
185 unsigned page_size;
186 };
187
188 struct sam4_chip_details {
189 /* THERE ARE DRAGONS HERE.. */
190 /* note: If you add pointers here */
191 /* be careful about them as they */
192 /* may need to be updated inside */
193 /* the function: "sam4_GetDetails() */
194 /* which copy/overwrites the */
195 /* 'runtime' copy of this structure */
196 uint32_t chipid_cidr;
197 const char *name;
198
199 unsigned n_gpnvms;
200 #define SAM4_N_NVM_BITS 3
201 unsigned gpnvm[SAM4_N_NVM_BITS];
202 unsigned total_flash_size;
203 unsigned total_sram_size;
204 unsigned n_banks;
205 #define SAM4_MAX_FLASH_BANKS 2
206 /* these are "initialized" from the global const data */
207 struct sam4_bank_private bank[SAM4_MAX_FLASH_BANKS];
208 };
209
210 struct sam4_chip {
211 struct sam4_chip *next;
212 int probed;
213
214 /* this is "initialized" from the global const structure */
215 struct sam4_chip_details details;
216 struct target *target;
217 struct sam4_cfg cfg;
218 };
219
220
221 struct sam4_reg_list {
222 uint32_t address; size_t struct_offset; const char *name;
223 void (*explain_func)(struct sam4_chip *pInfo);
224 };
225
226 static struct sam4_chip *all_sam4_chips;
227
228 static struct sam4_chip *get_current_sam4(struct command_context *cmd_ctx)
229 {
230 struct target *t;
231 static struct sam4_chip *p;
232
233 t = get_current_target(cmd_ctx);
234 if (!t) {
235 command_print(cmd_ctx, "No current target?");
236 return NULL;
237 }
238
239 p = all_sam4_chips;
240 if (!p) {
241 /* this should not happen */
242 /* the command is not registered until the chip is created? */
243 command_print(cmd_ctx, "No SAM4 chips exist?");
244 return NULL;
245 }
246
247 while (p) {
248 if (p->target == t)
249 return p;
250 p = p->next;
251 }
252 command_print(cmd_ctx, "Cannot find SAM4 chip?");
253 return NULL;
254 }
255
256 /*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
257 /*The lockregions are 8KB per lock region, with a 1024KB device having 128 lock regions. */
258 /*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
259 /*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
260
261 /* these are used to *initialize* the "pChip->details" structure. */
262 static const struct sam4_chip_details all_sam4_details[] = {
263 /* Start at91sam4s* series */
264 /*atsam4s16c - LQFP100/BGA100*/
265 {
266 .chipid_cidr = 0x28AC0CE0,
267 .name = "at91sam4s16c",
268 .total_flash_size = 1024 * 1024,
269 .total_sram_size = 128 * 1024,
270 .n_gpnvms = 2,
271 .n_banks = 1,
272 {
273 /* .bank[0] = {*/
274 {
275 .probed = 0,
276 .pChip = NULL,
277 .pBank = NULL,
278 .bank_number = 0,
279 .base_address = FLASH_BANK_BASE_S,
280 .controller_address = 0x400e0a00,
281 .flash_wait_states = 6, /* workaround silicon bug */
282 .present = 1,
283 .size_bytes = 1024 * 1024,
284 .nsectors = 128,
285 .sector_size = 8192,
286 .page_size = 512,
287 },
288 /* .bank[1] = {*/
289 {
290 .present = 0,
291 .probed = 0,
292 .bank_number = 1,
293
294 },
295 },
296 },
297 /*atsam4s16b - LQFP64/QFN64*/
298 {
299 .chipid_cidr = 0x289C0CE0,
300 .name = "at91sam4s16b",
301 .total_flash_size = 1024 * 1024,
302 .total_sram_size = 128 * 1024,
303 .n_gpnvms = 2,
304 .n_banks = 1,
305 {
306 /* .bank[0] = {*/
307 {
308 .probed = 0,
309 .pChip = NULL,
310 .pBank = NULL,
311 .bank_number = 0,
312 .base_address = FLASH_BANK_BASE_S,
313 .controller_address = 0x400e0a00,
314 .flash_wait_states = 6, /* workaround silicon bug */
315 .present = 1,
316 .size_bytes = 1024 * 1024,
317 .nsectors = 128,
318 .sector_size = 8192,
319 .page_size = 512,
320 },
321 /* .bank[1] = {*/
322 {
323 .present = 0,
324 .probed = 0,
325 .bank_number = 1,
326
327 },
328 },
329 },
330 /*atsam4s16a - LQFP48/QFN48*/
331 {
332 .chipid_cidr = 0x288C0CE0,
333 .name = "at91sam4s16a",
334 .total_flash_size = 1024 * 1024,
335 .total_sram_size = 128 * 1024,
336 .n_gpnvms = 2,
337 .n_banks = 1,
338 {
339 /* .bank[0] = {*/
340 {
341 .probed = 0,
342 .pChip = NULL,
343 .pBank = NULL,
344 .bank_number = 0,
345 .base_address = FLASH_BANK_BASE_S,
346 .controller_address = 0x400e0a00,
347 .flash_wait_states = 6, /* workaround silicon bug */
348 .present = 1,
349 .size_bytes = 1024 * 1024,
350 .nsectors = 128,
351 .sector_size = 8192,
352 .page_size = 512,
353 },
354 /* .bank[1] = {*/
355 {
356 .present = 0,
357 .probed = 0,
358 .bank_number = 1,
359
360 },
361 },
362 },
363 /*atsam4s8c - LQFP100/BGA100*/
364 {
365 .chipid_cidr = 0x28AC0AE0,
366 .name = "at91sam4s8c",
367 .total_flash_size = 512 * 1024,
368 .total_sram_size = 128 * 1024,
369 .n_gpnvms = 2,
370 .n_banks = 1,
371 {
372 /* .bank[0] = {*/
373 {
374 .probed = 0,
375 .pChip = NULL,
376 .pBank = NULL,
377 .bank_number = 0,
378 .base_address = FLASH_BANK_BASE_S,
379 .controller_address = 0x400e0a00,
380 .flash_wait_states = 6, /* workaround silicon bug */
381 .present = 1,
382 .size_bytes = 512 * 1024,
383 .nsectors = 64,
384 .sector_size = 8192,
385 .page_size = 512,
386 },
387 /* .bank[1] = {*/
388 {
389 .present = 0,
390 .probed = 0,
391 .bank_number = 1,
392
393 },
394 },
395 },
396 /*atsam4s8b - LQFP64/BGA64*/
397 {
398 .chipid_cidr = 0x289C0AE0,
399 .name = "at91sam4s8b",
400 .total_flash_size = 512 * 1024,
401 .total_sram_size = 128 * 1024,
402 .n_gpnvms = 2,
403 .n_banks = 1,
404 {
405 /* .bank[0] = {*/
406 {
407 .probed = 0,
408 .pChip = NULL,
409 .pBank = NULL,
410 .bank_number = 0,
411 .base_address = FLASH_BANK_BASE_S,
412 .controller_address = 0x400e0a00,
413 .flash_wait_states = 6, /* workaround silicon bug */
414 .present = 1,
415 .size_bytes = 512 * 1024,
416 .nsectors = 64,
417 .sector_size = 8192,
418 .page_size = 512,
419 },
420 /* .bank[1] = {*/
421 {
422 .present = 0,
423 .probed = 0,
424 .bank_number = 1,
425
426 },
427 },
428 },
429 /*atsam4s8a - LQFP48/BGA48*/
430 {
431 .chipid_cidr = 0x288C0AE0,
432 .name = "at91sam4s8a",
433 .total_flash_size = 512 * 1024,
434 .total_sram_size = 128 * 1024,
435 .n_gpnvms = 2,
436 .n_banks = 1,
437 {
438 /* .bank[0] = {*/
439 {
440 .probed = 0,
441 .pChip = NULL,
442 .pBank = NULL,
443 .bank_number = 0,
444 .base_address = FLASH_BANK_BASE_S,
445 .controller_address = 0x400e0a00,
446 .flash_wait_states = 6, /* workaround silicon bug */
447 .present = 1,
448 .size_bytes = 512 * 1024,
449 .nsectors = 64,
450 .sector_size = 8192,
451 .page_size = 512,
452 },
453 /* .bank[1] = {*/
454 {
455 .present = 0,
456 .probed = 0,
457 .bank_number = 1,
458
459 },
460 },
461 },
462
463 /*at91sam4sd32c*/
464 {
465 .chipid_cidr = 0x29a70ee0,
466 .name = "at91sam4sd32c",
467 .total_flash_size = 2048 * 1024,
468 .total_sram_size = 160 * 1024,
469 .n_gpnvms = 3,
470 .n_banks = 2,
471
472 /* .bank[0] = { */
473 {
474 {
475 .probed = 0,
476 .pChip = NULL,
477 .pBank = NULL,
478 .bank_number = 0,
479 .base_address = FLASH_BANK0_BASE_SD,
480 .controller_address = 0x400e0a00,
481 .flash_wait_states = 6, /* workaround silicon bug */
482 .present = 1,
483 .size_bytes = 1024 * 1024,
484 .nsectors = 128,
485 .sector_size = 8192,
486 .page_size = 512,
487 },
488
489 /* .bank[1] = { */
490 {
491 .probed = 0,
492 .pChip = NULL,
493 .pBank = NULL,
494 .bank_number = 1,
495 .base_address = FLASH_BANK1_BASE_2048K_SD,
496 .controller_address = 0x400e0c00,
497 .flash_wait_states = 6, /* workaround silicon bug */
498 .present = 1,
499 .size_bytes = 1024 * 1024,
500 .nsectors = 128,
501 .sector_size = 8192,
502 .page_size = 512,
503 },
504 },
505 },
506
507 /* terminate */
508 {
509 .chipid_cidr = 0,
510 .name = NULL,
511 }
512 };
513
514 /* Globals above */
515 /***********************************************************************
516 **********************************************************************
517 **********************************************************************
518 **********************************************************************
519 **********************************************************************
520 **********************************************************************/
521 /* *ATMEL* style code - from the SAM4 driver code */
522
523 /**
524 * Get the current status of the EEFC and
525 * the value of some status bits (LOCKE, PROGE).
526 * @param pPrivate - info about the bank
527 * @param v - result goes here
528 */
529 static int EFC_GetStatus(struct sam4_bank_private *pPrivate, uint32_t *v)
530 {
531 int r;
532 r = target_read_u32(pPrivate->pChip->target,
533 pPrivate->controller_address + offset_EFC_FSR,
534 v);
535 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
536 (unsigned int)(*v),
537 ((unsigned int)((*v >> 2) & 1)),
538 ((unsigned int)((*v >> 1) & 1)),
539 ((unsigned int)((*v >> 0) & 1)));
540
541 return r;
542 }
543
544 /**
545 * Get the result of the last executed command.
546 * @param pPrivate - info about the bank
547 * @param v - result goes here
548 */
549 static int EFC_GetResult(struct sam4_bank_private *pPrivate, uint32_t *v)
550 {
551 int r;
552 uint32_t rv;
553 r = target_read_u32(pPrivate->pChip->target,
554 pPrivate->controller_address + offset_EFC_FRR,
555 &rv);
556 if (v)
557 *v = rv;
558 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
559 return r;
560 }
561
562 static int EFC_StartCommand(struct sam4_bank_private *pPrivate,
563 unsigned command, unsigned argument)
564 {
565 uint32_t n, v;
566 int r;
567 int retry;
568
569 retry = 0;
570 do_retry:
571
572 /* Check command & argument */
573 switch (command) {
574
575 case AT91C_EFC_FCMD_WP:
576 case AT91C_EFC_FCMD_WPL:
577 case AT91C_EFC_FCMD_EWP:
578 case AT91C_EFC_FCMD_EWPL:
579 /* case AT91C_EFC_FCMD_EPL: */
580 case AT91C_EFC_FCMD_EPA:
581 case AT91C_EFC_FCMD_SLB:
582 case AT91C_EFC_FCMD_CLB:
583 n = (pPrivate->size_bytes / pPrivate->page_size);
584 if (argument >= n)
585 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
586 break;
587
588 case AT91C_EFC_FCMD_SFB:
589 case AT91C_EFC_FCMD_CFB:
590 if (argument >= pPrivate->pChip->details.n_gpnvms) {
591 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
592 pPrivate->pChip->details.n_gpnvms);
593 }
594 break;
595
596 case AT91C_EFC_FCMD_GETD:
597 case AT91C_EFC_FCMD_EA:
598 case AT91C_EFC_FCMD_GLB:
599 case AT91C_EFC_FCMD_GFB:
600 case AT91C_EFC_FCMD_STUI:
601 case AT91C_EFC_FCMD_SPUI:
602 if (argument != 0)
603 LOG_ERROR("Argument is meaningless for cmd: %d", command);
604 break;
605 default:
606 LOG_ERROR("Unknown command %d", command);
607 break;
608 }
609
610 if (command == AT91C_EFC_FCMD_SPUI) {
611 /* this is a very special situation. */
612 /* Situation (1) - error/retry - see below */
613 /* And we are being called recursively */
614 /* Situation (2) - normal, finished reading unique id */
615 } else {
616 /* it should be "ready" */
617 EFC_GetStatus(pPrivate, &v);
618 if (v & 1) {
619 /* then it is ready */
620 /* we go on */
621 } else {
622 if (retry) {
623 /* we have done this before */
624 /* the controller is not responding. */
625 LOG_ERROR("flash controller(%d) is not ready! Error",
626 pPrivate->bank_number);
627 return ERROR_FAIL;
628 } else {
629 retry++;
630 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
631 pPrivate->bank_number);
632 /* we do that by issuing the *STOP* command */
633 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
634 /* above is recursive, and further recursion is blocked by */
635 /* if (command == AT91C_EFC_FCMD_SPUI) above */
636 goto do_retry;
637 }
638 }
639 }
640
641 v = (0x5A << 24) | (argument << 8) | command;
642 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
643 r = target_write_u32(pPrivate->pBank->target,
644 pPrivate->controller_address + offset_EFC_FCR, v);
645 if (r != ERROR_OK)
646 LOG_DEBUG("Error Write failed");
647 return r;
648 }
649
650 /**
651 * Performs the given command and wait until its completion (or an error).
652 * @param pPrivate - info about the bank
653 * @param command - Command to perform.
654 * @param argument - Optional command argument.
655 * @param status - put command status bits here
656 */
657 static int EFC_PerformCommand(struct sam4_bank_private *pPrivate,
658 unsigned command,
659 unsigned argument,
660 uint32_t *status)
661 {
662
663 int r;
664 uint32_t v;
665 long long ms_now, ms_end;
666
667 /* default */
668 if (status)
669 *status = 0;
670
671 r = EFC_StartCommand(pPrivate, command, argument);
672 if (r != ERROR_OK)
673 return r;
674
675 ms_end = 10000 + timeval_ms();
676
677 do {
678 r = EFC_GetStatus(pPrivate, &v);
679 if (r != ERROR_OK)
680 return r;
681 ms_now = timeval_ms();
682 if (ms_now > ms_end) {
683 /* error */
684 LOG_ERROR("Command timeout");
685 return ERROR_FAIL;
686 }
687 } while ((v & 1) == 0);
688
689 /* error bits.. */
690 if (status)
691 *status = (v & 0x6);
692 return ERROR_OK;
693
694 }
695
696 /**
697 * Read the unique ID.
698 * @param pPrivate - info about the bank
699 * The unique ID is stored in the 'pPrivate' structure.
700 */
701 static int FLASHD_ReadUniqueID(struct sam4_bank_private *pPrivate)
702 {
703 int r;
704 uint32_t v;
705 int x;
706 /* assume 0 */
707 pPrivate->pChip->cfg.unique_id[0] = 0;
708 pPrivate->pChip->cfg.unique_id[1] = 0;
709 pPrivate->pChip->cfg.unique_id[2] = 0;
710 pPrivate->pChip->cfg.unique_id[3] = 0;
711
712 LOG_DEBUG("Begin");
713 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
714 if (r < 0)
715 return r;
716
717 for (x = 0; x < 4; x++) {
718 r = target_read_u32(pPrivate->pChip->target,
719 pPrivate->pBank->base + (x * 4),
720 &v);
721 if (r < 0)
722 return r;
723 pPrivate->pChip->cfg.unique_id[x] = v;
724 }
725
726 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
727 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
728 r,
729 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
730 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
731 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
732 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
733 return r;
734
735 }
736
737 /**
738 * Erases the entire flash.
739 * @param pPrivate - the info about the bank.
740 */
741 static int FLASHD_EraseEntireBank(struct sam4_bank_private *pPrivate)
742 {
743 LOG_DEBUG("Here");
744 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
745 }
746
747 /**
748 * Erases the entire flash.
749 * @param pPrivate - the info about the bank.
750 */
751 static int FLASHD_ErasePages(struct sam4_bank_private *pPrivate,
752 int firstPage,
753 int numPages,
754 uint32_t *status)
755 {
756 LOG_DEBUG("Here");
757 uint8_t erasePages;
758 switch (numPages) {
759 case 4:
760 erasePages = 0x00;
761 break;
762 case 8:
763 erasePages = 0x01;
764 break;
765 case 16:
766 erasePages = 0x02;
767 break;
768 case 32:
769 erasePages = 0x03;
770 break;
771 default:
772 erasePages = 0x00;
773 break;
774 }
775
776 /* AT91C_EFC_FCMD_EPA
777 * According to the datasheet FARG[15:2] defines the page from which
778 * the erase will start.This page must be modulo 4, 8, 16 or 32
779 * according to the number of pages to erase. FARG[1:0] defines the
780 * number of pages to be erased. Previously (firstpage << 2) was used
781 * to conform to this, seems it should not be shifted...
782 */
783 return EFC_PerformCommand(pPrivate,
784 /* send Erase Page */
785 AT91C_EFC_FCMD_EPA,
786 (firstPage) | erasePages,
787 status);
788 }
789
790 /**
791 * Gets current GPNVM state.
792 * @param pPrivate - info about the bank.
793 * @param gpnvm - GPNVM bit index.
794 * @param puthere - result stored here.
795 */
796 /* ------------------------------------------------------------------------------ */
797 static int FLASHD_GetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
798 {
799 uint32_t v;
800 int r;
801
802 LOG_DEBUG("Here");
803 if (pPrivate->bank_number != 0) {
804 LOG_ERROR("GPNVM only works with Bank0");
805 return ERROR_FAIL;
806 }
807
808 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
809 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
810 gpnvm, pPrivate->pChip->details.n_gpnvms);
811 return ERROR_FAIL;
812 }
813
814 /* Get GPNVMs status */
815 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
816 if (r != ERROR_OK) {
817 LOG_ERROR("Failed");
818 return r;
819 }
820
821 r = EFC_GetResult(pPrivate, &v);
822
823 if (puthere) {
824 /* Check if GPNVM is set */
825 /* get the bit and make it a 0/1 */
826 *puthere = (v >> gpnvm) & 1;
827 }
828
829 return r;
830 }
831
832 /**
833 * Clears the selected GPNVM bit.
834 * @param pPrivate info about the bank
835 * @param gpnvm GPNVM index.
836 * @returns 0 if successful; otherwise returns an error code.
837 */
838 static int FLASHD_ClrGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
839 {
840 int r;
841 unsigned v;
842
843 LOG_DEBUG("Here");
844 if (pPrivate->bank_number != 0) {
845 LOG_ERROR("GPNVM only works with Bank0");
846 return ERROR_FAIL;
847 }
848
849 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
850 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
851 gpnvm, pPrivate->pChip->details.n_gpnvms);
852 return ERROR_FAIL;
853 }
854
855 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
856 if (r != ERROR_OK) {
857 LOG_DEBUG("Failed: %d", r);
858 return r;
859 }
860 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
861 LOG_DEBUG("End: %d", r);
862 return r;
863 }
864
865 /**
866 * Sets the selected GPNVM bit.
867 * @param pPrivate info about the bank
868 * @param gpnvm GPNVM index.
869 */
870 static int FLASHD_SetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
871 {
872 int r;
873 unsigned v;
874
875 if (pPrivate->bank_number != 0) {
876 LOG_ERROR("GPNVM only works with Bank0");
877 return ERROR_FAIL;
878 }
879
880 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
881 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
882 gpnvm, pPrivate->pChip->details.n_gpnvms);
883 return ERROR_FAIL;
884 }
885
886 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
887 if (r != ERROR_OK)
888 return r;
889 if (v) {
890 /* already set */
891 r = ERROR_OK;
892 } else {
893 /* set it */
894 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
895 }
896 return r;
897 }
898
899 /**
900 * Returns a bit field (at most 64) of locked regions within a page.
901 * @param pPrivate info about the bank
902 * @param v where to store locked bits
903 */
904 static int FLASHD_GetLockBits(struct sam4_bank_private *pPrivate, uint32_t *v)
905 {
906 int r;
907 LOG_DEBUG("Here");
908 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
909 if (r == ERROR_OK) {
910 EFC_GetResult(pPrivate, v);
911 EFC_GetResult(pPrivate, v);
912 EFC_GetResult(pPrivate, v);
913 r = EFC_GetResult(pPrivate, v);
914 }
915 LOG_DEBUG("End: %d", r);
916 return r;
917 }
918
919 /**
920 * Unlocks all the regions in the given address range.
921 * @param pPrivate info about the bank
922 * @param start_sector first sector to unlock
923 * @param end_sector last (inclusive) to unlock
924 */
925
926 static int FLASHD_Unlock(struct sam4_bank_private *pPrivate,
927 unsigned start_sector,
928 unsigned end_sector)
929 {
930 int r;
931 uint32_t status;
932 uint32_t pg;
933 uint32_t pages_per_sector;
934
935 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
936
937 /* Unlock all pages */
938 while (start_sector <= end_sector) {
939 pg = start_sector * pages_per_sector;
940
941 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
942 if (r != ERROR_OK)
943 return r;
944 start_sector++;
945 }
946
947 return ERROR_OK;
948 }
949
950 /**
951 * Locks regions
952 * @param pPrivate - info about the bank
953 * @param start_sector - first sector to lock
954 * @param end_sector - last sector (inclusive) to lock
955 */
956 static int FLASHD_Lock(struct sam4_bank_private *pPrivate,
957 unsigned start_sector,
958 unsigned end_sector)
959 {
960 uint32_t status;
961 uint32_t pg;
962 uint32_t pages_per_sector;
963 int r;
964
965 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
966
967 /* Lock all pages */
968 while (start_sector <= end_sector) {
969 pg = start_sector * pages_per_sector;
970
971 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
972 if (r != ERROR_OK)
973 return r;
974 start_sector++;
975 }
976 return ERROR_OK;
977 }
978
979 /****** END SAM4 CODE ********/
980
981 /* begin helpful debug code */
982 /* print the fieldname, the field value, in dec & hex, and return field value */
983 static uint32_t sam4_reg_fieldname(struct sam4_chip *pChip,
984 const char *regname,
985 uint32_t value,
986 unsigned shift,
987 unsigned width)
988 {
989 uint32_t v;
990 int hwidth, dwidth;
991
992
993 /* extract the field */
994 v = value >> shift;
995 v = v & ((1 << width)-1);
996 if (width <= 16) {
997 hwidth = 4;
998 dwidth = 5;
999 } else {
1000 hwidth = 8;
1001 dwidth = 12;
1002 }
1003
1004 /* show the basics */
1005 LOG_USER_N("\t%*s: %*" PRId32 " [0x%0*" PRIx32 "] ",
1006 REG_NAME_WIDTH, regname,
1007 dwidth, v,
1008 hwidth, v);
1009 return v;
1010 }
1011
1012 static const char _unknown[] = "unknown";
1013 static const char *const eproc_names[] = {
1014 _unknown, /* 0 */
1015 "arm946es", /* 1 */
1016 "arm7tdmi", /* 2 */
1017 "cortex-m3", /* 3 */
1018 "arm920t", /* 4 */
1019 "arm926ejs", /* 5 */
1020 "cortex-a5", /* 6 */
1021 "cortex-m4", /* 7 */
1022 _unknown, /* 8 */
1023 _unknown, /* 9 */
1024 _unknown, /* 10 */
1025 _unknown, /* 11 */
1026 _unknown, /* 12 */
1027 _unknown, /* 13 */
1028 _unknown, /* 14 */
1029 _unknown, /* 15 */
1030 };
1031
1032 #define nvpsize2 nvpsize /* these two tables are identical */
1033 static const char *const nvpsize[] = {
1034 "none", /* 0 */
1035 "8K bytes", /* 1 */
1036 "16K bytes", /* 2 */
1037 "32K bytes", /* 3 */
1038 _unknown, /* 4 */
1039 "64K bytes", /* 5 */
1040 _unknown, /* 6 */
1041 "128K bytes", /* 7 */
1042 _unknown, /* 8 */
1043 "256K bytes", /* 9 */
1044 "512K bytes", /* 10 */
1045 _unknown, /* 11 */
1046 "1024K bytes", /* 12 */
1047 _unknown, /* 13 */
1048 "2048K bytes", /* 14 */
1049 _unknown, /* 15 */
1050 };
1051
1052 static const char *const sramsize[] = {
1053 "48K Bytes", /* 0 */
1054 "1K Bytes", /* 1 */
1055 "2K Bytes", /* 2 */
1056 "6K Bytes", /* 3 */
1057 "112K Bytes", /* 4 */
1058 "4K Bytes", /* 5 */
1059 "80K Bytes", /* 6 */
1060 "160K Bytes", /* 7 */
1061 "8K Bytes", /* 8 */
1062 "16K Bytes", /* 9 */
1063 "32K Bytes", /* 10 */
1064 "64K Bytes", /* 11 */
1065 "128K Bytes", /* 12 */
1066 "256K Bytes", /* 13 */
1067 "96K Bytes", /* 14 */
1068 "512K Bytes", /* 15 */
1069
1070 };
1071
1072 static const struct archnames { unsigned value; const char *name; } archnames[] = {
1073 { 0x19, "AT91SAM9xx Series" },
1074 { 0x29, "AT91SAM9XExx Series" },
1075 { 0x34, "AT91x34 Series" },
1076 { 0x37, "CAP7 Series" },
1077 { 0x39, "CAP9 Series" },
1078 { 0x3B, "CAP11 Series" },
1079 { 0x40, "AT91x40 Series" },
1080 { 0x42, "AT91x42 Series" },
1081 { 0x55, "AT91x55 Series" },
1082 { 0x60, "AT91SAM7Axx Series" },
1083 { 0x61, "AT91SAM7AQxx Series" },
1084 { 0x63, "AT91x63 Series" },
1085 { 0x70, "AT91SAM7Sxx Series" },
1086 { 0x71, "AT91SAM7XCxx Series" },
1087 { 0x72, "AT91SAM7SExx Series" },
1088 { 0x73, "AT91SAM7Lxx Series" },
1089 { 0x75, "AT91SAM7Xxx Series" },
1090 { 0x76, "AT91SAM7SLxx Series" },
1091 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1092 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1093 { 0x83, "ATSAM3A/SAM4A xC Series (100-pin version)"},
1094 { 0x84, "ATSAM3X/SAM4X xC Series (100-pin version)"},
1095 { 0x85, "ATSAM3X/SAM4X xE Series (144-pin version)"},
1096 { 0x86, "ATSAM3X/SAM4X xG Series (208/217-pin version)" },
1097 { 0x88, "ATSAM3S/SAM4S xA Series (48-pin version)" },
1098 { 0x89, "ATSAM3S/SAM4S xB Series (64-pin version)" },
1099 { 0x8A, "ATSAM3S/SAM4S xC Series (100-pin version)"},
1100 { 0x92, "AT91x92 Series" },
1101 { 0x93, "ATSAM3NxA Series (48-pin version)" },
1102 { 0x94, "ATSAM3NxB Series (64-pin version)" },
1103 { 0x95, "ATSAM3NxC Series (100-pin version)" },
1104 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
1105 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
1106 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
1107 { 0xA5, "ATSAM5A" },
1108 { 0xF0, "AT75Cxx Series" },
1109 { -1, NULL },
1110 };
1111
1112 static const char *const nvptype[] = {
1113 "rom", /* 0 */
1114 "romless or onchip flash", /* 1 */
1115 "embedded flash memory",/* 2 */
1116 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
1117 "sram emulating flash", /* 4 */
1118 _unknown, /* 5 */
1119 _unknown, /* 6 */
1120 _unknown, /* 7 */
1121 };
1122
1123 static const char *_yes_or_no(uint32_t v)
1124 {
1125 if (v)
1126 return "YES";
1127 else
1128 return "NO";
1129 }
1130
1131 static const char *const _rc_freq[] = {
1132 "4 MHz", "8 MHz", "12 MHz", "reserved"
1133 };
1134
1135 static void sam4_explain_ckgr_mor(struct sam4_chip *pChip)
1136 {
1137 uint32_t v;
1138 uint32_t rcen;
1139
1140 v = sam4_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
1141 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
1142 v = sam4_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
1143 LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
1144 rcen = sam4_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
1145 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
1146 v = sam4_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
1147 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
1148
1149 pChip->cfg.rc_freq = 0;
1150 if (rcen) {
1151 switch (v) {
1152 default:
1153 pChip->cfg.rc_freq = 0;
1154 break;
1155 case 0:
1156 pChip->cfg.rc_freq = 4 * 1000 * 1000;
1157 break;
1158 case 1:
1159 pChip->cfg.rc_freq = 8 * 1000 * 1000;
1160 break;
1161 case 2:
1162 pChip->cfg.rc_freq = 12 * 1000 * 1000;
1163 break;
1164 }
1165 }
1166
1167 v = sam4_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
1168 LOG_USER("(startup clks, time= %f uSecs)",
1169 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
1170 v = sam4_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
1171 LOG_USER("(mainosc source: %s)",
1172 v ? "external xtal" : "internal RC");
1173
1174 v = sam4_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
1175 LOG_USER("(clock failure enabled: %s)",
1176 _yes_or_no(v));
1177 }
1178
1179 static void sam4_explain_chipid_cidr(struct sam4_chip *pChip)
1180 {
1181 int x;
1182 uint32_t v;
1183 const char *cp;
1184
1185 sam4_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
1186 LOG_USER_N("\n");
1187
1188 v = sam4_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
1189 LOG_USER("%s", eproc_names[v]);
1190
1191 v = sam4_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
1192 LOG_USER("%s", nvpsize[v]);
1193
1194 v = sam4_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
1195 LOG_USER("%s", nvpsize2[v]);
1196
1197 v = sam4_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
1198 LOG_USER("%s", sramsize[v]);
1199
1200 v = sam4_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
1201 cp = _unknown;
1202 for (x = 0; archnames[x].name; x++) {
1203 if (v == archnames[x].value) {
1204 cp = archnames[x].name;
1205 break;
1206 }
1207 }
1208
1209 LOG_USER("%s", cp);
1210
1211 v = sam4_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
1212 LOG_USER("%s", nvptype[v]);
1213
1214 v = sam4_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
1215 LOG_USER("(exists: %s)", _yes_or_no(v));
1216 }
1217
1218 static void sam4_explain_ckgr_mcfr(struct sam4_chip *pChip)
1219 {
1220 uint32_t v;
1221
1222 v = sam4_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
1223 LOG_USER("(main ready: %s)", _yes_or_no(v));
1224
1225 v = sam4_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
1226
1227 v = (v * pChip->cfg.slow_freq) / 16;
1228 pChip->cfg.mainosc_freq = v;
1229
1230 LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
1231 _tomhz(v),
1232 (uint32_t)(pChip->cfg.slow_freq / 1000),
1233 (uint32_t)(pChip->cfg.slow_freq % 1000));
1234 }
1235
1236 static void sam4_explain_ckgr_plla(struct sam4_chip *pChip)
1237 {
1238 uint32_t mula, diva;
1239
1240 diva = sam4_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
1241 LOG_USER_N("\n");
1242 mula = sam4_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
1243 LOG_USER_N("\n");
1244 pChip->cfg.plla_freq = 0;
1245 if (mula == 0)
1246 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
1247 else if (diva == 0)
1248 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
1249 else if (diva >= 1) {
1250 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
1251 LOG_USER("\tPLLA Freq: %3.03f MHz",
1252 _tomhz(pChip->cfg.plla_freq));
1253 }
1254 }
1255
1256 static void sam4_explain_mckr(struct sam4_chip *pChip)
1257 {
1258 uint32_t css, pres, fin = 0;
1259 int pdiv = 0;
1260 const char *cp = NULL;
1261
1262 css = sam4_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
1263 switch (css & 3) {
1264 case 0:
1265 fin = pChip->cfg.slow_freq;
1266 cp = "slowclk";
1267 break;
1268 case 1:
1269 fin = pChip->cfg.mainosc_freq;
1270 cp = "mainosc";
1271 break;
1272 case 2:
1273 fin = pChip->cfg.plla_freq;
1274 cp = "plla";
1275 break;
1276 case 3:
1277 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
1278 fin = 480 * 1000 * 1000;
1279 cp = "upll";
1280 } else {
1281 fin = 0;
1282 cp = "upll (*ERROR* UPLL is disabled)";
1283 }
1284 break;
1285 default:
1286 assert(0);
1287 break;
1288 }
1289
1290 LOG_USER("%s (%3.03f Mhz)",
1291 cp,
1292 _tomhz(fin));
1293 pres = sam4_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
1294 switch (pres & 0x07) {
1295 case 0:
1296 pdiv = 1;
1297 cp = "selected clock";
1298 break;
1299 case 1:
1300 pdiv = 2;
1301 cp = "clock/2";
1302 break;
1303 case 2:
1304 pdiv = 4;
1305 cp = "clock/4";
1306 break;
1307 case 3:
1308 pdiv = 8;
1309 cp = "clock/8";
1310 break;
1311 case 4:
1312 pdiv = 16;
1313 cp = "clock/16";
1314 break;
1315 case 5:
1316 pdiv = 32;
1317 cp = "clock/32";
1318 break;
1319 case 6:
1320 pdiv = 64;
1321 cp = "clock/64";
1322 break;
1323 case 7:
1324 pdiv = 6;
1325 cp = "clock/6";
1326 break;
1327 default:
1328 assert(0);
1329 break;
1330 }
1331 LOG_USER("(%s)", cp);
1332 fin = fin / pdiv;
1333 /* sam4 has a *SINGLE* clock - */
1334 /* other at91 series parts have divisors for these. */
1335 pChip->cfg.cpu_freq = fin;
1336 pChip->cfg.mclk_freq = fin;
1337 pChip->cfg.fclk_freq = fin;
1338 LOG_USER("\t\tResult CPU Freq: %3.03f",
1339 _tomhz(fin));
1340 }
1341
1342 #if 0
1343 static struct sam4_chip *target2sam4(struct target *pTarget)
1344 {
1345 struct sam4_chip *pChip;
1346
1347 if (pTarget == NULL)
1348 return NULL;
1349
1350 pChip = all_sam4_chips;
1351 while (pChip) {
1352 if (pChip->target == pTarget)
1353 break; /* return below */
1354 else
1355 pChip = pChip->next;
1356 }
1357 return pChip;
1358 }
1359 #endif
1360
1361 static uint32_t *sam4_get_reg_ptr(struct sam4_cfg *pCfg, const struct sam4_reg_list *pList)
1362 {
1363 /* this function exists to help */
1364 /* keep funky offsetof() errors */
1365 /* and casting from causing bugs */
1366
1367 /* By using prototypes - we can detect what would */
1368 /* be casting errors. */
1369
1370 return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
1371 }
1372
1373
1374 #define SAM4_ENTRY(NAME, FUNC) { .address = SAM4_ ## NAME, .struct_offset = offsetof( \
1375 struct sam4_cfg, \
1376 NAME), # NAME, FUNC }
1377 static const struct sam4_reg_list sam4_all_regs[] = {
1378 SAM4_ENTRY(CKGR_MOR, sam4_explain_ckgr_mor),
1379 SAM4_ENTRY(CKGR_MCFR, sam4_explain_ckgr_mcfr),
1380 SAM4_ENTRY(CKGR_PLLAR, sam4_explain_ckgr_plla),
1381 SAM4_ENTRY(CKGR_UCKR, NULL),
1382 SAM4_ENTRY(PMC_FSMR, NULL),
1383 SAM4_ENTRY(PMC_FSPR, NULL),
1384 SAM4_ENTRY(PMC_IMR, NULL),
1385 SAM4_ENTRY(PMC_MCKR, sam4_explain_mckr),
1386 SAM4_ENTRY(PMC_PCK0, NULL),
1387 SAM4_ENTRY(PMC_PCK1, NULL),
1388 SAM4_ENTRY(PMC_PCK2, NULL),
1389 SAM4_ENTRY(PMC_PCSR, NULL),
1390 SAM4_ENTRY(PMC_SCSR, NULL),
1391 SAM4_ENTRY(PMC_SR, NULL),
1392 SAM4_ENTRY(CHIPID_CIDR, sam4_explain_chipid_cidr),
1393 SAM4_ENTRY(CHIPID_EXID, NULL),
1394 /* TERMINATE THE LIST */
1395 { .name = NULL }
1396 };
1397 #undef SAM4_ENTRY
1398
1399 static struct sam4_bank_private *get_sam4_bank_private(struct flash_bank *bank)
1400 {
1401 return bank->driver_priv;
1402 }
1403
1404 /**
1405 * Given a pointer to where it goes in the structure,
1406 * determine the register name, address from the all registers table.
1407 */
1408 static const struct sam4_reg_list *sam4_GetReg(struct sam4_chip *pChip, uint32_t *goes_here)
1409 {
1410 const struct sam4_reg_list *pReg;
1411
1412 pReg = &(sam4_all_regs[0]);
1413 while (pReg->name) {
1414 uint32_t *pPossible;
1415
1416 /* calculate where this one go.. */
1417 /* it is "possibly" this register. */
1418
1419 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
1420
1421 /* well? Is it this register */
1422 if (pPossible == goes_here) {
1423 /* Jump for joy! */
1424 return pReg;
1425 }
1426
1427 /* next... */
1428 pReg++;
1429 }
1430 /* This is *TOTAL*PANIC* - we are totally screwed. */
1431 LOG_ERROR("INVALID SAM4 REGISTER");
1432 return NULL;
1433 }
1434
1435 static int sam4_ReadThisReg(struct sam4_chip *pChip, uint32_t *goes_here)
1436 {
1437 const struct sam4_reg_list *pReg;
1438 int r;
1439
1440 pReg = sam4_GetReg(pChip, goes_here);
1441 if (!pReg)
1442 return ERROR_FAIL;
1443
1444 r = target_read_u32(pChip->target, pReg->address, goes_here);
1445 if (r != ERROR_OK) {
1446 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d",
1447 pReg->name, (unsigned)(pReg->address), r);
1448 }
1449 return r;
1450 }
1451
1452 static int sam4_ReadAllRegs(struct sam4_chip *pChip)
1453 {
1454 int r;
1455 const struct sam4_reg_list *pReg;
1456
1457 pReg = &(sam4_all_regs[0]);
1458 while (pReg->name) {
1459 r = sam4_ReadThisReg(pChip,
1460 sam4_get_reg_ptr(&(pChip->cfg), pReg));
1461 if (r != ERROR_OK) {
1462 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Error: %d",
1463 pReg->name, ((unsigned)(pReg->address)), r);
1464 return r;
1465 }
1466 pReg++;
1467 }
1468
1469 return ERROR_OK;
1470 }
1471
1472 static int sam4_GetInfo(struct sam4_chip *pChip)
1473 {
1474 const struct sam4_reg_list *pReg;
1475 uint32_t regval;
1476
1477 pReg = &(sam4_all_regs[0]);
1478 while (pReg->name) {
1479 /* display all regs */
1480 LOG_DEBUG("Start: %s", pReg->name);
1481 regval = *sam4_get_reg_ptr(&(pChip->cfg), pReg);
1482 LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
1483 REG_NAME_WIDTH,
1484 pReg->name,
1485 pReg->address,
1486 regval);
1487 if (pReg->explain_func)
1488 (*(pReg->explain_func))(pChip);
1489 LOG_DEBUG("End: %s", pReg->name);
1490 pReg++;
1491 }
1492 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
1493 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
1494 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
1495 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
1496 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
1497
1498 LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08"PRIx32,
1499 pChip->cfg.unique_id[0],
1500 pChip->cfg.unique_id[1],
1501 pChip->cfg.unique_id[2],
1502 pChip->cfg.unique_id[3]);
1503
1504 return ERROR_OK;
1505 }
1506
1507 static int sam4_protect_check(struct flash_bank *bank)
1508 {
1509 int r;
1510 uint32_t v[4] = {0};
1511 unsigned x;
1512 struct sam4_bank_private *pPrivate;
1513
1514 LOG_DEBUG("Begin");
1515 if (bank->target->state != TARGET_HALTED) {
1516 LOG_ERROR("Target not halted");
1517 return ERROR_TARGET_NOT_HALTED;
1518 }
1519
1520 pPrivate = get_sam4_bank_private(bank);
1521 if (!pPrivate) {
1522 LOG_ERROR("no private for this bank?");
1523 return ERROR_FAIL;
1524 }
1525 if (!(pPrivate->probed))
1526 return ERROR_FLASH_BANK_NOT_PROBED;
1527
1528 r = FLASHD_GetLockBits(pPrivate, v);
1529 if (r != ERROR_OK) {
1530 LOG_DEBUG("Failed: %d", r);
1531 return r;
1532 }
1533
1534 for (x = 0; x < pPrivate->nsectors; x++)
1535 bank->sectors[x].is_protected = (!!(v[x >> 5] & (1 << (x % 32))));
1536 LOG_DEBUG("Done");
1537 return ERROR_OK;
1538 }
1539
1540 FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
1541 {
1542 struct sam4_chip *pChip;
1543
1544 pChip = all_sam4_chips;
1545
1546 /* is this an existing chip? */
1547 while (pChip) {
1548 if (pChip->target == bank->target)
1549 break;
1550 pChip = pChip->next;
1551 }
1552
1553 if (!pChip) {
1554 /* this is a *NEW* chip */
1555 pChip = calloc(1, sizeof(struct sam4_chip));
1556 if (!pChip) {
1557 LOG_ERROR("NO RAM!");
1558 return ERROR_FAIL;
1559 }
1560 pChip->target = bank->target;
1561 /* insert at head */
1562 pChip->next = all_sam4_chips;
1563 all_sam4_chips = pChip;
1564 pChip->target = bank->target;
1565 /* assumption is this runs at 32khz */
1566 pChip->cfg.slow_freq = 32768;
1567 pChip->probed = 0;
1568 }
1569
1570 switch (bank->base) {
1571 default:
1572 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x"
1573 "[at91sam4s series] )",
1574 ((unsigned int)(bank->base)),
1575 ((unsigned int)(FLASH_BANK_BASE_S)));
1576 return ERROR_FAIL;
1577 break;
1578
1579 /* at91sam4s series only has bank 0*/
1580 /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/
1581 case FLASH_BANK_BASE_S:
1582 bank->driver_priv = &(pChip->details.bank[0]);
1583 bank->bank_number = 0;
1584 pChip->details.bank[0].pChip = pChip;
1585 pChip->details.bank[0].pBank = bank;
1586 break;
1587
1588 /* Bank 1 of at91sam4sd series */
1589 case FLASH_BANK1_BASE_1024K_SD:
1590 case FLASH_BANK1_BASE_2048K_SD:
1591 bank->driver_priv = &(pChip->details.bank[1]);
1592 bank->bank_number = 1;
1593 pChip->details.bank[1].pChip = pChip;
1594 pChip->details.bank[1].pBank = bank;
1595 break;
1596 }
1597
1598 /* we initialize after probing. */
1599 return ERROR_OK;
1600 }
1601
1602 static int sam4_GetDetails(struct sam4_bank_private *pPrivate)
1603 {
1604 const struct sam4_chip_details *pDetails;
1605 struct sam4_chip *pChip;
1606 struct flash_bank *saved_banks[SAM4_MAX_FLASH_BANKS];
1607 unsigned x;
1608
1609 LOG_DEBUG("Begin");
1610 pDetails = all_sam4_details;
1611 while (pDetails->name) {
1612 /* Compare cidr without version bits */
1613 if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
1614 break;
1615 else
1616 pDetails++;
1617 }
1618 if (pDetails->name == NULL) {
1619 LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
1620 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
1621 /* Help the victim, print details about the chip */
1622 LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
1623 pPrivate->pChip->cfg.CHIPID_CIDR);
1624 sam4_explain_chipid_cidr(pPrivate->pChip);
1625 return ERROR_FAIL;
1626 }
1627
1628 /* DANGER: THERE ARE DRAGONS HERE */
1629
1630 /* get our pChip - it is going */
1631 /* to be over-written shortly */
1632 pChip = pPrivate->pChip;
1633
1634 /* Note that, in reality: */
1635 /* */
1636 /* pPrivate = &(pChip->details.bank[0]) */
1637 /* or pPrivate = &(pChip->details.bank[1]) */
1638 /* */
1639
1640 /* save the "bank" pointers */
1641 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++)
1642 saved_banks[x] = pChip->details.bank[x].pBank;
1643
1644 /* Overwrite the "details" structure. */
1645 memcpy(&(pPrivate->pChip->details),
1646 pDetails,
1647 sizeof(pPrivate->pChip->details));
1648
1649 /* now fix the ghosted pointers */
1650 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
1651 pChip->details.bank[x].pChip = pChip;
1652 pChip->details.bank[x].pBank = saved_banks[x];
1653 }
1654
1655 /* update the *BANK*SIZE* */
1656
1657 LOG_DEBUG("End");
1658 return ERROR_OK;
1659 }
1660
1661 static int _sam4_probe(struct flash_bank *bank, int noise)
1662 {
1663 unsigned x;
1664 int r;
1665 struct sam4_bank_private *pPrivate;
1666
1667
1668 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
1669 if (bank->target->state != TARGET_HALTED) {
1670 LOG_ERROR("Target not halted");
1671 return ERROR_TARGET_NOT_HALTED;
1672 }
1673
1674 pPrivate = get_sam4_bank_private(bank);
1675 if (!pPrivate) {
1676 LOG_ERROR("Invalid/unknown bank number");
1677 return ERROR_FAIL;
1678 }
1679
1680 r = sam4_ReadAllRegs(pPrivate->pChip);
1681 if (r != ERROR_OK)
1682 return r;
1683
1684 LOG_DEBUG("Here");
1685 if (pPrivate->pChip->probed)
1686 r = sam4_GetInfo(pPrivate->pChip);
1687 else
1688 r = sam4_GetDetails(pPrivate);
1689 if (r != ERROR_OK)
1690 return r;
1691
1692 /* update the flash bank size */
1693 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
1694 if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
1695 bank->size = pPrivate->pChip->details.bank[x].size_bytes;
1696 break;
1697 }
1698 }
1699
1700 if (bank->sectors == NULL) {
1701 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
1702 if (bank->sectors == NULL) {
1703 LOG_ERROR("No memory!");
1704 return ERROR_FAIL;
1705 }
1706 bank->num_sectors = pPrivate->nsectors;
1707
1708 for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
1709 bank->sectors[x].size = pPrivate->sector_size;
1710 bank->sectors[x].offset = x * (pPrivate->sector_size);
1711 /* mark as unknown */
1712 bank->sectors[x].is_erased = -1;
1713 bank->sectors[x].is_protected = -1;
1714 }
1715 }
1716
1717 pPrivate->probed = 1;
1718
1719 r = sam4_protect_check(bank);
1720 if (r != ERROR_OK)
1721 return r;
1722
1723 LOG_DEBUG("Bank = %d, nbanks = %d",
1724 pPrivate->bank_number, pPrivate->pChip->details.n_banks);
1725 if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
1726 /* read unique id, */
1727 /* it appears to be associated with the *last* flash bank. */
1728 FLASHD_ReadUniqueID(pPrivate);
1729 }
1730
1731 return r;
1732 }
1733
1734 static int sam4_probe(struct flash_bank *bank)
1735 {
1736 return _sam4_probe(bank, 1);
1737 }
1738
1739 static int sam4_auto_probe(struct flash_bank *bank)
1740 {
1741 return _sam4_probe(bank, 0);
1742 }
1743
1744 static int sam4_erase(struct flash_bank *bank, int first, int last)
1745 {
1746 struct sam4_bank_private *pPrivate;
1747 int r;
1748 int i;
1749 int pageCount;
1750 /*16 pages equals 8KB - Same size as a lock region*/
1751 pageCount = 16;
1752 uint32_t status;
1753
1754 LOG_DEBUG("Here");
1755 if (bank->target->state != TARGET_HALTED) {
1756 LOG_ERROR("Target not halted");
1757 return ERROR_TARGET_NOT_HALTED;
1758 }
1759
1760 r = sam4_auto_probe(bank);
1761 if (r != ERROR_OK) {
1762 LOG_DEBUG("Here,r=%d", r);
1763 return r;
1764 }
1765
1766 pPrivate = get_sam4_bank_private(bank);
1767 if (!(pPrivate->probed))
1768 return ERROR_FLASH_BANK_NOT_PROBED;
1769
1770 if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
1771 /* whole chip */
1772 LOG_DEBUG("Here");
1773 return FLASHD_EraseEntireBank(pPrivate);
1774 }
1775 LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
1776 LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", (unsigned int)(first), (unsigned int)(last));
1777 for (i = first; i <= last; i++) {
1778 /*16 pages equals 8KB - Same size as a lock region*/
1779 r = FLASHD_ErasePages(pPrivate, (i * pageCount), pageCount, &status);
1780 LOG_INFO("Erasing sector: 0x%08x", (unsigned int)(i));
1781 if (r != ERROR_OK)
1782 LOG_ERROR("SAM4: Error performing Erase page @ lock region number %d",
1783 (unsigned int)(i));
1784 if (status & (1 << 2)) {
1785 LOG_ERROR("SAM4: Lock Region %d is locked", (unsigned int)(i));
1786 return ERROR_FAIL;
1787 }
1788 if (status & (1 << 1)) {
1789 LOG_ERROR("SAM4: Flash Command error @lock region %d", (unsigned int)(i));
1790 return ERROR_FAIL;
1791 }
1792 }
1793
1794 return ERROR_OK;
1795 }
1796
1797 static int sam4_protect(struct flash_bank *bank, int set, int first, int last)
1798 {
1799 struct sam4_bank_private *pPrivate;
1800 int r;
1801
1802 LOG_DEBUG("Here");
1803 if (bank->target->state != TARGET_HALTED) {
1804 LOG_ERROR("Target not halted");
1805 return ERROR_TARGET_NOT_HALTED;
1806 }
1807
1808 pPrivate = get_sam4_bank_private(bank);
1809 if (!(pPrivate->probed))
1810 return ERROR_FLASH_BANK_NOT_PROBED;
1811
1812 if (set)
1813 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
1814 else
1815 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
1816 LOG_DEBUG("End: r=%d", r);
1817
1818 return r;
1819
1820 }
1821
1822 static int sam4_page_read(struct sam4_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
1823 {
1824 uint32_t adr;
1825 int r;
1826
1827 adr = pagenum * pPrivate->page_size;
1828 adr = adr + pPrivate->base_address;
1829
1830 r = target_read_memory(pPrivate->pChip->target,
1831 adr,
1832 4, /* THIS*MUST*BE* in 32bit values */
1833 pPrivate->page_size / 4,
1834 buf);
1835 if (r != ERROR_OK)
1836 LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
1837 (unsigned int)(adr));
1838 return r;
1839 }
1840
1841 static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
1842 {
1843 uint32_t adr;
1844 uint32_t status;
1845 uint32_t fmr; /* EEFC Flash Mode Register */
1846 int r;
1847
1848 adr = pagenum * pPrivate->page_size;
1849 adr = (adr + pPrivate->base_address);
1850
1851 /* Get flash mode register value */
1852 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
1853 if (r != ERROR_OK)
1854 LOG_DEBUG("Error Read failed: read flash mode register");
1855
1856 /* Clear flash wait state field */
1857 fmr &= 0xfffff0ff;
1858
1859 /* set FWS (flash wait states) field in the FMR (flash mode register) */
1860 fmr |= (pPrivate->flash_wait_states << 8);
1861
1862 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
1863 r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
1864 if (r != ERROR_OK)
1865 LOG_DEBUG("Error Write failed: set flash mode register");
1866
1867 /* 1st sector 8kBytes - page 0 - 15*/
1868 /* 2nd sector 8kBytes - page 16 - 30*/
1869 /* 3rd sector 48kBytes - page 31 - 127*/
1870 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
1871 r = target_write_memory(pPrivate->pChip->target,
1872 adr,
1873 4, /* THIS*MUST*BE* in 32bit values */
1874 pPrivate->page_size / 4,
1875 buf);
1876 if (r != ERROR_OK) {
1877 LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
1878 (unsigned int)(adr));
1879 return r;
1880 }
1881
1882 r = EFC_PerformCommand(pPrivate,
1883 /* send Erase & Write Page */
1884 AT91C_EFC_FCMD_WP, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
1885 pagenum,
1886 &status);
1887
1888 if (r != ERROR_OK)
1889 LOG_ERROR("SAM4: Error performing Write page @ phys address 0x%08x",
1890 (unsigned int)(adr));
1891 if (status & (1 << 2)) {
1892 LOG_ERROR("SAM4: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
1893 return ERROR_FAIL;
1894 }
1895 if (status & (1 << 1)) {
1896 LOG_ERROR("SAM4: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
1897 return ERROR_FAIL;
1898 }
1899 return ERROR_OK;
1900 }
1901
1902 static int sam4_write(struct flash_bank *bank,
1903 uint8_t *buffer,
1904 uint32_t offset,
1905 uint32_t count)
1906 {
1907 int n;
1908 unsigned page_cur;
1909 unsigned page_end;
1910 int r;
1911 unsigned page_offset;
1912 struct sam4_bank_private *pPrivate;
1913 uint8_t *pagebuffer;
1914
1915 /* incase we bail further below, set this to null */
1916 pagebuffer = NULL;
1917
1918 /* ignore dumb requests */
1919 if (count == 0) {
1920 r = ERROR_OK;
1921 goto done;
1922 }
1923
1924 if (bank->target->state != TARGET_HALTED) {
1925 LOG_ERROR("Target not halted");
1926 r = ERROR_TARGET_NOT_HALTED;
1927 goto done;
1928 }
1929
1930 pPrivate = get_sam4_bank_private(bank);
1931 if (!(pPrivate->probed)) {
1932 r = ERROR_FLASH_BANK_NOT_PROBED;
1933 goto done;
1934 }
1935
1936 if ((offset + count) > pPrivate->size_bytes) {
1937 LOG_ERROR("Flash write error - past end of bank");
1938 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
1939 (unsigned int)(offset),
1940 (unsigned int)(count),
1941 (unsigned int)(pPrivate->size_bytes));
1942 r = ERROR_FAIL;
1943 goto done;
1944 }
1945
1946 pagebuffer = malloc(pPrivate->page_size);
1947 if (!pagebuffer) {
1948 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
1949 r = ERROR_FAIL;
1950 goto done;
1951 }
1952
1953 /* what page do we start & end in? */
1954 page_cur = offset / pPrivate->page_size;
1955 page_end = (offset + count - 1) / pPrivate->page_size;
1956
1957 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
1958 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
1959
1960 /* Special case: all one page */
1961 /* */
1962 /* Otherwise: */
1963 /* (1) non-aligned start */
1964 /* (2) body pages */
1965 /* (3) non-aligned end. */
1966
1967 /* Handle special case - all one page. */
1968 if (page_cur == page_end) {
1969 LOG_DEBUG("Special case, all in one page");
1970 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
1971 if (r != ERROR_OK)
1972 goto done;
1973
1974 page_offset = (offset & (pPrivate->page_size-1));
1975 memcpy(pagebuffer + page_offset,
1976 buffer,
1977 count);
1978
1979 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
1980 if (r != ERROR_OK)
1981 goto done;
1982 r = ERROR_OK;
1983 goto done;
1984 }
1985
1986 /* non-aligned start */
1987 page_offset = offset & (pPrivate->page_size - 1);
1988 if (page_offset) {
1989 LOG_DEBUG("Not-Aligned start");
1990 /* read the partial */
1991 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
1992 if (r != ERROR_OK)
1993 goto done;
1994
1995 /* over-write with new data */
1996 n = (pPrivate->page_size - page_offset);
1997 memcpy(pagebuffer + page_offset,
1998 buffer,
1999 n);
2000
2001 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2002 if (r != ERROR_OK)
2003 goto done;
2004
2005 count -= n;
2006 offset += n;
2007 buffer += n;
2008 page_cur++;
2009 }
2010
2011 /* By checking that offset is correct here, we also
2012 fix a clang warning */
2013 assert(offset % pPrivate->page_size == 0);
2014
2015 /* intermediate large pages */
2016 /* also - the final *terminal* */
2017 /* if that terminal page is a full page */
2018 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2019 (int)page_cur, (int)page_end, (unsigned int)(count));
2020
2021 while ((page_cur < page_end) &&
2022 (count >= pPrivate->page_size)) {
2023 r = sam4_page_write(pPrivate, page_cur, buffer);
2024 if (r != ERROR_OK)
2025 goto done;
2026 count -= pPrivate->page_size;
2027 buffer += pPrivate->page_size;
2028 page_cur += 1;
2029 }
2030
2031 /* terminal partial page? */
2032 if (count) {
2033 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
2034 /* we have a partial page */
2035 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2036 if (r != ERROR_OK)
2037 goto done;
2038 /* data goes at start */
2039 memcpy(pagebuffer, buffer, count);
2040 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2041 if (r != ERROR_OK)
2042 goto done;
2043 }
2044 LOG_DEBUG("Done!");
2045 r = ERROR_OK;
2046 done:
2047 if (pagebuffer)
2048 free(pagebuffer);
2049 return r;
2050 }
2051
2052 COMMAND_HANDLER(sam4_handle_info_command)
2053 {
2054 struct sam4_chip *pChip;
2055 pChip = get_current_sam4(CMD_CTX);
2056 if (!pChip)
2057 return ERROR_OK;
2058
2059 unsigned x;
2060 int r;
2061
2062 /* bank0 must exist before we can do anything */
2063 if (pChip->details.bank[0].pBank == NULL) {
2064 x = 0;
2065 need_define:
2066 command_print(CMD_CTX,
2067 "Please define bank %d via command: flash bank %s ... ",
2068 x,
2069 at91sam4_flash.name);
2070 return ERROR_FAIL;
2071 }
2072
2073 /* if bank 0 is not probed, then probe it */
2074 if (!(pChip->details.bank[0].probed)) {
2075 r = sam4_auto_probe(pChip->details.bank[0].pBank);
2076 if (r != ERROR_OK)
2077 return ERROR_FAIL;
2078 }
2079 /* above guarantees the "chip details" structure is valid */
2080 /* and thus, bank private areas are valid */
2081 /* and we have a SAM4 chip, what a concept! */
2082
2083 /* auto-probe other banks, 0 done above */
2084 for (x = 1; x < SAM4_MAX_FLASH_BANKS; x++) {
2085 /* skip banks not present */
2086 if (!(pChip->details.bank[x].present))
2087 continue;
2088
2089 if (pChip->details.bank[x].pBank == NULL)
2090 goto need_define;
2091
2092 if (pChip->details.bank[x].probed)
2093 continue;
2094
2095 r = sam4_auto_probe(pChip->details.bank[x].pBank);
2096 if (r != ERROR_OK)
2097 return r;
2098 }
2099
2100 r = sam4_GetInfo(pChip);
2101 if (r != ERROR_OK) {
2102 LOG_DEBUG("Sam4Info, Failed %d", r);
2103 return r;
2104 }
2105
2106 return ERROR_OK;
2107 }
2108
2109 COMMAND_HANDLER(sam4_handle_gpnvm_command)
2110 {
2111 unsigned x, v;
2112 int r, who;
2113 struct sam4_chip *pChip;
2114
2115 pChip = get_current_sam4(CMD_CTX);
2116 if (!pChip)
2117 return ERROR_OK;
2118
2119 if (pChip->target->state != TARGET_HALTED) {
2120 LOG_ERROR("sam4 - target not halted");
2121 return ERROR_TARGET_NOT_HALTED;
2122 }
2123
2124 if (pChip->details.bank[0].pBank == NULL) {
2125 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
2126 at91sam4_flash.name);
2127 return ERROR_FAIL;
2128 }
2129 if (!pChip->details.bank[0].probed) {
2130 r = sam4_auto_probe(pChip->details.bank[0].pBank);
2131 if (r != ERROR_OK)
2132 return r;
2133 }
2134
2135 switch (CMD_ARGC) {
2136 default:
2137 return ERROR_COMMAND_SYNTAX_ERROR;
2138 break;
2139 case 0:
2140 goto showall;
2141 break;
2142 case 1:
2143 who = -1;
2144 break;
2145 case 2:
2146 if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
2147 who = -1;
2148 else {
2149 uint32_t v32;
2150 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
2151 who = v32;
2152 }
2153 break;
2154 }
2155
2156 if (0 == strcmp("show", CMD_ARGV[0])) {
2157 if (who == -1) {
2158 showall:
2159 r = ERROR_OK;
2160 for (x = 0; x < pChip->details.n_gpnvms; x++) {
2161 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
2162 if (r != ERROR_OK)
2163 break;
2164 command_print(CMD_CTX, "sam4-gpnvm%u: %u", x, v);
2165 }
2166 return r;
2167 }
2168 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
2169 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
2170 command_print(CMD_CTX, "sam4-gpnvm%u: %u", who, v);
2171 return r;
2172 } else {
2173 command_print(CMD_CTX, "sam4-gpnvm invalid GPNVM: %u", who);
2174 return ERROR_COMMAND_SYNTAX_ERROR;
2175 }
2176 }
2177
2178 if (who == -1) {
2179 command_print(CMD_CTX, "Missing GPNVM number");
2180 return ERROR_COMMAND_SYNTAX_ERROR;
2181 }
2182
2183 if (0 == strcmp("set", CMD_ARGV[0]))
2184 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
2185 else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
2186 (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
2187 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
2188 else {
2189 command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
2190 r = ERROR_COMMAND_SYNTAX_ERROR;
2191 }
2192 return r;
2193 }
2194
2195 COMMAND_HANDLER(sam4_handle_slowclk_command)
2196 {
2197 struct sam4_chip *pChip;
2198
2199 pChip = get_current_sam4(CMD_CTX);
2200 if (!pChip)
2201 return ERROR_OK;
2202
2203 switch (CMD_ARGC) {
2204 case 0:
2205 /* show */
2206 break;
2207 case 1:
2208 {
2209 /* set */
2210 uint32_t v;
2211 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
2212 if (v > 200000) {
2213 /* absurd slow clock of 200Khz? */
2214 command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));
2215 return ERROR_COMMAND_SYNTAX_ERROR;
2216 }
2217 pChip->cfg.slow_freq = v;
2218 break;
2219 }
2220 default:
2221 /* error */
2222 command_print(CMD_CTX, "Too many parameters");
2223 return ERROR_COMMAND_SYNTAX_ERROR;
2224 break;
2225 }
2226 command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
2227 (int)(pChip->cfg.slow_freq / 1000),
2228 (int)(pChip->cfg.slow_freq % 1000));
2229 return ERROR_OK;
2230 }
2231
2232 static const struct command_registration at91sam4_exec_command_handlers[] = {
2233 {
2234 .name = "gpnvm",
2235 .handler = sam4_handle_gpnvm_command,
2236 .mode = COMMAND_EXEC,
2237 .usage = "[('clr'|'set'|'show') bitnum]",
2238 .help = "Without arguments, shows all bits in the gpnvm "
2239 "register. Otherwise, clears, sets, or shows one "
2240 "General Purpose Non-Volatile Memory (gpnvm) bit.",
2241 },
2242 {
2243 .name = "info",
2244 .handler = sam4_handle_info_command,
2245 .mode = COMMAND_EXEC,
2246 .help = "Print information about the current at91sam4 chip"
2247 "and its flash configuration.",
2248 },
2249 {
2250 .name = "slowclk",
2251 .handler = sam4_handle_slowclk_command,
2252 .mode = COMMAND_EXEC,
2253 .usage = "[clock_hz]",
2254 .help = "Display or set the slowclock frequency "
2255 "(default 32768 Hz).",
2256 },
2257 COMMAND_REGISTRATION_DONE
2258 };
2259 static const struct command_registration at91sam4_command_handlers[] = {
2260 {
2261 .name = "at91sam4",
2262 .mode = COMMAND_ANY,
2263 .help = "at91sam4 flash command group",
2264 .usage = "",
2265 .chain = at91sam4_exec_command_handlers,
2266 },
2267 COMMAND_REGISTRATION_DONE
2268 };
2269
2270 struct flash_driver at91sam4_flash = {
2271 .name = "at91sam4",
2272 .commands = at91sam4_command_handlers,
2273 .flash_bank_command = sam4_flash_bank_command,
2274 .erase = sam4_erase,
2275 .protect = sam4_protect,
2276 .write = sam4_write,
2277 .read = default_flash_read,
2278 .probe = sam4_probe,
2279 .auto_probe = sam4_auto_probe,
2280 .erase_check = default_flash_blank_check,
2281 .protect_check = sam4_protect_check,
2282 };

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)