flash/nor/at91sam4: remove FWS=6, rename at91samg to atsamg
[openocd.git] / src / flash / nor / at91sam4.c
1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
4 * *
5 * Copyright (C) 2010 by Olaf L√ľke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
7 * *
8 * Copyright (C) 2011 by Olivier Schonken, Jim Norris *
9 * (at91sam3x* & at91sam4 support)* *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ****************************************************************************/
24
25 /* Some of the the lower level code was based on code supplied by
26 * ATMEL under this copyright. */
27
28 /* BEGIN ATMEL COPYRIGHT */
29 /* ----------------------------------------------------------------------------
30 * ATMEL Microcontroller Software Support
31 * ----------------------------------------------------------------------------
32 * Copyright (c) 2009, Atmel Corporation
33 *
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions are met:
38 *
39 * - Redistributions of source code must retain the above copyright notice,
40 * this list of conditions and the disclaimer below.
41 *
42 * Atmel's name may not be used to endorse or promote products derived from
43 * this software without specific prior written permission.
44 *
45 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
47 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
48 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
50 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
51 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
52 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
53 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
54 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 * ----------------------------------------------------------------------------
56 */
57 /* END ATMEL COPYRIGHT */
58
59 #ifdef HAVE_CONFIG_H
60 #include "config.h"
61 #endif
62
63 #include "imp.h"
64 #include <helper/time_support.h>
65
66 #define REG_NAME_WIDTH (12)
67
68 /* at91sam4s/at91sam4e/at91sam4c series (has always one flash bank)*/
69 #define FLASH_BANK_BASE_S 0x00400000
70 #define FLASH_BANK_BASE_C 0x01000000
71
72 /* at91sam4sd series (two one flash banks), first bank address */
73 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
74 /* at91sam4sd16x, second bank address */
75 #define FLASH_BANK1_BASE_1024K_SD (FLASH_BANK0_BASE_SD+(1024*1024/2))
76 /* at91sam4sd32x, second bank address */
77 #define FLASH_BANK1_BASE_2048K_SD (FLASH_BANK0_BASE_SD+(2048*1024/2))
78
79 /* at91sam4c32x, first and second bank address */
80 #define FLASH_BANK0_BASE_C32 FLASH_BANK_BASE_C
81 #define FLASH_BANK1_BASE_C32 (FLASH_BANK_BASE_C+(2048*1024/2))
82
83 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
84 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
85 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
86 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
87 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
88 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
89 /* cmd6 is not present in the at91sam4u4/2/1 data sheet table 19-2 */
90 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
91 #define AT91C_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
92 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
93 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
94 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
95 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
96 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
97 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
98 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
99 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
100
101 #define offset_EFC_FMR 0
102 #define offset_EFC_FCR 4
103 #define offset_EFC_FSR 8
104 #define offset_EFC_FRR 12
105
106 extern struct flash_driver at91sam4_flash;
107
108 static float _tomhz(uint32_t freq_hz)
109 {
110 float f;
111
112 f = ((float)(freq_hz)) / 1000000.0;
113 return f;
114 }
115
116 /* How the chip is configured. */
117 struct sam4_cfg {
118 uint32_t unique_id[4];
119
120 uint32_t slow_freq;
121 uint32_t rc_freq;
122 uint32_t mainosc_freq;
123 uint32_t plla_freq;
124 uint32_t mclk_freq;
125 uint32_t cpu_freq;
126 uint32_t fclk_freq;
127 uint32_t pclk0_freq;
128 uint32_t pclk1_freq;
129 uint32_t pclk2_freq;
130
131
132 #define SAM4_CHIPID_CIDR (0x400E0740)
133 uint32_t CHIPID_CIDR;
134 #define SAM4_CHIPID_EXID (0x400E0744)
135 uint32_t CHIPID_EXID;
136
137 #define SAM4_PMC_BASE (0x400E0400)
138 #define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
139 uint32_t PMC_SCSR;
140 #define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
141 uint32_t PMC_PCSR;
142 #define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
143 uint32_t CKGR_UCKR;
144 #define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
145 uint32_t CKGR_MOR;
146 #define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
147 uint32_t CKGR_MCFR;
148 #define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
149 uint32_t CKGR_PLLAR;
150 #define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
151 uint32_t PMC_MCKR;
152 #define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
153 uint32_t PMC_PCK0;
154 #define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
155 uint32_t PMC_PCK1;
156 #define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
157 uint32_t PMC_PCK2;
158 #define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
159 uint32_t PMC_SR;
160 #define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
161 uint32_t PMC_IMR;
162 #define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
163 uint32_t PMC_FSMR;
164 #define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
165 uint32_t PMC_FSPR;
166 };
167
168 struct sam4_bank_private {
169 int probed;
170 /* DANGER: THERE ARE DRAGONS HERE.. */
171 /* NOTE: If you add more 'ghost' pointers */
172 /* be aware that you must *manually* update */
173 /* these pointers in the function sam4_GetDetails() */
174 /* See the comment "Here there be dragons" */
175
176 /* so we can find the chip we belong to */
177 struct sam4_chip *pChip;
178 /* so we can find the original bank pointer */
179 struct flash_bank *pBank;
180 unsigned bank_number;
181 uint32_t controller_address;
182 uint32_t base_address;
183 uint32_t flash_wait_states;
184 bool present;
185 unsigned size_bytes;
186 unsigned nsectors;
187 unsigned sector_size;
188 unsigned page_size;
189 };
190
191 struct sam4_chip_details {
192 /* THERE ARE DRAGONS HERE.. */
193 /* note: If you add pointers here */
194 /* be careful about them as they */
195 /* may need to be updated inside */
196 /* the function: "sam4_GetDetails() */
197 /* which copy/overwrites the */
198 /* 'runtime' copy of this structure */
199 uint32_t chipid_cidr;
200 const char *name;
201
202 unsigned n_gpnvms;
203 #define SAM4_N_NVM_BITS 3
204 unsigned gpnvm[SAM4_N_NVM_BITS];
205 unsigned total_flash_size;
206 unsigned total_sram_size;
207 unsigned n_banks;
208 #define SAM4_MAX_FLASH_BANKS 2
209 /* these are "initialized" from the global const data */
210 struct sam4_bank_private bank[SAM4_MAX_FLASH_BANKS];
211 };
212
213 struct sam4_chip {
214 struct sam4_chip *next;
215 int probed;
216
217 /* this is "initialized" from the global const structure */
218 struct sam4_chip_details details;
219 struct target *target;
220 struct sam4_cfg cfg;
221 };
222
223
224 struct sam4_reg_list {
225 uint32_t address; size_t struct_offset; const char *name;
226 void (*explain_func)(struct sam4_chip *pInfo);
227 };
228
229 static struct sam4_chip *all_sam4_chips;
230
231 static struct sam4_chip *get_current_sam4(struct command_context *cmd_ctx)
232 {
233 struct target *t;
234 static struct sam4_chip *p;
235
236 t = get_current_target(cmd_ctx);
237 if (!t) {
238 command_print(cmd_ctx, "No current target?");
239 return NULL;
240 }
241
242 p = all_sam4_chips;
243 if (!p) {
244 /* this should not happen */
245 /* the command is not registered until the chip is created? */
246 command_print(cmd_ctx, "No SAM4 chips exist?");
247 return NULL;
248 }
249
250 while (p) {
251 if (p->target == t)
252 return p;
253 p = p->next;
254 }
255 command_print(cmd_ctx, "Cannot find SAM4 chip?");
256 return NULL;
257 }
258
259 /*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
260 /*The lockregions are 8KB per lock region, with a 1024KB device having 128 lock regions. */
261 /*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
262 /*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
263
264 /* these are used to *initialize* the "pChip->details" structure. */
265 static const struct sam4_chip_details all_sam4_details[] = {
266 /* Start at91sam4c* series */
267 /* at91sam4c32e - LQFP144 */
268 {
269 .chipid_cidr = 0xA66D0EE0,
270 .name = "at91sam4c32e",
271 .total_flash_size = 2024 * 1024,
272 .total_sram_size = 256 * 1024,
273 .n_gpnvms = 3,
274 .n_banks = 2,
275 /* .bank[0] = { */
276 {
277 {
278 .probed = 0,
279 .pChip = NULL,
280 .pBank = NULL,
281 .bank_number = 0,
282 .base_address = FLASH_BANK0_BASE_C32,
283 .controller_address = 0x400e0a00,
284 .flash_wait_states = 5,
285 .present = 1,
286 .size_bytes = 1024 * 1024,
287 .nsectors = 128,
288 .sector_size = 8192,
289 .page_size = 512,
290 },
291 /* .bank[1] = { */
292 {
293 .probed = 0,
294 .pChip = NULL,
295 .pBank = NULL,
296 .bank_number = 1,
297 .base_address = FLASH_BANK1_BASE_C32,
298 .controller_address = 0x400e0c00,
299 .flash_wait_states = 5,
300 .present = 1,
301 .size_bytes = 1024 * 1024,
302 .nsectors = 128,
303 .sector_size = 8192,
304 .page_size = 512,
305 },
306 },
307 },
308 /* at91sam4c32c - LQFP100 */
309 {
310 .chipid_cidr = 0xA64D0EE0,
311 .name = "at91sam4c32c",
312 .total_flash_size = 2024 * 1024,
313 .total_sram_size = 256 * 1024,
314 .n_gpnvms = 3,
315 .n_banks = 2,
316 /* .bank[0] = { */
317 {
318 {
319 .probed = 0,
320 .pChip = NULL,
321 .pBank = NULL,
322 .bank_number = 0,
323 .base_address = FLASH_BANK0_BASE_C32,
324 .controller_address = 0x400e0a00,
325 .flash_wait_states = 5,
326 .present = 1,
327 .size_bytes = 1024 * 1024,
328 .nsectors = 128,
329 .sector_size = 8192,
330 .page_size = 512,
331 },
332 /* .bank[1] = { */
333 {
334 .probed = 0,
335 .pChip = NULL,
336 .pBank = NULL,
337 .bank_number = 1,
338 .base_address = FLASH_BANK1_BASE_C32,
339 .controller_address = 0x400e0c00,
340 .flash_wait_states = 5,
341 .present = 1,
342 .size_bytes = 1024 * 1024,
343 .nsectors = 128,
344 .sector_size = 8192,
345 .page_size = 512,
346 },
347 },
348 },
349 /* at91sam4c16c - LQFP100 */
350 {
351 .chipid_cidr = 0xA64C0CE0,
352 .name = "at91sam4c16c",
353 .total_flash_size = 1024 * 1024,
354 .total_sram_size = 128 * 1024,
355 .n_gpnvms = 2,
356 .n_banks = 1,
357 {
358 /* .bank[0] = {*/
359 {
360 .probed = 0,
361 .pChip = NULL,
362 .pBank = NULL,
363 .bank_number = 0,
364 .base_address = FLASH_BANK_BASE_C,
365 .controller_address = 0x400e0a00,
366 .flash_wait_states = 5,
367 .present = 1,
368 .size_bytes = 1024 * 1024,
369 .nsectors = 128,
370 .sector_size = 8192,
371 .page_size = 512,
372 },
373 /* .bank[1] = {*/
374 {
375 .present = 0,
376 .probed = 0,
377 .bank_number = 1,
378
379 },
380 },
381 },
382 /* at91sam4c8c - LQFP100 */
383 {
384 .chipid_cidr = 0xA64C0AE0,
385 .name = "at91sam4c8c",
386 .total_flash_size = 512 * 1024,
387 .total_sram_size = 128 * 1024,
388 .n_gpnvms = 2,
389 .n_banks = 1,
390 {
391 /* .bank[0] = {*/
392 {
393 .probed = 0,
394 .pChip = NULL,
395 .pBank = NULL,
396 .bank_number = 0,
397 .base_address = FLASH_BANK_BASE_C,
398 .controller_address = 0x400e0a00,
399 .flash_wait_states = 5,
400 .present = 1,
401 .size_bytes = 512 * 1024,
402 .nsectors = 64,
403 .sector_size = 8192,
404 .page_size = 512,
405 },
406 /* .bank[1] = {*/
407 {
408 .present = 0,
409 .probed = 0,
410 .bank_number = 1,
411
412 },
413 },
414 },
415 /* at91sam4c4c (rev B) - LQFP100 */
416 {
417 .chipid_cidr = 0xA64C0CE5,
418 .name = "at91sam4c4c",
419 .total_flash_size = 256 * 1024,
420 .total_sram_size = 128 * 1024,
421 .n_gpnvms = 2,
422 .n_banks = 1,
423 {
424 /* .bank[0] = {*/
425 {
426 .probed = 0,
427 .pChip = NULL,
428 .pBank = NULL,
429 .bank_number = 0,
430 .base_address = FLASH_BANK_BASE_C,
431 .controller_address = 0x400e0a00,
432 .flash_wait_states = 5,
433 .present = 1,
434 .size_bytes = 256 * 1024,
435 .nsectors = 32,
436 .sector_size = 8192,
437 .page_size = 512,
438 },
439 /* .bank[1] = {*/
440 {
441 .present = 0,
442 .probed = 0,
443 .bank_number = 1,
444
445 },
446 },
447 },
448
449 /* Start at91sam4e* series */
450 /*atsam4e16e - LQFP144/LFBGA144*/
451 {
452 .chipid_cidr = 0xA3CC0CE0,
453 .name = "at91sam4e16e",
454 .total_flash_size = 1024 * 1024,
455 .total_sram_size = 128 * 1024,
456 .n_gpnvms = 2,
457 .n_banks = 1,
458 {
459 /* .bank[0] = {*/
460 {
461 .probed = 0,
462 .pChip = NULL,
463 .pBank = NULL,
464 .bank_number = 0,
465 .base_address = FLASH_BANK_BASE_S,
466 .controller_address = 0x400e0a00,
467 .flash_wait_states = 5,
468 .present = 1,
469 .size_bytes = 1024 * 1024,
470 .nsectors = 128,
471 .sector_size = 8192,
472 .page_size = 512,
473 },
474 /* .bank[1] = {*/
475 {
476 .present = 0,
477 .probed = 0,
478 .bank_number = 1,
479
480 },
481 },
482 },
483
484 /* Start at91sam4n* series */
485 /*atsam4n8a - LQFP48/QFN48*/
486 {
487 .chipid_cidr = 0x293B0AE0,
488 .name = "at91sam4n8a",
489 .total_flash_size = 512 * 1024,
490 .total_sram_size = 64 * 1024,
491 .n_gpnvms = 2,
492 .n_banks = 1,
493 {
494 /* .bank[0] = {*/
495 {
496 .probed = 0,
497 .pChip = NULL,
498 .pBank = NULL,
499 .bank_number = 0,
500 .base_address = FLASH_BANK_BASE_S,
501 .controller_address = 0x400e0a00,
502 .flash_wait_states = 5,
503 .present = 1,
504 .size_bytes = 512 * 1024,
505 .nsectors = 64,
506 .sector_size = 8192,
507 .page_size = 512,
508 },
509 /* .bank[1] = {*/
510 {
511 .present = 0,
512 .probed = 0,
513 .bank_number = 1,
514
515 },
516 },
517 },
518 /*atsam4n8b - LQFP64/QFN64*/
519 {
520 .chipid_cidr = 0x294B0AE0,
521 .name = "at91sam4n8b",
522 .total_flash_size = 512 * 1024,
523 .total_sram_size = 64 * 1024,
524 .n_gpnvms = 2,
525 .n_banks = 1,
526 {
527 /* .bank[0] = {*/
528 {
529 .probed = 0,
530 .pChip = NULL,
531 .pBank = NULL,
532 .bank_number = 0,
533 .base_address = FLASH_BANK_BASE_S,
534 .controller_address = 0x400e0a00,
535 .flash_wait_states = 5,
536 .present = 1,
537 .size_bytes = 512 * 1024,
538 .nsectors = 64,
539 .sector_size = 8192,
540 .page_size = 512,
541 },
542 /* .bank[1] = {*/
543 {
544 .present = 0,
545 .probed = 0,
546 .bank_number = 1,
547
548 },
549 },
550 },
551 /*atsam4n8c - LQFP100/TFBGA100/VFBGA100*/
552 {
553 .chipid_cidr = 0x295B0AE0,
554 .name = "at91sam4n8c",
555 .total_flash_size = 512 * 1024,
556 .total_sram_size = 64 * 1024,
557 .n_gpnvms = 2,
558 .n_banks = 1,
559 {
560 /* .bank[0] = {*/
561 {
562 .probed = 0,
563 .pChip = NULL,
564 .pBank = NULL,
565 .bank_number = 0,
566 .base_address = FLASH_BANK_BASE_S,
567 .controller_address = 0x400e0a00,
568 .flash_wait_states = 5,
569 .present = 1,
570 .size_bytes = 512 * 1024,
571 .nsectors = 64,
572 .sector_size = 8192,
573 .page_size = 512,
574 },
575 /* .bank[1] = {*/
576 {
577 .present = 0,
578 .probed = 0,
579 .bank_number = 1,
580
581 },
582 },
583 },
584 /*atsam4n16b - LQFP64/QFN64*/
585 {
586 .chipid_cidr = 0x29460CE0,
587 .name = "at91sam4n16b",
588 .total_flash_size = 1024 * 1024,
589 .total_sram_size = 80 * 1024,
590 .n_gpnvms = 2,
591 .n_banks = 1,
592 {
593 /* .bank[0] = {*/
594 {
595 .probed = 0,
596 .pChip = NULL,
597 .pBank = NULL,
598 .bank_number = 0,
599 .base_address = FLASH_BANK_BASE_S,
600 .controller_address = 0x400e0a00,
601 .flash_wait_states = 5,
602 .present = 1,
603 .size_bytes = 1024 * 1024,
604 .nsectors = 128,
605 .sector_size = 8192,
606 .page_size = 512,
607 },
608 /* .bank[1] = {*/
609 {
610 .present = 0,
611 .probed = 0,
612 .bank_number = 1,
613
614 },
615 },
616 },
617 /*atsam4n16c - LQFP100/TFBGA100/VFBGA100*/
618 {
619 .chipid_cidr = 0x29560CE0,
620 .name = "at91sam4n16c",
621 .total_flash_size = 1024 * 1024,
622 .total_sram_size = 80 * 1024,
623 .n_gpnvms = 2,
624 .n_banks = 1,
625 {
626 /* .bank[0] = {*/
627 {
628 .probed = 0,
629 .pChip = NULL,
630 .pBank = NULL,
631 .bank_number = 0,
632 .base_address = FLASH_BANK_BASE_S,
633 .controller_address = 0x400e0a00,
634 .flash_wait_states = 5,
635 .present = 1,
636 .size_bytes = 1024 * 1024,
637 .nsectors = 128,
638 .sector_size = 8192,
639 .page_size = 512,
640 },
641 /* .bank[1] = {*/
642 {
643 .present = 0,
644 .probed = 0,
645 .bank_number = 1,
646
647 },
648 },
649 },
650
651 /* Start at91sam4s* series */
652 /*atsam4s16c - LQFP100/BGA100*/
653 {
654 .chipid_cidr = 0x28AC0CE0,
655 .name = "at91sam4s16c",
656 .total_flash_size = 1024 * 1024,
657 .total_sram_size = 128 * 1024,
658 .n_gpnvms = 2,
659 .n_banks = 1,
660 {
661 /* .bank[0] = {*/
662 {
663 .probed = 0,
664 .pChip = NULL,
665 .pBank = NULL,
666 .bank_number = 0,
667 .base_address = FLASH_BANK_BASE_S,
668 .controller_address = 0x400e0a00,
669 .flash_wait_states = 5,
670 .present = 1,
671 .size_bytes = 1024 * 1024,
672 .nsectors = 128,
673 .sector_size = 8192,
674 .page_size = 512,
675 },
676 /* .bank[1] = {*/
677 {
678 .present = 0,
679 .probed = 0,
680 .bank_number = 1,
681
682 },
683 },
684 },
685 /*atsam4s16b - LQFP64/QFN64/WLCSP64*/
686 {
687 .chipid_cidr = 0x289C0CE0,
688 .name = "at91sam4s16b",
689 .total_flash_size = 1024 * 1024,
690 .total_sram_size = 128 * 1024,
691 .n_gpnvms = 2,
692 .n_banks = 1,
693 {
694 /* .bank[0] = {*/
695 {
696 .probed = 0,
697 .pChip = NULL,
698 .pBank = NULL,
699 .bank_number = 0,
700 .base_address = FLASH_BANK_BASE_S,
701 .controller_address = 0x400e0a00,
702 .flash_wait_states = 5,
703 .present = 1,
704 .size_bytes = 1024 * 1024,
705 .nsectors = 128,
706 .sector_size = 8192,
707 .page_size = 512,
708 },
709 /* .bank[1] = {*/
710 {
711 .present = 0,
712 .probed = 0,
713 .bank_number = 1,
714
715 },
716 },
717 },
718 /*atsam4sa16b - LQFP64/QFN64*/
719 {
720 .chipid_cidr = 0x28970CE0,
721 .name = "at91sam4sa16b",
722 .total_flash_size = 1024 * 1024,
723 .total_sram_size = 160 * 1024,
724 .n_gpnvms = 2,
725 .n_banks = 1,
726 {
727 /* .bank[0] = {*/
728 {
729 .probed = 0,
730 .pChip = NULL,
731 .pBank = NULL,
732 .bank_number = 0,
733 .base_address = FLASH_BANK_BASE_S,
734 .controller_address = 0x400e0a00,
735 .flash_wait_states = 5,
736 .present = 1,
737 .size_bytes = 1024 * 1024,
738 .nsectors = 128,
739 .sector_size = 8192,
740 .page_size = 512,
741 },
742 /* .bank[1] = {*/
743 {
744 .present = 0,
745 .probed = 0,
746 .bank_number = 1,
747
748 },
749 },
750 },
751 /*atsam4s16a - LQFP48/QFN48*/
752 {
753 .chipid_cidr = 0x288C0CE0,
754 .name = "at91sam4s16a",
755 .total_flash_size = 1024 * 1024,
756 .total_sram_size = 128 * 1024,
757 .n_gpnvms = 2,
758 .n_banks = 1,
759 {
760 /* .bank[0] = {*/
761 {
762 .probed = 0,
763 .pChip = NULL,
764 .pBank = NULL,
765 .bank_number = 0,
766 .base_address = FLASH_BANK_BASE_S,
767 .controller_address = 0x400e0a00,
768 .flash_wait_states = 5,
769 .present = 1,
770 .size_bytes = 1024 * 1024,
771 .nsectors = 128,
772 .sector_size = 8192,
773 .page_size = 512,
774 },
775 /* .bank[1] = {*/
776 {
777 .present = 0,
778 .probed = 0,
779 .bank_number = 1,
780
781 },
782 },
783 },
784 /*atsam4s8c - LQFP100/BGA100*/
785 {
786 .chipid_cidr = 0x28AC0AE0,
787 .name = "at91sam4s8c",
788 .total_flash_size = 512 * 1024,
789 .total_sram_size = 128 * 1024,
790 .n_gpnvms = 2,
791 .n_banks = 1,
792 {
793 /* .bank[0] = {*/
794 {
795 .probed = 0,
796 .pChip = NULL,
797 .pBank = NULL,
798 .bank_number = 0,
799 .base_address = FLASH_BANK_BASE_S,
800 .controller_address = 0x400e0a00,
801 .flash_wait_states = 5,
802 .present = 1,
803 .size_bytes = 512 * 1024,
804 .nsectors = 64,
805 .sector_size = 8192,
806 .page_size = 512,
807 },
808 /* .bank[1] = {*/
809 {
810 .present = 0,
811 .probed = 0,
812 .bank_number = 1,
813
814 },
815 },
816 },
817 /*atsam4s8b - LQFP64/QFN64/WLCSP64*/
818 {
819 .chipid_cidr = 0x289C0AE0,
820 .name = "at91sam4s8b",
821 .total_flash_size = 512 * 1024,
822 .total_sram_size = 128 * 1024,
823 .n_gpnvms = 2,
824 .n_banks = 1,
825 {
826 /* .bank[0] = {*/
827 {
828 .probed = 0,
829 .pChip = NULL,
830 .pBank = NULL,
831 .bank_number = 0,
832 .base_address = FLASH_BANK_BASE_S,
833 .controller_address = 0x400e0a00,
834 .flash_wait_states = 5,
835 .present = 1,
836 .size_bytes = 512 * 1024,
837 .nsectors = 64,
838 .sector_size = 8192,
839 .page_size = 512,
840 },
841 /* .bank[1] = {*/
842 {
843 .present = 0,
844 .probed = 0,
845 .bank_number = 1,
846
847 },
848 },
849 },
850 /*atsam4s8a - LQFP48/BGA48*/
851 {
852 .chipid_cidr = 0x288C0AE0,
853 .name = "at91sam4s8a",
854 .total_flash_size = 512 * 1024,
855 .total_sram_size = 128 * 1024,
856 .n_gpnvms = 2,
857 .n_banks = 1,
858 {
859 /* .bank[0] = {*/
860 {
861 .probed = 0,
862 .pChip = NULL,
863 .pBank = NULL,
864 .bank_number = 0,
865 .base_address = FLASH_BANK_BASE_S,
866 .controller_address = 0x400e0a00,
867 .flash_wait_states = 5,
868 .present = 1,
869 .size_bytes = 512 * 1024,
870 .nsectors = 64,
871 .sector_size = 8192,
872 .page_size = 512,
873 },
874 /* .bank[1] = {*/
875 {
876 .present = 0,
877 .probed = 0,
878 .bank_number = 1,
879
880 },
881 },
882 },
883
884 /*atsam4s4c - LQFP100/BGA100*/
885 {
886 .chipid_cidr = 0x28ab09e0,
887 .name = "at91sam4s4c",
888 .total_flash_size = 256 * 1024,
889 .total_sram_size = 64 * 1024,
890 .n_gpnvms = 2,
891 .n_banks = 1,
892 {
893 /* .bank[0] = {*/
894 {
895 .probed = 0,
896 .pChip = NULL,
897 .pBank = NULL,
898 .bank_number = 0,
899 .base_address = FLASH_BANK_BASE_S,
900 .controller_address = 0x400e0a00,
901 .flash_wait_states = 5,
902 .present = 1,
903 .size_bytes = 256 * 1024,
904 .nsectors = 32,
905 .sector_size = 8192,
906 .page_size = 512,
907 },
908 /* .bank[1] = {*/
909 {
910 .present = 0,
911 .probed = 0,
912 .bank_number = 1,
913
914 },
915 },
916 },
917
918 /*atsam4s4b - LQFP64/QFN64/WLCSP64*/
919 {
920 .chipid_cidr = 0x289b09e0,
921 .name = "at91sam4s4b",
922 .total_flash_size = 256 * 1024,
923 .total_sram_size = 64 * 1024,
924 .n_gpnvms = 2,
925 .n_banks = 1,
926 {
927 /* .bank[0] = {*/
928 {
929 .probed = 0,
930 .pChip = NULL,
931 .pBank = NULL,
932 .bank_number = 0,
933 .base_address = FLASH_BANK_BASE_S,
934 .controller_address = 0x400e0a00,
935 .flash_wait_states = 5,
936 .present = 1,
937 .size_bytes = 256 * 1024,
938 .nsectors = 32,
939 .sector_size = 8192,
940 .page_size = 512,
941 },
942 /* .bank[1] = {*/
943 {
944 .present = 0,
945 .probed = 0,
946 .bank_number = 1,
947
948 },
949 },
950 },
951
952 /*atsam4s4a - LQFP48/QFN48*/
953 {
954 .chipid_cidr = 0x288b09e0,
955 .name = "at91sam4s4a",
956 .total_flash_size = 256 * 1024,
957 .total_sram_size = 64 * 1024,
958 .n_gpnvms = 2,
959 .n_banks = 1,
960 {
961 /* .bank[0] = {*/
962 {
963 .probed = 0,
964 .pChip = NULL,
965 .pBank = NULL,
966 .bank_number = 0,
967 .base_address = FLASH_BANK_BASE_S,
968 .controller_address = 0x400e0a00,
969 .flash_wait_states = 5,
970 .present = 1,
971 .size_bytes = 256 * 1024,
972 .nsectors = 32,
973 .sector_size = 8192,
974 .page_size = 512,
975 },
976 /* .bank[1] = {*/
977 {
978 .present = 0,
979 .probed = 0,
980 .bank_number = 1,
981
982 },
983 },
984 },
985
986 /*atsam4s2c - LQFP100/BGA100*/
987 {
988 .chipid_cidr = 0x28ab07e0,
989 .name = "at91sam4s2c",
990 .total_flash_size = 128 * 1024,
991 .total_sram_size = 64 * 1024,
992 .n_gpnvms = 2,
993 .n_banks = 1,
994 {
995 /* .bank[0] = {*/
996 {
997 .probed = 0,
998 .pChip = NULL,
999 .pBank = NULL,
1000 .bank_number = 0,
1001 .base_address = FLASH_BANK_BASE_S,
1002 .controller_address = 0x400e0a00,
1003 .flash_wait_states = 5,
1004 .present = 1,
1005 .size_bytes = 128 * 1024,
1006 .nsectors = 16,
1007 .sector_size = 8192,
1008 .page_size = 512,
1009 },
1010 /* .bank[1] = {*/
1011 {
1012 .present = 0,
1013 .probed = 0,
1014 .bank_number = 1,
1015
1016 },
1017 },
1018 },
1019
1020 /*atsam4s2b - LQPF64/QFN64/WLCSP64*/
1021 {
1022 .chipid_cidr = 0x289b07e0,
1023 .name = "at91sam4s2b",
1024 .total_flash_size = 128 * 1024,
1025 .total_sram_size = 64 * 1024,
1026 .n_gpnvms = 2,
1027 .n_banks = 1,
1028 {
1029 /* .bank[0] = {*/
1030 {
1031 .probed = 0,
1032 .pChip = NULL,
1033 .pBank = NULL,
1034 .bank_number = 0,
1035 .base_address = FLASH_BANK_BASE_S,
1036 .controller_address = 0x400e0a00,
1037 .flash_wait_states = 5,
1038 .present = 1,
1039 .size_bytes = 128 * 1024,
1040 .nsectors = 16,
1041 .sector_size = 8192,
1042 .page_size = 512,
1043 },
1044 /* .bank[1] = {*/
1045 {
1046 .present = 0,
1047 .probed = 0,
1048 .bank_number = 1,
1049
1050 },
1051 },
1052 },
1053
1054 /*atsam4s2a - LQFP48/QFN48*/
1055 {
1056 .chipid_cidr = 0x288b07e0,
1057 .name = "at91sam4s2a",
1058 .total_flash_size = 128 * 1024,
1059 .total_sram_size = 64 * 1024,
1060 .n_gpnvms = 2,
1061 .n_banks = 1,
1062 {
1063 /* .bank[0] = {*/
1064 {
1065 .probed = 0,
1066 .pChip = NULL,
1067 .pBank = NULL,
1068 .bank_number = 0,
1069 .base_address = FLASH_BANK_BASE_S,
1070 .controller_address = 0x400e0a00,
1071 .flash_wait_states = 5,
1072 .present = 1,
1073 .size_bytes = 128 * 1024,
1074 .nsectors = 16,
1075 .sector_size = 8192,
1076 .page_size = 512,
1077 },
1078 /* .bank[1] = {*/
1079 {
1080 .present = 0,
1081 .probed = 0,
1082 .bank_number = 1,
1083
1084 },
1085 },
1086 },
1087
1088 /*at91sam4sd32c - LQFP100/BGA100*/
1089 {
1090 .chipid_cidr = 0x29a70ee0,
1091 .name = "at91sam4sd32c",
1092 .total_flash_size = 2048 * 1024,
1093 .total_sram_size = 160 * 1024,
1094 .n_gpnvms = 3,
1095 .n_banks = 2,
1096
1097 /* .bank[0] = { */
1098 {
1099 {
1100 .probed = 0,
1101 .pChip = NULL,
1102 .pBank = NULL,
1103 .bank_number = 0,
1104 .base_address = FLASH_BANK0_BASE_SD,
1105 .controller_address = 0x400e0a00,
1106 .flash_wait_states = 5,
1107 .present = 1,
1108 .size_bytes = 1024 * 1024,
1109 .nsectors = 128,
1110 .sector_size = 8192,
1111 .page_size = 512,
1112 },
1113
1114 /* .bank[1] = { */
1115 {
1116 .probed = 0,
1117 .pChip = NULL,
1118 .pBank = NULL,
1119 .bank_number = 1,
1120 .base_address = FLASH_BANK1_BASE_2048K_SD,
1121 .controller_address = 0x400e0c00,
1122 .flash_wait_states = 5,
1123 .present = 1,
1124 .size_bytes = 1024 * 1024,
1125 .nsectors = 128,
1126 .sector_size = 8192,
1127 .page_size = 512,
1128 },
1129 },
1130 },
1131
1132 /*at91sam4sd32b - LQFP64/BGA64*/
1133 {
1134 .chipid_cidr = 0x29970ee0,
1135 .name = "at91sam4sd32b",
1136 .total_flash_size = 2048 * 1024,
1137 .total_sram_size = 160 * 1024,
1138 .n_gpnvms = 3,
1139 .n_banks = 2,
1140
1141 /* .bank[0] = { */
1142 {
1143 {
1144 .probed = 0,
1145 .pChip = NULL,
1146 .pBank = NULL,
1147 .bank_number = 0,
1148 .base_address = FLASH_BANK0_BASE_SD,
1149 .controller_address = 0x400e0a00,
1150 .flash_wait_states = 5,
1151 .present = 1,
1152 .size_bytes = 1024 * 1024,
1153 .nsectors = 128,
1154 .sector_size = 8192,
1155 .page_size = 512,
1156 },
1157
1158 /* .bank[1] = { */
1159 {
1160 .probed = 0,
1161 .pChip = NULL,
1162 .pBank = NULL,
1163 .bank_number = 1,
1164 .base_address = FLASH_BANK1_BASE_2048K_SD,
1165 .controller_address = 0x400e0c00,
1166 .flash_wait_states = 5,
1167 .present = 1,
1168 .size_bytes = 1024 * 1024,
1169 .nsectors = 128,
1170 .sector_size = 8192,
1171 .page_size = 512,
1172 },
1173 },
1174 },
1175
1176 /*at91sam4sd16c - LQFP100/BGA100*/
1177 {
1178 .chipid_cidr = 0x29a70ce0,
1179 .name = "at91sam4sd16c",
1180 .total_flash_size = 1024 * 1024,
1181 .total_sram_size = 160 * 1024,
1182 .n_gpnvms = 3,
1183 .n_banks = 2,
1184
1185 /* .bank[0] = { */
1186 {
1187 {
1188 .probed = 0,
1189 .pChip = NULL,
1190 .pBank = NULL,
1191 .bank_number = 0,
1192 .base_address = FLASH_BANK0_BASE_SD,
1193 .controller_address = 0x400e0a00,
1194 .flash_wait_states = 5,
1195 .present = 1,
1196 .size_bytes = 512 * 1024,
1197 .nsectors = 64,
1198 .sector_size = 8192,
1199 .page_size = 512,
1200 },
1201
1202 /* .bank[1] = { */
1203 {
1204 .probed = 0,
1205 .pChip = NULL,
1206 .pBank = NULL,
1207 .bank_number = 1,
1208 .base_address = FLASH_BANK1_BASE_1024K_SD,
1209 .controller_address = 0x400e0c00,
1210 .flash_wait_states = 5,
1211 .present = 1,
1212 .size_bytes = 512 * 1024,
1213 .nsectors = 64,
1214 .sector_size = 8192,
1215 .page_size = 512,
1216 },
1217 },
1218 },
1219
1220 /*at91sam4sd16b - LQFP64/BGA64*/
1221 {
1222 .chipid_cidr = 0x29970ce0,
1223 .name = "at91sam4sd16b",
1224 .total_flash_size = 1024 * 1024,
1225 .total_sram_size = 160 * 1024,
1226 .n_gpnvms = 3,
1227 .n_banks = 2,
1228
1229 /* .bank[0] = { */
1230 {
1231 {
1232 .probed = 0,
1233 .pChip = NULL,
1234 .pBank = NULL,
1235 .bank_number = 0,
1236 .base_address = FLASH_BANK0_BASE_SD,
1237 .controller_address = 0x400e0a00,
1238 .flash_wait_states = 5,
1239 .present = 1,
1240 .size_bytes = 512 * 1024,
1241 .nsectors = 64,
1242 .sector_size = 8192,
1243 .page_size = 512,
1244 },
1245
1246 /* .bank[1] = { */
1247 {
1248 .probed = 0,
1249 .pChip = NULL,
1250 .pBank = NULL,
1251 .bank_number = 1,
1252 .base_address = FLASH_BANK1_BASE_1024K_SD,
1253 .controller_address = 0x400e0c00,
1254 .flash_wait_states = 5,
1255 .present = 1,
1256 .size_bytes = 512 * 1024,
1257 .nsectors = 64,
1258 .sector_size = 8192,
1259 .page_size = 512,
1260 },
1261 },
1262 },
1263
1264 /*at91sam4sa16c*/
1265 {
1266 .chipid_cidr = 0x28a70ce0,
1267 .name = "at91sam4sa16c",
1268 .total_flash_size = 1024 * 1024,
1269 .total_sram_size = 160 * 1024,
1270 .n_gpnvms = 3,
1271 .n_banks = 2,
1272
1273 /* .bank[0] = { */
1274 {
1275 {
1276 .probed = 0,
1277 .pChip = NULL,
1278 .pBank = NULL,
1279 .bank_number = 0,
1280 .base_address = FLASH_BANK0_BASE_SD,
1281 .controller_address = 0x400e0a00,
1282 .flash_wait_states = 5,
1283 .present = 1,
1284 .size_bytes = 512 * 1024,
1285 .nsectors = 64,
1286 .sector_size = 8192,
1287 .page_size = 512,
1288 },
1289
1290 /* .bank[1] = { */
1291 {
1292 .probed = 0,
1293 .pChip = NULL,
1294 .pBank = NULL,
1295 .bank_number = 1,
1296 .base_address = FLASH_BANK1_BASE_1024K_SD,
1297 .controller_address = 0x400e0c00,
1298 .flash_wait_states = 5,
1299 .present = 1,
1300 .size_bytes = 512 * 1024,
1301 .nsectors = 64,
1302 .sector_size = 8192,
1303 .page_size = 512,
1304 },
1305 },
1306 },
1307
1308 /* atsamg53n19 */
1309 {
1310 .chipid_cidr = 0x247e0ae0,
1311 .name = "atsamg53n19",
1312 .total_flash_size = 512 * 1024,
1313 .total_sram_size = 96 * 1024,
1314 .n_gpnvms = 2,
1315 .n_banks = 1,
1316
1317 /* .bank[0] = {*/
1318 {
1319 {
1320 .probed = 0,
1321 .pChip = NULL,
1322 .pBank = NULL,
1323 .bank_number = 0,
1324 .base_address = FLASH_BANK_BASE_S,
1325 .controller_address = 0x400e0a00,
1326 .flash_wait_states = 5,
1327 .present = 1,
1328 .size_bytes = 512 * 1024,
1329 .nsectors = 64,
1330 .sector_size = 8192,
1331 .page_size = 512,
1332 },
1333 /* .bank[1] = {*/
1334 {
1335 .present = 0,
1336 .probed = 0,
1337 .bank_number = 1,
1338
1339 },
1340 }
1341 },
1342
1343 /* atsamg55g19 */
1344 {
1345 .chipid_cidr = 0x24470ae0,
1346 .name = "atsamg55g19",
1347 .total_flash_size = 512 * 1024,
1348 .total_sram_size = 160 * 1024,
1349 .n_gpnvms = 2,
1350 .n_banks = 1,
1351
1352 {
1353 /* .bank[0] = */
1354 {
1355 .probed = 0,
1356 .pChip = NULL,
1357 .pBank = NULL,
1358 .bank_number = 0,
1359 .base_address = FLASH_BANK_BASE_S,
1360 .controller_address = 0x400e0a00,
1361 .flash_wait_states = 5,
1362 .present = 1,
1363 .size_bytes = 512 * 1024,
1364 .nsectors = 64,
1365 .sector_size = 8192,
1366 .page_size = 512,
1367 },
1368 /* .bank[1] = */
1369 {
1370 .present = 0,
1371 .probed = 0,
1372 .bank_number = 1,
1373 },
1374 }
1375 },
1376
1377 /* atsamg55j19 */
1378 {
1379 .chipid_cidr = 0x24570ae0,
1380 .name = "atsamg55j19",
1381 .total_flash_size = 512 * 1024,
1382 .total_sram_size = 160 * 1024,
1383 .n_gpnvms = 2,
1384 .n_banks = 1,
1385
1386 {
1387 /* .bank[0] = */
1388 {
1389 .probed = 0,
1390 .pChip = NULL,
1391 .pBank = NULL,
1392 .bank_number = 0,
1393 .base_address = FLASH_BANK_BASE_S,
1394 .controller_address = 0x400e0a00,
1395 .flash_wait_states = 5,
1396 .present = 1,
1397 .size_bytes = 512 * 1024,
1398 .nsectors = 64,
1399 .sector_size = 8192,
1400 .page_size = 512,
1401 },
1402 /* .bank[1] = */
1403 {
1404 .present = 0,
1405 .probed = 0,
1406 .bank_number = 1,
1407 },
1408 }
1409 },
1410
1411 /* terminate */
1412 {
1413 .chipid_cidr = 0,
1414 .name = NULL,
1415 }
1416 };
1417
1418 /* Globals above */
1419 /***********************************************************************
1420 **********************************************************************
1421 **********************************************************************
1422 **********************************************************************
1423 **********************************************************************
1424 **********************************************************************/
1425 /* *ATMEL* style code - from the SAM4 driver code */
1426
1427 /**
1428 * Get the current status of the EEFC and
1429 * the value of some status bits (LOCKE, PROGE).
1430 * @param pPrivate - info about the bank
1431 * @param v - result goes here
1432 */
1433 static int EFC_GetStatus(struct sam4_bank_private *pPrivate, uint32_t *v)
1434 {
1435 int r;
1436 r = target_read_u32(pPrivate->pChip->target,
1437 pPrivate->controller_address + offset_EFC_FSR,
1438 v);
1439 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1440 (unsigned int)(*v),
1441 ((unsigned int)((*v >> 2) & 1)),
1442 ((unsigned int)((*v >> 1) & 1)),
1443 ((unsigned int)((*v >> 0) & 1)));
1444
1445 return r;
1446 }
1447
1448 /**
1449 * Get the result of the last executed command.
1450 * @param pPrivate - info about the bank
1451 * @param v - result goes here
1452 */
1453 static int EFC_GetResult(struct sam4_bank_private *pPrivate, uint32_t *v)
1454 {
1455 int r;
1456 uint32_t rv;
1457 r = target_read_u32(pPrivate->pChip->target,
1458 pPrivate->controller_address + offset_EFC_FRR,
1459 &rv);
1460 if (v)
1461 *v = rv;
1462 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
1463 return r;
1464 }
1465
1466 static int EFC_StartCommand(struct sam4_bank_private *pPrivate,
1467 unsigned command, unsigned argument)
1468 {
1469 uint32_t n, v;
1470 int r;
1471 int retry;
1472
1473 retry = 0;
1474 do_retry:
1475
1476 /* Check command & argument */
1477 switch (command) {
1478
1479 case AT91C_EFC_FCMD_WP:
1480 case AT91C_EFC_FCMD_WPL:
1481 case AT91C_EFC_FCMD_EWP:
1482 case AT91C_EFC_FCMD_EWPL:
1483 /* case AT91C_EFC_FCMD_EPL: */
1484 case AT91C_EFC_FCMD_EPA:
1485 case AT91C_EFC_FCMD_SLB:
1486 case AT91C_EFC_FCMD_CLB:
1487 n = (pPrivate->size_bytes / pPrivate->page_size);
1488 if (argument >= n)
1489 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
1490 break;
1491
1492 case AT91C_EFC_FCMD_SFB:
1493 case AT91C_EFC_FCMD_CFB:
1494 if (argument >= pPrivate->pChip->details.n_gpnvms) {
1495 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1496 pPrivate->pChip->details.n_gpnvms);
1497 }
1498 break;
1499
1500 case AT91C_EFC_FCMD_GETD:
1501 case AT91C_EFC_FCMD_EA:
1502 case AT91C_EFC_FCMD_GLB:
1503 case AT91C_EFC_FCMD_GFB:
1504 case AT91C_EFC_FCMD_STUI:
1505 case AT91C_EFC_FCMD_SPUI:
1506 if (argument != 0)
1507 LOG_ERROR("Argument is meaningless for cmd: %d", command);
1508 break;
1509 default:
1510 LOG_ERROR("Unknown command %d", command);
1511 break;
1512 }
1513
1514 if (command == AT91C_EFC_FCMD_SPUI) {
1515 /* this is a very special situation. */
1516 /* Situation (1) - error/retry - see below */
1517 /* And we are being called recursively */
1518 /* Situation (2) - normal, finished reading unique id */
1519 } else {
1520 /* it should be "ready" */
1521 EFC_GetStatus(pPrivate, &v);
1522 if (v & 1) {
1523 /* then it is ready */
1524 /* we go on */
1525 } else {
1526 if (retry) {
1527 /* we have done this before */
1528 /* the controller is not responding. */
1529 LOG_ERROR("flash controller(%d) is not ready! Error",
1530 pPrivate->bank_number);
1531 return ERROR_FAIL;
1532 } else {
1533 retry++;
1534 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1535 pPrivate->bank_number);
1536 /* we do that by issuing the *STOP* command */
1537 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
1538 /* above is recursive, and further recursion is blocked by */
1539 /* if (command == AT91C_EFC_FCMD_SPUI) above */
1540 goto do_retry;
1541 }
1542 }
1543 }
1544
1545 v = (0x5A << 24) | (argument << 8) | command;
1546 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
1547 r = target_write_u32(pPrivate->pBank->target,
1548 pPrivate->controller_address + offset_EFC_FCR, v);
1549 if (r != ERROR_OK)
1550 LOG_DEBUG("Error Write failed");
1551 return r;
1552 }
1553
1554 /**
1555 * Performs the given command and wait until its completion (or an error).
1556 * @param pPrivate - info about the bank
1557 * @param command - Command to perform.
1558 * @param argument - Optional command argument.
1559 * @param status - put command status bits here
1560 */
1561 static int EFC_PerformCommand(struct sam4_bank_private *pPrivate,
1562 unsigned command,
1563 unsigned argument,
1564 uint32_t *status)
1565 {
1566
1567 int r;
1568 uint32_t v;
1569 int64_t ms_now, ms_end;
1570
1571 /* default */
1572 if (status)
1573 *status = 0;
1574
1575 r = EFC_StartCommand(pPrivate, command, argument);
1576 if (r != ERROR_OK)
1577 return r;
1578
1579 ms_end = 10000 + timeval_ms();
1580
1581 do {
1582 r = EFC_GetStatus(pPrivate, &v);
1583 if (r != ERROR_OK)
1584 return r;
1585 ms_now = timeval_ms();
1586 if (ms_now > ms_end) {
1587 /* error */
1588 LOG_ERROR("Command timeout");
1589 return ERROR_FAIL;
1590 }
1591 } while ((v & 1) == 0);
1592
1593 /* error bits.. */
1594 if (status)
1595 *status = (v & 0x6);
1596 return ERROR_OK;
1597
1598 }
1599
1600 /**
1601 * Read the unique ID.
1602 * @param pPrivate - info about the bank
1603 * The unique ID is stored in the 'pPrivate' structure.
1604 */
1605 static int FLASHD_ReadUniqueID(struct sam4_bank_private *pPrivate)
1606 {
1607 int r;
1608 uint32_t v;
1609 int x;
1610 /* assume 0 */
1611 pPrivate->pChip->cfg.unique_id[0] = 0;
1612 pPrivate->pChip->cfg.unique_id[1] = 0;
1613 pPrivate->pChip->cfg.unique_id[2] = 0;
1614 pPrivate->pChip->cfg.unique_id[3] = 0;
1615
1616 LOG_DEBUG("Begin");
1617 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
1618 if (r < 0)
1619 return r;
1620
1621 for (x = 0; x < 4; x++) {
1622 r = target_read_u32(pPrivate->pChip->target,
1623 pPrivate->pBank->base + (x * 4),
1624 &v);
1625 if (r < 0)
1626 return r;
1627 pPrivate->pChip->cfg.unique_id[x] = v;
1628 }
1629
1630 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
1631 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1632 r,
1633 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
1634 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
1635 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
1636 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
1637 return r;
1638
1639 }
1640
1641 /**
1642 * Erases the entire flash.
1643 * @param pPrivate - the info about the bank.
1644 */
1645 static int FLASHD_EraseEntireBank(struct sam4_bank_private *pPrivate)
1646 {
1647 LOG_DEBUG("Here");
1648 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
1649 }
1650
1651 /**
1652 * Erases the entire flash.
1653 * @param pPrivate - the info about the bank.
1654 */
1655 static int FLASHD_ErasePages(struct sam4_bank_private *pPrivate,
1656 int firstPage,
1657 int numPages,
1658 uint32_t *status)
1659 {
1660 LOG_DEBUG("Here");
1661 uint8_t erasePages;
1662 switch (numPages) {
1663 case 4:
1664 erasePages = 0x00;
1665 break;
1666 case 8:
1667 erasePages = 0x01;
1668 break;
1669 case 16:
1670 erasePages = 0x02;
1671 break;
1672 case 32:
1673 erasePages = 0x03;
1674 break;
1675 default:
1676 erasePages = 0x00;
1677 break;
1678 }
1679
1680 /* AT91C_EFC_FCMD_EPA
1681 * According to the datasheet FARG[15:2] defines the page from which
1682 * the erase will start.This page must be modulo 4, 8, 16 or 32
1683 * according to the number of pages to erase. FARG[1:0] defines the
1684 * number of pages to be erased. Previously (firstpage << 2) was used
1685 * to conform to this, seems it should not be shifted...
1686 */
1687 return EFC_PerformCommand(pPrivate,
1688 /* send Erase Page */
1689 AT91C_EFC_FCMD_EPA,
1690 (firstPage) | erasePages,
1691 status);
1692 }
1693
1694 /**
1695 * Gets current GPNVM state.
1696 * @param pPrivate - info about the bank.
1697 * @param gpnvm - GPNVM bit index.
1698 * @param puthere - result stored here.
1699 */
1700 /* ------------------------------------------------------------------------------ */
1701 static int FLASHD_GetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
1702 {
1703 uint32_t v;
1704 int r;
1705
1706 LOG_DEBUG("Here");
1707 if (pPrivate->bank_number != 0) {
1708 LOG_ERROR("GPNVM only works with Bank0");
1709 return ERROR_FAIL;
1710 }
1711
1712 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1713 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1714 gpnvm, pPrivate->pChip->details.n_gpnvms);
1715 return ERROR_FAIL;
1716 }
1717
1718 /* Get GPNVMs status */
1719 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
1720 if (r != ERROR_OK) {
1721 LOG_ERROR("Failed");
1722 return r;
1723 }
1724
1725 r = EFC_GetResult(pPrivate, &v);
1726
1727 if (puthere) {
1728 /* Check if GPNVM is set */
1729 /* get the bit and make it a 0/1 */
1730 *puthere = (v >> gpnvm) & 1;
1731 }
1732
1733 return r;
1734 }
1735
1736 /**
1737 * Clears the selected GPNVM bit.
1738 * @param pPrivate info about the bank
1739 * @param gpnvm GPNVM index.
1740 * @returns 0 if successful; otherwise returns an error code.
1741 */
1742 static int FLASHD_ClrGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
1743 {
1744 int r;
1745 unsigned v;
1746
1747 LOG_DEBUG("Here");
1748 if (pPrivate->bank_number != 0) {
1749 LOG_ERROR("GPNVM only works with Bank0");
1750 return ERROR_FAIL;
1751 }
1752
1753 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1754 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1755 gpnvm, pPrivate->pChip->details.n_gpnvms);
1756 return ERROR_FAIL;
1757 }
1758
1759 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1760 if (r != ERROR_OK) {
1761 LOG_DEBUG("Failed: %d", r);
1762 return r;
1763 }
1764 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
1765 LOG_DEBUG("End: %d", r);
1766 return r;
1767 }
1768
1769 /**
1770 * Sets the selected GPNVM bit.
1771 * @param pPrivate info about the bank
1772 * @param gpnvm GPNVM index.
1773 */
1774 static int FLASHD_SetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
1775 {
1776 int r;
1777 unsigned v;
1778
1779 if (pPrivate->bank_number != 0) {
1780 LOG_ERROR("GPNVM only works with Bank0");
1781 return ERROR_FAIL;
1782 }
1783
1784 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1785 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1786 gpnvm, pPrivate->pChip->details.n_gpnvms);
1787 return ERROR_FAIL;
1788 }
1789
1790 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1791 if (r != ERROR_OK)
1792 return r;
1793 if (v) {
1794 /* already set */
1795 r = ERROR_OK;
1796 } else {
1797 /* set it */
1798 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
1799 }
1800 return r;
1801 }
1802
1803 /**
1804 * Returns a bit field (at most 64) of locked regions within a page.
1805 * @param pPrivate info about the bank
1806 * @param v where to store locked bits
1807 */
1808 static int FLASHD_GetLockBits(struct sam4_bank_private *pPrivate, uint32_t *v)
1809 {
1810 int r;
1811 LOG_DEBUG("Here");
1812 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
1813 if (r == ERROR_OK) {
1814 EFC_GetResult(pPrivate, v);
1815 EFC_GetResult(pPrivate, v);
1816 EFC_GetResult(pPrivate, v);
1817 r = EFC_GetResult(pPrivate, v);
1818 }
1819 LOG_DEBUG("End: %d", r);
1820 return r;
1821 }
1822
1823 /**
1824 * Unlocks all the regions in the given address range.
1825 * @param pPrivate info about the bank
1826 * @param start_sector first sector to unlock
1827 * @param end_sector last (inclusive) to unlock
1828 */
1829
1830 static int FLASHD_Unlock(struct sam4_bank_private *pPrivate,
1831 unsigned start_sector,
1832 unsigned end_sector)
1833 {
1834 int r;
1835 uint32_t status;
1836 uint32_t pg;
1837 uint32_t pages_per_sector;
1838
1839 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1840
1841 /* Unlock all pages */
1842 while (start_sector <= end_sector) {
1843 pg = start_sector * pages_per_sector;
1844
1845 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
1846 if (r != ERROR_OK)
1847 return r;
1848 start_sector++;
1849 }
1850
1851 return ERROR_OK;
1852 }
1853
1854 /**
1855 * Locks regions
1856 * @param pPrivate - info about the bank
1857 * @param start_sector - first sector to lock
1858 * @param end_sector - last sector (inclusive) to lock
1859 */
1860 static int FLASHD_Lock(struct sam4_bank_private *pPrivate,
1861 unsigned start_sector,
1862 unsigned end_sector)
1863 {
1864 uint32_t status;
1865 uint32_t pg;
1866 uint32_t pages_per_sector;
1867 int r;
1868
1869 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1870
1871 /* Lock all pages */
1872 while (start_sector <= end_sector) {
1873 pg = start_sector * pages_per_sector;
1874
1875 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
1876 if (r != ERROR_OK)
1877 return r;
1878 start_sector++;
1879 }
1880 return ERROR_OK;
1881 }
1882
1883 /****** END SAM4 CODE ********/
1884
1885 /* begin helpful debug code */
1886 /* print the fieldname, the field value, in dec & hex, and return field value */
1887 static uint32_t sam4_reg_fieldname(struct sam4_chip *pChip,
1888 const char *regname,
1889 uint32_t value,
1890 unsigned shift,
1891 unsigned width)
1892 {
1893 uint32_t v;
1894 int hwidth, dwidth;
1895
1896
1897 /* extract the field */
1898 v = value >> shift;
1899 v = v & ((1 << width)-1);
1900 if (width <= 16) {
1901 hwidth = 4;
1902 dwidth = 5;
1903 } else {
1904 hwidth = 8;
1905 dwidth = 12;
1906 }
1907
1908 /* show the basics */
1909 LOG_USER_N("\t%*s: %*" PRId32 " [0x%0*" PRIx32 "] ",
1910 REG_NAME_WIDTH, regname,
1911 dwidth, v,
1912 hwidth, v);
1913 return v;
1914 }
1915
1916 static const char _unknown[] = "unknown";
1917 static const char *const eproc_names[] = {
1918 "Cortex-M7", /* 0 */
1919 "arm946es", /* 1 */
1920 "arm7tdmi", /* 2 */
1921 "Cortex-M3", /* 3 */
1922 "arm920t", /* 4 */
1923 "arm926ejs", /* 5 */
1924 "Cortex-A5", /* 6 */
1925 "Cortex-M4", /* 7 */
1926 _unknown, /* 8 */
1927 _unknown, /* 9 */
1928 _unknown, /* 10 */
1929 _unknown, /* 11 */
1930 _unknown, /* 12 */
1931 _unknown, /* 13 */
1932 _unknown, /* 14 */
1933 _unknown, /* 15 */
1934 };
1935
1936 #define nvpsize2 nvpsize /* these two tables are identical */
1937 static const char *const nvpsize[] = {
1938 "none", /* 0 */
1939 "8K bytes", /* 1 */
1940 "16K bytes", /* 2 */
1941 "32K bytes", /* 3 */
1942 _unknown, /* 4 */
1943 "64K bytes", /* 5 */
1944 _unknown, /* 6 */
1945 "128K bytes", /* 7 */
1946 "160K bytes", /* 8 */
1947 "256K bytes", /* 9 */
1948 "512K bytes", /* 10 */
1949 _unknown, /* 11 */
1950 "1024K bytes", /* 12 */
1951 _unknown, /* 13 */
1952 "2048K bytes", /* 14 */
1953 _unknown, /* 15 */
1954 };
1955
1956 static const char *const sramsize[] = {
1957 "48K Bytes", /* 0 */
1958 "1K Bytes", /* 1 */
1959 "2K Bytes", /* 2 */
1960 "6K Bytes", /* 3 */
1961 "112K Bytes", /* 4 */
1962 "4K Bytes", /* 5 */
1963 "80K Bytes", /* 6 */
1964 "160K Bytes", /* 7 */
1965 "8K Bytes", /* 8 */
1966 "16K Bytes", /* 9 */
1967 "32K Bytes", /* 10 */
1968 "64K Bytes", /* 11 */
1969 "128K Bytes", /* 12 */
1970 "256K Bytes", /* 13 */
1971 "96K Bytes", /* 14 */
1972 "512K Bytes", /* 15 */
1973
1974 };
1975
1976 static const struct archnames { unsigned value; const char *name; } archnames[] = {
1977 { 0x19, "AT91SAM9xx Series" },
1978 { 0x29, "AT91SAM9XExx Series" },
1979 { 0x34, "AT91x34 Series" },
1980 { 0x37, "CAP7 Series" },
1981 { 0x39, "CAP9 Series" },
1982 { 0x3B, "CAP11 Series" },
1983 { 0x3C, "ATSAM4E" },
1984 { 0x40, "AT91x40 Series" },
1985 { 0x42, "AT91x42 Series" },
1986 { 0x43, "SAMG51 Series"
1987 },
1988 { 0x44, "SAMG55 Series (49-pin WLCSP)" },
1989 { 0x45, "SAMG55 Series (64-pin)" },
1990 { 0x47, "SAMG53 Series"
1991 },
1992 { 0x55, "AT91x55 Series" },
1993 { 0x60, "AT91SAM7Axx Series" },
1994 { 0x61, "AT91SAM7AQxx Series" },
1995 { 0x63, "AT91x63 Series" },
1996 { 0x64, "SAM4CxxC (100-pin version)" },
1997 { 0x66, "SAM4CxxE (144-pin version)" },
1998 { 0x70, "AT91SAM7Sxx Series" },
1999 { 0x71, "AT91SAM7XCxx Series" },
2000 { 0x72, "AT91SAM7SExx Series" },
2001 { 0x73, "AT91SAM7Lxx Series" },
2002 { 0x75, "AT91SAM7Xxx Series" },
2003 { 0x76, "AT91SAM7SLxx Series" },
2004 { 0x80, "ATSAM3UxC Series (100-pin version)" },
2005 { 0x81, "ATSAM3UxE Series (144-pin version)" },
2006 { 0x83, "ATSAM3A/SAM4A xC Series (100-pin version)"},
2007 { 0x84, "ATSAM3X/SAM4X xC Series (100-pin version)"},
2008 { 0x85, "ATSAM3X/SAM4X xE Series (144-pin version)"},
2009 { 0x86, "ATSAM3X/SAM4X xG Series (208/217-pin version)" },
2010 { 0x88, "ATSAM3S/SAM4S xA Series (48-pin version)" },
2011 { 0x89, "ATSAM3S/SAM4S xB Series (64-pin version)" },
2012 { 0x8A, "ATSAM3S/SAM4S xC Series (100-pin version)"},
2013 { 0x92, "AT91x92 Series" },
2014 { 0x93, "ATSAM3NxA Series (48-pin version)" },
2015 { 0x94, "ATSAM3NxB Series (64-pin version)" },
2016 { 0x95, "ATSAM3NxC Series (100-pin version)" },
2017 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
2018 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
2019 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
2020 { 0xA5, "ATSAM5A" },
2021 { 0xF0, "AT75Cxx Series" },
2022 { -1, NULL },
2023 };
2024
2025 static const char *const nvptype[] = {
2026 "rom", /* 0 */
2027 "romless or onchip flash", /* 1 */
2028 "embedded flash memory",/* 2 */
2029 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
2030 "sram emulating flash", /* 4 */
2031 _unknown, /* 5 */
2032 _unknown, /* 6 */
2033 _unknown, /* 7 */
2034 };
2035
2036 static const char *_yes_or_no(uint32_t v)
2037 {
2038 if (v)
2039 return "YES";
2040 else
2041 return "NO";
2042 }
2043
2044 static const char *const _rc_freq[] = {
2045 "4 MHz", "8 MHz", "12 MHz", "reserved"
2046 };
2047
2048 static void sam4_explain_ckgr_mor(struct sam4_chip *pChip)
2049 {
2050 uint32_t v;
2051 uint32_t rcen;
2052
2053 v = sam4_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
2054 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2055 v = sam4_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
2056 LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2057 rcen = sam4_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
2058 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2059 v = sam4_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
2060 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2061
2062 pChip->cfg.rc_freq = 0;
2063 if (rcen) {
2064 switch (v) {
2065 default:
2066 pChip->cfg.rc_freq = 0;
2067 break;
2068 case 0:
2069 pChip->cfg.rc_freq = 4 * 1000 * 1000;
2070 break;
2071 case 1:
2072 pChip->cfg.rc_freq = 8 * 1000 * 1000;
2073 break;
2074 case 2:
2075 pChip->cfg.rc_freq = 12 * 1000 * 1000;
2076 break;
2077 }
2078 }
2079
2080 v = sam4_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
2081 LOG_USER("(startup clks, time= %f uSecs)",
2082 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
2083 v = sam4_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
2084 LOG_USER("(mainosc source: %s)",
2085 v ? "external xtal" : "internal RC");
2086
2087 v = sam4_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
2088 LOG_USER("(clock failure enabled: %s)",
2089 _yes_or_no(v));
2090 }
2091
2092 static void sam4_explain_chipid_cidr(struct sam4_chip *pChip)
2093 {
2094 int x;
2095 uint32_t v;
2096 const char *cp;
2097
2098 sam4_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
2099 LOG_USER_N("\n");
2100
2101 v = sam4_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
2102 LOG_USER("%s", eproc_names[v]);
2103
2104 v = sam4_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
2105 LOG_USER("%s", nvpsize[v]);
2106
2107 v = sam4_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
2108 LOG_USER("%s", nvpsize2[v]);
2109
2110 v = sam4_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
2111 LOG_USER("%s", sramsize[v]);
2112
2113 v = sam4_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
2114 cp = _unknown;
2115 for (x = 0; archnames[x].name; x++) {
2116 if (v == archnames[x].value) {
2117 cp = archnames[x].name;
2118 break;
2119 }
2120 }
2121
2122 LOG_USER("%s", cp);
2123
2124 v = sam4_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
2125 LOG_USER("%s", nvptype[v]);
2126
2127 v = sam4_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
2128 LOG_USER("(exists: %s)", _yes_or_no(v));
2129 }
2130
2131 static void sam4_explain_ckgr_mcfr(struct sam4_chip *pChip)
2132 {
2133 uint32_t v;
2134
2135 v = sam4_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
2136 LOG_USER("(main ready: %s)", _yes_or_no(v));
2137
2138 v = sam4_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
2139
2140 v = (v * pChip->cfg.slow_freq) / 16;
2141 pChip->cfg.mainosc_freq = v;
2142
2143 LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
2144 _tomhz(v),
2145 (uint32_t)(pChip->cfg.slow_freq / 1000),
2146 (uint32_t)(pChip->cfg.slow_freq % 1000));
2147 }
2148
2149 static void sam4_explain_ckgr_plla(struct sam4_chip *pChip)
2150 {
2151 uint32_t mula, diva;
2152
2153 diva = sam4_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
2154 LOG_USER_N("\n");
2155 mula = sam4_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
2156 LOG_USER_N("\n");
2157 pChip->cfg.plla_freq = 0;
2158 if (mula == 0)
2159 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2160 else if (diva == 0)
2161 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2162 else if (diva >= 1) {
2163 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
2164 LOG_USER("\tPLLA Freq: %3.03f MHz",
2165 _tomhz(pChip->cfg.plla_freq));
2166 }
2167 }
2168
2169 static void sam4_explain_mckr(struct sam4_chip *pChip)
2170 {
2171 uint32_t css, pres, fin = 0;
2172 int pdiv = 0;
2173 const char *cp = NULL;
2174
2175 css = sam4_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
2176 switch (css & 3) {
2177 case 0:
2178 fin = pChip->cfg.slow_freq;
2179 cp = "slowclk";
2180 break;
2181 case 1:
2182 fin = pChip->cfg.mainosc_freq;
2183 cp = "mainosc";
2184 break;
2185 case 2:
2186 fin = pChip->cfg.plla_freq;
2187 cp = "plla";
2188 break;
2189 case 3:
2190 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
2191 fin = 480 * 1000 * 1000;
2192 cp = "upll";
2193 } else {
2194 fin = 0;
2195 cp = "upll (*ERROR* UPLL is disabled)";
2196 }
2197 break;
2198 default:
2199 assert(0);
2200 break;
2201 }
2202
2203 LOG_USER("%s (%3.03f Mhz)",
2204 cp,
2205 _tomhz(fin));
2206 pres = sam4_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
2207 switch (pres & 0x07) {
2208 case 0:
2209 pdiv = 1;
2210 cp = "selected clock";
2211 break;
2212 case 1:
2213 pdiv = 2;
2214 cp = "clock/2";
2215 break;
2216 case 2:
2217 pdiv = 4;
2218 cp = "clock/4";
2219 break;
2220 case 3:
2221 pdiv = 8;
2222 cp = "clock/8";
2223 break;
2224 case 4:
2225 pdiv = 16;
2226 cp = "clock/16";
2227 break;
2228 case 5:
2229 pdiv = 32;
2230 cp = "clock/32";
2231 break;
2232 case 6:
2233 pdiv = 64;
2234 cp = "clock/64";
2235 break;
2236 case 7:
2237 pdiv = 6;
2238 cp = "clock/6";
2239 break;
2240 default:
2241 assert(0);
2242 break;
2243 }
2244 LOG_USER("(%s)", cp);
2245 fin = fin / pdiv;
2246 /* sam4 has a *SINGLE* clock - */
2247 /* other at91 series parts have divisors for these. */
2248 pChip->cfg.cpu_freq = fin;
2249 pChip->cfg.mclk_freq = fin;
2250 pChip->cfg.fclk_freq = fin;
2251 LOG_USER("\t\tResult CPU Freq: %3.03f",
2252 _tomhz(fin));
2253 }
2254
2255 #if 0
2256 static struct sam4_chip *target2sam4(struct target *pTarget)
2257 {
2258 struct sam4_chip *pChip;
2259
2260 if (pTarget == NULL)
2261 return NULL;
2262
2263 pChip = all_sam4_chips;
2264 while (pChip) {
2265 if (pChip->target == pTarget)
2266 break; /* return below */
2267 else
2268 pChip = pChip->next;
2269 }
2270 return pChip;
2271 }
2272 #endif
2273
2274 static uint32_t *sam4_get_reg_ptr(struct sam4_cfg *pCfg, const struct sam4_reg_list *pList)
2275 {
2276 /* this function exists to help */
2277 /* keep funky offsetof() errors */
2278 /* and casting from causing bugs */
2279
2280 /* By using prototypes - we can detect what would */
2281 /* be casting errors. */
2282
2283 return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
2284 }
2285
2286
2287 #define SAM4_ENTRY(NAME, FUNC) { .address = SAM4_ ## NAME, .struct_offset = offsetof( \
2288 struct sam4_cfg, \
2289 NAME), # NAME, FUNC }
2290 static const struct sam4_reg_list sam4_all_regs[] = {
2291 SAM4_ENTRY(CKGR_MOR, sam4_explain_ckgr_mor),
2292 SAM4_ENTRY(CKGR_MCFR, sam4_explain_ckgr_mcfr),
2293 SAM4_ENTRY(CKGR_PLLAR, sam4_explain_ckgr_plla),
2294 SAM4_ENTRY(CKGR_UCKR, NULL),
2295 SAM4_ENTRY(PMC_FSMR, NULL),
2296 SAM4_ENTRY(PMC_FSPR, NULL),
2297 SAM4_ENTRY(PMC_IMR, NULL),
2298 SAM4_ENTRY(PMC_MCKR, sam4_explain_mckr),
2299 SAM4_ENTRY(PMC_PCK0, NULL),
2300 SAM4_ENTRY(PMC_PCK1, NULL),
2301 SAM4_ENTRY(PMC_PCK2, NULL),
2302 SAM4_ENTRY(PMC_PCSR, NULL),
2303 SAM4_ENTRY(PMC_SCSR, NULL),
2304 SAM4_ENTRY(PMC_SR, NULL),
2305 SAM4_ENTRY(CHIPID_CIDR, sam4_explain_chipid_cidr),
2306 SAM4_ENTRY(CHIPID_EXID, NULL),
2307 /* TERMINATE THE LIST */
2308 { .name = NULL }
2309 };
2310 #undef SAM4_ENTRY
2311
2312 static struct sam4_bank_private *get_sam4_bank_private(struct flash_bank *bank)
2313 {
2314 return bank->driver_priv;
2315 }
2316
2317 /**
2318 * Given a pointer to where it goes in the structure,
2319 * determine the register name, address from the all registers table.
2320 */
2321 static const struct sam4_reg_list *sam4_GetReg(struct sam4_chip *pChip, uint32_t *goes_here)
2322 {
2323 const struct sam4_reg_list *pReg;
2324
2325 pReg = &(sam4_all_regs[0]);
2326 while (pReg->name) {
2327 uint32_t *pPossible;
2328
2329 /* calculate where this one go.. */
2330 /* it is "possibly" this register. */
2331
2332 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
2333
2334 /* well? Is it this register */
2335 if (pPossible == goes_here) {
2336 /* Jump for joy! */
2337 return pReg;
2338 }
2339
2340 /* next... */
2341 pReg++;
2342 }
2343 /* This is *TOTAL*PANIC* - we are totally screwed. */
2344 LOG_ERROR("INVALID SAM4 REGISTER");
2345 return NULL;
2346 }
2347
2348 static int sam4_ReadThisReg(struct sam4_chip *pChip, uint32_t *goes_here)
2349 {
2350 const struct sam4_reg_list *pReg;
2351 int r;
2352
2353 pReg = sam4_GetReg(pChip, goes_here);
2354 if (!pReg)
2355 return ERROR_FAIL;
2356
2357 r = target_read_u32(pChip->target, pReg->address, goes_here);
2358 if (r != ERROR_OK) {
2359 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d",
2360 pReg->name, (unsigned)(pReg->address), r);
2361 }
2362 return r;
2363 }
2364
2365 static int sam4_ReadAllRegs(struct sam4_chip *pChip)
2366 {
2367 int r;
2368 const struct sam4_reg_list *pReg;
2369
2370 pReg = &(sam4_all_regs[0]);
2371 while (pReg->name) {
2372 r = sam4_ReadThisReg(pChip,
2373 sam4_get_reg_ptr(&(pChip->cfg), pReg));
2374 if (r != ERROR_OK) {
2375 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Error: %d",
2376 pReg->name, ((unsigned)(pReg->address)), r);
2377 return r;
2378 }
2379 pReg++;
2380 }
2381
2382 return ERROR_OK;
2383 }
2384
2385 static int sam4_GetInfo(struct sam4_chip *pChip)
2386 {
2387 const struct sam4_reg_list *pReg;
2388 uint32_t regval;
2389
2390 pReg = &(sam4_all_regs[0]);
2391 while (pReg->name) {
2392 /* display all regs */
2393 LOG_DEBUG("Start: %s", pReg->name);
2394 regval = *sam4_get_reg_ptr(&(pChip->cfg), pReg);
2395 LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
2396 REG_NAME_WIDTH,
2397 pReg->name,
2398 pReg->address,
2399 regval);
2400 if (pReg->explain_func)
2401 (*(pReg->explain_func))(pChip);
2402 LOG_DEBUG("End: %s", pReg->name);
2403 pReg++;
2404 }
2405 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
2406 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
2407 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
2408 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
2409 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
2410
2411 LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08"PRIx32,
2412 pChip->cfg.unique_id[0],
2413 pChip->cfg.unique_id[1],
2414 pChip->cfg.unique_id[2],
2415 pChip->cfg.unique_id[3]);
2416
2417 return ERROR_OK;
2418 }
2419
2420 static int sam4_protect_check(struct flash_bank *bank)
2421 {
2422 int r;
2423 uint32_t v[4] = {0};
2424 unsigned x;
2425 struct sam4_bank_private *pPrivate;
2426
2427 LOG_DEBUG("Begin");
2428 if (bank->target->state != TARGET_HALTED) {
2429 LOG_ERROR("Target not halted");
2430 return ERROR_TARGET_NOT_HALTED;
2431 }
2432
2433 pPrivate = get_sam4_bank_private(bank);
2434 if (!pPrivate) {
2435 LOG_ERROR("no private for this bank?");
2436 return ERROR_FAIL;
2437 }
2438 if (!(pPrivate->probed))
2439 return ERROR_FLASH_BANK_NOT_PROBED;
2440
2441 r = FLASHD_GetLockBits(pPrivate, v);
2442 if (r != ERROR_OK) {
2443 LOG_DEBUG("Failed: %d", r);
2444 return r;
2445 }
2446
2447 for (x = 0; x < pPrivate->nsectors; x++)
2448 bank->sectors[x].is_protected = (!!(v[x >> 5] & (1 << (x % 32))));
2449 LOG_DEBUG("Done");
2450 return ERROR_OK;
2451 }
2452
2453 FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
2454 {
2455 struct sam4_chip *pChip;
2456
2457 pChip = all_sam4_chips;
2458
2459 /* is this an existing chip? */
2460 while (pChip) {
2461 if (pChip->target == bank->target)
2462 break;
2463 pChip = pChip->next;
2464 }
2465
2466 if (!pChip) {
2467 /* this is a *NEW* chip */
2468 pChip = calloc(1, sizeof(struct sam4_chip));
2469 if (!pChip) {
2470 LOG_ERROR("NO RAM!");
2471 return ERROR_FAIL;
2472 }
2473 pChip->target = bank->target;
2474 /* insert at head */
2475 pChip->next = all_sam4_chips;
2476 all_sam4_chips = pChip;
2477 pChip->target = bank->target;
2478 /* assumption is this runs at 32khz */
2479 pChip->cfg.slow_freq = 32768;
2480 pChip->probed = 0;
2481 }
2482
2483 switch (bank->base) {
2484 default:
2485 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x"
2486 "[at91sam4s series] )",
2487 ((unsigned int)(bank->base)),
2488 ((unsigned int)(FLASH_BANK_BASE_S)));
2489 return ERROR_FAIL;
2490 break;
2491
2492 /* at91sam4s series only has bank 0*/
2493 /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/
2494 case FLASH_BANK_BASE_S:
2495 case FLASH_BANK_BASE_C:
2496 bank->driver_priv = &(pChip->details.bank[0]);
2497 bank->bank_number = 0;
2498 pChip->details.bank[0].pChip = pChip;
2499 pChip->details.bank[0].pBank = bank;
2500 break;
2501
2502 /* Bank 1 of at91sam4sd/at91sam4c32 series */
2503 case FLASH_BANK1_BASE_1024K_SD:
2504 case FLASH_BANK1_BASE_2048K_SD:
2505 case FLASH_BANK1_BASE_C32:
2506 bank->driver_priv = &(pChip->details.bank[1]);
2507 bank->bank_number = 1;
2508 pChip->details.bank[1].pChip = pChip;
2509 pChip->details.bank[1].pBank = bank;
2510 break;
2511 }
2512
2513 /* we initialize after probing. */
2514 return ERROR_OK;
2515 }
2516
2517 static int sam4_GetDetails(struct sam4_bank_private *pPrivate)
2518 {
2519 const struct sam4_chip_details *pDetails;
2520 struct sam4_chip *pChip;
2521 struct flash_bank *saved_banks[SAM4_MAX_FLASH_BANKS];
2522 unsigned x;
2523
2524 LOG_DEBUG("Begin");
2525 pDetails = all_sam4_details;
2526 while (pDetails->name) {
2527 /* Compare cidr without version bits */
2528 if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
2529 break;
2530 else
2531 pDetails++;
2532 }
2533 if (pDetails->name == NULL) {
2534 LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
2535 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
2536 /* Help the victim, print details about the chip */
2537 LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
2538 pPrivate->pChip->cfg.CHIPID_CIDR);
2539 sam4_explain_chipid_cidr(pPrivate->pChip);
2540 return ERROR_FAIL;
2541 }
2542
2543 /* DANGER: THERE ARE DRAGONS HERE */
2544
2545 /* get our pChip - it is going */
2546 /* to be over-written shortly */
2547 pChip = pPrivate->pChip;
2548
2549 /* Note that, in reality: */
2550 /* */
2551 /* pPrivate = &(pChip->details.bank[0]) */
2552 /* or pPrivate = &(pChip->details.bank[1]) */
2553 /* */
2554
2555 /* save the "bank" pointers */
2556 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++)
2557 saved_banks[x] = pChip->details.bank[x].pBank;
2558
2559 /* Overwrite the "details" structure. */
2560 memcpy(&(pPrivate->pChip->details),
2561 pDetails,
2562 sizeof(pPrivate->pChip->details));
2563
2564 /* now fix the ghosted pointers */
2565 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2566 pChip->details.bank[x].pChip = pChip;
2567 pChip->details.bank[x].pBank = saved_banks[x];
2568 }
2569
2570 /* update the *BANK*SIZE* */
2571
2572 LOG_DEBUG("End");
2573 return ERROR_OK;
2574 }
2575
2576 static int _sam4_probe(struct flash_bank *bank, int noise)
2577 {
2578 unsigned x;
2579 int r;
2580 struct sam4_bank_private *pPrivate;
2581
2582
2583 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
2584 if (bank->target->state != TARGET_HALTED) {
2585 LOG_ERROR("Target not halted");
2586 return ERROR_TARGET_NOT_HALTED;
2587 }
2588
2589 pPrivate = get_sam4_bank_private(bank);
2590 if (!pPrivate) {
2591 LOG_ERROR("Invalid/unknown bank number");
2592 return ERROR_FAIL;
2593 }
2594
2595 r = sam4_ReadAllRegs(pPrivate->pChip);
2596 if (r != ERROR_OK)
2597 return r;
2598
2599 LOG_DEBUG("Here");
2600 if (pPrivate->pChip->probed)
2601 r = sam4_GetInfo(pPrivate->pChip);
2602 else
2603 r = sam4_GetDetails(pPrivate);
2604 if (r != ERROR_OK)
2605 return r;
2606
2607 /* update the flash bank size */
2608 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
2609 if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
2610 bank->size = pPrivate->pChip->details.bank[x].size_bytes;
2611 break;
2612 }
2613 }
2614
2615 if (bank->sectors == NULL) {
2616 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
2617 if (bank->sectors == NULL) {
2618 LOG_ERROR("No memory!");
2619 return ERROR_FAIL;
2620 }
2621 bank->num_sectors = pPrivate->nsectors;
2622
2623 for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
2624 bank->sectors[x].size = pPrivate->sector_size;
2625 bank->sectors[x].offset = x * (pPrivate->sector_size);
2626 /* mark as unknown */
2627 bank->sectors[x].is_erased = -1;
2628 bank->sectors[x].is_protected = -1;
2629 }
2630 }
2631
2632 pPrivate->probed = 1;
2633
2634 r = sam4_protect_check(bank);
2635 if (r != ERROR_OK)
2636 return r;
2637
2638 LOG_DEBUG("Bank = %d, nbanks = %d",
2639 pPrivate->bank_number, pPrivate->pChip->details.n_banks);
2640 if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
2641 /* read unique id, */
2642 /* it appears to be associated with the *last* flash bank. */
2643 FLASHD_ReadUniqueID(pPrivate);
2644 }
2645
2646 return r;
2647 }
2648
2649 static int sam4_probe(struct flash_bank *bank)
2650 {
2651 return _sam4_probe(bank, 1);
2652 }
2653
2654 static int sam4_auto_probe(struct flash_bank *bank)
2655 {
2656 return _sam4_probe(bank, 0);
2657 }
2658
2659 static int sam4_erase(struct flash_bank *bank, int first, int last)
2660 {
2661 struct sam4_bank_private *pPrivate;
2662 int r;
2663 int i;
2664 int pageCount;
2665 /*16 pages equals 8KB - Same size as a lock region*/
2666 pageCount = 16;
2667 uint32_t status;
2668
2669 LOG_DEBUG("Here");
2670 if (bank->target->state != TARGET_HALTED) {
2671 LOG_ERROR("Target not halted");
2672 return ERROR_TARGET_NOT_HALTED;
2673 }
2674
2675 r = sam4_auto_probe(bank);
2676 if (r != ERROR_OK) {
2677 LOG_DEBUG("Here,r=%d", r);
2678 return r;
2679 }
2680
2681 pPrivate = get_sam4_bank_private(bank);
2682 if (!(pPrivate->probed))
2683 return ERROR_FLASH_BANK_NOT_PROBED;
2684
2685 if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
2686 /* whole chip */
2687 LOG_DEBUG("Here");
2688 return FLASHD_EraseEntireBank(pPrivate);
2689 }
2690 LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
2691 LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", (unsigned int)(first), (unsigned int)(last));
2692 for (i = first; i <= last; i++) {
2693 /*16 pages equals 8KB - Same size as a lock region*/
2694 r = FLASHD_ErasePages(pPrivate, (i * pageCount), pageCount, &status);
2695 LOG_INFO("Erasing sector: 0x%08x", (unsigned int)(i));
2696 if (r != ERROR_OK)
2697 LOG_ERROR("SAM4: Error performing Erase page @ lock region number %d",
2698 (unsigned int)(i));
2699 if (status & (1 << 2)) {
2700 LOG_ERROR("SAM4: Lock Region %d is locked", (unsigned int)(i));
2701 return ERROR_FAIL;
2702 }
2703 if (status & (1 << 1)) {
2704 LOG_ERROR("SAM4: Flash Command error @lock region %d", (unsigned int)(i));
2705 return ERROR_FAIL;
2706 }
2707 }
2708
2709 return ERROR_OK;
2710 }
2711
2712 static int sam4_protect(struct flash_bank *bank, int set, int first, int last)
2713 {
2714 struct sam4_bank_private *pPrivate;
2715 int r;
2716
2717 LOG_DEBUG("Here");
2718 if (bank->target->state != TARGET_HALTED) {
2719 LOG_ERROR("Target not halted");
2720 return ERROR_TARGET_NOT_HALTED;
2721 }
2722
2723 pPrivate = get_sam4_bank_private(bank);
2724 if (!(pPrivate->probed))
2725 return ERROR_FLASH_BANK_NOT_PROBED;
2726
2727 if (set)
2728 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
2729 else
2730 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
2731 LOG_DEBUG("End: r=%d", r);
2732
2733 return r;
2734
2735 }
2736
2737 static int sam4_page_read(struct sam4_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2738 {
2739 uint32_t adr;
2740 int r;
2741
2742 adr = pagenum * pPrivate->page_size;
2743 adr = adr + pPrivate->base_address;
2744
2745 r = target_read_memory(pPrivate->pChip->target,
2746 adr,
2747 4, /* THIS*MUST*BE* in 32bit values */
2748 pPrivate->page_size / 4,
2749 buf);
2750 if (r != ERROR_OK)
2751 LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
2752 (unsigned int)(adr));
2753 return r;
2754 }
2755
2756 static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, const uint8_t *buf)
2757 {
2758 uint32_t adr;
2759 uint32_t status;
2760 uint32_t fmr; /* EEFC Flash Mode Register */
2761 int r;
2762
2763 adr = pagenum * pPrivate->page_size;
2764 adr = (adr + pPrivate->base_address);
2765
2766 /* Get flash mode register value */
2767 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
2768 if (r != ERROR_OK)
2769 LOG_DEBUG("Error Read failed: read flash mode register");
2770
2771 /* Clear flash wait state field */
2772 fmr &= 0xfffff0ff;
2773
2774 /* set FWS (flash wait states) field in the FMR (flash mode register) */
2775 fmr |= (pPrivate->flash_wait_states << 8);
2776
2777 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
2778 r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
2779 if (r != ERROR_OK)
2780 LOG_DEBUG("Error Write failed: set flash mode register");
2781
2782 /* 1st sector 8kBytes - page 0 - 15*/
2783 /* 2nd sector 8kBytes - page 16 - 30*/
2784 /* 3rd sector 48kBytes - page 31 - 127*/
2785 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
2786 r = target_write_memory(pPrivate->pChip->target,
2787 adr,
2788 4, /* THIS*MUST*BE* in 32bit values */
2789 pPrivate->page_size / 4,
2790 buf);
2791 if (r != ERROR_OK) {
2792 LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
2793 (unsigned int)(adr));
2794 return r;
2795 }
2796
2797 r = EFC_PerformCommand(pPrivate,
2798 /* send Erase & Write Page */
2799 AT91C_EFC_FCMD_WP, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
2800 pagenum,
2801 &status);
2802
2803 if (r != ERROR_OK)
2804 LOG_ERROR("SAM4: Error performing Write page @ phys address 0x%08x",
2805 (unsigned int)(adr));
2806 if (status & (1 << 2)) {
2807 LOG_ERROR("SAM4: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
2808 return ERROR_FAIL;
2809 }
2810 if (status & (1 << 1)) {
2811 LOG_ERROR("SAM4: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
2812 return ERROR_FAIL;
2813 }
2814 return ERROR_OK;
2815 }
2816
2817 static int sam4_write(struct flash_bank *bank,
2818 const uint8_t *buffer,
2819 uint32_t offset,
2820 uint32_t count)
2821 {
2822 int n;
2823 unsigned page_cur;
2824 unsigned page_end;
2825 int r;
2826 unsigned page_offset;
2827 struct sam4_bank_private *pPrivate;
2828 uint8_t *pagebuffer;
2829
2830 /* incase we bail further below, set this to null */
2831 pagebuffer = NULL;
2832
2833 /* ignore dumb requests */
2834 if (count == 0) {
2835 r = ERROR_OK;
2836 goto done;
2837 }
2838
2839 if (bank->target->state != TARGET_HALTED) {
2840 LOG_ERROR("Target not halted");
2841 r = ERROR_TARGET_NOT_HALTED;
2842 goto done;
2843 }
2844
2845 pPrivate = get_sam4_bank_private(bank);
2846 if (!(pPrivate->probed)) {
2847 r = ERROR_FLASH_BANK_NOT_PROBED;
2848 goto done;
2849 }
2850
2851 if ((offset + count) > pPrivate->size_bytes) {
2852 LOG_ERROR("Flash write error - past end of bank");
2853 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2854 (unsigned int)(offset),
2855 (unsigned int)(count),
2856 (unsigned int)(pPrivate->size_bytes));
2857 r = ERROR_FAIL;
2858 goto done;
2859 }
2860
2861 pagebuffer = malloc(pPrivate->page_size);
2862 if (!pagebuffer) {
2863 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
2864 r = ERROR_FAIL;
2865 goto done;
2866 }
2867
2868 /* what page do we start & end in? */
2869 page_cur = offset / pPrivate->page_size;
2870 page_end = (offset + count - 1) / pPrivate->page_size;
2871
2872 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
2873 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
2874
2875 /* Special case: all one page */
2876 /* */
2877 /* Otherwise: */
2878 /* (1) non-aligned start */
2879 /* (2) body pages */
2880 /* (3) non-aligned end. */
2881
2882 /* Handle special case - all one page. */
2883 if (page_cur == page_end) {
2884 LOG_DEBUG("Special case, all in one page");
2885 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2886 if (r != ERROR_OK)
2887 goto done;
2888
2889 page_offset = (offset & (pPrivate->page_size-1));
2890 memcpy(pagebuffer + page_offset,
2891 buffer,
2892 count);
2893
2894 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2895 if (r != ERROR_OK)
2896 goto done;
2897 r = ERROR_OK;
2898 goto done;
2899 }
2900
2901 /* non-aligned start */
2902 page_offset = offset & (pPrivate->page_size - 1);
2903 if (page_offset) {
2904 LOG_DEBUG("Not-Aligned start");
2905 /* read the partial */
2906 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2907 if (r != ERROR_OK)
2908 goto done;
2909
2910 /* over-write with new data */
2911 n = (pPrivate->page_size - page_offset);
2912 memcpy(pagebuffer + page_offset,
2913 buffer,
2914 n);
2915
2916 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2917 if (r != ERROR_OK)
2918 goto done;
2919
2920 count -= n;
2921 offset += n;
2922 buffer += n;
2923 page_cur++;
2924 }
2925
2926 /* By checking that offset is correct here, we also
2927 fix a clang warning */
2928 assert(offset % pPrivate->page_size == 0);
2929
2930 /* intermediate large pages */
2931 /* also - the final *terminal* */
2932 /* if that terminal page is a full page */
2933 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2934 (int)page_cur, (int)page_end, (unsigned int)(count));
2935
2936 while ((page_cur < page_end) &&
2937 (count >= pPrivate->page_size)) {
2938 r = sam4_page_write(pPrivate, page_cur, buffer);
2939 if (r != ERROR_OK)
2940 goto done;
2941 count -= pPrivate->page_size;
2942 buffer += pPrivate->page_size;
2943 page_cur += 1;
2944 }
2945
2946 /* terminal partial page? */
2947 if (count) {
2948 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
2949 /* we have a partial page */
2950 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2951 if (r != ERROR_OK)
2952 goto done;
2953 /* data goes at start */
2954 memcpy(pagebuffer, buffer, count);
2955 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2956 if (r != ERROR_OK)
2957 goto done;
2958 }
2959 LOG_DEBUG("Done!");
2960 r = ERROR_OK;
2961 done:
2962 if (pagebuffer)
2963 free(pagebuffer);
2964 return r;
2965 }
2966
2967 COMMAND_HANDLER(sam4_handle_info_command)
2968 {
2969 struct sam4_chip *pChip;
2970 pChip = get_current_sam4(CMD_CTX);
2971 if (!pChip)
2972 return ERROR_OK;
2973
2974 unsigned x;
2975 int r;
2976
2977 /* bank0 must exist before we can do anything */
2978 if (pChip->details.bank[0].pBank == NULL) {
2979 x = 0;
2980 need_define:
2981 command_print(CMD_CTX,
2982 "Please define bank %d via command: flash bank %s ... ",
2983 x,
2984 at91sam4_flash.name);
2985 return ERROR_FAIL;
2986 }
2987
2988 /* if bank 0 is not probed, then probe it */
2989 if (!(pChip->details.bank[0].probed)) {
2990 r = sam4_auto_probe(pChip->details.bank[0].pBank);
2991 if (r != ERROR_OK)
2992 return ERROR_FAIL;
2993 }
2994 /* above guarantees the "chip details" structure is valid */
2995 /* and thus, bank private areas are valid */
2996 /* and we have a SAM4 chip, what a concept! */
2997
2998 /* auto-probe other banks, 0 done above */
2999 for (x = 1; x < SAM4_MAX_FLASH_BANKS; x++) {
3000 /* skip banks not present */
3001 if (!(pChip->details.bank[x].present))
3002 continue;
3003
3004 if (pChip->details.bank[x].pBank == NULL)
3005 goto need_define;
3006
3007 if (pChip->details.bank[x].probed)
3008 continue;
3009
3010 r = sam4_auto_probe(pChip->details.bank[x].pBank);
3011 if (r != ERROR_OK)
3012 return r;
3013 }
3014
3015 r = sam4_GetInfo(pChip);
3016 if (r != ERROR_OK) {
3017 LOG_DEBUG("Sam4Info, Failed %d", r);
3018 return r;
3019 }
3020
3021 return ERROR_OK;
3022 }
3023
3024 COMMAND_HANDLER(sam4_handle_gpnvm_command)
3025 {
3026 unsigned x, v;
3027 int r, who;
3028 struct sam4_chip *pChip;
3029
3030 pChip = get_current_sam4(CMD_CTX);
3031 if (!pChip)
3032 return ERROR_OK;
3033
3034 if (pChip->target->state != TARGET_HALTED) {
3035 LOG_ERROR("sam4 - target not halted");
3036 return ERROR_TARGET_NOT_HALTED;
3037 }
3038
3039 if (pChip->details.bank[0].pBank == NULL) {
3040 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
3041 at91sam4_flash.name);
3042 return ERROR_FAIL;
3043 }
3044 if (!pChip->details.bank[0].probed) {
3045 r = sam4_auto_probe(pChip->details.bank[0].pBank);
3046 if (r != ERROR_OK)
3047 return r;
3048 }
3049
3050 switch (CMD_ARGC) {
3051 default:
3052 return ERROR_COMMAND_SYNTAX_ERROR;
3053 break;
3054 case 0:
3055 goto showall;
3056 break;
3057 case 1:
3058 who = -1;
3059 break;
3060 case 2:
3061 if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
3062 who = -1;
3063 else {
3064 uint32_t v32;
3065 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
3066 who = v32;
3067 }
3068 break;
3069 }
3070
3071 if (0 == strcmp("show", CMD_ARGV[0])) {
3072 if (who == -1) {
3073 showall:
3074 r = ERROR_OK;
3075 for (x = 0; x < pChip->details.n_gpnvms; x++) {
3076 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
3077 if (r != ERROR_OK)
3078 break;
3079 command_print(CMD_CTX, "sam4-gpnvm%u: %u", x, v);
3080 }
3081 return r;
3082 }
3083 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
3084 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
3085 command_print(CMD_CTX, "sam4-gpnvm%u: %u", who, v);
3086 return r;
3087 } else {
3088 command_print(CMD_CTX, "sam4-gpnvm invalid GPNVM: %u", who);
3089 return ERROR_COMMAND_SYNTAX_ERROR;
3090 }
3091 }
3092
3093 if (who == -1) {
3094 command_print(CMD_CTX, "Missing GPNVM number");
3095 return ERROR_COMMAND_SYNTAX_ERROR;
3096 }
3097
3098 if (0 == strcmp("set", CMD_ARGV[0]))
3099 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
3100 else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
3101 (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
3102 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
3103 else {
3104 command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
3105 r = ERROR_COMMAND_SYNTAX_ERROR;
3106 }
3107 return r;
3108 }
3109
3110 COMMAND_HANDLER(sam4_handle_slowclk_command)
3111 {
3112 struct sam4_chip *pChip;
3113
3114 pChip = get_current_sam4(CMD_CTX);
3115 if (!pChip)
3116 return ERROR_OK;
3117
3118 switch (CMD_ARGC) {
3119 case 0:
3120 /* show */
3121 break;
3122 case 1:
3123 {
3124 /* set */
3125 uint32_t v;
3126 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3127 if (v > 200000) {
3128 /* absurd slow clock of 200Khz? */