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Added Atmel SAM4SA16C chip (chip ID 0x28a70ce0).
[openocd.git] / src / flash / nor / at91sam4.c
1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
4 * *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
7 * *
8 * Copyright (C) 2011 by Olivier Schonken, Jim Norris *
9 * (at91sam3x* & at91sam4 support)* *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
19 * GNU General public License for more details. *
20 * *
21 * You should have received a copy of the GNU General public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
25 ****************************************************************************/
26
27 /* Some of the the lower level code was based on code supplied by
28 * ATMEL under this copyright. */
29
30 /* BEGIN ATMEL COPYRIGHT */
31 /* ----------------------------------------------------------------------------
32 * ATMEL Microcontroller Software Support
33 * ----------------------------------------------------------------------------
34 * Copyright (c) 2009, Atmel Corporation
35 *
36 * All rights reserved.
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions are met:
40 *
41 * - Redistributions of source code must retain the above copyright notice,
42 * this list of conditions and the disclaimer below.
43 *
44 * Atmel's name may not be used to endorse or promote products derived from
45 * this software without specific prior written permission.
46 *
47 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
49 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
50 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
52 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
53 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
54 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
55 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
56 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
57 * ----------------------------------------------------------------------------
58 */
59 /* END ATMEL COPYRIGHT */
60
61 #ifdef HAVE_CONFIG_H
62 #include "config.h"
63 #endif
64
65 #include "imp.h"
66 #include <helper/time_support.h>
67
68 #define REG_NAME_WIDTH (12)
69
70 /* at91sam4s/at91sam4e series (has always one flash bank)*/
71 #define FLASH_BANK_BASE_S 0x00400000
72
73 /* at91sam4sd series (two one flash banks), first bank address */
74 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
75 /* at91sam4sd16x, second bank address */
76 #define FLASH_BANK1_BASE_1024K_SD (FLASH_BANK0_BASE_SD+(1024*1024/2))
77 /* at91sam4sd32x, second bank address */
78 #define FLASH_BANK1_BASE_2048K_SD (FLASH_BANK0_BASE_SD+(2048*1024/2))
79
80 #define AT91C_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
81 #define AT91C_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
82 #define AT91C_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
83 #define AT91C_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
84 #define AT91C_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page and Write Page then Lock */
85 #define AT91C_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
86 /* cmd6 is not present in the at91sam4u4/2/1 data sheet table 19-2 */
87 /* #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane? */
88 #define AT91C_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
89 #define AT91C_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
90 #define AT91C_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
91 #define AT91C_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
92 #define AT91C_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
93 #define AT91C_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
94 #define AT91C_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
95 #define AT91C_EFC_FCMD_STUI (0xE) /* (EFC) Start Read Unique ID */
96 #define AT91C_EFC_FCMD_SPUI (0xF) /* (EFC) Stop Read Unique ID */
97
98 #define offset_EFC_FMR 0
99 #define offset_EFC_FCR 4
100 #define offset_EFC_FSR 8
101 #define offset_EFC_FRR 12
102
103 extern struct flash_driver at91sam4_flash;
104
105 static float _tomhz(uint32_t freq_hz)
106 {
107 float f;
108
109 f = ((float)(freq_hz)) / 1000000.0;
110 return f;
111 }
112
113 /* How the chip is configured. */
114 struct sam4_cfg {
115 uint32_t unique_id[4];
116
117 uint32_t slow_freq;
118 uint32_t rc_freq;
119 uint32_t mainosc_freq;
120 uint32_t plla_freq;
121 uint32_t mclk_freq;
122 uint32_t cpu_freq;
123 uint32_t fclk_freq;
124 uint32_t pclk0_freq;
125 uint32_t pclk1_freq;
126 uint32_t pclk2_freq;
127
128
129 #define SAM4_CHIPID_CIDR (0x400E0740)
130 uint32_t CHIPID_CIDR;
131 #define SAM4_CHIPID_EXID (0x400E0744)
132 uint32_t CHIPID_EXID;
133
134 #define SAM4_PMC_BASE (0x400E0400)
135 #define SAM4_PMC_SCSR (SAM4_PMC_BASE + 0x0008)
136 uint32_t PMC_SCSR;
137 #define SAM4_PMC_PCSR (SAM4_PMC_BASE + 0x0018)
138 uint32_t PMC_PCSR;
139 #define SAM4_CKGR_UCKR (SAM4_PMC_BASE + 0x001c)
140 uint32_t CKGR_UCKR;
141 #define SAM4_CKGR_MOR (SAM4_PMC_BASE + 0x0020)
142 uint32_t CKGR_MOR;
143 #define SAM4_CKGR_MCFR (SAM4_PMC_BASE + 0x0024)
144 uint32_t CKGR_MCFR;
145 #define SAM4_CKGR_PLLAR (SAM4_PMC_BASE + 0x0028)
146 uint32_t CKGR_PLLAR;
147 #define SAM4_PMC_MCKR (SAM4_PMC_BASE + 0x0030)
148 uint32_t PMC_MCKR;
149 #define SAM4_PMC_PCK0 (SAM4_PMC_BASE + 0x0040)
150 uint32_t PMC_PCK0;
151 #define SAM4_PMC_PCK1 (SAM4_PMC_BASE + 0x0044)
152 uint32_t PMC_PCK1;
153 #define SAM4_PMC_PCK2 (SAM4_PMC_BASE + 0x0048)
154 uint32_t PMC_PCK2;
155 #define SAM4_PMC_SR (SAM4_PMC_BASE + 0x0068)
156 uint32_t PMC_SR;
157 #define SAM4_PMC_IMR (SAM4_PMC_BASE + 0x006c)
158 uint32_t PMC_IMR;
159 #define SAM4_PMC_FSMR (SAM4_PMC_BASE + 0x0070)
160 uint32_t PMC_FSMR;
161 #define SAM4_PMC_FSPR (SAM4_PMC_BASE + 0x0074)
162 uint32_t PMC_FSPR;
163 };
164
165 struct sam4_bank_private {
166 int probed;
167 /* DANGER: THERE ARE DRAGONS HERE.. */
168 /* NOTE: If you add more 'ghost' pointers */
169 /* be aware that you must *manually* update */
170 /* these pointers in the function sam4_GetDetails() */
171 /* See the comment "Here there be dragons" */
172
173 /* so we can find the chip we belong to */
174 struct sam4_chip *pChip;
175 /* so we can find the original bank pointer */
176 struct flash_bank *pBank;
177 unsigned bank_number;
178 uint32_t controller_address;
179 uint32_t base_address;
180 uint32_t flash_wait_states;
181 bool present;
182 unsigned size_bytes;
183 unsigned nsectors;
184 unsigned sector_size;
185 unsigned page_size;
186 };
187
188 struct sam4_chip_details {
189 /* THERE ARE DRAGONS HERE.. */
190 /* note: If you add pointers here */
191 /* be careful about them as they */
192 /* may need to be updated inside */
193 /* the function: "sam4_GetDetails() */
194 /* which copy/overwrites the */
195 /* 'runtime' copy of this structure */
196 uint32_t chipid_cidr;
197 const char *name;
198
199 unsigned n_gpnvms;
200 #define SAM4_N_NVM_BITS 3
201 unsigned gpnvm[SAM4_N_NVM_BITS];
202 unsigned total_flash_size;
203 unsigned total_sram_size;
204 unsigned n_banks;
205 #define SAM4_MAX_FLASH_BANKS 2
206 /* these are "initialized" from the global const data */
207 struct sam4_bank_private bank[SAM4_MAX_FLASH_BANKS];
208 };
209
210 struct sam4_chip {
211 struct sam4_chip *next;
212 int probed;
213
214 /* this is "initialized" from the global const structure */
215 struct sam4_chip_details details;
216 struct target *target;
217 struct sam4_cfg cfg;
218 };
219
220
221 struct sam4_reg_list {
222 uint32_t address; size_t struct_offset; const char *name;
223 void (*explain_func)(struct sam4_chip *pInfo);
224 };
225
226 static struct sam4_chip *all_sam4_chips;
227
228 static struct sam4_chip *get_current_sam4(struct command_context *cmd_ctx)
229 {
230 struct target *t;
231 static struct sam4_chip *p;
232
233 t = get_current_target(cmd_ctx);
234 if (!t) {
235 command_print(cmd_ctx, "No current target?");
236 return NULL;
237 }
238
239 p = all_sam4_chips;
240 if (!p) {
241 /* this should not happen */
242 /* the command is not registered until the chip is created? */
243 command_print(cmd_ctx, "No SAM4 chips exist?");
244 return NULL;
245 }
246
247 while (p) {
248 if (p->target == t)
249 return p;
250 p = p->next;
251 }
252 command_print(cmd_ctx, "Cannot find SAM4 chip?");
253 return NULL;
254 }
255
256 /*The actual sector size of the SAM4S flash memory is 65536 bytes. 16 sectors for a 1024KB device*/
257 /*The lockregions are 8KB per lock region, with a 1024KB device having 128 lock regions. */
258 /*For the best results, nsectors are thus set to the amount of lock regions, and the sector_size*/
259 /*set to the lock region size. Page erases are used to erase 8KB sections when programming*/
260
261 /* these are used to *initialize* the "pChip->details" structure. */
262 static const struct sam4_chip_details all_sam4_details[] = {
263
264 /* Start at91sam4e* series */
265 /*atsam4e16e - LQFP144/LFBGA144*/
266 {
267 .chipid_cidr = 0xA3CC0CE0,
268 .name = "at91sam4e16e",
269 .total_flash_size = 1024 * 1024,
270 .total_sram_size = 128 * 1024,
271 .n_gpnvms = 2,
272 .n_banks = 1,
273 {
274 /* .bank[0] = {*/
275 {
276 .probed = 0,
277 .pChip = NULL,
278 .pBank = NULL,
279 .bank_number = 0,
280 .base_address = FLASH_BANK_BASE_S,
281 .controller_address = 0x400e0a00,
282 .flash_wait_states = 6, /* workaround silicon bug */
283 .present = 1,
284 .size_bytes = 1024 * 1024,
285 .nsectors = 128,
286 .sector_size = 8192,
287 .page_size = 512,
288 },
289 /* .bank[1] = {*/
290 {
291 .present = 0,
292 .probed = 0,
293 .bank_number = 1,
294
295 },
296 },
297 },
298
299 /* Start at91sam4s* series */
300 /*atsam4s16c - LQFP100/BGA100*/
301 {
302 .chipid_cidr = 0x28AC0CE0,
303 .name = "at91sam4s16c",
304 .total_flash_size = 1024 * 1024,
305 .total_sram_size = 128 * 1024,
306 .n_gpnvms = 2,
307 .n_banks = 1,
308 {
309 /* .bank[0] = {*/
310 {
311 .probed = 0,
312 .pChip = NULL,
313 .pBank = NULL,
314 .bank_number = 0,
315 .base_address = FLASH_BANK_BASE_S,
316 .controller_address = 0x400e0a00,
317 .flash_wait_states = 6, /* workaround silicon bug */
318 .present = 1,
319 .size_bytes = 1024 * 1024,
320 .nsectors = 128,
321 .sector_size = 8192,
322 .page_size = 512,
323 },
324 /* .bank[1] = {*/
325 {
326 .present = 0,
327 .probed = 0,
328 .bank_number = 1,
329
330 },
331 },
332 },
333 /*atsam4s16b - LQFP64/QFN64*/
334 {
335 .chipid_cidr = 0x289C0CE0,
336 .name = "at91sam4s16b",
337 .total_flash_size = 1024 * 1024,
338 .total_sram_size = 128 * 1024,
339 .n_gpnvms = 2,
340 .n_banks = 1,
341 {
342 /* .bank[0] = {*/
343 {
344 .probed = 0,
345 .pChip = NULL,
346 .pBank = NULL,
347 .bank_number = 0,
348 .base_address = FLASH_BANK_BASE_S,
349 .controller_address = 0x400e0a00,
350 .flash_wait_states = 6, /* workaround silicon bug */
351 .present = 1,
352 .size_bytes = 1024 * 1024,
353 .nsectors = 128,
354 .sector_size = 8192,
355 .page_size = 512,
356 },
357 /* .bank[1] = {*/
358 {
359 .present = 0,
360 .probed = 0,
361 .bank_number = 1,
362
363 },
364 },
365 },
366 /*atsam4s16a - LQFP48/QFN48*/
367 {
368 .chipid_cidr = 0x288C0CE0,
369 .name = "at91sam4s16a",
370 .total_flash_size = 1024 * 1024,
371 .total_sram_size = 128 * 1024,
372 .n_gpnvms = 2,
373 .n_banks = 1,
374 {
375 /* .bank[0] = {*/
376 {
377 .probed = 0,
378 .pChip = NULL,
379 .pBank = NULL,
380 .bank_number = 0,
381 .base_address = FLASH_BANK_BASE_S,
382 .controller_address = 0x400e0a00,
383 .flash_wait_states = 6, /* workaround silicon bug */
384 .present = 1,
385 .size_bytes = 1024 * 1024,
386 .nsectors = 128,
387 .sector_size = 8192,
388 .page_size = 512,
389 },
390 /* .bank[1] = {*/
391 {
392 .present = 0,
393 .probed = 0,
394 .bank_number = 1,
395
396 },
397 },
398 },
399 /*atsam4s8c - LQFP100/BGA100*/
400 {
401 .chipid_cidr = 0x28AC0AE0,
402 .name = "at91sam4s8c",
403 .total_flash_size = 512 * 1024,
404 .total_sram_size = 128 * 1024,
405 .n_gpnvms = 2,
406 .n_banks = 1,
407 {
408 /* .bank[0] = {*/
409 {
410 .probed = 0,
411 .pChip = NULL,
412 .pBank = NULL,
413 .bank_number = 0,
414 .base_address = FLASH_BANK_BASE_S,
415 .controller_address = 0x400e0a00,
416 .flash_wait_states = 6, /* workaround silicon bug */
417 .present = 1,
418 .size_bytes = 512 * 1024,
419 .nsectors = 64,
420 .sector_size = 8192,
421 .page_size = 512,
422 },
423 /* .bank[1] = {*/
424 {
425 .present = 0,
426 .probed = 0,
427 .bank_number = 1,
428
429 },
430 },
431 },
432 /*atsam4s8b - LQFP64/BGA64*/
433 {
434 .chipid_cidr = 0x289C0AE0,
435 .name = "at91sam4s8b",
436 .total_flash_size = 512 * 1024,
437 .total_sram_size = 128 * 1024,
438 .n_gpnvms = 2,
439 .n_banks = 1,
440 {
441 /* .bank[0] = {*/
442 {
443 .probed = 0,
444 .pChip = NULL,
445 .pBank = NULL,
446 .bank_number = 0,
447 .base_address = FLASH_BANK_BASE_S,
448 .controller_address = 0x400e0a00,
449 .flash_wait_states = 6, /* workaround silicon bug */
450 .present = 1,
451 .size_bytes = 512 * 1024,
452 .nsectors = 64,
453 .sector_size = 8192,
454 .page_size = 512,
455 },
456 /* .bank[1] = {*/
457 {
458 .present = 0,
459 .probed = 0,
460 .bank_number = 1,
461
462 },
463 },
464 },
465 /*atsam4s8a - LQFP48/BGA48*/
466 {
467 .chipid_cidr = 0x288C0AE0,
468 .name = "at91sam4s8a",
469 .total_flash_size = 512 * 1024,
470 .total_sram_size = 128 * 1024,
471 .n_gpnvms = 2,
472 .n_banks = 1,
473 {
474 /* .bank[0] = {*/
475 {
476 .probed = 0,
477 .pChip = NULL,
478 .pBank = NULL,
479 .bank_number = 0,
480 .base_address = FLASH_BANK_BASE_S,
481 .controller_address = 0x400e0a00,
482 .flash_wait_states = 6, /* workaround silicon bug */
483 .present = 1,
484 .size_bytes = 512 * 1024,
485 .nsectors = 64,
486 .sector_size = 8192,
487 .page_size = 512,
488 },
489 /* .bank[1] = {*/
490 {
491 .present = 0,
492 .probed = 0,
493 .bank_number = 1,
494
495 },
496 },
497 },
498
499 /*atsam4s4a - LQFP48/BGA48*/
500 {
501 .chipid_cidr = 0x288b09e0,
502 .name = "at91sam4s4a",
503 .total_flash_size = 256 * 1024,
504 .total_sram_size = 64 * 1024,
505 .n_gpnvms = 2,
506 .n_banks = 1,
507 {
508 /* .bank[0] = {*/
509 {
510 .probed = 0,
511 .pChip = NULL,
512 .pBank = NULL,
513 .bank_number = 0,
514 .base_address = FLASH_BANK_BASE_S,
515 .controller_address = 0x400e0a00,
516 .flash_wait_states = 6, /* workaround silicon bug */
517 .present = 1,
518 .size_bytes = 256 * 1024,
519 .nsectors = 32,
520 .sector_size = 8192,
521 .page_size = 512,
522 },
523 /* .bank[1] = {*/
524 {
525 .present = 0,
526 .probed = 0,
527 .bank_number = 1,
528
529 },
530 },
531 },
532
533 /*at91sam4sd32c*/
534 {
535 .chipid_cidr = 0x29a70ee0,
536 .name = "at91sam4sd32c",
537 .total_flash_size = 2048 * 1024,
538 .total_sram_size = 160 * 1024,
539 .n_gpnvms = 3,
540 .n_banks = 2,
541
542 /* .bank[0] = { */
543 {
544 {
545 .probed = 0,
546 .pChip = NULL,
547 .pBank = NULL,
548 .bank_number = 0,
549 .base_address = FLASH_BANK0_BASE_SD,
550 .controller_address = 0x400e0a00,
551 .flash_wait_states = 6, /* workaround silicon bug */
552 .present = 1,
553 .size_bytes = 1024 * 1024,
554 .nsectors = 128,
555 .sector_size = 8192,
556 .page_size = 512,
557 },
558
559 /* .bank[1] = { */
560 {
561 .probed = 0,
562 .pChip = NULL,
563 .pBank = NULL,
564 .bank_number = 1,
565 .base_address = FLASH_BANK1_BASE_2048K_SD,
566 .controller_address = 0x400e0c00,
567 .flash_wait_states = 6, /* workaround silicon bug */
568 .present = 1,
569 .size_bytes = 1024 * 1024,
570 .nsectors = 128,
571 .sector_size = 8192,
572 .page_size = 512,
573 },
574 },
575 },
576
577 /*at91sam4sd16c*/
578 {
579 .chipid_cidr = 0x29a70ce0,
580 .name = "at91sam4sd16c",
581 .total_flash_size = 1024 * 1024,
582 .total_sram_size = 160 * 1024,
583 .n_gpnvms = 3,
584 .n_banks = 2,
585
586 /* .bank[0] = { */
587 {
588 {
589 .probed = 0,
590 .pChip = NULL,
591 .pBank = NULL,
592 .bank_number = 0,
593 .base_address = FLASH_BANK0_BASE_SD,
594 .controller_address = 0x400e0a00,
595 .flash_wait_states = 6, /* workaround silicon bug */
596 .present = 1,
597 .size_bytes = 512 * 1024,
598 .nsectors = 64,
599 .sector_size = 8192,
600 .page_size = 512,
601 },
602
603 /* .bank[1] = { */
604 {
605 .probed = 0,
606 .pChip = NULL,
607 .pBank = NULL,
608 .bank_number = 1,
609 .base_address = FLASH_BANK1_BASE_1024K_SD,
610 .controller_address = 0x400e0c00,
611 .flash_wait_states = 6, /* workaround silicon bug */
612 .present = 1,
613 .size_bytes = 512 * 1024,
614 .nsectors = 64,
615 .sector_size = 8192,
616 .page_size = 512,
617 },
618 },
619 },
620
621 /*at91sam4sa16c*/
622 {
623 .chipid_cidr = 0x28a70ce0,
624 .name = "at91sam4sa16c",
625 .total_flash_size = 1024 * 1024,
626 .total_sram_size = 160 * 1024,
627 .n_gpnvms = 3,
628 .n_banks = 2,
629
630 /* .bank[0] = { */
631 {
632 {
633 .probed = 0,
634 .pChip = NULL,
635 .pBank = NULL,
636 .bank_number = 0,
637 .base_address = FLASH_BANK0_BASE_SD,
638 .controller_address = 0x400e0a00,
639 .flash_wait_states = 6, /* workaround silicon bug */
640 .present = 1,
641 .size_bytes = 512 * 1024,
642 .nsectors = 64,
643 .sector_size = 8192,
644 .page_size = 512,
645 },
646
647 /* .bank[1] = { */
648 {
649 .probed = 0,
650 .pChip = NULL,
651 .pBank = NULL,
652 .bank_number = 1,
653 .base_address = FLASH_BANK1_BASE_1024K_SD,
654 .controller_address = 0x400e0c00,
655 .flash_wait_states = 6, /* workaround silicon bug */
656 .present = 1,
657 .size_bytes = 512 * 1024,
658 .nsectors = 64,
659 .sector_size = 8192,
660 .page_size = 512,
661 },
662 },
663 },
664
665 /* at91samg53n19 */
666 {
667 .chipid_cidr = 0x247e0ae0,
668 .name = "at91samg53n19",
669 .total_flash_size = 512 * 1024,
670 .total_sram_size = 96 * 1024,
671 .n_gpnvms = 2,
672 .n_banks = 1,
673
674 /* .bank[0] = {*/
675 {
676 {
677 .probed = 0,
678 .pChip = NULL,
679 .pBank = NULL,
680 .bank_number = 0,
681 .base_address = FLASH_BANK_BASE_S,
682 .controller_address = 0x400e0a00,
683 .flash_wait_states = 6, /* workaround silicon bug */
684 .present = 1,
685 .size_bytes = 512 * 1024,
686 .nsectors = 64,
687 .sector_size = 8192,
688 .page_size = 512,
689 },
690 /* .bank[1] = {*/
691 {
692 .present = 0,
693 .probed = 0,
694 .bank_number = 1,
695
696 },
697 }
698 },
699
700 /* terminate */
701 {
702 .chipid_cidr = 0,
703 .name = NULL,
704 }
705 };
706
707 /* Globals above */
708 /***********************************************************************
709 **********************************************************************
710 **********************************************************************
711 **********************************************************************
712 **********************************************************************
713 **********************************************************************/
714 /* *ATMEL* style code - from the SAM4 driver code */
715
716 /**
717 * Get the current status of the EEFC and
718 * the value of some status bits (LOCKE, PROGE).
719 * @param pPrivate - info about the bank
720 * @param v - result goes here
721 */
722 static int EFC_GetStatus(struct sam4_bank_private *pPrivate, uint32_t *v)
723 {
724 int r;
725 r = target_read_u32(pPrivate->pChip->target,
726 pPrivate->controller_address + offset_EFC_FSR,
727 v);
728 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
729 (unsigned int)(*v),
730 ((unsigned int)((*v >> 2) & 1)),
731 ((unsigned int)((*v >> 1) & 1)),
732 ((unsigned int)((*v >> 0) & 1)));
733
734 return r;
735 }
736
737 /**
738 * Get the result of the last executed command.
739 * @param pPrivate - info about the bank
740 * @param v - result goes here
741 */
742 static int EFC_GetResult(struct sam4_bank_private *pPrivate, uint32_t *v)
743 {
744 int r;
745 uint32_t rv;
746 r = target_read_u32(pPrivate->pChip->target,
747 pPrivate->controller_address + offset_EFC_FRR,
748 &rv);
749 if (v)
750 *v = rv;
751 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
752 return r;
753 }
754
755 static int EFC_StartCommand(struct sam4_bank_private *pPrivate,
756 unsigned command, unsigned argument)
757 {
758 uint32_t n, v;
759 int r;
760 int retry;
761
762 retry = 0;
763 do_retry:
764
765 /* Check command & argument */
766 switch (command) {
767
768 case AT91C_EFC_FCMD_WP:
769 case AT91C_EFC_FCMD_WPL:
770 case AT91C_EFC_FCMD_EWP:
771 case AT91C_EFC_FCMD_EWPL:
772 /* case AT91C_EFC_FCMD_EPL: */
773 case AT91C_EFC_FCMD_EPA:
774 case AT91C_EFC_FCMD_SLB:
775 case AT91C_EFC_FCMD_CLB:
776 n = (pPrivate->size_bytes / pPrivate->page_size);
777 if (argument >= n)
778 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
779 break;
780
781 case AT91C_EFC_FCMD_SFB:
782 case AT91C_EFC_FCMD_CFB:
783 if (argument >= pPrivate->pChip->details.n_gpnvms) {
784 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
785 pPrivate->pChip->details.n_gpnvms);
786 }
787 break;
788
789 case AT91C_EFC_FCMD_GETD:
790 case AT91C_EFC_FCMD_EA:
791 case AT91C_EFC_FCMD_GLB:
792 case AT91C_EFC_FCMD_GFB:
793 case AT91C_EFC_FCMD_STUI:
794 case AT91C_EFC_FCMD_SPUI:
795 if (argument != 0)
796 LOG_ERROR("Argument is meaningless for cmd: %d", command);
797 break;
798 default:
799 LOG_ERROR("Unknown command %d", command);
800 break;
801 }
802
803 if (command == AT91C_EFC_FCMD_SPUI) {
804 /* this is a very special situation. */
805 /* Situation (1) - error/retry - see below */
806 /* And we are being called recursively */
807 /* Situation (2) - normal, finished reading unique id */
808 } else {
809 /* it should be "ready" */
810 EFC_GetStatus(pPrivate, &v);
811 if (v & 1) {
812 /* then it is ready */
813 /* we go on */
814 } else {
815 if (retry) {
816 /* we have done this before */
817 /* the controller is not responding. */
818 LOG_ERROR("flash controller(%d) is not ready! Error",
819 pPrivate->bank_number);
820 return ERROR_FAIL;
821 } else {
822 retry++;
823 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
824 pPrivate->bank_number);
825 /* we do that by issuing the *STOP* command */
826 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
827 /* above is recursive, and further recursion is blocked by */
828 /* if (command == AT91C_EFC_FCMD_SPUI) above */
829 goto do_retry;
830 }
831 }
832 }
833
834 v = (0x5A << 24) | (argument << 8) | command;
835 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
836 r = target_write_u32(pPrivate->pBank->target,
837 pPrivate->controller_address + offset_EFC_FCR, v);
838 if (r != ERROR_OK)
839 LOG_DEBUG("Error Write failed");
840 return r;
841 }
842
843 /**
844 * Performs the given command and wait until its completion (or an error).
845 * @param pPrivate - info about the bank
846 * @param command - Command to perform.
847 * @param argument - Optional command argument.
848 * @param status - put command status bits here
849 */
850 static int EFC_PerformCommand(struct sam4_bank_private *pPrivate,
851 unsigned command,
852 unsigned argument,
853 uint32_t *status)
854 {
855
856 int r;
857 uint32_t v;
858 long long ms_now, ms_end;
859
860 /* default */
861 if (status)
862 *status = 0;
863
864 r = EFC_StartCommand(pPrivate, command, argument);
865 if (r != ERROR_OK)
866 return r;
867
868 ms_end = 10000 + timeval_ms();
869
870 do {
871 r = EFC_GetStatus(pPrivate, &v);
872 if (r != ERROR_OK)
873 return r;
874 ms_now = timeval_ms();
875 if (ms_now > ms_end) {
876 /* error */
877 LOG_ERROR("Command timeout");
878 return ERROR_FAIL;
879 }
880 } while ((v & 1) == 0);
881
882 /* error bits.. */
883 if (status)
884 *status = (v & 0x6);
885 return ERROR_OK;
886
887 }
888
889 /**
890 * Read the unique ID.
891 * @param pPrivate - info about the bank
892 * The unique ID is stored in the 'pPrivate' structure.
893 */
894 static int FLASHD_ReadUniqueID(struct sam4_bank_private *pPrivate)
895 {
896 int r;
897 uint32_t v;
898 int x;
899 /* assume 0 */
900 pPrivate->pChip->cfg.unique_id[0] = 0;
901 pPrivate->pChip->cfg.unique_id[1] = 0;
902 pPrivate->pChip->cfg.unique_id[2] = 0;
903 pPrivate->pChip->cfg.unique_id[3] = 0;
904
905 LOG_DEBUG("Begin");
906 r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
907 if (r < 0)
908 return r;
909
910 for (x = 0; x < 4; x++) {
911 r = target_read_u32(pPrivate->pChip->target,
912 pPrivate->pBank->base + (x * 4),
913 &v);
914 if (r < 0)
915 return r;
916 pPrivate->pChip->cfg.unique_id[x] = v;
917 }
918
919 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
920 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
921 r,
922 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
923 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
924 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
925 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
926 return r;
927
928 }
929
930 /**
931 * Erases the entire flash.
932 * @param pPrivate - the info about the bank.
933 */
934 static int FLASHD_EraseEntireBank(struct sam4_bank_private *pPrivate)
935 {
936 LOG_DEBUG("Here");
937 return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
938 }
939
940 /**
941 * Erases the entire flash.
942 * @param pPrivate - the info about the bank.
943 */
944 static int FLASHD_ErasePages(struct sam4_bank_private *pPrivate,
945 int firstPage,
946 int numPages,
947 uint32_t *status)
948 {
949 LOG_DEBUG("Here");
950 uint8_t erasePages;
951 switch (numPages) {
952 case 4:
953 erasePages = 0x00;
954 break;
955 case 8:
956 erasePages = 0x01;
957 break;
958 case 16:
959 erasePages = 0x02;
960 break;
961 case 32:
962 erasePages = 0x03;
963 break;
964 default:
965 erasePages = 0x00;
966 break;
967 }
968
969 /* AT91C_EFC_FCMD_EPA
970 * According to the datasheet FARG[15:2] defines the page from which
971 * the erase will start.This page must be modulo 4, 8, 16 or 32
972 * according to the number of pages to erase. FARG[1:0] defines the
973 * number of pages to be erased. Previously (firstpage << 2) was used
974 * to conform to this, seems it should not be shifted...
975 */
976 return EFC_PerformCommand(pPrivate,
977 /* send Erase Page */
978 AT91C_EFC_FCMD_EPA,
979 (firstPage) | erasePages,
980 status);
981 }
982
983 /**
984 * Gets current GPNVM state.
985 * @param pPrivate - info about the bank.
986 * @param gpnvm - GPNVM bit index.
987 * @param puthere - result stored here.
988 */
989 /* ------------------------------------------------------------------------------ */
990 static int FLASHD_GetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
991 {
992 uint32_t v;
993 int r;
994
995 LOG_DEBUG("Here");
996 if (pPrivate->bank_number != 0) {
997 LOG_ERROR("GPNVM only works with Bank0");
998 return ERROR_FAIL;
999 }
1000
1001 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1002 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1003 gpnvm, pPrivate->pChip->details.n_gpnvms);
1004 return ERROR_FAIL;
1005 }
1006
1007 /* Get GPNVMs status */
1008 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
1009 if (r != ERROR_OK) {
1010 LOG_ERROR("Failed");
1011 return r;
1012 }
1013
1014 r = EFC_GetResult(pPrivate, &v);
1015
1016 if (puthere) {
1017 /* Check if GPNVM is set */
1018 /* get the bit and make it a 0/1 */
1019 *puthere = (v >> gpnvm) & 1;
1020 }
1021
1022 return r;
1023 }
1024
1025 /**
1026 * Clears the selected GPNVM bit.
1027 * @param pPrivate info about the bank
1028 * @param gpnvm GPNVM index.
1029 * @returns 0 if successful; otherwise returns an error code.
1030 */
1031 static int FLASHD_ClrGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
1032 {
1033 int r;
1034 unsigned v;
1035
1036 LOG_DEBUG("Here");
1037 if (pPrivate->bank_number != 0) {
1038 LOG_ERROR("GPNVM only works with Bank0");
1039 return ERROR_FAIL;
1040 }
1041
1042 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1043 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1044 gpnvm, pPrivate->pChip->details.n_gpnvms);
1045 return ERROR_FAIL;
1046 }
1047
1048 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1049 if (r != ERROR_OK) {
1050 LOG_DEBUG("Failed: %d", r);
1051 return r;
1052 }
1053 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
1054 LOG_DEBUG("End: %d", r);
1055 return r;
1056 }
1057
1058 /**
1059 * Sets the selected GPNVM bit.
1060 * @param pPrivate info about the bank
1061 * @param gpnvm GPNVM index.
1062 */
1063 static int FLASHD_SetGPNVM(struct sam4_bank_private *pPrivate, unsigned gpnvm)
1064 {
1065 int r;
1066 unsigned v;
1067
1068 if (pPrivate->bank_number != 0) {
1069 LOG_ERROR("GPNVM only works with Bank0");
1070 return ERROR_FAIL;
1071 }
1072
1073 if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
1074 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1075 gpnvm, pPrivate->pChip->details.n_gpnvms);
1076 return ERROR_FAIL;
1077 }
1078
1079 r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
1080 if (r != ERROR_OK)
1081 return r;
1082 if (v) {
1083 /* already set */
1084 r = ERROR_OK;
1085 } else {
1086 /* set it */
1087 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
1088 }
1089 return r;
1090 }
1091
1092 /**
1093 * Returns a bit field (at most 64) of locked regions within a page.
1094 * @param pPrivate info about the bank
1095 * @param v where to store locked bits
1096 */
1097 static int FLASHD_GetLockBits(struct sam4_bank_private *pPrivate, uint32_t *v)
1098 {
1099 int r;
1100 LOG_DEBUG("Here");
1101 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
1102 if (r == ERROR_OK) {
1103 EFC_GetResult(pPrivate, v);
1104 EFC_GetResult(pPrivate, v);
1105 EFC_GetResult(pPrivate, v);
1106 r = EFC_GetResult(pPrivate, v);
1107 }
1108 LOG_DEBUG("End: %d", r);
1109 return r;
1110 }
1111
1112 /**
1113 * Unlocks all the regions in the given address range.
1114 * @param pPrivate info about the bank
1115 * @param start_sector first sector to unlock
1116 * @param end_sector last (inclusive) to unlock
1117 */
1118
1119 static int FLASHD_Unlock(struct sam4_bank_private *pPrivate,
1120 unsigned start_sector,
1121 unsigned end_sector)
1122 {
1123 int r;
1124 uint32_t status;
1125 uint32_t pg;
1126 uint32_t pages_per_sector;
1127
1128 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1129
1130 /* Unlock all pages */
1131 while (start_sector <= end_sector) {
1132 pg = start_sector * pages_per_sector;
1133
1134 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
1135 if (r != ERROR_OK)
1136 return r;
1137 start_sector++;
1138 }
1139
1140 return ERROR_OK;
1141 }
1142
1143 /**
1144 * Locks regions
1145 * @param pPrivate - info about the bank
1146 * @param start_sector - first sector to lock
1147 * @param end_sector - last sector (inclusive) to lock
1148 */
1149 static int FLASHD_Lock(struct sam4_bank_private *pPrivate,
1150 unsigned start_sector,
1151 unsigned end_sector)
1152 {
1153 uint32_t status;
1154 uint32_t pg;
1155 uint32_t pages_per_sector;
1156 int r;
1157
1158 pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
1159
1160 /* Lock all pages */
1161 while (start_sector <= end_sector) {
1162 pg = start_sector * pages_per_sector;
1163
1164 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
1165 if (r != ERROR_OK)
1166 return r;
1167 start_sector++;
1168 }
1169 return ERROR_OK;
1170 }
1171
1172 /****** END SAM4 CODE ********/
1173
1174 /* begin helpful debug code */
1175 /* print the fieldname, the field value, in dec & hex, and return field value */
1176 static uint32_t sam4_reg_fieldname(struct sam4_chip *pChip,
1177 const char *regname,
1178 uint32_t value,
1179 unsigned shift,
1180 unsigned width)
1181 {
1182 uint32_t v;
1183 int hwidth, dwidth;
1184
1185
1186 /* extract the field */
1187 v = value >> shift;
1188 v = v & ((1 << width)-1);
1189 if (width <= 16) {
1190 hwidth = 4;
1191 dwidth = 5;
1192 } else {
1193 hwidth = 8;
1194 dwidth = 12;
1195 }
1196
1197 /* show the basics */
1198 LOG_USER_N("\t%*s: %*" PRId32 " [0x%0*" PRIx32 "] ",
1199 REG_NAME_WIDTH, regname,
1200 dwidth, v,
1201 hwidth, v);
1202 return v;
1203 }
1204
1205 static const char _unknown[] = "unknown";
1206 static const char *const eproc_names[] = {
1207 _unknown, /* 0 */
1208 "arm946es", /* 1 */
1209 "arm7tdmi", /* 2 */
1210 "cortex-m3", /* 3 */
1211 "arm920t", /* 4 */
1212 "arm926ejs", /* 5 */
1213 "cortex-a5", /* 6 */
1214 "cortex-m4", /* 7 */
1215 _unknown, /* 8 */
1216 _unknown, /* 9 */
1217 _unknown, /* 10 */
1218 _unknown, /* 11 */
1219 _unknown, /* 12 */
1220 _unknown, /* 13 */
1221 _unknown, /* 14 */
1222 _unknown, /* 15 */
1223 };
1224
1225 #define nvpsize2 nvpsize /* these two tables are identical */
1226 static const char *const nvpsize[] = {
1227 "none", /* 0 */
1228 "8K bytes", /* 1 */
1229 "16K bytes", /* 2 */
1230 "32K bytes", /* 3 */
1231 _unknown, /* 4 */
1232 "64K bytes", /* 5 */
1233 _unknown, /* 6 */
1234 "128K bytes", /* 7 */
1235 _unknown, /* 8 */
1236 "256K bytes", /* 9 */
1237 "512K bytes", /* 10 */
1238 _unknown, /* 11 */
1239 "1024K bytes", /* 12 */
1240 _unknown, /* 13 */
1241 "2048K bytes", /* 14 */
1242 _unknown, /* 15 */
1243 };
1244
1245 static const char *const sramsize[] = {
1246 "48K Bytes", /* 0 */
1247 "1K Bytes", /* 1 */
1248 "2K Bytes", /* 2 */
1249 "6K Bytes", /* 3 */
1250 "112K Bytes", /* 4 */
1251 "4K Bytes", /* 5 */
1252 "80K Bytes", /* 6 */
1253 "160K Bytes", /* 7 */
1254 "8K Bytes", /* 8 */
1255 "16K Bytes", /* 9 */
1256 "32K Bytes", /* 10 */
1257 "64K Bytes", /* 11 */
1258 "128K Bytes", /* 12 */
1259 "256K Bytes", /* 13 */
1260 "96K Bytes", /* 14 */
1261 "512K Bytes", /* 15 */
1262
1263 };
1264
1265 static const struct archnames { unsigned value; const char *name; } archnames[] = {
1266 { 0x19, "AT91SAM9xx Series" },
1267 { 0x29, "AT91SAM9XExx Series" },
1268 { 0x34, "AT91x34 Series" },
1269 { 0x37, "CAP7 Series" },
1270 { 0x39, "CAP9 Series" },
1271 { 0x3B, "CAP11 Series" },
1272 { 0x3C, "ATSAM4E" },
1273 { 0x40, "AT91x40 Series" },
1274 { 0x42, "AT91x42 Series" },
1275 { 0x43, "SAMG51 Series"
1276 },
1277 { 0x47, "SAMG53 Series"
1278 },
1279 { 0x55, "AT91x55 Series" },
1280 { 0x60, "AT91SAM7Axx Series" },
1281 { 0x61, "AT91SAM7AQxx Series" },
1282 { 0x63, "AT91x63 Series" },
1283 { 0x70, "AT91SAM7Sxx Series" },
1284 { 0x71, "AT91SAM7XCxx Series" },
1285 { 0x72, "AT91SAM7SExx Series" },
1286 { 0x73, "AT91SAM7Lxx Series" },
1287 { 0x75, "AT91SAM7Xxx Series" },
1288 { 0x76, "AT91SAM7SLxx Series" },
1289 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1290 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1291 { 0x83, "ATSAM3A/SAM4A xC Series (100-pin version)"},
1292 { 0x84, "ATSAM3X/SAM4X xC Series (100-pin version)"},
1293 { 0x85, "ATSAM3X/SAM4X xE Series (144-pin version)"},
1294 { 0x86, "ATSAM3X/SAM4X xG Series (208/217-pin version)" },
1295 { 0x88, "ATSAM3S/SAM4S xA Series (48-pin version)" },
1296 { 0x89, "ATSAM3S/SAM4S xB Series (64-pin version)" },
1297 { 0x8A, "ATSAM3S/SAM4S xC Series (100-pin version)"},
1298 { 0x92, "AT91x92 Series" },
1299 { 0x93, "ATSAM3NxA Series (48-pin version)" },
1300 { 0x94, "ATSAM3NxB Series (64-pin version)" },
1301 { 0x95, "ATSAM3NxC Series (100-pin version)" },
1302 { 0x98, "ATSAM3SDxA Series (48-pin version)" },
1303 { 0x99, "ATSAM3SDxB Series (64-pin version)" },
1304 { 0x9A, "ATSAM3SDxC Series (100-pin version)" },
1305 { 0xA5, "ATSAM5A" },
1306 { 0xF0, "AT75Cxx Series" },
1307 { -1, NULL },
1308 };
1309
1310 static const char *const nvptype[] = {
1311 "rom", /* 0 */
1312 "romless or onchip flash", /* 1 */
1313 "embedded flash memory",/* 2 */
1314 "rom(nvpsiz) + embedded flash (nvpsiz2)", /* 3 */
1315 "sram emulating flash", /* 4 */
1316 _unknown, /* 5 */
1317 _unknown, /* 6 */
1318 _unknown, /* 7 */
1319 };
1320
1321 static const char *_yes_or_no(uint32_t v)
1322 {
1323 if (v)
1324 return "YES";
1325 else
1326 return "NO";
1327 }
1328
1329 static const char *const _rc_freq[] = {
1330 "4 MHz", "8 MHz", "12 MHz", "reserved"
1331 };
1332
1333 static void sam4_explain_ckgr_mor(struct sam4_chip *pChip)
1334 {
1335 uint32_t v;
1336 uint32_t rcen;
1337
1338 v = sam4_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
1339 LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
1340 v = sam4_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
1341 LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
1342 rcen = sam4_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
1343 LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
1344 v = sam4_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
1345 LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
1346
1347 pChip->cfg.rc_freq = 0;
1348 if (rcen) {
1349 switch (v) {
1350 default:
1351 pChip->cfg.rc_freq = 0;
1352 break;
1353 case 0:
1354 pChip->cfg.rc_freq = 4 * 1000 * 1000;
1355 break;
1356 case 1:
1357 pChip->cfg.rc_freq = 8 * 1000 * 1000;
1358 break;
1359 case 2:
1360 pChip->cfg.rc_freq = 12 * 1000 * 1000;
1361 break;
1362 }
1363 }
1364
1365 v = sam4_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
1366 LOG_USER("(startup clks, time= %f uSecs)",
1367 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
1368 v = sam4_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
1369 LOG_USER("(mainosc source: %s)",
1370 v ? "external xtal" : "internal RC");
1371
1372 v = sam4_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
1373 LOG_USER("(clock failure enabled: %s)",
1374 _yes_or_no(v));
1375 }
1376
1377 static void sam4_explain_chipid_cidr(struct sam4_chip *pChip)
1378 {
1379 int x;
1380 uint32_t v;
1381 const char *cp;
1382
1383 sam4_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
1384 LOG_USER_N("\n");
1385
1386 v = sam4_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
1387 LOG_USER("%s", eproc_names[v]);
1388
1389 v = sam4_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
1390 LOG_USER("%s", nvpsize[v]);
1391
1392 v = sam4_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
1393 LOG_USER("%s", nvpsize2[v]);
1394
1395 v = sam4_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
1396 LOG_USER("%s", sramsize[v]);
1397
1398 v = sam4_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
1399 cp = _unknown;
1400 for (x = 0; archnames[x].name; x++) {
1401 if (v == archnames[x].value) {
1402 cp = archnames[x].name;
1403 break;
1404 }
1405 }
1406
1407 LOG_USER("%s", cp);
1408
1409 v = sam4_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
1410 LOG_USER("%s", nvptype[v]);
1411
1412 v = sam4_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
1413 LOG_USER("(exists: %s)", _yes_or_no(v));
1414 }
1415
1416 static void sam4_explain_ckgr_mcfr(struct sam4_chip *pChip)
1417 {
1418 uint32_t v;
1419
1420 v = sam4_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
1421 LOG_USER("(main ready: %s)", _yes_or_no(v));
1422
1423 v = sam4_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
1424
1425 v = (v * pChip->cfg.slow_freq) / 16;
1426 pChip->cfg.mainosc_freq = v;
1427
1428 LOG_USER("(%3.03f Mhz (%" PRIu32 ".%03" PRIu32 "khz slowclk)",
1429 _tomhz(v),
1430 (uint32_t)(pChip->cfg.slow_freq / 1000),
1431 (uint32_t)(pChip->cfg.slow_freq % 1000));
1432 }
1433
1434 static void sam4_explain_ckgr_plla(struct sam4_chip *pChip)
1435 {
1436 uint32_t mula, diva;
1437
1438 diva = sam4_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
1439 LOG_USER_N("\n");
1440 mula = sam4_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
1441 LOG_USER_N("\n");
1442 pChip->cfg.plla_freq = 0;
1443 if (mula == 0)
1444 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
1445 else if (diva == 0)
1446 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
1447 else if (diva >= 1) {
1448 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
1449 LOG_USER("\tPLLA Freq: %3.03f MHz",
1450 _tomhz(pChip->cfg.plla_freq));
1451 }
1452 }
1453
1454 static void sam4_explain_mckr(struct sam4_chip *pChip)
1455 {
1456 uint32_t css, pres, fin = 0;
1457 int pdiv = 0;
1458 const char *cp = NULL;
1459
1460 css = sam4_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
1461 switch (css & 3) {
1462 case 0:
1463 fin = pChip->cfg.slow_freq;
1464 cp = "slowclk";
1465 break;
1466 case 1:
1467 fin = pChip->cfg.mainosc_freq;
1468 cp = "mainosc";
1469 break;
1470 case 2:
1471 fin = pChip->cfg.plla_freq;
1472 cp = "plla";
1473 break;
1474 case 3:
1475 if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
1476 fin = 480 * 1000 * 1000;
1477 cp = "upll";
1478 } else {
1479 fin = 0;
1480 cp = "upll (*ERROR* UPLL is disabled)";
1481 }
1482 break;
1483 default:
1484 assert(0);
1485 break;
1486 }
1487
1488 LOG_USER("%s (%3.03f Mhz)",
1489 cp,
1490 _tomhz(fin));
1491 pres = sam4_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
1492 switch (pres & 0x07) {
1493 case 0:
1494 pdiv = 1;
1495 cp = "selected clock";
1496 break;
1497 case 1:
1498 pdiv = 2;
1499 cp = "clock/2";
1500 break;
1501 case 2:
1502 pdiv = 4;
1503 cp = "clock/4";
1504 break;
1505 case 3:
1506 pdiv = 8;
1507 cp = "clock/8";
1508 break;
1509 case 4:
1510 pdiv = 16;
1511 cp = "clock/16";
1512 break;
1513 case 5:
1514 pdiv = 32;
1515 cp = "clock/32";
1516 break;
1517 case 6:
1518 pdiv = 64;
1519 cp = "clock/64";
1520 break;
1521 case 7:
1522 pdiv = 6;
1523 cp = "clock/6";
1524 break;
1525 default:
1526 assert(0);
1527 break;
1528 }
1529 LOG_USER("(%s)", cp);
1530 fin = fin / pdiv;
1531 /* sam4 has a *SINGLE* clock - */
1532 /* other at91 series parts have divisors for these. */
1533 pChip->cfg.cpu_freq = fin;
1534 pChip->cfg.mclk_freq = fin;
1535 pChip->cfg.fclk_freq = fin;
1536 LOG_USER("\t\tResult CPU Freq: %3.03f",
1537 _tomhz(fin));
1538 }
1539
1540 #if 0
1541 static struct sam4_chip *target2sam4(struct target *pTarget)
1542 {
1543 struct sam4_chip *pChip;
1544
1545 if (pTarget == NULL)
1546 return NULL;
1547
1548 pChip = all_sam4_chips;
1549 while (pChip) {
1550 if (pChip->target == pTarget)
1551 break; /* return below */
1552 else
1553 pChip = pChip->next;
1554 }
1555 return pChip;
1556 }
1557 #endif
1558
1559 static uint32_t *sam4_get_reg_ptr(struct sam4_cfg *pCfg, const struct sam4_reg_list *pList)
1560 {
1561 /* this function exists to help */
1562 /* keep funky offsetof() errors */
1563 /* and casting from causing bugs */
1564
1565 /* By using prototypes - we can detect what would */
1566 /* be casting errors. */
1567
1568 return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
1569 }
1570
1571
1572 #define SAM4_ENTRY(NAME, FUNC) { .address = SAM4_ ## NAME, .struct_offset = offsetof( \
1573 struct sam4_cfg, \
1574 NAME), # NAME, FUNC }
1575 static const struct sam4_reg_list sam4_all_regs[] = {
1576 SAM4_ENTRY(CKGR_MOR, sam4_explain_ckgr_mor),
1577 SAM4_ENTRY(CKGR_MCFR, sam4_explain_ckgr_mcfr),
1578 SAM4_ENTRY(CKGR_PLLAR, sam4_explain_ckgr_plla),
1579 SAM4_ENTRY(CKGR_UCKR, NULL),
1580 SAM4_ENTRY(PMC_FSMR, NULL),
1581 SAM4_ENTRY(PMC_FSPR, NULL),
1582 SAM4_ENTRY(PMC_IMR, NULL),
1583 SAM4_ENTRY(PMC_MCKR, sam4_explain_mckr),
1584 SAM4_ENTRY(PMC_PCK0, NULL),
1585 SAM4_ENTRY(PMC_PCK1, NULL),
1586 SAM4_ENTRY(PMC_PCK2, NULL),
1587 SAM4_ENTRY(PMC_PCSR, NULL),
1588 SAM4_ENTRY(PMC_SCSR, NULL),
1589 SAM4_ENTRY(PMC_SR, NULL),
1590 SAM4_ENTRY(CHIPID_CIDR, sam4_explain_chipid_cidr),
1591 SAM4_ENTRY(CHIPID_EXID, NULL),
1592 /* TERMINATE THE LIST */
1593 { .name = NULL }
1594 };
1595 #undef SAM4_ENTRY
1596
1597 static struct sam4_bank_private *get_sam4_bank_private(struct flash_bank *bank)
1598 {
1599 return bank->driver_priv;
1600 }
1601
1602 /**
1603 * Given a pointer to where it goes in the structure,
1604 * determine the register name, address from the all registers table.
1605 */
1606 static const struct sam4_reg_list *sam4_GetReg(struct sam4_chip *pChip, uint32_t *goes_here)
1607 {
1608 const struct sam4_reg_list *pReg;
1609
1610 pReg = &(sam4_all_regs[0]);
1611 while (pReg->name) {
1612 uint32_t *pPossible;
1613
1614 /* calculate where this one go.. */
1615 /* it is "possibly" this register. */
1616
1617 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
1618
1619 /* well? Is it this register */
1620 if (pPossible == goes_here) {
1621 /* Jump for joy! */
1622 return pReg;
1623 }
1624
1625 /* next... */
1626 pReg++;
1627 }
1628 /* This is *TOTAL*PANIC* - we are totally screwed. */
1629 LOG_ERROR("INVALID SAM4 REGISTER");
1630 return NULL;
1631 }
1632
1633 static int sam4_ReadThisReg(struct sam4_chip *pChip, uint32_t *goes_here)
1634 {
1635 const struct sam4_reg_list *pReg;
1636 int r;
1637
1638 pReg = sam4_GetReg(pChip, goes_here);
1639 if (!pReg)
1640 return ERROR_FAIL;
1641
1642 r = target_read_u32(pChip->target, pReg->address, goes_here);
1643 if (r != ERROR_OK) {
1644 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Err: %d",
1645 pReg->name, (unsigned)(pReg->address), r);
1646 }
1647 return r;
1648 }
1649
1650 static int sam4_ReadAllRegs(struct sam4_chip *pChip)
1651 {
1652 int r;
1653 const struct sam4_reg_list *pReg;
1654
1655 pReg = &(sam4_all_regs[0]);
1656 while (pReg->name) {
1657 r = sam4_ReadThisReg(pChip,
1658 sam4_get_reg_ptr(&(pChip->cfg), pReg));
1659 if (r != ERROR_OK) {
1660 LOG_ERROR("Cannot read SAM4 register: %s @ 0x%08x, Error: %d",
1661 pReg->name, ((unsigned)(pReg->address)), r);
1662 return r;
1663 }
1664 pReg++;
1665 }
1666
1667 return ERROR_OK;
1668 }
1669
1670 static int sam4_GetInfo(struct sam4_chip *pChip)
1671 {
1672 const struct sam4_reg_list *pReg;
1673 uint32_t regval;
1674
1675 pReg = &(sam4_all_regs[0]);
1676 while (pReg->name) {
1677 /* display all regs */
1678 LOG_DEBUG("Start: %s", pReg->name);
1679 regval = *sam4_get_reg_ptr(&(pChip->cfg), pReg);
1680 LOG_USER("%*s: [0x%08" PRIx32 "] -> 0x%08" PRIx32,
1681 REG_NAME_WIDTH,
1682 pReg->name,
1683 pReg->address,
1684 regval);
1685 if (pReg->explain_func)
1686 (*(pReg->explain_func))(pChip);
1687 LOG_DEBUG("End: %s", pReg->name);
1688 pReg++;
1689 }
1690 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
1691 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
1692 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
1693 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
1694 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
1695
1696 LOG_USER(" UniqueId: 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08" PRIx32 " 0x%08"PRIx32,
1697 pChip->cfg.unique_id[0],
1698 pChip->cfg.unique_id[1],
1699 pChip->cfg.unique_id[2],
1700 pChip->cfg.unique_id[3]);
1701
1702 return ERROR_OK;
1703 }
1704
1705 static int sam4_protect_check(struct flash_bank *bank)
1706 {
1707 int r;
1708 uint32_t v[4] = {0};
1709 unsigned x;
1710 struct sam4_bank_private *pPrivate;
1711
1712 LOG_DEBUG("Begin");
1713 if (bank->target->state != TARGET_HALTED) {
1714 LOG_ERROR("Target not halted");
1715 return ERROR_TARGET_NOT_HALTED;
1716 }
1717
1718 pPrivate = get_sam4_bank_private(bank);
1719 if (!pPrivate) {
1720 LOG_ERROR("no private for this bank?");
1721 return ERROR_FAIL;
1722 }
1723 if (!(pPrivate->probed))
1724 return ERROR_FLASH_BANK_NOT_PROBED;
1725
1726 r = FLASHD_GetLockBits(pPrivate, v);
1727 if (r != ERROR_OK) {
1728 LOG_DEBUG("Failed: %d", r);
1729 return r;
1730 }
1731
1732 for (x = 0; x < pPrivate->nsectors; x++)
1733 bank->sectors[x].is_protected = (!!(v[x >> 5] & (1 << (x % 32))));
1734 LOG_DEBUG("Done");
1735 return ERROR_OK;
1736 }
1737
1738 FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
1739 {
1740 struct sam4_chip *pChip;
1741
1742 pChip = all_sam4_chips;
1743
1744 /* is this an existing chip? */
1745 while (pChip) {
1746 if (pChip->target == bank->target)
1747 break;
1748 pChip = pChip->next;
1749 }
1750
1751 if (!pChip) {
1752 /* this is a *NEW* chip */
1753 pChip = calloc(1, sizeof(struct sam4_chip));
1754 if (!pChip) {
1755 LOG_ERROR("NO RAM!");
1756 return ERROR_FAIL;
1757 }
1758 pChip->target = bank->target;
1759 /* insert at head */
1760 pChip->next = all_sam4_chips;
1761 all_sam4_chips = pChip;
1762 pChip->target = bank->target;
1763 /* assumption is this runs at 32khz */
1764 pChip->cfg.slow_freq = 32768;
1765 pChip->probed = 0;
1766 }
1767
1768 switch (bank->base) {
1769 default:
1770 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x"
1771 "[at91sam4s series] )",
1772 ((unsigned int)(bank->base)),
1773 ((unsigned int)(FLASH_BANK_BASE_S)));
1774 return ERROR_FAIL;
1775 break;
1776
1777 /* at91sam4s series only has bank 0*/
1778 /* at91sam4sd series has the same address for bank 0 (FLASH_BANK0_BASE_SD)*/
1779 case FLASH_BANK_BASE_S:
1780 bank->driver_priv = &(pChip->details.bank[0]);
1781 bank->bank_number = 0;
1782 pChip->details.bank[0].pChip = pChip;
1783 pChip->details.bank[0].pBank = bank;
1784 break;
1785
1786 /* Bank 1 of at91sam4sd series */
1787 case FLASH_BANK1_BASE_1024K_SD:
1788 case FLASH_BANK1_BASE_2048K_SD:
1789 bank->driver_priv = &(pChip->details.bank[1]);
1790 bank->bank_number = 1;
1791 pChip->details.bank[1].pChip = pChip;
1792 pChip->details.bank[1].pBank = bank;
1793 break;
1794 }
1795
1796 /* we initialize after probing. */
1797 return ERROR_OK;
1798 }
1799
1800 static int sam4_GetDetails(struct sam4_bank_private *pPrivate)
1801 {
1802 const struct sam4_chip_details *pDetails;
1803 struct sam4_chip *pChip;
1804 struct flash_bank *saved_banks[SAM4_MAX_FLASH_BANKS];
1805 unsigned x;
1806
1807 LOG_DEBUG("Begin");
1808 pDetails = all_sam4_details;
1809 while (pDetails->name) {
1810 /* Compare cidr without version bits */
1811 if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
1812 break;
1813 else
1814 pDetails++;
1815 }
1816 if (pDetails->name == NULL) {
1817 LOG_ERROR("SAM4 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
1818 (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
1819 /* Help the victim, print details about the chip */
1820 LOG_INFO("SAM4 CHIPID_CIDR: 0x%08" PRIx32 " decodes as follows",
1821 pPrivate->pChip->cfg.CHIPID_CIDR);
1822 sam4_explain_chipid_cidr(pPrivate->pChip);
1823 return ERROR_FAIL;
1824 }
1825
1826 /* DANGER: THERE ARE DRAGONS HERE */
1827
1828 /* get our pChip - it is going */
1829 /* to be over-written shortly */
1830 pChip = pPrivate->pChip;
1831
1832 /* Note that, in reality: */
1833 /* */
1834 /* pPrivate = &(pChip->details.bank[0]) */
1835 /* or pPrivate = &(pChip->details.bank[1]) */
1836 /* */
1837
1838 /* save the "bank" pointers */
1839 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++)
1840 saved_banks[x] = pChip->details.bank[x].pBank;
1841
1842 /* Overwrite the "details" structure. */
1843 memcpy(&(pPrivate->pChip->details),
1844 pDetails,
1845 sizeof(pPrivate->pChip->details));
1846
1847 /* now fix the ghosted pointers */
1848 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
1849 pChip->details.bank[x].pChip = pChip;
1850 pChip->details.bank[x].pBank = saved_banks[x];
1851 }
1852
1853 /* update the *BANK*SIZE* */
1854
1855 LOG_DEBUG("End");
1856 return ERROR_OK;
1857 }
1858
1859 static int _sam4_probe(struct flash_bank *bank, int noise)
1860 {
1861 unsigned x;
1862 int r;
1863 struct sam4_bank_private *pPrivate;
1864
1865
1866 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
1867 if (bank->target->state != TARGET_HALTED) {
1868 LOG_ERROR("Target not halted");
1869 return ERROR_TARGET_NOT_HALTED;
1870 }
1871
1872 pPrivate = get_sam4_bank_private(bank);
1873 if (!pPrivate) {
1874 LOG_ERROR("Invalid/unknown bank number");
1875 return ERROR_FAIL;
1876 }
1877
1878 r = sam4_ReadAllRegs(pPrivate->pChip);
1879 if (r != ERROR_OK)
1880 return r;
1881
1882 LOG_DEBUG("Here");
1883 if (pPrivate->pChip->probed)
1884 r = sam4_GetInfo(pPrivate->pChip);
1885 else
1886 r = sam4_GetDetails(pPrivate);
1887 if (r != ERROR_OK)
1888 return r;
1889
1890 /* update the flash bank size */
1891 for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
1892 if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
1893 bank->size = pPrivate->pChip->details.bank[x].size_bytes;
1894 break;
1895 }
1896 }
1897
1898 if (bank->sectors == NULL) {
1899 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
1900 if (bank->sectors == NULL) {
1901 LOG_ERROR("No memory!");
1902 return ERROR_FAIL;
1903 }
1904 bank->num_sectors = pPrivate->nsectors;
1905
1906 for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
1907 bank->sectors[x].size = pPrivate->sector_size;
1908 bank->sectors[x].offset = x * (pPrivate->sector_size);
1909 /* mark as unknown */
1910 bank->sectors[x].is_erased = -1;
1911 bank->sectors[x].is_protected = -1;
1912 }
1913 }
1914
1915 pPrivate->probed = 1;
1916
1917 r = sam4_protect_check(bank);
1918 if (r != ERROR_OK)
1919 return r;
1920
1921 LOG_DEBUG("Bank = %d, nbanks = %d",
1922 pPrivate->bank_number, pPrivate->pChip->details.n_banks);
1923 if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
1924 /* read unique id, */
1925 /* it appears to be associated with the *last* flash bank. */
1926 FLASHD_ReadUniqueID(pPrivate);
1927 }
1928
1929 return r;
1930 }
1931
1932 static int sam4_probe(struct flash_bank *bank)
1933 {
1934 return _sam4_probe(bank, 1);
1935 }
1936
1937 static int sam4_auto_probe(struct flash_bank *bank)
1938 {
1939 return _sam4_probe(bank, 0);
1940 }
1941
1942 static int sam4_erase(struct flash_bank *bank, int first, int last)
1943 {
1944 struct sam4_bank_private *pPrivate;
1945 int r;
1946 int i;
1947 int pageCount;
1948 /*16 pages equals 8KB - Same size as a lock region*/
1949 pageCount = 16;
1950 uint32_t status;
1951
1952 LOG_DEBUG("Here");
1953 if (bank->target->state != TARGET_HALTED) {
1954 LOG_ERROR("Target not halted");
1955 return ERROR_TARGET_NOT_HALTED;
1956 }
1957
1958 r = sam4_auto_probe(bank);
1959 if (r != ERROR_OK) {
1960 LOG_DEBUG("Here,r=%d", r);
1961 return r;
1962 }
1963
1964 pPrivate = get_sam4_bank_private(bank);
1965 if (!(pPrivate->probed))
1966 return ERROR_FLASH_BANK_NOT_PROBED;
1967
1968 if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
1969 /* whole chip */
1970 LOG_DEBUG("Here");
1971 return FLASHD_EraseEntireBank(pPrivate);
1972 }
1973 LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
1974 LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", (unsigned int)(first), (unsigned int)(last));
1975 for (i = first; i <= last; i++) {
1976 /*16 pages equals 8KB - Same size as a lock region*/
1977 r = FLASHD_ErasePages(pPrivate, (i * pageCount), pageCount, &status);
1978 LOG_INFO("Erasing sector: 0x%08x", (unsigned int)(i));
1979 if (r != ERROR_OK)
1980 LOG_ERROR("SAM4: Error performing Erase page @ lock region number %d",
1981 (unsigned int)(i));
1982 if (status & (1 << 2)) {
1983 LOG_ERROR("SAM4: Lock Region %d is locked", (unsigned int)(i));
1984 return ERROR_FAIL;
1985 }
1986 if (status & (1 << 1)) {
1987 LOG_ERROR("SAM4: Flash Command error @lock region %d", (unsigned int)(i));
1988 return ERROR_FAIL;
1989 }
1990 }
1991
1992 return ERROR_OK;
1993 }
1994
1995 static int sam4_protect(struct flash_bank *bank, int set, int first, int last)
1996 {
1997 struct sam4_bank_private *pPrivate;
1998 int r;
1999
2000 LOG_DEBUG("Here");
2001 if (bank->target->state != TARGET_HALTED) {
2002 LOG_ERROR("Target not halted");
2003 return ERROR_TARGET_NOT_HALTED;
2004 }
2005
2006 pPrivate = get_sam4_bank_private(bank);
2007 if (!(pPrivate->probed))
2008 return ERROR_FLASH_BANK_NOT_PROBED;
2009
2010 if (set)
2011 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
2012 else
2013 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
2014 LOG_DEBUG("End: r=%d", r);
2015
2016 return r;
2017
2018 }
2019
2020 static int sam4_page_read(struct sam4_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
2021 {
2022 uint32_t adr;
2023 int r;
2024
2025 adr = pagenum * pPrivate->page_size;
2026 adr = adr + pPrivate->base_address;
2027
2028 r = target_read_memory(pPrivate->pChip->target,
2029 adr,
2030 4, /* THIS*MUST*BE* in 32bit values */
2031 pPrivate->page_size / 4,
2032 buf);
2033 if (r != ERROR_OK)
2034 LOG_ERROR("SAM4: Flash program failed to read page phys address: 0x%08x",
2035 (unsigned int)(adr));
2036 return r;
2037 }
2038
2039 static int sam4_page_write(struct sam4_bank_private *pPrivate, unsigned pagenum, const uint8_t *buf)
2040 {
2041 uint32_t adr;
2042 uint32_t status;
2043 uint32_t fmr; /* EEFC Flash Mode Register */
2044 int r;
2045
2046 adr = pagenum * pPrivate->page_size;
2047 adr = (adr + pPrivate->base_address);
2048
2049 /* Get flash mode register value */
2050 r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
2051 if (r != ERROR_OK)
2052 LOG_DEBUG("Error Read failed: read flash mode register");
2053
2054 /* Clear flash wait state field */
2055 fmr &= 0xfffff0ff;
2056
2057 /* set FWS (flash wait states) field in the FMR (flash mode register) */
2058 fmr |= (pPrivate->flash_wait_states << 8);
2059
2060 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
2061 r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
2062 if (r != ERROR_OK)
2063 LOG_DEBUG("Error Write failed: set flash mode register");
2064
2065 /* 1st sector 8kBytes - page 0 - 15*/
2066 /* 2nd sector 8kBytes - page 16 - 30*/
2067 /* 3rd sector 48kBytes - page 31 - 127*/
2068 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
2069 r = target_write_memory(pPrivate->pChip->target,
2070 adr,
2071 4, /* THIS*MUST*BE* in 32bit values */
2072 pPrivate->page_size / 4,
2073 buf);
2074 if (r != ERROR_OK) {
2075 LOG_ERROR("SAM4: Failed to write (buffer) page at phys address 0x%08x",
2076 (unsigned int)(adr));
2077 return r;
2078 }
2079
2080 r = EFC_PerformCommand(pPrivate,
2081 /* send Erase & Write Page */
2082 AT91C_EFC_FCMD_WP, /*AT91C_EFC_FCMD_EWP only works on first two 8kb sectors*/
2083 pagenum,
2084 &status);
2085
2086 if (r != ERROR_OK)
2087 LOG_ERROR("SAM4: Error performing Write page @ phys address 0x%08x",
2088 (unsigned int)(adr));
2089 if (status & (1 << 2)) {
2090 LOG_ERROR("SAM4: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
2091 return ERROR_FAIL;
2092 }
2093 if (status & (1 << 1)) {
2094 LOG_ERROR("SAM4: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
2095 return ERROR_FAIL;
2096 }
2097 return ERROR_OK;
2098 }
2099
2100 static int sam4_write(struct flash_bank *bank,
2101 const uint8_t *buffer,
2102 uint32_t offset,
2103 uint32_t count)
2104 {
2105 int n;
2106 unsigned page_cur;
2107 unsigned page_end;
2108 int r;
2109 unsigned page_offset;
2110 struct sam4_bank_private *pPrivate;
2111 uint8_t *pagebuffer;
2112
2113 /* incase we bail further below, set this to null */
2114 pagebuffer = NULL;
2115
2116 /* ignore dumb requests */
2117 if (count == 0) {
2118 r = ERROR_OK;
2119 goto done;
2120 }
2121
2122 if (bank->target->state != TARGET_HALTED) {
2123 LOG_ERROR("Target not halted");
2124 r = ERROR_TARGET_NOT_HALTED;
2125 goto done;
2126 }
2127
2128 pPrivate = get_sam4_bank_private(bank);
2129 if (!(pPrivate->probed)) {
2130 r = ERROR_FLASH_BANK_NOT_PROBED;
2131 goto done;
2132 }
2133
2134 if ((offset + count) > pPrivate->size_bytes) {
2135 LOG_ERROR("Flash write error - past end of bank");
2136 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2137 (unsigned int)(offset),
2138 (unsigned int)(count),
2139 (unsigned int)(pPrivate->size_bytes));
2140 r = ERROR_FAIL;
2141 goto done;
2142 }
2143
2144 pagebuffer = malloc(pPrivate->page_size);
2145 if (!pagebuffer) {
2146 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
2147 r = ERROR_FAIL;
2148 goto done;
2149 }
2150
2151 /* what page do we start & end in? */
2152 page_cur = offset / pPrivate->page_size;
2153 page_end = (offset + count - 1) / pPrivate->page_size;
2154
2155 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
2156 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
2157
2158 /* Special case: all one page */
2159 /* */
2160 /* Otherwise: */
2161 /* (1) non-aligned start */
2162 /* (2) body pages */
2163 /* (3) non-aligned end. */
2164
2165 /* Handle special case - all one page. */
2166 if (page_cur == page_end) {
2167 LOG_DEBUG("Special case, all in one page");
2168 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2169 if (r != ERROR_OK)
2170 goto done;
2171
2172 page_offset = (offset & (pPrivate->page_size-1));
2173 memcpy(pagebuffer + page_offset,
2174 buffer,
2175 count);
2176
2177 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2178 if (r != ERROR_OK)
2179 goto done;
2180 r = ERROR_OK;
2181 goto done;
2182 }
2183
2184 /* non-aligned start */
2185 page_offset = offset & (pPrivate->page_size - 1);
2186 if (page_offset) {
2187 LOG_DEBUG("Not-Aligned start");
2188 /* read the partial */
2189 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2190 if (r != ERROR_OK)
2191 goto done;
2192
2193 /* over-write with new data */
2194 n = (pPrivate->page_size - page_offset);
2195 memcpy(pagebuffer + page_offset,
2196 buffer,
2197 n);
2198
2199 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2200 if (r != ERROR_OK)
2201 goto done;
2202
2203 count -= n;
2204 offset += n;
2205 buffer += n;
2206 page_cur++;
2207 }
2208
2209 /* By checking that offset is correct here, we also
2210 fix a clang warning */
2211 assert(offset % pPrivate->page_size == 0);
2212
2213 /* intermediate large pages */
2214 /* also - the final *terminal* */
2215 /* if that terminal page is a full page */
2216 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2217 (int)page_cur, (int)page_end, (unsigned int)(count));
2218
2219 while ((page_cur < page_end) &&
2220 (count >= pPrivate->page_size)) {
2221 r = sam4_page_write(pPrivate, page_cur, buffer);
2222 if (r != ERROR_OK)
2223 goto done;
2224 count -= pPrivate->page_size;
2225 buffer += pPrivate->page_size;
2226 page_cur += 1;
2227 }
2228
2229 /* terminal partial page? */
2230 if (count) {
2231 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
2232 /* we have a partial page */
2233 r = sam4_page_read(pPrivate, page_cur, pagebuffer);
2234 if (r != ERROR_OK)
2235 goto done;
2236 /* data goes at start */
2237 memcpy(pagebuffer, buffer, count);
2238 r = sam4_page_write(pPrivate, page_cur, pagebuffer);
2239 if (r != ERROR_OK)
2240 goto done;
2241 }
2242 LOG_DEBUG("Done!");
2243 r = ERROR_OK;
2244 done:
2245 if (pagebuffer)
2246 free(pagebuffer);
2247 return r;
2248 }
2249
2250 COMMAND_HANDLER(sam4_handle_info_command)
2251 {
2252 struct sam4_chip *pChip;
2253 pChip = get_current_sam4(CMD_CTX);
2254 if (!pChip)
2255 return ERROR_OK;
2256
2257 unsigned x;
2258 int r;
2259
2260 /* bank0 must exist before we can do anything */
2261 if (pChip->details.bank[0].pBank == NULL) {
2262 x = 0;
2263 need_define:
2264 command_print(CMD_CTX,
2265 "Please define bank %d via command: flash bank %s ... ",
2266 x,
2267 at91sam4_flash.name);
2268 return ERROR_FAIL;
2269 }
2270
2271 /* if bank 0 is not probed, then probe it */
2272 if (!(pChip->details.bank[0].probed)) {
2273 r = sam4_auto_probe(pChip->details.bank[0].pBank);
2274 if (r != ERROR_OK)
2275 return ERROR_FAIL;
2276 }
2277 /* above guarantees the "chip details" structure is valid */
2278 /* and thus, bank private areas are valid */
2279 /* and we have a SAM4 chip, what a concept! */
2280
2281 /* auto-probe other banks, 0 done above */
2282 for (x = 1; x < SAM4_MAX_FLASH_BANKS; x++) {
2283 /* skip banks not present */
2284 if (!(pChip->details.bank[x].present))
2285 continue;
2286
2287 if (pChip->details.bank[x].pBank == NULL)
2288 goto need_define;
2289
2290 if (pChip->details.bank[x].probed)
2291 continue;
2292
2293 r = sam4_auto_probe(pChip->details.bank[x].pBank);
2294 if (r != ERROR_OK)
2295 return r;
2296 }
2297
2298 r = sam4_GetInfo(pChip);
2299 if (r != ERROR_OK) {
2300 LOG_DEBUG("Sam4Info, Failed %d", r);
2301 return r;
2302 }
2303
2304 return ERROR_OK;
2305 }
2306
2307 COMMAND_HANDLER(sam4_handle_gpnvm_command)
2308 {
2309 unsigned x, v;
2310 int r, who;
2311 struct sam4_chip *pChip;
2312
2313 pChip = get_current_sam4(CMD_CTX);
2314 if (!pChip)
2315 return ERROR_OK;
2316
2317 if (pChip->target->state != TARGET_HALTED) {
2318 LOG_ERROR("sam4 - target not halted");
2319 return ERROR_TARGET_NOT_HALTED;
2320 }
2321
2322 if (pChip->details.bank[0].pBank == NULL) {
2323 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
2324 at91sam4_flash.name);
2325 return ERROR_FAIL;
2326 }
2327 if (!pChip->details.bank[0].probed) {
2328 r = sam4_auto_probe(pChip->details.bank[0].pBank);
2329 if (r != ERROR_OK)
2330 return r;
2331 }
2332
2333 switch (CMD_ARGC) {
2334 default:
2335 return ERROR_COMMAND_SYNTAX_ERROR;
2336 break;
2337 case 0:
2338 goto showall;
2339 break;
2340 case 1:
2341 who = -1;
2342 break;
2343 case 2:
2344 if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
2345 who = -1;
2346 else {
2347 uint32_t v32;
2348 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
2349 who = v32;
2350 }
2351 break;
2352 }
2353
2354 if (0 == strcmp("show", CMD_ARGV[0])) {
2355 if (who == -1) {
2356 showall:
2357 r = ERROR_OK;
2358 for (x = 0; x < pChip->details.n_gpnvms; x++) {
2359 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
2360 if (r != ERROR_OK)
2361 break;
2362 command_print(CMD_CTX, "sam4-gpnvm%u: %u", x, v);
2363 }
2364 return r;
2365 }
2366 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
2367 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
2368 command_print(CMD_CTX, "sam4-gpnvm%u: %u", who, v);
2369 return r;
2370 } else {
2371 command_print(CMD_CTX, "sam4-gpnvm invalid GPNVM: %u", who);
2372 return ERROR_COMMAND_SYNTAX_ERROR;
2373 }
2374 }
2375
2376 if (who == -1) {
2377 command_print(CMD_CTX, "Missing GPNVM number");
2378 return ERROR_COMMAND_SYNTAX_ERROR;
2379 }
2380
2381 if (0 == strcmp("set", CMD_ARGV[0]))
2382 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
2383 else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
2384 (0 == strcmp("clear", CMD_ARGV[0]))) /* quietly accept both */
2385 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
2386 else {
2387 command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
2388 r = ERROR_COMMAND_SYNTAX_ERROR;
2389 }
2390 return r;
2391 }
2392
2393 COMMAND_HANDLER(sam4_handle_slowclk_command)
2394 {
2395 struct sam4_chip *pChip;
2396
2397 pChip = get_current_sam4(CMD_CTX);
2398 if (!pChip)
2399 return ERROR_OK;
2400
2401 switch (CMD_ARGC) {
2402 case 0:
2403 /* show */
2404 break;
2405 case 1:
2406 {
2407 /* set */
2408 uint32_t v;
2409 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
2410 if (v > 200000) {
2411 /* absurd slow clock of 200Khz? */
2412 command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));
2413 return ERROR_COMMAND_SYNTAX_ERROR;
2414 }
2415 pChip->cfg.slow_freq = v;
2416 break;
2417 }
2418 default:
2419 /* error */
2420 command_print(CMD_CTX, "Too many parameters");
2421 return ERROR_COMMAND_SYNTAX_ERROR;
2422 break;
2423 }
2424 command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
2425 (int)(pChip->cfg.slow_freq / 1000),
2426 (int)(pChip->cfg.slow_freq % 1000));
2427 return ERROR_OK;
2428 }
2429
2430 static const struct command_registration at91sam4_exec_command_handlers[] = {
2431 {
2432 .name = "gpnvm",
2433 .handler = sam4_handle_gpnvm_command,
2434 .mode = COMMAND_EXEC,
2435 .usage = "[('clr'|'set'|'show') bitnum]",
2436 .help = "Without arguments, shows all bits in the gpnvm "
2437 "register. Otherwise, clears, sets, or shows one "
2438 "General Purpose Non-Volatile Memory (gpnvm) bit.",
2439 },
2440 {
2441 .name = "info",
2442 .handler = sam4_handle_info_command,
2443 .mode = COMMAND_EXEC,
2444 .help = "Print information about the current at91sam4 chip"
2445 "and its flash configuration.",
2446 },
2447 {
2448 .name = "slowclk",
2449 .handler = sam4_handle_slowclk_command,
2450 .mode = COMMAND_EXEC,
2451 .usage = "[clock_hz]",
2452 .help = "Display or set the slowclock frequency "
2453 "(default 32768 Hz).",
2454 },
2455 COMMAND_REGISTRATION_DONE
2456 };
2457 static const struct command_registration at91sam4_command_handlers[] = {
2458 {
2459 .name = "at91sam4",
2460 .mode = COMMAND_ANY,
2461 .help = "at91sam4 flash command group",
2462 .usage = "",
2463 .chain = at91sam4_exec_command_handlers,
2464 },
2465 COMMAND_REGISTRATION_DONE
2466 };
2467
2468 struct flash_driver at91sam4_flash = {
2469 .name = "at91sam4",
2470 .commands = at91sam4_command_handlers,
2471 .flash_bank_command = sam4_flash_bank_command,
2472 .erase = sam4_erase,
2473 .protect = sam4_protect,
2474 .write = sam4_write,
2475 .read = default_flash_read,
2476 .probe = sam4_probe,
2477 .auto_probe = sam4_auto_probe,
2478 .erase_check = default_flash_blank_check,
2479 .protect_check = sam4_protect_check,
2480 };
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