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jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / flash / nor / at91sam7.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 /***************************************************************************
4 * Copyright (C) 2006 by Magnus Lundin *
5 * lundin@mlu.mine.nu *
6 * *
7 * Copyright (C) 2008 by Gheorghe Guran (atlas) *
8 ****************************************************************************/
9
10 /***************************************************************************
11 *
12 * New flash setup command:
13 *
14 * flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_id>
15 * [<chip_type> <banks>
16 * <sectors_per_bank> <pages_per_sector>
17 * <page_size> <num_nvmbits>
18 * <ext_freq_khz>]
19 *
20 * <ext_freq_khz> - MUST be used if clock is from external source,
21 * CAN be used if main oscillator frequency is known (recommended)
22 * Examples:
23 * ==== RECOMMENDED (covers clock speed) ============
24 * flash bank at91sam7 0x00100000 0 0 4 $_TARGETNAME AT91SAM7XC256 1 16 64 256 3 25000
25 * (if auto-detect fails; provides clock spec)
26 * flash bank at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 25000
27 * (auto-detect everything except the clock)
28 * ==== NOT RECOMMENDED !!! (clock speed is not configured) ====
29 * flash bank at91sam7 0x00100000 0 0 4 $_TARGETNAME AT91SAM7XC256 1 16 64 256 3 0
30 * (if auto-detect fails)
31 * flash bank at91sam7 0 0 0 0 $_TARGETNAME
32 * (old style, auto-detect everything)
33 ****************************************************************************/
34
35 #ifdef HAVE_CONFIG_H
36 #include "config.h"
37 #endif
38
39 #include "imp.h"
40 #include <helper/binarybuffer.h>
41
42 /* AT91SAM7 control registers */
43 #define DBGU_CIDR 0xFFFFF240
44 #define CKGR_MCFR 0xFFFFFC24
45 #define CKGR_MOR 0xFFFFFC20
46 #define CKGR_MCFR_MAINRDY 0x10000
47 #define CKGR_PLLR 0xFFFFFC2c
48 #define CKGR_PLLR_DIV 0xff
49 #define CKGR_PLLR_MUL 0x07ff0000
50 #define PMC_MCKR 0xFFFFFC30
51 #define PMC_MCKR_CSS 0x03
52 #define PMC_MCKR_PRES 0x1c
53
54 /* Flash Controller Commands */
55 #define WP 0x01
56 #define SLB 0x02
57 #define WPL 0x03
58 #define CLB 0x04
59 #define EA 0x08
60 #define SGPB 0x0B
61 #define CGPB 0x0D
62 #define SSB 0x0F
63
64 /* MC_FSR bit definitions */
65 #define MC_FSR_FRDY 1
66 #define MC_FSR_EOL 2
67
68 /* AT91SAM7 constants */
69 #define RC_FREQ 32000
70
71 /* Flash timing modes */
72 #define FMR_TIMING_NONE 0
73 #define FMR_TIMING_NVBITS 1
74 #define FMR_TIMING_FLASH 2
75
76 /* Flash size constants */
77 #define FLASH_SIZE_8KB 1
78 #define FLASH_SIZE_16KB 2
79 #define FLASH_SIZE_32KB 3
80 #define FLASH_SIZE_64KB 5
81 #define FLASH_SIZE_128KB 7
82 #define FLASH_SIZE_256KB 9
83 #define FLASH_SIZE_512KB 10
84 #define FLASH_SIZE_1024KB 12
85 #define FLASH_SIZE_2048KB 14
86
87 static int at91sam7_protect_check(struct flash_bank *bank);
88 static int at91sam7_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset,
89 uint32_t count);
90
91 static uint32_t at91sam7_get_flash_status(struct target *target, int bank_number);
92 static void at91sam7_set_flash_mode(struct flash_bank *bank, int mode);
93 static uint32_t at91sam7_wait_status_busy(struct flash_bank *bank, uint32_t waitbits, int timeout);
94 static int at91sam7_flash_command(struct flash_bank *bank, uint8_t cmd, uint16_t pagen);
95
96 static const uint32_t mc_fmr[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
97 static const uint32_t mc_fcr[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
98 static const uint32_t mc_fsr[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
99
100 static const char *eproc[8] = {
101 "Unknown", "ARM946-E", "ARM7TDMI", "Unknown", "ARM920T", "ARM926EJ-S", "Unknown", "Unknown"
102 };
103
104 struct at91sam7_flash_bank {
105 /* chip id register */
106 uint32_t cidr;
107 uint16_t cidr_ext;
108 uint16_t cidr_nvptyp;
109 uint16_t cidr_arch;
110 uint16_t cidr_sramsiz;
111 uint16_t cidr_nvpsiz;
112 uint16_t cidr_nvpsiz2;
113 uint16_t cidr_eproc;
114 uint16_t cidr_version;
115 const char *target_name;
116
117 /* flash auto-detection */
118 uint8_t flash_autodetection;
119
120 /* flash geometry */
121 uint16_t pages_per_sector;
122 uint16_t pagesize;
123 uint16_t pages_in_lockregion;
124
125 /* nv memory bits */
126 uint16_t num_lockbits_on;
127 uint16_t lockbits;
128 uint16_t num_nvmbits;
129 uint16_t num_nvmbits_on;
130 uint16_t nvmbits;
131 uint8_t securitybit;
132
133 /* 0: not init
134 * 1: fmcn for nvbits (1uS)
135 * 2: fmcn for flash (1.5uS) */
136 uint8_t flashmode;
137
138 /* main clock status */
139 uint8_t mck_valid;
140 uint32_t mck_freq;
141
142 /* external clock frequency */
143 uint32_t ext_freq;
144
145 };
146
147 #if 0
148 static long SRAMSIZ[16] = {
149 -1,
150 0x0400, /* 1K */
151 0x0800, /* 2K */
152 -1,
153 0x1c000, /* 112K */
154 0x1000, /* 4K */
155 0x14000, /* 80K */
156 0x28000, /* 160K */
157 0x2000, /* 8K */
158 0x4000, /* 16K */
159 0x8000, /* 32K */
160 0x10000, /* 64K */
161 0x20000, /* 128K */
162 0x40000, /* 256K */
163 0x18000, /* 96K */
164 0x80000, /* 512K */
165 };
166 #endif
167
168 static uint32_t at91sam7_get_flash_status(struct target *target, int bank_number)
169 {
170 uint32_t fsr;
171 target_read_u32(target, mc_fsr[bank_number], &fsr);
172
173 return fsr;
174 }
175
176 /* Read clock configuration and set at91sam7_info->mck_freq */
177 static void at91sam7_read_clock_info(struct flash_bank *bank)
178 {
179 struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
180 struct target *target = bank->target;
181 uint32_t mckr, mcfr, pllr, mor;
182 unsigned long tmp = 0, mainfreq;
183
184 /* Read Clock Generator Main Oscillator Register */
185 target_read_u32(target, CKGR_MOR, &mor);
186 /* Read Clock Generator Main Clock Frequency Register */
187 target_read_u32(target, CKGR_MCFR, &mcfr);
188 /* Read Master Clock Register*/
189 target_read_u32(target, PMC_MCKR, &mckr);
190 /* Read Clock Generator PLL Register */
191 target_read_u32(target, CKGR_PLLR, &pllr);
192
193 at91sam7_info->mck_valid = 0;
194 at91sam7_info->mck_freq = 0;
195 switch (mckr & PMC_MCKR_CSS) {
196 case 0: /* Slow Clock */
197 at91sam7_info->mck_valid = 1;
198 tmp = RC_FREQ;
199 break;
200
201 case 1: /* Main Clock */
202 if ((mcfr & CKGR_MCFR_MAINRDY) &&
203 (at91sam7_info->ext_freq == 0)) {
204 at91sam7_info->mck_valid = 1;
205 tmp = RC_FREQ / 16ul * (mcfr & 0xffff);
206 } else if (at91sam7_info->ext_freq != 0) {
207 at91sam7_info->mck_valid = 1;
208 tmp = at91sam7_info->ext_freq;
209 }
210 break;
211
212 case 2: /* Reserved */
213 break;
214
215 case 3: /* PLL Clock */
216 if ((mcfr & CKGR_MCFR_MAINRDY) &&
217 (at91sam7_info->ext_freq == 0)) {
218 target_read_u32(target, CKGR_PLLR, &pllr);
219 if (!(pllr & CKGR_PLLR_DIV))
220 break; /* 0 Hz */
221 at91sam7_info->mck_valid = 1;
222 mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
223 /* Integer arithmetic should have sufficient precision
224 * as long as PLL is properly configured. */
225 tmp = mainfreq / (pllr & CKGR_PLLR_DIV)*
226 (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
227 } else if ((at91sam7_info->ext_freq != 0) &&
228 ((pllr&CKGR_PLLR_DIV) != 0)) {
229 at91sam7_info->mck_valid = 1;
230 tmp = at91sam7_info->ext_freq / (pllr&CKGR_PLLR_DIV)*
231 (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
232 }
233 break;
234 }
235
236 /* Prescaler adjust */
237 if ((((mckr & PMC_MCKR_PRES) >> 2) == 7) || (tmp == 0)) {
238 at91sam7_info->mck_valid = 0;
239 at91sam7_info->mck_freq = 0;
240 } else if (((mckr & PMC_MCKR_PRES) >> 2) != 0)
241 at91sam7_info->mck_freq = tmp >> ((mckr & PMC_MCKR_PRES) >> 2);
242 else
243 at91sam7_info->mck_freq = tmp;
244 }
245
246 /* Setup the timing registers for nvbits or normal flash */
247 static void at91sam7_set_flash_mode(struct flash_bank *bank, int mode)
248 {
249 uint32_t fmr, fmcn = 0, fws = 0;
250 struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
251 struct target *target = bank->target;
252
253 if (mode && (mode != at91sam7_info->flashmode)) {
254 /* Always round up (ceil) */
255 if (mode == FMR_TIMING_NVBITS) {
256 if (at91sam7_info->cidr_arch == 0x60) {
257 /* AT91SAM7A3 uses master clocks in 100 ns */
258 fmcn = (at91sam7_info->mck_freq/10000000ul) + 1;
259 } else {
260 /* master clocks in 1uS for ARCH 0x7 types */
261 fmcn = (at91sam7_info->mck_freq/1000000ul) + 1;
262 }
263 } else if (mode == FMR_TIMING_FLASH) {
264 /* main clocks in 1.5uS */
265 fmcn = (at91sam7_info->mck_freq/1000000ul)+
266 (at91sam7_info->mck_freq/2000000ul) + 1;
267 }
268
269 /* hard overclocking */
270 if (fmcn > 0xFF)
271 fmcn = 0xFF;
272
273 /* Only allow fmcn = 0 if clock period is > 30 us = 33kHz. */
274 if (at91sam7_info->mck_freq <= 33333ul)
275 fmcn = 0;
276 /* Only allow fws = 0 if clock frequency is < 30 MHz. */
277 if (at91sam7_info->mck_freq > 30000000ul)
278 fws = 1;
279
280 LOG_DEBUG("fmcn[%i]: %i", bank->bank_number, (int)(fmcn));
281 fmr = fmcn << 16 | fws << 8;
282 target_write_u32(target, mc_fmr[bank->bank_number], fmr);
283 }
284
285 at91sam7_info->flashmode = mode;
286 }
287
288 static uint32_t at91sam7_wait_status_busy(struct flash_bank *bank, uint32_t waitbits, int timeout)
289 {
290 uint32_t status;
291
292 while ((!((status = at91sam7_get_flash_status(bank->target,
293 bank->bank_number)) & waitbits)) && (timeout-- > 0)) {
294 LOG_DEBUG("status[%i]: 0x%" PRIx32 "", (int)bank->bank_number, status);
295 alive_sleep(1);
296 }
297
298 LOG_DEBUG("status[%i]: 0x%" PRIx32 "", bank->bank_number, status);
299
300 if (status & 0x0C) {
301 LOG_ERROR("status register: 0x%" PRIx32 "", status);
302 if (status & 0x4)
303 LOG_ERROR("Lock Error Bit Detected, Operation Abort");
304 if (status & 0x8)
305 LOG_ERROR("Invalid command and/or bad keyword, Operation Abort");
306 if (status & 0x10)
307 LOG_ERROR("Security Bit Set, Operation Abort");
308 }
309
310 return status;
311 }
312
313 /* Send one command to the AT91SAM flash controller */
314 static int at91sam7_flash_command(struct flash_bank *bank, uint8_t cmd, uint16_t pagen)
315 {
316 uint32_t fcr;
317 struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
318 struct target *target = bank->target;
319
320 fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd;
321 target_write_u32(target, mc_fcr[bank->bank_number], fcr);
322 LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u",
323 fcr,
324 bank->bank_number + 1,
325 pagen);
326
327 if ((at91sam7_info->cidr_arch == 0x60) && ((cmd == SLB) | (cmd == CLB))) {
328 /* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
329 if (at91sam7_wait_status_busy(bank, MC_FSR_EOL, 10)&0x0C)
330 return ERROR_FLASH_OPERATION_FAILED;
331 return ERROR_OK;
332 }
333
334 if (at91sam7_wait_status_busy(bank, MC_FSR_FRDY, 10)&0x0C)
335 return ERROR_FLASH_OPERATION_FAILED;
336
337 return ERROR_OK;
338 }
339
340 /* Read device id register, main clock frequency register and fill in driver info structure */
341 static int at91sam7_read_part_info(struct flash_bank *bank)
342 {
343 struct at91sam7_flash_bank *at91sam7_info;
344 struct target *target = bank->target;
345
346 uint16_t bnk, sec;
347 uint16_t arch;
348 uint32_t cidr;
349 uint8_t banks_num = 0;
350 uint16_t num_nvmbits = 0;
351 uint16_t sectors_num = 0;
352 uint16_t pages_per_sector = 0;
353 uint16_t page_size = 0;
354 uint32_t ext_freq;
355 uint32_t bank_size;
356 uint32_t base_address = 0;
357 char *target_name_t = "Unknown";
358
359 at91sam7_info = bank->driver_priv;
360
361 if (at91sam7_info->cidr != 0) {
362 /* flash already configured, update clock and check for protected sectors */
363 for (struct flash_bank *t_bank = bank; t_bank; t_bank = t_bank->next) {
364 if (t_bank->target != target)
365 continue;
366 /* re-calculate master clock frequency */
367 at91sam7_read_clock_info(t_bank);
368
369 /* no timing */
370 at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
371
372 /* check protect state */
373 at91sam7_protect_check(t_bank);
374 }
375
376 return ERROR_OK;
377 }
378
379 /* Read and parse chip identification register */
380 target_read_u32(target, DBGU_CIDR, &cidr);
381 if (cidr == 0) {
382 LOG_WARNING("Cannot identify target as an AT91SAM");
383 return ERROR_FLASH_OPERATION_FAILED;
384 }
385
386 if (at91sam7_info->flash_autodetection == 0) {
387 /* banks and sectors are already created, based on data from input file */
388 for (struct flash_bank *t_bank = bank; t_bank; t_bank = t_bank->next) {
389 if (t_bank->target != target)
390 continue;
391
392 at91sam7_info = t_bank->driver_priv;
393
394 at91sam7_info->cidr = cidr;
395 at91sam7_info->cidr_ext = (cidr >> 31)&0x0001;
396 at91sam7_info->cidr_nvptyp = (cidr >> 28)&0x0007;
397 at91sam7_info->cidr_arch = (cidr >> 20)&0x00FF;
398 at91sam7_info->cidr_sramsiz = (cidr >> 16)&0x000F;
399 at91sam7_info->cidr_nvpsiz2 = (cidr >> 12)&0x000F;
400 at91sam7_info->cidr_nvpsiz = (cidr >> 8)&0x000F;
401 at91sam7_info->cidr_eproc = (cidr >> 5)&0x0007;
402 at91sam7_info->cidr_version = cidr&0x001F;
403
404 /* calculate master clock frequency */
405 at91sam7_read_clock_info(t_bank);
406
407 /* no timing */
408 at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
409
410 /* check protect state */
411 at91sam7_protect_check(t_bank);
412 }
413
414 return ERROR_OK;
415 }
416
417 arch = (cidr >> 20)&0x00FF;
418
419 /* check flash size */
420 switch ((cidr >> 8)&0x000F) {
421 case FLASH_SIZE_8KB:
422 break;
423
424 case FLASH_SIZE_16KB:
425 banks_num = 1;
426 sectors_num = 8;
427 pages_per_sector = 32;
428 page_size = 64;
429 base_address = 0x00100000;
430 if (arch == 0x70) {
431 num_nvmbits = 2;
432 target_name_t = "AT91SAM7S161/16";
433 }
434 break;
435
436 case FLASH_SIZE_32KB:
437 banks_num = 1;
438 sectors_num = 8;
439 pages_per_sector = 32;
440 page_size = 128;
441 base_address = 0x00100000;
442 if (arch == 0x70) {
443 num_nvmbits = 2;
444 target_name_t = "AT91SAM7S321/32";
445 }
446 if (arch == 0x72) {
447 num_nvmbits = 3;
448 target_name_t = "AT91SAM7SE32";
449 }
450 break;
451
452 case FLASH_SIZE_64KB:
453 banks_num = 1;
454 sectors_num = 16;
455 pages_per_sector = 32;
456 page_size = 128;
457 base_address = 0x00100000;
458 if (arch == 0x70) {
459 num_nvmbits = 2;
460 target_name_t = "AT91SAM7S64";
461 }
462 break;
463
464 case FLASH_SIZE_128KB:
465 banks_num = 1;
466 sectors_num = 8;
467 pages_per_sector = 64;
468 page_size = 256;
469 base_address = 0x00100000;
470 if (arch == 0x70) {
471 num_nvmbits = 2;
472 target_name_t = "AT91SAM7S128";
473 }
474 if (arch == 0x71) {
475 num_nvmbits = 3;
476 target_name_t = "AT91SAM7XC128";
477 }
478 if (arch == 0x72) {
479 num_nvmbits = 3;
480 target_name_t = "AT91SAM7SE128";
481 }
482 if (arch == 0x75) {
483 num_nvmbits = 3;
484 target_name_t = "AT91SAM7X128";
485 }
486 break;
487
488 case FLASH_SIZE_256KB:
489 banks_num = 1;
490 sectors_num = 16;
491 pages_per_sector = 64;
492 page_size = 256;
493 base_address = 0x00100000;
494 if (arch == 0x60) {
495 num_nvmbits = 3;
496 target_name_t = "AT91SAM7A3";
497 }
498 if (arch == 0x70) {
499 num_nvmbits = 2;
500 target_name_t = "AT91SAM7S256";
501 }
502 if (arch == 0x71) {
503 num_nvmbits = 3;
504 target_name_t = "AT91SAM7XC256";
505 }
506 if (arch == 0x72) {
507 num_nvmbits = 3;
508 target_name_t = "AT91SAM7SE256";
509 }
510 if (arch == 0x75) {
511 num_nvmbits = 3;
512 target_name_t = "AT91SAM7X256";
513 }
514 break;
515
516 case FLASH_SIZE_512KB:
517 banks_num = 2;
518 sectors_num = 16;
519 pages_per_sector = 64;
520 page_size = 256;
521 base_address = 0x00100000;
522 if (arch == 0x70) {
523 num_nvmbits = 2;
524 target_name_t = "AT91SAM7S512";
525 }
526 if (arch == 0x71) {
527 num_nvmbits = 3;
528 target_name_t = "AT91SAM7XC512";
529 }
530 if (arch == 0x72) {
531 num_nvmbits = 3;
532 target_name_t = "AT91SAM7SE512";
533 }
534 if (arch == 0x75) {
535 num_nvmbits = 3;
536 target_name_t = "AT91SAM7X512";
537 }
538 break;
539
540 case FLASH_SIZE_1024KB:
541 break;
542
543 case FLASH_SIZE_2048KB:
544 break;
545 }
546
547 if (strcmp(target_name_t, "Unknown") == 0) {
548 LOG_ERROR(
549 "Target autodetection failed! Please specify target parameters in configuration file");
550 return ERROR_FLASH_OPERATION_FAILED;
551 }
552
553 ext_freq = at91sam7_info->ext_freq;
554
555 /* calculate bank size */
556 bank_size = sectors_num * pages_per_sector * page_size;
557
558 for (bnk = 0; bnk < banks_num; bnk++) {
559 struct flash_bank *t_bank = bank;
560 if (bnk > 0) {
561 if (!t_bank->next) {
562 /* create a new flash bank element */
563 struct flash_bank *fb = calloc(sizeof(struct flash_bank), 1);
564 if (!fb) {
565 LOG_ERROR("No memory for flash bank");
566 return ERROR_FAIL;
567 }
568 fb->target = target;
569 fb->driver = bank->driver;
570 fb->default_padded_value = 0xff;
571 fb->erased_value = 0xff;
572 fb->driver_priv = malloc(sizeof(struct at91sam7_flash_bank));
573 if (!fb->driver_priv) {
574 free(fb);
575 LOG_ERROR("No memory for flash driver priv");
576 return ERROR_FAIL;
577 }
578 fb->name = strdup("sam7_probed");
579
580 /* link created bank in 'flash_banks' list */
581 t_bank->next = fb;
582 }
583 t_bank = t_bank->next;
584 }
585
586 t_bank->bank_number = bnk;
587 t_bank->base = base_address + bnk * bank_size;
588 t_bank->size = bank_size;
589 t_bank->num_sectors = sectors_num;
590
591 /* allocate sectors */
592 t_bank->sectors = malloc(sectors_num * sizeof(struct flash_sector));
593 for (sec = 0; sec < sectors_num; sec++) {
594 t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
595 t_bank->sectors[sec].size = pages_per_sector * page_size;
596 t_bank->sectors[sec].is_erased = -1;
597 t_bank->sectors[sec].is_protected = -1;
598 }
599
600 at91sam7_info = t_bank->driver_priv;
601
602 at91sam7_info->cidr = cidr;
603 at91sam7_info->cidr_ext = (cidr >> 31)&0x0001;
604 at91sam7_info->cidr_nvptyp = (cidr >> 28)&0x0007;
605 at91sam7_info->cidr_arch = (cidr >> 20)&0x00FF;
606 at91sam7_info->cidr_sramsiz = (cidr >> 16)&0x000F;
607 at91sam7_info->cidr_nvpsiz2 = (cidr >> 12)&0x000F;
608 at91sam7_info->cidr_nvpsiz = (cidr >> 8)&0x000F;
609 at91sam7_info->cidr_eproc = (cidr >> 5)&0x0007;
610 at91sam7_info->cidr_version = cidr&0x001F;
611
612 at91sam7_info->target_name = target_name_t;
613 at91sam7_info->flashmode = 0;
614 at91sam7_info->ext_freq = ext_freq;
615 at91sam7_info->num_nvmbits = num_nvmbits;
616 at91sam7_info->num_nvmbits_on = 0;
617 at91sam7_info->pagesize = page_size;
618 at91sam7_info->pages_per_sector = pages_per_sector;
619
620 /* calculate master clock frequency */
621 at91sam7_read_clock_info(t_bank);
622
623 /* no timing */
624 at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
625
626 /* check protect state */
627 at91sam7_protect_check(t_bank);
628 }
629
630 LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x",
631 at91sam7_info->cidr_nvptyp,
632 at91sam7_info->cidr_arch);
633
634 return ERROR_OK;
635 }
636
637 static int at91sam7_erase_check(struct flash_bank *bank)
638 {
639 if (bank->target->state != TARGET_HALTED) {
640 LOG_ERROR("Target not halted");
641 return ERROR_TARGET_NOT_HALTED;
642 }
643
644 /* Configure the flash controller timing */
645 at91sam7_read_clock_info(bank);
646 at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
647
648 return default_flash_blank_check(bank);
649 }
650
651 static int at91sam7_protect_check(struct flash_bank *bank)
652 {
653 uint8_t lock_pos, gpnvm_pos;
654 uint32_t status;
655
656 struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
657
658 if (at91sam7_info->cidr == 0)
659 return ERROR_FLASH_BANK_NOT_PROBED;
660 if (bank->target->state != TARGET_HALTED) {
661 LOG_ERROR("Target not halted");
662 return ERROR_TARGET_NOT_HALTED;
663 }
664
665 status = at91sam7_get_flash_status(bank->target, bank->bank_number);
666 at91sam7_info->lockbits = (status >> 16);
667
668 at91sam7_info->num_lockbits_on = 0;
669 for (lock_pos = 0; lock_pos < bank->num_sectors; lock_pos++) {
670 if (((status >> (16 + lock_pos))&(0x0001)) == 1) {
671 at91sam7_info->num_lockbits_on++;
672 bank->sectors[lock_pos].is_protected = 1;
673 } else
674 bank->sectors[lock_pos].is_protected = 0;
675 }
676
677 /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
678 status = at91sam7_get_flash_status(bank->target, 0);
679
680 at91sam7_info->securitybit = (status >> 4)&0x01;
681 at91sam7_info->nvmbits = (status >> 8)&0xFF;
682
683 at91sam7_info->num_nvmbits_on = 0;
684 for (gpnvm_pos = 0; gpnvm_pos < at91sam7_info->num_nvmbits; gpnvm_pos++) {
685 if (((status >> (8 + gpnvm_pos))&(0x01)) == 1)
686 at91sam7_info->num_nvmbits_on++;
687 }
688
689 return ERROR_OK;
690 }
691
692 FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
693 {
694 struct flash_bank *t_bank = bank;
695 struct at91sam7_flash_bank *at91sam7_info;
696 struct target *target = t_bank->target;
697
698 uint32_t base_address;
699 uint32_t bank_size;
700 uint32_t ext_freq = 0;
701
702 unsigned int banks_num;
703 unsigned int num_sectors;
704
705 uint16_t pages_per_sector;
706 uint16_t page_size;
707 uint16_t num_nvmbits;
708
709 at91sam7_info = malloc(sizeof(struct at91sam7_flash_bank));
710 t_bank->driver_priv = at91sam7_info;
711
712 /* part wasn't probed for info yet */
713 at91sam7_info->cidr = 0;
714 at91sam7_info->flashmode = 0;
715 at91sam7_info->ext_freq = 0;
716 at91sam7_info->flash_autodetection = 0;
717
718 if (CMD_ARGC < 13) {
719 at91sam7_info->flash_autodetection = 1;
720 return ERROR_OK;
721 }
722
723 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], base_address);
724
725 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[8], banks_num);
726 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[9], num_sectors);
727 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[10], pages_per_sector);
728 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[11], page_size);
729 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[12], num_nvmbits);
730
731 if (CMD_ARGC == 14) {
732 unsigned long freq;
733 COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[13], freq);
734 ext_freq = freq * 1000;
735 at91sam7_info->ext_freq = ext_freq;
736 }
737
738 if ((banks_num == 0) || (num_sectors == 0) ||
739 (pages_per_sector == 0) || (page_size == 0) || (num_nvmbits == 0)) {
740 at91sam7_info->flash_autodetection = 1;
741 return ERROR_OK;
742 }
743
744 /* calculate bank size */
745 bank_size = num_sectors * pages_per_sector * page_size;
746
747 for (unsigned int bnk = 0; bnk < banks_num; bnk++) {
748 if (bnk > 0) {
749 if (!t_bank->next) {
750 /* create a new bank element */
751 struct flash_bank *fb = calloc(sizeof(struct flash_bank), 1);
752 if (!fb) {
753 LOG_ERROR("No memory for flash bank");
754 return ERROR_FAIL;
755 }
756 fb->target = target;
757 fb->driver = bank->driver;
758 fb->default_padded_value = 0xff;
759 fb->erased_value = 0xff;
760 fb->driver_priv = malloc(sizeof(struct at91sam7_flash_bank));
761 if (!fb->driver_priv) {
762 free(fb);
763 LOG_ERROR("No memory for flash driver priv");
764 return ERROR_FAIL;
765 }
766 fb->name = strdup("sam7_probed");
767
768 /* link created bank in 'flash_banks' list */
769 t_bank->next = fb;
770 }
771 t_bank = t_bank->next;
772 }
773
774 t_bank->bank_number = bnk;
775 t_bank->base = base_address + bnk * bank_size;
776 t_bank->size = bank_size;
777 t_bank->num_sectors = num_sectors;
778
779 /* allocate sectors */
780 t_bank->sectors = malloc(num_sectors * sizeof(struct flash_sector));
781 for (unsigned int sec = 0; sec < num_sectors; sec++) {
782 t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
783 t_bank->sectors[sec].size = pages_per_sector * page_size;
784 t_bank->sectors[sec].is_erased = -1;
785 t_bank->sectors[sec].is_protected = -1;
786 }
787
788 at91sam7_info = t_bank->driver_priv;
789
790 at91sam7_info->target_name = strdup(CMD_ARGV[7]);
791 at91sam7_info->flashmode = 0;
792 at91sam7_info->ext_freq = ext_freq;
793 at91sam7_info->num_nvmbits = num_nvmbits;
794 at91sam7_info->num_nvmbits_on = 0;
795 at91sam7_info->pagesize = page_size;
796 at91sam7_info->pages_per_sector = pages_per_sector;
797 }
798
799 return ERROR_OK;
800 }
801
802 static int at91sam7_erase(struct flash_bank *bank, unsigned int first,
803 unsigned int last)
804 {
805 struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
806 uint32_t nbytes, pos;
807 uint8_t *buffer;
808 uint8_t erase_all;
809
810 if (at91sam7_info->cidr == 0)
811 return ERROR_FLASH_BANK_NOT_PROBED;
812
813 if (bank->target->state != TARGET_HALTED) {
814 LOG_ERROR("Target not halted");
815 return ERROR_TARGET_NOT_HALTED;
816 }
817
818 if ((last < first) || (last >= bank->num_sectors))
819 return ERROR_FLASH_SECTOR_INVALID;
820
821 erase_all = 0;
822 if ((first == 0) && (last == (bank->num_sectors-1)))
823 erase_all = 1;
824
825 /* Configure the flash controller timing */
826 at91sam7_read_clock_info(bank);
827 at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
828
829 if (erase_all) {
830 if (at91sam7_flash_command(bank, EA, 0) != ERROR_OK)
831 return ERROR_FLASH_OPERATION_FAILED;
832 } else {
833 /* allocate and clean buffer */
834 nbytes = (last - first + 1) * bank->sectors[first].size;
835 buffer = malloc(nbytes * sizeof(uint8_t));
836 for (pos = 0; pos < nbytes; pos++)
837 buffer[pos] = 0xFF;
838
839 if (at91sam7_write(bank, buffer, bank->sectors[first].offset, nbytes) != ERROR_OK) {
840 free(buffer);
841 return ERROR_FLASH_OPERATION_FAILED;
842 }
843
844 free(buffer);
845 }
846
847 /* mark erased sectors */
848 for (unsigned int sec = first; sec <= last; sec++)
849 bank->sectors[sec].is_erased = 1;
850
851 return ERROR_OK;
852 }
853
854 static int at91sam7_protect(struct flash_bank *bank, int set,
855 unsigned int first, unsigned int last)
856 {
857 uint32_t cmd;
858 uint32_t pagen;
859
860 struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
861
862 if (at91sam7_info->cidr == 0)
863 return ERROR_FLASH_BANK_NOT_PROBED;
864
865 if (bank->target->state != TARGET_HALTED) {
866 LOG_ERROR("Target not halted");
867 return ERROR_TARGET_NOT_HALTED;
868 }
869
870 if ((last < first) || (last >= bank->num_sectors))
871 return ERROR_FLASH_SECTOR_INVALID;
872
873 /* Configure the flash controller timing */
874 at91sam7_read_clock_info(bank);
875 at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
876
877 for (unsigned int sector = first; sector <= last; sector++) {
878 if (set)
879 cmd = SLB;
880 else
881 cmd = CLB;
882
883 /* if we lock a page from one sector then entire sector will be locked, also,
884 * if we unlock a page from a locked sector, entire sector will be unlocked */
885 pagen = sector * at91sam7_info->pages_per_sector;
886
887 if (at91sam7_flash_command(bank, cmd, pagen) != ERROR_OK)
888 return ERROR_FLASH_OPERATION_FAILED;
889 }
890
891 at91sam7_protect_check(bank);
892
893 return ERROR_OK;
894 }
895
896 static int at91sam7_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
897 {
898 int retval;
899 struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
900 struct target *target = bank->target;
901 uint32_t dst_min_alignment, wcount, bytes_remaining = count;
902 uint32_t first_page, last_page, pagen, buffer_pos;
903
904 if (at91sam7_info->cidr == 0)
905 return ERROR_FLASH_BANK_NOT_PROBED;
906
907 if (bank->target->state != TARGET_HALTED) {
908 LOG_ERROR("Target not halted");
909 return ERROR_TARGET_NOT_HALTED;
910 }
911
912 if (offset + count > bank->size)
913 return ERROR_FLASH_DST_OUT_OF_BANK;
914
915 dst_min_alignment = at91sam7_info->pagesize;
916
917 if (offset % dst_min_alignment) {
918 LOG_WARNING("offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32 "",
919 offset,
920 dst_min_alignment);
921 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
922 }
923
924 if (at91sam7_info->cidr_arch == 0)
925 return ERROR_FLASH_BANK_NOT_PROBED;
926
927 first_page = offset/dst_min_alignment;
928 last_page = DIV_ROUND_UP(offset + count, dst_min_alignment);
929
930 LOG_DEBUG("first_page: %i, last_page: %i, count %i",
931 (int)first_page,
932 (int)last_page,
933 (int)count);
934
935 /* Configure the flash controller timing */
936 at91sam7_read_clock_info(bank);
937 at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
938
939 for (pagen = first_page; pagen < last_page; pagen++) {
940 if (bytes_remaining < dst_min_alignment)
941 count = bytes_remaining;
942 else
943 count = dst_min_alignment;
944 bytes_remaining -= count;
945
946 /* Write one block to the PageWriteBuffer */
947 buffer_pos = (pagen-first_page)*dst_min_alignment;
948 wcount = DIV_ROUND_UP(count, 4);
949 retval = target_write_memory(target, bank->base + pagen*dst_min_alignment, 4,
950 wcount, buffer + buffer_pos);
951 if (retval != ERROR_OK)
952 return retval;
953
954 /* Send Write Page command to Flash Controller */
955 if (at91sam7_flash_command(bank, WP, pagen) != ERROR_OK)
956 return ERROR_FLASH_OPERATION_FAILED;
957 LOG_DEBUG("Write flash bank:%u page number:%" PRIu32, bank->bank_number, pagen);
958 }
959
960 return ERROR_OK;
961 }
962
963 static int at91sam7_probe(struct flash_bank *bank)
964 {
965 /* we can't probe on an at91sam7
966 * if this is an at91sam7, it has the configured flash */
967 int retval;
968
969 if (bank->target->state != TARGET_HALTED) {
970 LOG_ERROR("Target not halted");
971 return ERROR_TARGET_NOT_HALTED;
972 }
973
974 retval = at91sam7_read_part_info(bank);
975 if (retval != ERROR_OK)
976 return retval;
977
978 return ERROR_OK;
979 }
980
981 static int get_at91sam7_info(struct flash_bank *bank, struct command_invocation *cmd)
982 {
983 struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
984
985 if (at91sam7_info->cidr == 0)
986 return ERROR_FLASH_BANK_NOT_PROBED;
987
988 command_print_sameline(cmd, "\n at91sam7 driver information: Chip is %s\n",
989 at91sam7_info->target_name);
990
991 command_print_sameline(cmd,
992 " Cidr: 0x%8.8" PRIx32 " | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | "
993 "Flashsize: 0x%8.8" PRIx32 "\n",
994 at91sam7_info->cidr,
995 at91sam7_info->cidr_arch,
996 eproc[at91sam7_info->cidr_eproc],
997 at91sam7_info->cidr_version,
998 bank->size);
999
1000 command_print_sameline(cmd,
1001 " Master clock (estimated): %u kHz | External clock: %u kHz\n",
1002 (unsigned)(at91sam7_info->mck_freq / 1000),
1003 (unsigned)(at91sam7_info->ext_freq / 1000));
1004
1005 command_print_sameline(cmd,
1006 " Pagesize: %i bytes | Lockbits(%u): %i 0x%4.4x | Pages in lock region: %i\n",
1007 at91sam7_info->pagesize,
1008 bank->num_sectors,
1009 at91sam7_info->num_lockbits_on,
1010 at91sam7_info->lockbits,
1011 at91sam7_info->pages_per_sector * at91sam7_info->num_lockbits_on);
1012
1013 command_print_sameline(cmd, " Securitybit: %i | Nvmbits(%i): %i 0x%1.1x\n",
1014 at91sam7_info->securitybit, at91sam7_info->num_nvmbits,
1015 at91sam7_info->num_nvmbits_on, at91sam7_info->nvmbits);
1016
1017 return ERROR_OK;
1018 }
1019
1020 /*
1021 * On AT91SAM7S: When the gpnvm bits are set with
1022 * > at91sam7 gpnvm bitnr set
1023 * the changes are not visible in the flash controller status register MC_FSR
1024 * until the processor has been reset.
1025 * On the Olimex board this requires a power cycle.
1026 * Note that the AT91SAM7S has the following errata (doc6175.pdf sec 14.1.3):
1027 * The maximum number of write/erase cycles for Non volatile Memory bits is 100. this includes
1028 * Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
1029 */
1030 COMMAND_HANDLER(at91sam7_handle_gpnvm_command)
1031 {
1032 struct flash_bank *bank;
1033 int bit;
1034 uint8_t flashcmd;
1035 uint32_t status;
1036 struct at91sam7_flash_bank *at91sam7_info;
1037 int retval;
1038
1039 if (CMD_ARGC != 2)
1040 return ERROR_COMMAND_SYNTAX_ERROR;
1041
1042 bank = get_flash_bank_by_num_noprobe(0);
1043 if (!bank)
1044 return ERROR_FLASH_BANK_INVALID;
1045 if (strcmp(bank->driver->name, "at91sam7")) {
1046 command_print(CMD, "not an at91sam7 flash bank '%s'", CMD_ARGV[0]);
1047 return ERROR_FLASH_BANK_INVALID;
1048 }
1049 if (bank->target->state != TARGET_HALTED) {
1050 LOG_ERROR("target has to be halted to perform flash operation");
1051 return ERROR_TARGET_NOT_HALTED;
1052 }
1053
1054 if (strcmp(CMD_ARGV[1], "set") == 0)
1055 flashcmd = SGPB;
1056 else if (strcmp(CMD_ARGV[1], "clear") == 0)
1057 flashcmd = CGPB;
1058 else
1059 return ERROR_COMMAND_SYNTAX_ERROR;
1060
1061 at91sam7_info = bank->driver_priv;
1062 if (at91sam7_info->cidr == 0) {
1063 retval = at91sam7_read_part_info(bank);
1064 if (retval != ERROR_OK)
1065 return retval;
1066 }
1067
1068 COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], bit);
1069 if ((bit < 0) || (bit >= at91sam7_info->num_nvmbits)) {
1070 command_print(CMD,
1071 "gpnvm bit '#%s' is out of bounds for target %s",
1072 CMD_ARGV[0],
1073 at91sam7_info->target_name);
1074 return ERROR_OK;
1075 }
1076
1077 /* Configure the flash controller timing */
1078 at91sam7_read_clock_info(bank);
1079 at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
1080
1081 if (at91sam7_flash_command(bank, flashcmd, bit) != ERROR_OK)
1082 return ERROR_FLASH_OPERATION_FAILED;
1083
1084 /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
1085 status = at91sam7_get_flash_status(bank->target, 0);
1086 LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value %d, status 0x%" PRIx32,
1087 flashcmd,
1088 bit,
1089 status);
1090
1091 /* check protect state */
1092 at91sam7_protect_check(bank);
1093
1094 return ERROR_OK;
1095 }
1096
1097 static const struct command_registration at91sam7_exec_command_handlers[] = {
1098 {
1099 .name = "gpnvm",
1100 .handler = at91sam7_handle_gpnvm_command,
1101 .mode = COMMAND_EXEC,
1102 .help = "set or clear one General Purpose Non-Volatile Memory "
1103 "(gpnvm) bit",
1104 .usage = "bitnum ('set'|'clear')",
1105 },
1106 COMMAND_REGISTRATION_DONE
1107 };
1108 static const struct command_registration at91sam7_command_handlers[] = {
1109 {
1110 .name = "at91sam7",
1111 .mode = COMMAND_ANY,
1112 .help = "at91sam7 flash command group",
1113 .usage = "",
1114 .chain = at91sam7_exec_command_handlers,
1115 },
1116 COMMAND_REGISTRATION_DONE
1117 };
1118
1119 const struct flash_driver at91sam7_flash = {
1120 .name = "at91sam7",
1121 .usage = "gpnvm <bit> <set | clear>",
1122 .commands = at91sam7_command_handlers,
1123 .flash_bank_command = at91sam7_flash_bank_command,
1124 .erase = at91sam7_erase,
1125 .protect = at91sam7_protect,
1126 .write = at91sam7_write,
1127 .read = default_flash_read,
1128 .probe = at91sam7_probe,
1129 .auto_probe = at91sam7_probe,
1130 .erase_check = at91sam7_erase_check,
1131 .protect_check = at91sam7_protect_check,
1132 .info = get_at91sam7_info,
1133 };
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