Code Review / openocd.git / blob
? search:


d73a4916fac1d2ebaf4147302dff9b533c823285
[openocd.git] / src / flash / nor / ath79.c
1 /***************************************************************************
2 * Copyright (C) 2015 by Tobias Diedrich *
3 * <ranma+openwrt@tdiedrich.de> *
4 * *
5 * based on the stmsmi code written by Antonio Borneo *
6 * <borneo.antonio@gmail.com> *
7 * *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
12 * *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
17 * *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc. *
21 * *
22 ***************************************************************************/
23 /*
24 * Driver for the Atheros AR7xxx/AR9xxx SPI flash interface.
25 *
26 * Since no SPI mode register is present, presumably only
27 * SPI "mode 3" (CPOL=1 and CPHA=1) is supported.
28 *
29 * The SPI interface supports up to 3 chip selects, however the SPI flash
30 * used for booting the system must be connected to CS0.
31 *
32 * On boot, the first 4MiB of flash space are memory-mapped into the
33 * area bf000000 - bfffffff (4 copies), so the MIPS bootstrap
34 * vector bfc00000 is mapped to the beginning of the flash.
35 *
36 * By writing a 1 to the REMAP_DISABLE bit in the SPI_CONTROL register,
37 * the full area of 16MiB is mapped.
38 *
39 * By writing a 0 to the SPI_FUNCTION_SELECT register (write-only dword
40 * register @bf000000), memory mapping is disabled and the SPI registers
41 * are exposed to the CPU instead:
42 * bf000000 SPI_FUNCTION_SELECT
43 * bf000004 SPI_CONTROL
44 * bf000008 SPI_IO_CONTROL
45 * bf00000c SPI_READ_DATA
46 *
47 * When not memory-mapped, the SPI interface is essentially bitbanged
48 * using SPI_CONTROL and SPI_IO_CONTROL with the only hardware-assistance
49 * being the 32bit read-only shift-register SPI_READ_DATA.
50 */
51
52 #ifdef HAVE_CONFIG_H
53 #include "config.h"
54 #endif
55
56 #include "imp.h"
57 #include "spi.h"
58 #include <jtag/jtag.h>
59 #include <helper/time_support.h>
60 #include <helper/types.h>
61 #include <target/mips32.h>
62 #include <target/mips32_pracc.h>
63 #include <target/target.h>
64
65 #define BITS_PER_BYTE 8
66
67 #define ATH79_REG_FS 0
68 #define ATH79_REG_CLOCK 4
69 #define ATH79_REG_WRITE 8
70 #define ATH79_REG_DATA 12
71
72 #define ATH79_SPI_CS_ALLHI 0x70000
73 #define ATH79_SPI_CS0_HI 0x10000
74 #define ATH79_SPI_CS1_HI 0x20000
75 #define ATH79_SPI_CS2_HI 0x40000
76 #define ATH79_SPI_CE_HI 0x00100
77 #define ATH79_SPI_DO_HI 0x00001
78
79 #define ATH79_XFER_FINAL 0x00000001
80 #define ATH79_XFER_PARTIAL 0x00000000
81
82 /* Timeout in ms */
83 #define ATH79_MAX_TIMEOUT (3000)
84
85 struct ath79_spi_ctx {
86 uint8_t *page_buf;
87 int pre_deselect;
88 int post_deselect;
89 };
90
91 struct ath79_flash_bank {
92 int probed;
93 int chipselect;
94 uint32_t io_base;
95 const struct flash_device *dev;
96 struct ath79_spi_ctx spi;
97 };
98
99 struct ath79_target {
100 char *name;
101 uint32_t tap_idcode;
102 uint32_t io_base;
103 };
104
105 static const struct ath79_target target_devices[] = {
106 /* name, tap_idcode, io_base */
107 { "ATH79", 0x00000001, 0xbf000000 },
108 { NULL, 0, 0 }
109 };
110
111 static const uint32_t ath79_chipselects[] = {
112 (~ATH79_SPI_CS0_HI & ATH79_SPI_CS_ALLHI),
113 (~ATH79_SPI_CS1_HI & ATH79_SPI_CS_ALLHI),
114 (~ATH79_SPI_CS2_HI & ATH79_SPI_CS_ALLHI),
115 };
116
117 static void ath79_pracc_addn(struct pracc_queue_info *ctx,
118 const uint32_t *instr,
119 int n)
120 {
121 for (int i = 0; i < n; i++)
122 pracc_add(ctx, 0, instr[i]);
123 }
124
125 static int ath79_spi_bitbang_codegen(struct ath79_flash_bank *ath79_info,
126 struct pracc_queue_info *ctx,
127 uint8_t *data, int len,
128 int partial_xfer)
129 {
130 uint32_t cs_high = ATH79_SPI_CS_ALLHI;
131 uint32_t cs_low = ath79_chipselects[ath79_info->chipselect];
132 uint32_t clock_high = cs_low | ATH79_SPI_CE_HI;
133 uint32_t clock_low = cs_low;
134 uint32_t pracc_out = 0;
135 uint32_t io_base = ath79_info->io_base;
136
137 const uint32_t preamble1[] = {
138 /* $15 = MIPS32_PRACC_BASE_ADDR */
139 MIPS32_LUI(0, 15, PRACC_UPPER_BASE_ADDR),
140 /* $1 = io_base */
141 MIPS32_LUI(0, 1, UPPER16(io_base)),
142 };
143 ath79_pracc_addn(ctx, preamble1, ARRAY_SIZE(preamble1));
144 if (ath79_info->spi.pre_deselect) {
145 /* Clear deselect flag so we don't deselect again if
146 * this is a partial xfer.
147 */
148 ath79_info->spi.pre_deselect = 0;
149 const uint32_t pre_deselect[] = {
150 /* [$1 + FS] = 1 (enable flash io register access) */
151 MIPS32_LUI(0, 2, UPPER16(1)),
152 MIPS32_ORI(0, 2, 2, LOWER16(1)),
153 MIPS32_SW(0, 2, ATH79_REG_FS, 1),
154 /* deselect flash just in case */
155 /* $2 = SPI_CS_DIS */
156 MIPS32_LUI(0, 2, UPPER16(cs_high)),
157 MIPS32_ORI(0, 2, 2, LOWER16(cs_high)),
158 /* [$1 + WRITE] = $2 */
159 MIPS32_SW(0, 2, ATH79_REG_WRITE, 1),
160 };
161 ath79_pracc_addn(ctx, pre_deselect, ARRAY_SIZE(pre_deselect));
162 }
163 const uint32_t preamble2[] = {
164 /* t0 = CLOCK_LOW + 0-bit */
165 MIPS32_LUI(0, 8, UPPER16((clock_low + 0))),
166 MIPS32_ORI(0, 8, 8, LOWER16((clock_low + 0))),
167 /* t1 = CLOCK_LOW + 1-bit */
168 MIPS32_LUI(0, 9, UPPER16((clock_low + 1))),
169 MIPS32_ORI(0, 9, 9, LOWER16((clock_low + 1))),
170 /* t2 = CLOCK_HIGH + 0-bit */
171 MIPS32_LUI(0, 10, UPPER16((clock_high + 0))),
172 MIPS32_ORI(0, 10, 10, LOWER16((clock_high + 0))),
173 /* t3 = CLOCK_HIGH + 1-bit */
174 MIPS32_LUI(0, 11, UPPER16((clock_high + 1))),
175 MIPS32_ORI(0, 11, 11, LOWER16((clock_high + 1))),
176 };
177 ath79_pracc_addn(ctx, preamble2, ARRAY_SIZE(preamble2));
178
179 for (int i = 0; i < len; i++) {
180 uint8_t x = data[i];
181
182 /* Generate bitbang code for one byte, highest bit first .*/
183 for (int j = BITS_PER_BYTE - 1; j >= 0; j--) {
184 int bit = ((x >> j) & 1);
185
186 if (bit) {
187 /* [$1 + WRITE] = t1 */
188 pracc_add(ctx, 0,
189 MIPS32_SW(0, 9, ATH79_REG_WRITE, 1));
190 /* [$1 + WRITE] = t3 */
191 pracc_add(ctx, 0,
192 MIPS32_SW(0, 11, ATH79_REG_WRITE, 1));
193 } else {
194 /* [$1 + WRITE] = t0 */
195 pracc_add(ctx, 0,
196 MIPS32_SW(0, 8, ATH79_REG_WRITE, 1));
197 /* [$1 + WRITE] = t2 */
198 pracc_add(ctx, 0,
199 MIPS32_SW(0, 10, ATH79_REG_WRITE, 1));
200 }
201 }
202 if (i % 4 == 3) {
203 /* $3 = [$1 + DATA] */
204 pracc_add(ctx, 0, MIPS32_LW(0, 3, ATH79_REG_DATA, 1));
205 /* [OUTi] = $3 */
206 pracc_add(ctx, MIPS32_PRACC_PARAM_OUT + pracc_out,
207 MIPS32_SW(0, 3, PRACC_OUT_OFFSET +
208 pracc_out, 15));
209 pracc_out += 4;
210 }
211 }
212 if (len & 3) { /* not a multiple of 4 bytes */
213 /* $3 = [$1 + DATA] */
214 pracc_add(ctx, 0, MIPS32_LW(0, 3, ATH79_REG_DATA, 1));
215 /* [OUTi] = $3 */
216 pracc_add(ctx, MIPS32_PRACC_PARAM_OUT + pracc_out,
217 MIPS32_SW(0, 3, PRACC_OUT_OFFSET + pracc_out, 15));
218 pracc_out += 4;
219 }
220
221 if (ath79_info->spi.post_deselect && !partial_xfer) {
222 const uint32_t post_deselect[] = {
223 /* $2 = SPI_CS_DIS */
224 MIPS32_LUI(0, 2, UPPER16(cs_high)),
225 MIPS32_ORI(0, 2, 2, LOWER16(cs_high)),
226 /* [$1 + WRITE] = $2 */
227 MIPS32_SW(0, 2, ATH79_REG_WRITE, 1),
228
229 /* [$1 + FS] = 0 (disable flash io register access) */
230 MIPS32_XORI(0, 2, 2, 0),
231 MIPS32_SW(0, 2, ATH79_REG_FS, 1),
232 };
233 ath79_pracc_addn(ctx, post_deselect, ARRAY_SIZE(post_deselect));
234 }
235
236 /* common pracc epilogue */
237 /* jump to start */
238 pracc_add(ctx, 0, MIPS32_B(0, NEG16(ctx->code_count + 1)));
239 /* restore $15 from DeSave */
240 pracc_add(ctx, 0, MIPS32_MFC0(0, 15, 31, 0));
241
242 return pracc_out / 4;
243 }
244
245 static int ath79_spi_bitbang_chunk(struct flash_bank *bank,
246 uint8_t *data, int len, int *transferred)
247 {
248 struct target *target = bank->target;
249 struct ath79_flash_bank *ath79_info = bank->driver_priv;
250 struct mips32_common *mips32 = target_to_mips32(target);
251 struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
252 int pracc_words;
253
254 /*
255 * These constants must match the worst case in the above code
256 * generator function ath79_spi_bitbang_codegen.
257 */
258 const int pracc_pre_post = 26;
259 const int pracc_loop_byte = 8 * 2 + 2;
260
261 struct pracc_queue_info ctx = {
262 .ejtag_info = ejtag_info
263 };
264 int max_len = (PRACC_MAX_INSTRUCTIONS - pracc_pre_post) / pracc_loop_byte;
265 int to_xfer = len > max_len ? max_len : len;
266 int partial_xfer = len != to_xfer;
267 int padded_len = (to_xfer + 3) & ~3;
268 uint32_t *out = malloc(padded_len);
269
270 if (!out) {
271 LOG_ERROR("not enough memory");
272 return ERROR_FAIL;
273 }
274
275 *transferred = 0;
276 pracc_queue_init(&ctx);
277
278 LOG_DEBUG("ath79_spi_bitbang_bytes(%p, %08x, %p, %d)",
279 target, ath79_info->io_base, data, len);
280
281 LOG_DEBUG("max code %d => max len %d. to_xfer %d",
282 PRACC_MAX_INSTRUCTIONS, max_len, to_xfer);
283
284 pracc_words = ath79_spi_bitbang_codegen(
285 ath79_info, &ctx, data, to_xfer, partial_xfer);
286
287 LOG_DEBUG("Assembled %d instructions, %d stores",
288 ctx.code_count, ctx.store_count);
289
290 ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, out, 1);
291 if (ctx.retval != ERROR_OK)
292 goto exit;
293
294 if (to_xfer & 3) { /* Not a multiple of 4 bytes. */
295 /*
296 * Need to realign last word since we didn't shift the
297 * full 32 bits.
298 */
299 int missed_bytes = 4 - (to_xfer & 3);
300
301 out[pracc_words - 1] <<= BITS_PER_BYTE * missed_bytes;
302 }
303
304 /*
305 * pracc reads return uint32_t in host endianness, convert to
306 * target endianness.
307 * Since we know the ATH79 target is big endian and the SPI
308 * shift register has the bytes in highest to lowest bit order,
309 * this will ensure correct memory byte order regardless of host
310 * endianness.
311 */
312 target_buffer_set_u32_array(target, (uint8_t *)out, pracc_words, out);
313
314 if (LOG_LEVEL_IS(LOG_LVL_DEBUG)) {
315 for (int i = 0; i < to_xfer; i++) {
316 LOG_DEBUG("bitbang %02x => %02x",
317 data[i], ((uint8_t *)out)[i]);
318 }
319 }
320 memcpy(data, out, to_xfer);
321 *transferred = to_xfer;
322
323 exit:
324 pracc_queue_free(&ctx);
325 free(out);
326 return ctx.retval;
327 }
328
329 static void ath79_spi_bitbang_prepare(struct flash_bank *bank)
330 {
331 struct ath79_flash_bank *ath79_info = bank->driver_priv;
332
333 ath79_info->spi.pre_deselect = 1;
334 }
335
336 static int ath79_spi_bitbang_bytes(struct flash_bank *bank,
337 uint8_t *data, int len, uint32_t flags)
338 {
339 struct ath79_flash_bank *ath79_info = bank->driver_priv;
340 int retval;
341 int transferred;
342
343 ath79_info->spi.post_deselect = !!(flags & ATH79_XFER_FINAL);
344
345 do {
346 transferred = 0;
347 retval = ath79_spi_bitbang_chunk(
348 bank, data, len, &transferred);
349 if (retval != ERROR_OK)
350 return retval;
351
352 data += transferred;
353 len -= transferred;
354 } while (len > 0);
355
356 return ERROR_OK;
357 }
358
359 FLASH_BANK_COMMAND_HANDLER(ath79_flash_bank_command)
360 {
361 struct ath79_flash_bank *ath79_info;
362 int chipselect = 0;
363
364 LOG_DEBUG("%s", __func__);
365
366 if (CMD_ARGC < 6 || CMD_ARGC > 7)
367 return ERROR_COMMAND_SYNTAX_ERROR;
368
369 if (CMD_ARGC == 7) {
370 if (strcmp(CMD_ARGV[6], "cs0") == 0)
371 chipselect = 0; /* default */
372 else if (strcmp(CMD_ARGV[6], "cs1") == 0)
373 chipselect = 1;
374 else if (strcmp(CMD_ARGV[6], "cs2") == 0)
375 chipselect = 2;
376 else {
377 LOG_ERROR("Unknown arg: %s", CMD_ARGV[6]);
378 return ERROR_COMMAND_SYNTAX_ERROR;
379 }
380 }
381
382 ath79_info = calloc(1, sizeof(struct ath79_flash_bank));
383 if (!ath79_info) {
384 LOG_ERROR("not enough memory");
385 return ERROR_FAIL;
386 }
387
388 ath79_info->chipselect = chipselect;
389 bank->driver_priv = ath79_info;
390
391 return ERROR_OK;
392 }
393
394 /* Read the status register of the external SPI flash chip. */
395 static int read_status_reg(struct flash_bank *bank, uint32_t *status)
396 {
397 uint8_t spi_bytes[] = {SPIFLASH_READ_STATUS, 0};
398 int retval;
399
400 /* Send SPI command "read STATUS" */
401 ath79_spi_bitbang_prepare(bank);
402 retval = ath79_spi_bitbang_bytes(
403 bank, spi_bytes, sizeof(spi_bytes),
404 ATH79_XFER_FINAL);
405
406 *status = spi_bytes[1];
407
408 return retval;
409 }
410
411 /* check for WIP (write in progress) bit in status register */
412 /* timeout in ms */
413 static int wait_till_ready(struct flash_bank *bank, int timeout)
414 {
415 uint32_t status;
416 int retval;
417 long long endtime;
418
419 endtime = timeval_ms() + timeout;
420 do {
421 /* read flash status register */
422 retval = read_status_reg(bank, &status);
423 if (retval != ERROR_OK)
424 return retval;
425
426 if ((status & SPIFLASH_BSY_BIT) == 0)
427 return ERROR_OK;
428 alive_sleep(1);
429 } while (timeval_ms() < endtime);
430
431 LOG_ERROR("timeout");
432 return ERROR_FAIL;
433 }
434
435 /* Send "write enable" command to SPI flash chip. */
436 static int ath79_write_enable(struct flash_bank *bank)
437 {
438 uint32_t status;
439 int retval;
440
441 uint8_t spi_bytes[] = {SPIFLASH_WRITE_ENABLE};
442
443 /* Send SPI command "write enable" */
444 ath79_spi_bitbang_prepare(bank);
445 retval = ath79_spi_bitbang_bytes(
446 bank, spi_bytes, sizeof(spi_bytes),
447 ATH79_XFER_FINAL);
448 if (retval != ERROR_OK)
449 return retval;
450
451 /* read flash status register */
452 retval = read_status_reg(bank, &status);
453 if (retval != ERROR_OK)
454 return retval;
455
456 /* Check write enabled */
457 if ((status & SPIFLASH_WE_BIT) == 0) {
458 LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32,
459 status);
460 return ERROR_FAIL;
461 }
462
463 return ERROR_OK;
464 }
465
466 static int erase_command(struct flash_bank *bank, int sector)
467 {
468 struct ath79_flash_bank *ath79_info = bank->driver_priv;
469 uint32_t offset = bank->sectors[sector].offset;
470
471 uint8_t spi_bytes[] = {
472 ath79_info->dev->erase_cmd,
473 offset >> 16,
474 offset >> 8,
475 offset
476 };
477
478 /* bitbang command */
479 ath79_spi_bitbang_prepare(bank);
480 return ath79_spi_bitbang_bytes(
481 bank, spi_bytes, sizeof(spi_bytes),
482 ATH79_XFER_FINAL);
483 }
484
485 static int ath79_erase_sector(struct flash_bank *bank, int sector)
486 {
487 int retval = ath79_write_enable(bank);
488
489 if (retval != ERROR_OK)
490 return retval;
491
492 /* send SPI command "block erase" */
493 retval = erase_command(bank, sector);
494 if (retval != ERROR_OK)
495 return retval;
496
497 /* poll WIP for end of self timed Sector Erase cycle */
498 return wait_till_ready(bank, ATH79_MAX_TIMEOUT);
499 }
500
501 static int ath79_erase(struct flash_bank *bank, int first, int last)
502 {
503 struct target *target = bank->target;
504 struct ath79_flash_bank *ath79_info = bank->driver_priv;
505 int retval = ERROR_OK;
506 int sector;
507
508 LOG_DEBUG("%s: from sector %d to sector %d", __func__, first, last);
509
510 if (target->state != TARGET_HALTED) {
511 LOG_ERROR("Target not halted");
512 return ERROR_TARGET_NOT_HALTED;
513 }
514
515 if ((first < 0) || (last < first) || (last >= bank->num_sectors)) {
516 LOG_ERROR("Flash sector invalid");
517 return ERROR_FLASH_SECTOR_INVALID;
518 }
519
520 if (!ath79_info->probed) {
521 LOG_ERROR("Flash bank not probed");
522 return ERROR_FLASH_BANK_NOT_PROBED;
523 }
524
525 if (ath79_info->dev->erase_cmd == 0x00)
526 return ERROR_FLASH_OPER_UNSUPPORTED;
527
528 for (sector = first; sector <= last; sector++) {
529 if (bank->sectors[sector].is_protected) {
530 LOG_ERROR("Flash sector %d protected", sector);
531 return ERROR_FAIL;
532 }
533 }
534
535 for (sector = first; sector <= last; sector++) {
536 retval = ath79_erase_sector(bank, sector);
537 if (retval != ERROR_OK)
538 break;
539 keep_alive();
540 }
541
542 return retval;
543 }
544
545 static int ath79_protect(struct flash_bank *bank, int set,
546 int first, int last)
547 {
548 int sector;
549
550 for (sector = first; sector <= last; sector++)
551 bank->sectors[sector].is_protected = set;
552 return ERROR_OK;
553 }
554
555 static int ath79_write_page(struct flash_bank *bank, const uint8_t *buffer,
556 uint32_t address, uint32_t len)
557 {
558 struct ath79_flash_bank *ath79_info = bank->driver_priv;
559 uint8_t spi_bytes[] = {
560 SPIFLASH_PAGE_PROGRAM,
561 address >> 16,
562 address >> 8,
563 address,
564 };
565 int retval;
566 uint32_t i, pagesize;
567
568 /* if no write pagesize, use reasonable default */
569 pagesize = ath79_info->dev->pagesize ?
570 ath79_info->dev->pagesize : SPIFLASH_DEF_PAGESIZE;
571
572 if (address & 0xff) {
573 LOG_ERROR("ath79_write_page: unaligned write address: %08x",
574 address);
575 return ERROR_FAIL;
576 }
577 if (!ath79_info->spi.page_buf) {
578 LOG_ERROR("ath79_write_page: page buffer not initialized");
579 return ERROR_FAIL;
580 }
581 if (len > ath79_info->dev->pagesize) {
582 LOG_ERROR("ath79_write_page: len bigger than page size %d: %d",
583 pagesize, len);
584 return ERROR_FAIL;
585 }
586
587 for (i = 0; i < len; i++) {
588 if (buffer[i] != 0xff)
589 break;
590 }
591 if (i == len) /* all 0xff, no need to program. */
592 return ERROR_OK;
593
594 LOG_INFO("writing %d bytes to flash page @0x%08x", len, address);
595
596 memcpy(ath79_info->spi.page_buf, buffer, len);
597
598 /* unlock writes */
599 retval = ath79_write_enable(bank);
600 if (retval != ERROR_OK)
601 return retval;
602
603 /* bitbang command */
604 ath79_spi_bitbang_prepare(bank);
605 retval = ath79_spi_bitbang_bytes(
606 bank, spi_bytes, sizeof(spi_bytes),
607 ATH79_XFER_PARTIAL);
608 if (retval != ERROR_OK)
609 return retval;
610
611 /* write data */
612 return ath79_spi_bitbang_bytes(
613 bank, ath79_info->spi.page_buf, len,
614 ATH79_XFER_FINAL);
615 }
616
617 static int ath79_write_buffer(struct flash_bank *bank, const uint8_t *buffer,
618 uint32_t address, uint32_t len)
619 {
620 struct ath79_flash_bank *ath79_info = bank->driver_priv;
621 uint32_t page_size;
622 int retval;
623
624 LOG_DEBUG("%s: address=0x%08" PRIx32 " len=0x%08" PRIx32,
625 __func__, address, len);
626
627 /* if no valid page_size, use reasonable default */
628 page_size = ath79_info->dev->pagesize ?
629 ath79_info->dev->pagesize : SPIFLASH_DEF_PAGESIZE;
630
631 while (len > 0) {
632 int page_len = len > page_size ? page_size : len;
633
634 retval = ath79_write_page(
635 bank, buffer, address, page_len);
636 if (retval != ERROR_OK)
637 return retval;
638
639 buffer += page_size;
640 address += page_size;
641 len -= page_len;
642 }
643
644 return ERROR_OK;
645 }
646
647 static int ath79_write(struct flash_bank *bank, const uint8_t *buffer,
648 uint32_t offset, uint32_t count)
649 {
650 struct target *target = bank->target;
651 int sector;
652
653 LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
654 __func__, offset, count);
655
656 if (offset < bank->base || offset >= bank->base + bank->size) {
657 LOG_ERROR("Start address out of range");
658 return ERROR_FAIL;
659 }
660
661 offset -= bank->base;
662
663 if (target->state != TARGET_HALTED) {
664 LOG_ERROR("Target not halted");
665 return ERROR_TARGET_NOT_HALTED;
666 }
667
668 if (offset + count > bank->size) {
669 LOG_WARNING("Write pasts end of flash. Extra data discarded.");
670 count = bank->size - offset;
671 }
672
673 /* Check sector protection */
674 for (sector = 0; sector < bank->num_sectors; sector++) {
675 /* Start offset in or before this sector? */
676 /* End offset in or behind this sector? */
677 struct flash_sector *bs = &bank->sectors[sector];
678
679 if ((offset < (bs->offset + bs->size)) &&
680 ((offset + count - 1) >= bs->offset) &&
681 bs->is_protected) {
682 LOG_ERROR("Flash sector %d protected", sector);
683 return ERROR_FAIL;
684 }
685 }
686
687 return ath79_write_buffer(bank, buffer, offset, count);
688 }
689
690 static int ath79_read_buffer(struct flash_bank *bank, uint8_t *buffer,
691 uint32_t address, uint32_t len)
692 {
693 uint8_t spi_bytes[] = {
694 SPIFLASH_READ,
695 address >> 16,
696 address >> 8,
697 address,
698 };
699 int retval;
700
701 LOG_DEBUG("%s: address=0x%08" PRIx32 " len=0x%08" PRIx32,
702 __func__, address, len);
703
704 if (address & 0xff) {
705 LOG_ERROR("ath79_read_buffer: unaligned read address: %08x",
706 address);
707 return ERROR_FAIL;
708 }
709
710 LOG_INFO("reading %d bytes from flash @0x%08x", len, address);
711
712 /* bitbang command */
713 ath79_spi_bitbang_prepare(bank);
714 retval = ath79_spi_bitbang_bytes(
715 bank, spi_bytes, sizeof(spi_bytes), ATH79_XFER_PARTIAL);
716 if (retval != ERROR_OK)
717 return retval;
718
719 /* read data */
720 return ath79_spi_bitbang_bytes(
721 bank, buffer, len, ATH79_XFER_FINAL);
722 }
723
724 static int ath79_read(struct flash_bank *bank, uint8_t *buffer,
725 uint32_t offset, uint32_t count)
726 {
727 struct target *target = bank->target;
728
729 LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
730 __func__, offset, count);
731
732 if (offset < bank->base || offset >= bank->base + bank->size) {
733 LOG_ERROR("Start address out of range");
734 return ERROR_FAIL;
735 }
736
737 offset -= bank->base;
738
739 if (target->state != TARGET_HALTED) {
740 LOG_ERROR("Target not halted");
741 return ERROR_TARGET_NOT_HALTED;
742 }
743
744 if (offset + count > bank->size) {
745 LOG_WARNING("Reads past end of flash. Extra data discarded.");
746 count = bank->size - offset;
747 }
748
749 return ath79_read_buffer(bank, buffer, offset, count);
750 }
751
752 /* Return ID of flash device */
753 static int read_flash_id(struct flash_bank *bank, uint32_t *id)
754 {
755 struct target *target = bank->target;
756 int retval;
757 uint8_t spi_bytes[] = {SPIFLASH_READ_ID, 0, 0, 0};
758
759 if (target->state != TARGET_HALTED) {
760 LOG_ERROR("Target not halted");
761 return ERROR_TARGET_NOT_HALTED;
762 }
763
764 /* Send SPI command "read ID" */
765 ath79_spi_bitbang_prepare(bank);
766 retval = ath79_spi_bitbang_bytes(
767 bank, spi_bytes, sizeof(spi_bytes), ATH79_XFER_FINAL);
768 if (retval != ERROR_OK)
769 return retval;
770
771 *id = (spi_bytes[1] << 0)
772 | (spi_bytes[2] << 8)
773 | (spi_bytes[3] << 16);
774
775 if (*id == 0xffffff) {
776 LOG_ERROR("No SPI flash found");
777 return ERROR_FAIL;
778 }
779
780 return ERROR_OK;
781 }
782
783 static int ath79_probe(struct flash_bank *bank)
784 {
785 struct target *target = bank->target;
786 struct ath79_flash_bank *ath79_info = bank->driver_priv;
787 struct flash_sector *sectors;
788 uint32_t id = 0; /* silence uninitialized warning */
789 uint32_t pagesize, sectorsize;
790 const struct ath79_target *target_device;
791 int retval;
792
793 if (ath79_info->probed) {
794 free(bank->sectors);
795 free(ath79_info->spi.page_buf);
796 }
797 ath79_info->probed = 0;
798
799 for (target_device = target_devices; target_device->name;
800 ++target_device)
801 if (target_device->tap_idcode == target->tap->idcode)
802 break;
803 if (!target_device->name) {
804 LOG_ERROR("Device ID 0x%" PRIx32 " is not known",
805 target->tap->idcode);
806 return ERROR_FAIL;
807 }
808
809 ath79_info->io_base = target_device->io_base;
810
811 LOG_DEBUG("Found device %s at address 0x%" PRIx32,
812 target_device->name, bank->base);
813
814 retval = read_flash_id(bank, &id);
815 if (retval != ERROR_OK)
816 return retval;
817
818 ath79_info->dev = NULL;
819 for (const struct flash_device *p = flash_devices; p->name; p++)
820 if (p->device_id == id) {
821 ath79_info->dev = p;
822 break;
823 }
824
825 if (!ath79_info->dev) {
826 LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", id);
827 return ERROR_FAIL;
828 }
829
830 LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
831 ath79_info->dev->name, ath79_info->dev->device_id);
832
833 /* Set correct size value */
834 bank->size = ath79_info->dev->size_in_bytes;
835 if (bank->size <= (1UL << 16))
836 LOG_WARNING("device needs 2-byte addresses - not implemented");
837 if (bank->size > (1UL << 24))
838 LOG_WARNING("device needs paging or 4-byte addresses - not implemented");
839
840 /* if no sectors, treat whole bank as single sector */
841 sectorsize = ath79_info->dev->sectorsize ?
842 ath79_info->dev->sectorsize : ath79_info->dev->size_in_bytes;
843
844 /* create and fill sectors array */
845 bank->num_sectors = ath79_info->dev->size_in_bytes / sectorsize;
846 sectors = calloc(1, sizeof(struct flash_sector) * bank->num_sectors);
847 if (!sectors) {
848 LOG_ERROR("not enough memory");
849 return ERROR_FAIL;
850 }
851
852 /* if no write pagesize, use reasonable default */
853 pagesize = ath79_info->dev->pagesize ? ath79_info->dev->pagesize : SPIFLASH_DEF_PAGESIZE;
854
855 ath79_info->spi.page_buf = malloc(pagesize);
856 if (!ath79_info->spi.page_buf) {
857 LOG_ERROR("not enough memory");
858 free(sectors);
859 return ERROR_FAIL;
860 }
861
862 for (int sector = 0; sector < bank->num_sectors; sector++) {
863 sectors[sector].offset = sector * sectorsize;
864 sectors[sector].size = sectorsize;
865 sectors[sector].is_erased = 0;
866 sectors[sector].is_protected = 1;
867 }
868
869 bank->sectors = sectors;
870 ath79_info->probed = 1;
871 return ERROR_OK;
872 }
873
874 static int ath79_auto_probe(struct flash_bank *bank)
875 {
876 struct ath79_flash_bank *ath79_info = bank->driver_priv;
877
878 if (ath79_info->probed)
879 return ERROR_OK;
880 return ath79_probe(bank);
881 }
882
883 static int ath79_flash_blank_check(struct flash_bank *bank)
884 {
885 /* Not implemented */
886 return ERROR_OK;
887 }
888
889 static int ath79_protect_check(struct flash_bank *bank)
890 {
891 /* Not implemented */
892 return ERROR_OK;
893 }
894
895 static int get_ath79_info(struct flash_bank *bank, char *buf, int buf_size)
896 {
897 struct ath79_flash_bank *ath79_info = bank->driver_priv;
898
899 if (!ath79_info->probed) {
900 snprintf(buf, buf_size,
901 "\nATH79 flash bank not probed yet\n");
902 return ERROR_OK;
903 }
904
905 snprintf(buf, buf_size, "\nATH79 flash information:\n"
906 " Device \'%s\' (ID 0x%08" PRIx32 ")\n",
907 ath79_info->dev->name, ath79_info->dev->device_id);
908
909 return ERROR_OK;
910 }
911
912 struct flash_driver ath79_flash = {
913 .name = "ath79",
914 .flash_bank_command = ath79_flash_bank_command,
915 .erase = ath79_erase,
916 .protect = ath79_protect,
917 .write = ath79_write,
918 .read = ath79_read,
919 .probe = ath79_probe,
920 .auto_probe = ath79_auto_probe,
921 .erase_check = ath79_flash_blank_check,
922 .protect_check = ath79_protect_check,
923 .info = get_ath79_info,
924 .free_driver_priv = default_flash_free_driver_priv,
925 };
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)