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ARM: rename ARMV4_5_STATE_* as ARM_STATE_*
[openocd.git] / src / flash / nor / cfi.c
1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ***************************************************************************/
22 #ifdef HAVE_CONFIG_H
23 #include "config.h"
24 #endif
25
26 #include "imp.h"
27 #include "cfi.h"
28 #include "non_cfi.h"
29 #include <target/armv4_5.h>
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32
33
34 #define CFI_MAX_BUS_WIDTH 4
35 #define CFI_MAX_CHIP_WIDTH 4
36
37 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
38 #define CFI_MAX_INTEL_CODESIZE 256
39
40 static struct cfi_unlock_addresses cfi_unlock_addresses[] =
41 {
42 [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
43 [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
44 };
45
46 /* CFI fixups foward declarations */
47 static void cfi_fixup_0002_erase_regions(struct flash_bank *flash, void *param);
48 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *flash, void *param);
49 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *flash, void *param);
50
51 /* fixup after reading cmdset 0002 primary query table */
52 static const struct cfi_fixup cfi_0002_fixups[] = {
53 {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
54 {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
55 {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
56 {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
57 {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
58 {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
59 {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
60 {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
61 {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
62 {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
63 {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
64 {0, 0, NULL, NULL}
65 };
66
67 /* fixup after reading cmdset 0001 primary query table */
68 static const struct cfi_fixup cfi_0001_fixups[] = {
69 {0, 0, NULL, NULL}
70 };
71
72 static void cfi_fixup(struct flash_bank *bank, const struct cfi_fixup *fixups)
73 {
74 struct cfi_flash_bank *cfi_info = bank->driver_priv;
75 const struct cfi_fixup *f;
76
77 for (f = fixups; f->fixup; f++)
78 {
79 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
80 ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
81 {
82 f->fixup(bank, f->param);
83 }
84 }
85 }
86
87 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
88 static __inline__ uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset)
89 {
90 struct cfi_flash_bank *cfi_info = bank->driver_priv;
91
92 if (cfi_info->x16_as_x8) offset *= 2;
93
94 /* while the sector list isn't built, only accesses to sector 0 work */
95 if (sector == 0)
96 return bank->base + offset * bank->bus_width;
97 else
98 {
99 if (!bank->sectors)
100 {
101 LOG_ERROR("BUG: sector list not yet built");
102 exit(-1);
103 }
104 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
105 }
106
107 }
108
109 static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
110 {
111 int i;
112
113 /* clear whole buffer, to ensure bits that exceed the bus_width
114 * are set to zero
115 */
116 for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
117 cmd_buf[i] = 0;
118
119 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
120 {
121 for (i = bank->bus_width; i > 0; i--)
122 {
123 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
124 }
125 }
126 else
127 {
128 for (i = 1; i <= bank->bus_width; i++)
129 {
130 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
131 }
132 }
133 }
134
135 /* read unsigned 8-bit value from the bank
136 * flash banks are expected to be made of similar chips
137 * the query result should be the same for all
138 */
139 static uint8_t cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset)
140 {
141 struct target *target = bank->target;
142 uint8_t data[CFI_MAX_BUS_WIDTH];
143
144 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
145
146 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
147 return data[0];
148 else
149 return data[bank->bus_width - 1];
150 }
151
152 /* read unsigned 8-bit value from the bank
153 * in case of a bank made of multiple chips,
154 * the individual values are ORed
155 */
156 static uint8_t cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset)
157 {
158 struct target *target = bank->target;
159 uint8_t data[CFI_MAX_BUS_WIDTH];
160 int i;
161
162 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
163
164 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
165 {
166 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
167 data[0] |= data[i];
168
169 return data[0];
170 }
171 else
172 {
173 uint8_t value = 0;
174 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
175 value |= data[bank->bus_width - 1 - i];
176
177 return value;
178 }
179 }
180
181 static uint16_t cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset)
182 {
183 struct target *target = bank->target;
184 struct cfi_flash_bank *cfi_info = bank->driver_priv;
185 uint8_t data[CFI_MAX_BUS_WIDTH * 2];
186
187 if (cfi_info->x16_as_x8)
188 {
189 uint8_t i;
190 for (i = 0;i < 2;i++)
191 target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
192 &data[i*bank->bus_width]);
193 }
194 else
195 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
196
197 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
198 return data[0] | data[bank->bus_width] << 8;
199 else
200 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
201 }
202
203 static uint32_t cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset)
204 {
205 struct target *target = bank->target;
206 struct cfi_flash_bank *cfi_info = bank->driver_priv;
207 uint8_t data[CFI_MAX_BUS_WIDTH * 4];
208
209 if (cfi_info->x16_as_x8)
210 {
211 uint8_t i;
212 for (i = 0;i < 4;i++)
213 target_read_memory(target, flash_address(bank, sector, offset + i), bank->bus_width, 1,
214 &data[i*bank->bus_width]);
215 }
216 else
217 target_read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
218
219 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
220 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
221 else
222 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
223 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
224 }
225
226 static void cfi_intel_clear_status_register(struct flash_bank *bank)
227 {
228 struct target *target = bank->target;
229 uint8_t command[8];
230
231 if (target->state != TARGET_HALTED)
232 {
233 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
234 exit(-1);
235 }
236
237 cfi_command(bank, 0x50, command);
238 target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
239 }
240
241 uint8_t cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout)
242 {
243 uint8_t status;
244
245 while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
246 {
247 LOG_DEBUG("status: 0x%x", status);
248 alive_sleep(1);
249 }
250
251 /* mask out bit 0 (reserved) */
252 status = status & 0xfe;
253
254 LOG_DEBUG("status: 0x%x", status);
255
256 if ((status & 0x80) != 0x80)
257 {
258 LOG_ERROR("timeout while waiting for WSM to become ready");
259 }
260 else if (status != 0x80)
261 {
262 LOG_ERROR("status register: 0x%x", status);
263 if (status & 0x2)
264 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
265 if (status & 0x4)
266 LOG_ERROR("Program suspended");
267 if (status & 0x8)
268 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
269 if (status & 0x10)
270 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
271 if (status & 0x20)
272 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
273 if (status & 0x40)
274 LOG_ERROR("Block Erase Suspended");
275
276 cfi_intel_clear_status_register(bank);
277 }
278
279 return status;
280 }
281
282 int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
283 {
284 uint8_t status, oldstatus;
285 struct cfi_flash_bank *cfi_info = bank->driver_priv;
286
287 oldstatus = cfi_get_u8(bank, 0, 0x0);
288
289 do {
290 status = cfi_get_u8(bank, 0, 0x0);
291 if ((status ^ oldstatus) & 0x40) {
292 if (status & cfi_info->status_poll_mask & 0x20) {
293 oldstatus = cfi_get_u8(bank, 0, 0x0);
294 status = cfi_get_u8(bank, 0, 0x0);
295 if ((status ^ oldstatus) & 0x40) {
296 LOG_ERROR("dq5 timeout, status: 0x%x", status);
297 return(ERROR_FLASH_OPERATION_FAILED);
298 } else {
299 LOG_DEBUG("status: 0x%x", status);
300 return(ERROR_OK);
301 }
302 }
303 } else { /* no toggle: finished, OK */
304 LOG_DEBUG("status: 0x%x", status);
305 return(ERROR_OK);
306 }
307
308 oldstatus = status;
309 alive_sleep(1);
310 } while (timeout-- > 0);
311
312 LOG_ERROR("timeout, status: 0x%x", status);
313
314 return(ERROR_FLASH_BUSY);
315 }
316
317 static int cfi_read_intel_pri_ext(struct flash_bank *bank)
318 {
319 int retval;
320 struct cfi_flash_bank *cfi_info = bank->driver_priv;
321 struct cfi_intel_pri_ext *pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
322 struct target *target = bank->target;
323 uint8_t command[8];
324
325 cfi_info->pri_ext = pri_ext;
326
327 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
328 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
329 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
330
331 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
332 {
333 cfi_command(bank, 0xf0, command);
334 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
335 {
336 return retval;
337 }
338 cfi_command(bank, 0xff, command);
339 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
340 {
341 return retval;
342 }
343 LOG_ERROR("Could not read bank flash bank information");
344 return ERROR_FLASH_BANK_INVALID;
345 }
346
347 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
348 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
349
350 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
351
352 pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
353 pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
354 pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
355
356 LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
357 pri_ext->feature_support,
358 pri_ext->suspend_cmd_support,
359 pri_ext->blk_status_reg_mask);
360
361 pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
362 pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
363
364 LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
365 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
366 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
367
368 pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
369 if (pri_ext->num_protection_fields != 1)
370 {
371 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
372 }
373
374 pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
375 pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
376 pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
377
378 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
379
380 return ERROR_OK;
381 }
382
383 static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
384 {
385 int retval;
386 struct cfi_flash_bank *cfi_info = bank->driver_priv;
387 struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
388 struct target *target = bank->target;
389 uint8_t command[8];
390
391 cfi_info->pri_ext = pri_ext;
392
393 pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
394 pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
395 pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
396
397 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
398 {
399 cfi_command(bank, 0xf0, command);
400 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
401 {
402 return retval;
403 }
404 LOG_ERROR("Could not read spansion bank information");
405 return ERROR_FLASH_BANK_INVALID;
406 }
407
408 pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
409 pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
410
411 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
412
413 pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
414 pri_ext->EraseSuspend = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
415 pri_ext->BlkProt = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
416 pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
417 pri_ext->BlkProtUnprot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
418 pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
419 pri_ext->BurstMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
420 pri_ext->PageMode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
421 pri_ext->VppMin = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
422 pri_ext->VppMax = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
423 pri_ext->TopBottom = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
424
425 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
426 pri_ext->EraseSuspend, pri_ext->BlkProt);
427
428 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
429 pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
430
431 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
432
433
434 LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
435 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
436 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
437
438 LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
439
440 /* default values for implementation specific workarounds */
441 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
442 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
443 pri_ext->_reversed_geometry = 0;
444
445 return ERROR_OK;
446 }
447
448 static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
449 {
450 int retval;
451 struct cfi_atmel_pri_ext atmel_pri_ext;
452 struct cfi_flash_bank *cfi_info = bank->driver_priv;
453 struct cfi_spansion_pri_ext *pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
454 struct target *target = bank->target;
455 uint8_t command[8];
456
457 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
458 * but a different primary extended query table.
459 * We read the atmel table, and prepare a valid AMD/Spansion query table.
460 */
461
462 memset(pri_ext, 0, sizeof(struct cfi_spansion_pri_ext));
463
464 cfi_info->pri_ext = pri_ext;
465
466 atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
467 atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
468 atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
469
470 if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
471 {
472 cfi_command(bank, 0xf0, command);
473 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
474 {
475 return retval;
476 }
477 LOG_ERROR("Could not read atmel bank information");
478 return ERROR_FLASH_BANK_INVALID;
479 }
480
481 pri_ext->pri[0] = atmel_pri_ext.pri[0];
482 pri_ext->pri[1] = atmel_pri_ext.pri[1];
483 pri_ext->pri[2] = atmel_pri_ext.pri[2];
484
485 atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
486 atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
487
488 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
489
490 pri_ext->major_version = atmel_pri_ext.major_version;
491 pri_ext->minor_version = atmel_pri_ext.minor_version;
492
493 atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
494 atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
495 atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
496 atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
497
498 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
499 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
500
501 if (atmel_pri_ext.features & 0x02)
502 pri_ext->EraseSuspend = 2;
503
504 if (atmel_pri_ext.bottom_boot)
505 pri_ext->TopBottom = 2;
506 else
507 pri_ext->TopBottom = 3;
508
509 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
510 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
511
512 return ERROR_OK;
513 }
514
515 static int cfi_read_0002_pri_ext(struct flash_bank *bank)
516 {
517 struct cfi_flash_bank *cfi_info = bank->driver_priv;
518
519 if (cfi_info->manufacturer == CFI_MFR_ATMEL)
520 {
521 return cfi_read_atmel_pri_ext(bank);
522 }
523 else
524 {
525 return cfi_read_spansion_pri_ext(bank);
526 }
527 }
528
529 static int cfi_spansion_info(struct flash_bank *bank, char *buf, int buf_size)
530 {
531 int printed;
532 struct cfi_flash_bank *cfi_info = bank->driver_priv;
533 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
534
535 printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
536 buf += printed;
537 buf_size -= printed;
538
539 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
540 pri_ext->pri[1], pri_ext->pri[2],
541 pri_ext->major_version, pri_ext->minor_version);
542 buf += printed;
543 buf_size -= printed;
544
545 printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
546 (pri_ext->SiliconRevision) >> 2,
547 (pri_ext->SiliconRevision) & 0x03);
548 buf += printed;
549 buf_size -= printed;
550
551 printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
552 pri_ext->EraseSuspend,
553 pri_ext->BlkProt);
554 buf += printed;
555 buf_size -= printed;
556
557 printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
558 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
559 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
560
561 return ERROR_OK;
562 }
563
564 static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size)
565 {
566 int printed;
567 struct cfi_flash_bank *cfi_info = bank->driver_priv;
568 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
569
570 printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
571 buf += printed;
572 buf_size -= printed;
573
574 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
575 buf += printed;
576 buf_size -= printed;
577
578 printed = snprintf(buf, buf_size, "feature_support: 0x%" PRIx32 ", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
579 buf += printed;
580 buf_size -= printed;
581
582 printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
583 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
584 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
585 buf += printed;
586 buf_size -= printed;
587
588 printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
589
590 return ERROR_OK;
591 }
592
593 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
594 */
595 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
596 {
597 struct cfi_flash_bank *cfi_info;
598
599 if (CMD_ARGC < 6)
600 {
601 LOG_WARNING("incomplete flash_bank cfi configuration");
602 return ERROR_FLASH_BANK_INVALID;
603 }
604
605 uint16_t chip_width, bus_width;
606 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[3], bus_width);
607 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[4], chip_width);
608
609 if ((chip_width > CFI_MAX_CHIP_WIDTH)
610 || (bus_width > CFI_MAX_BUS_WIDTH))
611 {
612 LOG_ERROR("chip and bus width have to specified in bytes");
613 return ERROR_FLASH_BANK_INVALID;
614 }
615
616 cfi_info = malloc(sizeof(struct cfi_flash_bank));
617 cfi_info->probed = 0;
618 bank->driver_priv = cfi_info;
619
620 cfi_info->write_algorithm = NULL;
621
622 cfi_info->x16_as_x8 = 0;
623 cfi_info->jedec_probe = 0;
624 cfi_info->not_cfi = 0;
625
626 for (unsigned i = 6; i < CMD_ARGC; i++)
627 {
628 if (strcmp(CMD_ARGV[i], "x16_as_x8") == 0)
629 {
630 cfi_info->x16_as_x8 = 1;
631 }
632 else if (strcmp(CMD_ARGV[i], "jedec_probe") == 0)
633 {
634 cfi_info->jedec_probe = 1;
635 }
636 }
637
638 cfi_info->write_algorithm = NULL;
639
640 /* bank wasn't probed yet */
641 cfi_info->qry[0] = -1;
642
643 return ERROR_OK;
644 }
645
646 static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
647 {
648 int retval;
649 struct cfi_flash_bank *cfi_info = bank->driver_priv;
650 struct target *target = bank->target;
651 uint8_t command[8];
652 int i;
653
654 cfi_intel_clear_status_register(bank);
655
656 for (i = first; i <= last; i++)
657 {
658 cfi_command(bank, 0x20, command);
659 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
660 {
661 return retval;
662 }
663
664 cfi_command(bank, 0xd0, command);
665 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
666 {
667 return retval;
668 }
669
670 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
671 bank->sectors[i].is_erased = 1;
672 else
673 {
674 cfi_command(bank, 0xff, command);
675 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
676 {
677 return retval;
678 }
679
680 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32 , i, bank->base);
681 return ERROR_FLASH_OPERATION_FAILED;
682 }
683 }
684
685 cfi_command(bank, 0xff, command);
686 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
687
688 }
689
690 static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
691 {
692 int retval;
693 struct cfi_flash_bank *cfi_info = bank->driver_priv;
694 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
695 struct target *target = bank->target;
696 uint8_t command[8];
697 int i;
698
699 for (i = first; i <= last; i++)
700 {
701 cfi_command(bank, 0xaa, command);
702 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
703 {
704 return retval;
705 }
706
707 cfi_command(bank, 0x55, command);
708 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
709 {
710 return retval;
711 }
712
713 cfi_command(bank, 0x80, command);
714 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
715 {
716 return retval;
717 }
718
719 cfi_command(bank, 0xaa, command);
720 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
721 {
722 return retval;
723 }
724
725 cfi_command(bank, 0x55, command);
726 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
727 {
728 return retval;
729 }
730
731 cfi_command(bank, 0x30, command);
732 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
733 {
734 return retval;
735 }
736
737 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
738 bank->sectors[i].is_erased = 1;
739 else
740 {
741 cfi_command(bank, 0xf0, command);
742 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
743 {
744 return retval;
745 }
746
747 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32, i, bank->base);
748 return ERROR_FLASH_OPERATION_FAILED;
749 }
750 }
751
752 cfi_command(bank, 0xf0, command);
753 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
754 }
755
756 static int cfi_erase(struct flash_bank *bank, int first, int last)
757 {
758 struct cfi_flash_bank *cfi_info = bank->driver_priv;
759
760 if (bank->target->state != TARGET_HALTED)
761 {
762 LOG_ERROR("Target not halted");
763 return ERROR_TARGET_NOT_HALTED;
764 }
765
766 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
767 {
768 return ERROR_FLASH_SECTOR_INVALID;
769 }
770
771 if (cfi_info->qry[0] != 'Q')
772 return ERROR_FLASH_BANK_NOT_PROBED;
773
774 switch (cfi_info->pri_id)
775 {
776 case 1:
777 case 3:
778 return cfi_intel_erase(bank, first, last);
779 break;
780 case 2:
781 return cfi_spansion_erase(bank, first, last);
782 break;
783 default:
784 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
785 break;
786 }
787
788 return ERROR_OK;
789 }
790
791 static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int last)
792 {
793 int retval;
794 struct cfi_flash_bank *cfi_info = bank->driver_priv;
795 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
796 struct target *target = bank->target;
797 uint8_t command[8];
798 int retry = 0;
799 int i;
800
801 /* if the device supports neither legacy lock/unlock (bit 3) nor
802 * instant individual block locking (bit 5).
803 */
804 if (!(pri_ext->feature_support & 0x28))
805 return ERROR_FLASH_OPERATION_FAILED;
806
807 cfi_intel_clear_status_register(bank);
808
809 for (i = first; i <= last; i++)
810 {
811 cfi_command(bank, 0x60, command);
812 LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32, flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
813 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
814 {
815 return retval;
816 }
817 if (set)
818 {
819 cfi_command(bank, 0x01, command);
820 LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32 , flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
821 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
822 {
823 return retval;
824 }
825 bank->sectors[i].is_protected = 1;
826 }
827 else
828 {
829 cfi_command(bank, 0xd0, command);
830 LOG_DEBUG("address: 0x%4.4" PRIx32 ", command: 0x%4.4" PRIx32, flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
831 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
832 {
833 return retval;
834 }
835 bank->sectors[i].is_protected = 0;
836 }
837
838 /* instant individual block locking doesn't require reading of the status register */
839 if (!(pri_ext->feature_support & 0x20))
840 {
841 /* Clear lock bits operation may take up to 1.4s */
842 cfi_intel_wait_status_busy(bank, 1400);
843 }
844 else
845 {
846 uint8_t block_status;
847 /* read block lock bit, to verify status */
848 cfi_command(bank, 0x90, command);
849 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
850 {
851 return retval;
852 }
853 block_status = cfi_get_u8(bank, i, 0x2);
854
855 if ((block_status & 0x1) != set)
856 {
857 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
858 cfi_command(bank, 0x70, command);
859 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
860 {
861 return retval;
862 }
863 cfi_intel_wait_status_busy(bank, 10);
864
865 if (retry > 10)
866 return ERROR_FLASH_OPERATION_FAILED;
867 else
868 {
869 i--;
870 retry++;
871 }
872 }
873 }
874 }
875
876 /* if the device doesn't support individual block lock bits set/clear,
877 * all blocks have been unlocked in parallel, so we set those that should be protected
878 */
879 if ((!set) && (!(pri_ext->feature_support & 0x20)))
880 {
881 for (i = 0; i < bank->num_sectors; i++)
882 {
883 if (bank->sectors[i].is_protected == 1)
884 {
885 cfi_intel_clear_status_register(bank);
886
887 cfi_command(bank, 0x60, command);
888 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
889 {
890 return retval;
891 }
892
893 cfi_command(bank, 0x01, command);
894 if ((retval = target_write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
895 {
896 return retval;
897 }
898
899 cfi_intel_wait_status_busy(bank, 100);
900 }
901 }
902 }
903
904 cfi_command(bank, 0xff, command);
905 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
906 }
907
908 static int cfi_protect(struct flash_bank *bank, int set, int first, int last)
909 {
910 struct cfi_flash_bank *cfi_info = bank->driver_priv;
911
912 if (bank->target->state != TARGET_HALTED)
913 {
914 LOG_ERROR("Target not halted");
915 return ERROR_TARGET_NOT_HALTED;
916 }
917
918 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
919 {
920 return ERROR_FLASH_SECTOR_INVALID;
921 }
922
923 if (cfi_info->qry[0] != 'Q')
924 return ERROR_FLASH_BANK_NOT_PROBED;
925
926 switch (cfi_info->pri_id)
927 {
928 case 1:
929 case 3:
930 cfi_intel_protect(bank, set, first, last);
931 break;
932 default:
933 LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
934 break;
935 }
936
937 return ERROR_OK;
938 }
939
940 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
941 static void cfi_add_byte(struct flash_bank *bank, uint8_t *word, uint8_t byte)
942 {
943 /* struct target *target = bank->target; */
944
945 int i;
946
947 /* NOTE:
948 * The data to flash must not be changed in endian! We write a bytestrem in
949 * target byte order already. Only the control and status byte lane of the flash
950 * WSM is interpreted by the CPU in different ways, when read a uint16_t or uint32_t
951 * word (data seems to be in the upper or lower byte lane for uint16_t accesses).
952 */
953
954 #if 0
955 if (target->endianness == TARGET_LITTLE_ENDIAN)
956 {
957 #endif
958 /* shift bytes */
959 for (i = 0; i < bank->bus_width - 1; i++)
960 word[i] = word[i + 1];
961 word[bank->bus_width - 1] = byte;
962 #if 0
963 }
964 else
965 {
966 /* shift bytes */
967 for (i = bank->bus_width - 1; i > 0; i--)
968 word[i] = word[i - 1];
969 word[0] = byte;
970 }
971 #endif
972 }
973
974 /* Convert code image to target endian */
975 /* FIXME create general block conversion fcts in target.c?) */
976 static void cfi_fix_code_endian(struct target *target, uint8_t *dest, const uint32_t *src, uint32_t count)
977 {
978 uint32_t i;
979 for (i = 0; i< count; i++)
980 {
981 target_buffer_set_u32(target, dest, *src);
982 dest += 4;
983 src++;
984 }
985 }
986
987 static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd)
988 {
989 struct target *target = bank->target;
990
991 uint8_t buf[CFI_MAX_BUS_WIDTH];
992 cfi_command(bank, cmd, buf);
993 switch (bank->bus_width)
994 {
995 case 1 :
996 return buf[0];
997 break;
998 case 2 :
999 return target_buffer_get_u16(target, buf);
1000 break;
1001 case 4 :
1002 return target_buffer_get_u32(target, buf);
1003 break;
1004 default :
1005 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1006 return 0;
1007 }
1008 }
1009
1010 static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1011 {
1012 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1013 struct target *target = bank->target;
1014 struct reg_param reg_params[7];
1015 struct armv4_5_algorithm armv4_5_info;
1016 struct working_area *source;
1017 uint32_t buffer_size = 32768;
1018 uint32_t write_command_val, busy_pattern_val, error_pattern_val;
1019
1020 /* algorithm register usage:
1021 * r0: source address (in RAM)
1022 * r1: target address (in Flash)
1023 * r2: count
1024 * r3: flash write command
1025 * r4: status byte (returned to host)
1026 * r5: busy test pattern
1027 * r6: error test pattern
1028 */
1029
1030 static const uint32_t word_32_code[] = {
1031 0xe4904004, /* loop: ldr r4, [r0], #4 */
1032 0xe5813000, /* str r3, [r1] */
1033 0xe5814000, /* str r4, [r1] */
1034 0xe5914000, /* busy: ldr r4, [r1] */
1035 0xe0047005, /* and r7, r4, r5 */
1036 0xe1570005, /* cmp r7, r5 */
1037 0x1afffffb, /* bne busy */
1038 0xe1140006, /* tst r4, r6 */
1039 0x1a000003, /* bne done */
1040 0xe2522001, /* subs r2, r2, #1 */
1041 0x0a000001, /* beq done */
1042 0xe2811004, /* add r1, r1 #4 */
1043 0xeafffff2, /* b loop */
1044 0xeafffffe /* done: b -2 */
1045 };
1046
1047 static const uint32_t word_16_code[] = {
1048 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1049 0xe1c130b0, /* strh r3, [r1] */
1050 0xe1c140b0, /* strh r4, [r1] */
1051 0xe1d140b0, /* busy ldrh r4, [r1] */
1052 0xe0047005, /* and r7, r4, r5 */
1053 0xe1570005, /* cmp r7, r5 */
1054 0x1afffffb, /* bne busy */
1055 0xe1140006, /* tst r4, r6 */
1056 0x1a000003, /* bne done */
1057 0xe2522001, /* subs r2, r2, #1 */
1058 0x0a000001, /* beq done */
1059 0xe2811002, /* add r1, r1 #2 */
1060 0xeafffff2, /* b loop */
1061 0xeafffffe /* done: b -2 */
1062 };
1063
1064 static const uint32_t word_8_code[] = {
1065 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1066 0xe5c13000, /* strb r3, [r1] */
1067 0xe5c14000, /* strb r4, [r1] */
1068 0xe5d14000, /* busy ldrb r4, [r1] */
1069 0xe0047005, /* and r7, r4, r5 */
1070 0xe1570005, /* cmp r7, r5 */
1071 0x1afffffb, /* bne busy */
1072 0xe1140006, /* tst r4, r6 */
1073 0x1a000003, /* bne done */
1074 0xe2522001, /* subs r2, r2, #1 */
1075 0x0a000001, /* beq done */
1076 0xe2811001, /* add r1, r1 #1 */
1077 0xeafffff2, /* b loop */
1078 0xeafffffe /* done: b -2 */
1079 };
1080 uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
1081 const uint32_t *target_code_src;
1082 uint32_t target_code_size;
1083 int retval = ERROR_OK;
1084
1085
1086 cfi_intel_clear_status_register(bank);
1087
1088 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1089 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1090 armv4_5_info.core_state = ARM_STATE_ARM;
1091
1092 /* If we are setting up the write_algorith, we need target_code_src */
1093 /* if not we only need target_code_size. */
1094
1095 /* However, we don't want to create multiple code paths, so we */
1096 /* do the unecessary evaluation of target_code_src, which the */
1097 /* compiler will probably nicely optimize away if not needed */
1098
1099 /* prepare algorithm code for target endian */
1100 switch (bank->bus_width)
1101 {
1102 case 1 :
1103 target_code_src = word_8_code;
1104 target_code_size = sizeof(word_8_code);
1105 break;
1106 case 2 :
1107 target_code_src = word_16_code;
1108 target_code_size = sizeof(word_16_code);
1109 break;
1110 case 4 :
1111 target_code_src = word_32_code;
1112 target_code_size = sizeof(word_32_code);
1113 break;
1114 default:
1115 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1116 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1117 }
1118
1119 /* flash write code */
1120 if (!cfi_info->write_algorithm)
1121 {
1122 if (target_code_size > sizeof(target_code))
1123 {
1124 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1125 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1126 }
1127 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1128
1129 /* Get memory for block write handler */
1130 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1131 if (retval != ERROR_OK)
1132 {
1133 LOG_WARNING("No working area available, can't do block memory writes");
1134 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1135 };
1136
1137 /* write algorithm code to working area */
1138 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1139 if (retval != ERROR_OK)
1140 {
1141 LOG_ERROR("Unable to write block write code to target");
1142 goto cleanup;
1143 }
1144 }
1145
1146 /* Get a workspace buffer for the data to flash starting with 32k size.
1147 Half size until buffer would be smaller 256 Bytem then fail back */
1148 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1149 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1150 {
1151 buffer_size /= 2;
1152 if (buffer_size <= 256)
1153 {
1154 LOG_WARNING("no large enough working area available, can't do block memory writes");
1155 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1156 goto cleanup;
1157 }
1158 };
1159
1160 /* setup algo registers */
1161 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1162 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1163 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1164 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1165 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1166 init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1167 init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1168
1169 /* prepare command and status register patterns */
1170 write_command_val = cfi_command_val(bank, 0x40);
1171 busy_pattern_val = cfi_command_val(bank, 0x80);
1172 error_pattern_val = cfi_command_val(bank, 0x7e);
1173
1174 LOG_INFO("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32, source->address, buffer_size);
1175
1176 /* Programming main loop */
1177 while (count > 0)
1178 {
1179 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1180 uint32_t wsm_error;
1181
1182 if ((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1183 {
1184 goto cleanup;
1185 }
1186
1187 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1188 buf_set_u32(reg_params[1].value, 0, 32, address);
1189 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1190
1191 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1192 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1193 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1194
1195 LOG_INFO("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
1196
1197 /* Execute algorithm, assume breakpoint for last instruction */
1198 retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
1199 cfi_info->write_algorithm->address,
1200 cfi_info->write_algorithm->address + target_code_size - sizeof(uint32_t),
1201 10000, /* 10s should be enough for max. 32k of data */
1202 &armv4_5_info);
1203
1204 /* On failure try a fall back to direct word writes */
1205 if (retval != ERROR_OK)
1206 {
1207 cfi_intel_clear_status_register(bank);
1208 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1209 retval = ERROR_FLASH_OPERATION_FAILED;
1210 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1211 /* FIXME To allow fall back or recovery, we must save the actual status
1212 somewhere, so that a higher level code can start recovery. */
1213 goto cleanup;
1214 }
1215
1216 /* Check return value from algo code */
1217 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1218 if (wsm_error)
1219 {
1220 /* read status register (outputs debug inforation) */
1221 cfi_intel_wait_status_busy(bank, 100);
1222 cfi_intel_clear_status_register(bank);
1223 retval = ERROR_FLASH_OPERATION_FAILED;
1224 goto cleanup;
1225 }
1226
1227 buffer += thisrun_count;
1228 address += thisrun_count;
1229 count -= thisrun_count;
1230 }
1231
1232 /* free up resources */
1233 cleanup:
1234 if (source)
1235 target_free_working_area(target, source);
1236
1237 if (cfi_info->write_algorithm)
1238 {
1239 target_free_working_area(target, cfi_info->write_algorithm);
1240 cfi_info->write_algorithm = NULL;
1241 }
1242
1243 destroy_reg_param(&reg_params[0]);
1244 destroy_reg_param(&reg_params[1]);
1245 destroy_reg_param(&reg_params[2]);
1246 destroy_reg_param(&reg_params[3]);
1247 destroy_reg_param(&reg_params[4]);
1248 destroy_reg_param(&reg_params[5]);
1249 destroy_reg_param(&reg_params[6]);
1250
1251 return retval;
1252 }
1253
1254 static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer, uint32_t address, uint32_t count)
1255 {
1256 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1257 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1258 struct target *target = bank->target;
1259 struct reg_param reg_params[10];
1260 struct armv4_5_algorithm armv4_5_info;
1261 struct working_area *source;
1262 uint32_t buffer_size = 32768;
1263 uint32_t status;
1264 int retval, retvaltemp;
1265 int exit_code = ERROR_OK;
1266
1267 /* input parameters - */
1268 /* R0 = source address */
1269 /* R1 = destination address */
1270 /* R2 = number of writes */
1271 /* R3 = flash write command */
1272 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1273 /* output parameters - */
1274 /* R5 = 0x80 ok 0x00 bad */
1275 /* temp registers - */
1276 /* R6 = value read from flash to test status */
1277 /* R7 = holding register */
1278 /* unlock registers - */
1279 /* R8 = unlock1_addr */
1280 /* R9 = unlock1_cmd */
1281 /* R10 = unlock2_addr */
1282 /* R11 = unlock2_cmd */
1283
1284 static const uint32_t word_32_code[] = {
1285 /* 00008100 <sp_32_code>: */
1286 0xe4905004, /* ldr r5, [r0], #4 */
1287 0xe5889000, /* str r9, [r8] */
1288 0xe58ab000, /* str r11, [r10] */
1289 0xe5883000, /* str r3, [r8] */
1290 0xe5815000, /* str r5, [r1] */
1291 0xe1a00000, /* nop */
1292 /* */
1293 /* 00008110 <sp_32_busy>: */
1294 0xe5916000, /* ldr r6, [r1] */
1295 0xe0257006, /* eor r7, r5, r6 */
1296 0xe0147007, /* ands r7, r4, r7 */
1297 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1298 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1299 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1300 0xe5916000, /* ldr r6, [r1] */
1301 0xe0257006, /* eor r7, r5, r6 */
1302 0xe0147007, /* ands r7, r4, r7 */
1303 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1304 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1305 0x1a000004, /* bne 8154 <sp_32_done> */
1306 /* */
1307 /* 00008140 <sp_32_cont>: */
1308 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1309 0x03a05080, /* moveq r5, #128 ; 0x80 */
1310 0x0a000001, /* beq 8154 <sp_32_done> */
1311 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1312 0xeaffffe8, /* b 8100 <sp_32_code> */
1313 /* */
1314 /* 00008154 <sp_32_done>: */
1315 0xeafffffe /* b 8154 <sp_32_done> */
1316 };
1317
1318 static const uint32_t word_16_code[] = {
1319 /* 00008158 <sp_16_code>: */
1320 0xe0d050b2, /* ldrh r5, [r0], #2 */
1321 0xe1c890b0, /* strh r9, [r8] */
1322 0xe1cab0b0, /* strh r11, [r10] */
1323 0xe1c830b0, /* strh r3, [r8] */
1324 0xe1c150b0, /* strh r5, [r1] */
1325 0xe1a00000, /* nop (mov r0,r0) */
1326 /* */
1327 /* 00008168 <sp_16_busy>: */
1328 0xe1d160b0, /* ldrh r6, [r1] */
1329 0xe0257006, /* eor r7, r5, r6 */
1330 0xe0147007, /* ands r7, r4, r7 */
1331 0x0a000007, /* beq 8198 <sp_16_cont> */
1332 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1333 0x0afffff9, /* beq 8168 <sp_16_busy> */
1334 0xe1d160b0, /* ldrh r6, [r1] */
1335 0xe0257006, /* eor r7, r5, r6 */
1336 0xe0147007, /* ands r7, r4, r7 */
1337 0x0a000001, /* beq 8198 <sp_16_cont> */
1338 0xe3a05000, /* mov r5, #0 ; 0x0 */
1339 0x1a000004, /* bne 81ac <sp_16_done> */
1340 /* */
1341 /* 00008198 <sp_16_cont>: */
1342 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1343 0x03a05080, /* moveq r5, #128 ; 0x80 */
1344 0x0a000001, /* beq 81ac <sp_16_done> */
1345 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1346 0xeaffffe8, /* b 8158 <sp_16_code> */
1347 /* */
1348 /* 000081ac <sp_16_done>: */
1349 0xeafffffe /* b 81ac <sp_16_done> */
1350 };
1351
1352 static const uint32_t word_16_code_dq7only[] = {
1353 /* <sp_16_code>: */
1354 0xe0d050b2, /* ldrh r5, [r0], #2 */
1355 0xe1c890b0, /* strh r9, [r8] */
1356 0xe1cab0b0, /* strh r11, [r10] */
1357 0xe1c830b0, /* strh r3, [r8] */
1358 0xe1c150b0, /* strh r5, [r1] */
1359 0xe1a00000, /* nop (mov r0,r0) */
1360 /* */
1361 /* <sp_16_busy>: */
1362 0xe1d160b0, /* ldrh r6, [r1] */
1363 0xe0257006, /* eor r7, r5, r6 */
1364 0xe2177080, /* ands r7, #0x80 */
1365 0x1afffffb, /* bne 8168 <sp_16_busy> */
1366 /* */
1367 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1368 0x03a05080, /* moveq r5, #128 ; 0x80 */
1369 0x0a000001, /* beq 81ac <sp_16_done> */
1370 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1371 0xeafffff0, /* b 8158 <sp_16_code> */
1372 /* */
1373 /* 000081ac <sp_16_done>: */
1374 0xeafffffe /* b 81ac <sp_16_done> */
1375 };
1376
1377 static const uint32_t word_8_code[] = {
1378 /* 000081b0 <sp_16_code_end>: */
1379 0xe4d05001, /* ldrb r5, [r0], #1 */
1380 0xe5c89000, /* strb r9, [r8] */
1381 0xe5cab000, /* strb r11, [r10] */
1382 0xe5c83000, /* strb r3, [r8] */
1383 0xe5c15000, /* strb r5, [r1] */
1384 0xe1a00000, /* nop (mov r0,r0) */
1385 /* */
1386 /* 000081c0 <sp_8_busy>: */
1387 0xe5d16000, /* ldrb r6, [r1] */
1388 0xe0257006, /* eor r7, r5, r6 */
1389 0xe0147007, /* ands r7, r4, r7 */
1390 0x0a000007, /* beq 81f0 <sp_8_cont> */
1391 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1392 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1393 0xe5d16000, /* ldrb r6, [r1] */
1394 0xe0257006, /* eor r7, r5, r6 */
1395 0xe0147007, /* ands r7, r4, r7 */
1396 0x0a000001, /* beq 81f0 <sp_8_cont> */
1397 0xe3a05000, /* mov r5, #0 ; 0x0 */
1398 0x1a000004, /* bne 8204 <sp_8_done> */
1399 /* */
1400 /* 000081f0 <sp_8_cont>: */
1401 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1402 0x03a05080, /* moveq r5, #128 ; 0x80 */
1403 0x0a000001, /* beq 8204 <sp_8_done> */
1404 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1405 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1406 /* */
1407 /* 00008204 <sp_8_done>: */
1408 0xeafffffe /* b 8204 <sp_8_done> */
1409 };
1410
1411 armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1412 armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1413 armv4_5_info.core_state = ARM_STATE_ARM;
1414
1415 int target_code_size;
1416 const uint32_t *target_code_src;
1417
1418 switch (bank->bus_width)
1419 {
1420 case 1 :
1421 target_code_src = word_8_code;
1422 target_code_size = sizeof(word_8_code);
1423 break;
1424 case 2 :
1425 /* Check for DQ5 support */
1426 if( cfi_info->status_poll_mask & (1 << 5) )
1427 {
1428 target_code_src = word_16_code;
1429 target_code_size = sizeof(word_16_code);
1430 }
1431 else
1432 {
1433 /* No DQ5 support. Use DQ7 DATA# polling only. */
1434 target_code_src = word_16_code_dq7only;
1435 target_code_size = sizeof(word_16_code_dq7only);
1436 }
1437 break;
1438 case 4 :
1439 target_code_src = word_32_code;
1440 target_code_size = sizeof(word_32_code);
1441 break;
1442 default:
1443 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1444 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1445 }
1446
1447 /* flash write code */
1448 if (!cfi_info->write_algorithm)
1449 {
1450 uint8_t *target_code;
1451
1452 /* convert bus-width dependent algorithm code to correct endiannes */
1453 target_code = malloc(target_code_size);
1454 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1455
1456 /* allocate working area */
1457 retval = target_alloc_working_area(target, target_code_size,
1458 &cfi_info->write_algorithm);
1459 if (retval != ERROR_OK)
1460 {
1461 free(target_code);
1462 return retval;
1463 }
1464
1465 /* write algorithm code to working area */
1466 if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1467 target_code_size, target_code)) != ERROR_OK)
1468 {
1469 free(target_code);
1470 return retval;
1471 }
1472
1473 free(target_code);
1474 }
1475 /* the following code still assumes target code is fixed 24*4 bytes */
1476
1477 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1478 {
1479 buffer_size /= 2;
1480 if (buffer_size <= 256)
1481 {
1482 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1483 if (cfi_info->write_algorithm)
1484 target_free_working_area(target, cfi_info->write_algorithm);
1485
1486 LOG_WARNING("not enough working area available, can't do block memory writes");
1487 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1488 }
1489 };
1490
1491 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1492 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1493 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1494 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1495 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1496 init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1497 init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1498 init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1499 init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1500 init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1501
1502 while (count > 0)
1503 {
1504 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1505
1506 retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);
1507
1508 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1509 buf_set_u32(reg_params[1].value, 0, 32, address);
1510 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1511 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1512 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1513 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1514 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1515 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1516 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1517
1518 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1519 cfi_info->write_algorithm->address,
1520 cfi_info->write_algorithm->address + ((target_code_size) - 4),
1521 10000, &armv4_5_info);
1522
1523 status = buf_get_u32(reg_params[5].value, 0, 32);
1524
1525 if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
1526 {
1527 LOG_DEBUG("status: 0x%" PRIx32 , status);
1528 exit_code = ERROR_FLASH_OPERATION_FAILED;
1529 break;
1530 }
1531
1532 buffer += thisrun_count;
1533 address += thisrun_count;
1534 count -= thisrun_count;
1535 }
1536
1537 target_free_all_working_areas(target);
1538
1539 destroy_reg_param(&reg_params[0]);
1540 destroy_reg_param(&reg_params[1]);
1541 destroy_reg_param(&reg_params[2]);
1542 destroy_reg_param(&reg_params[3]);
1543 destroy_reg_param(&reg_params[4]);
1544 destroy_reg_param(&reg_params[5]);
1545 destroy_reg_param(&reg_params[6]);
1546 destroy_reg_param(&reg_params[7]);
1547 destroy_reg_param(&reg_params[8]);
1548 destroy_reg_param(&reg_params[9]);
1549
1550 return exit_code;
1551 }
1552
1553 static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1554 {
1555 int retval;
1556 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1557 struct target *target = bank->target;
1558 uint8_t command[8];
1559
1560 cfi_intel_clear_status_register(bank);
1561 cfi_command(bank, 0x40, command);
1562 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1563 {
1564 return retval;
1565 }
1566
1567 if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1568 {
1569 return retval;
1570 }
1571
1572 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1573 {
1574 cfi_command(bank, 0xff, command);
1575 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1576 {
1577 return retval;
1578 }
1579
1580 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1581 return ERROR_FLASH_OPERATION_FAILED;
1582 }
1583
1584 return ERROR_OK;
1585 }
1586
1587 static int cfi_intel_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1588 {
1589 int retval;
1590 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1591 struct target *target = bank->target;
1592 uint8_t command[8];
1593
1594 /* Calculate buffer size and boundary mask */
1595 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1596 uint32_t buffermask = buffersize-1;
1597 uint32_t bufferwsize;
1598
1599 /* Check for valid range */
1600 if (address & buffermask)
1601 {
1602 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary",
1603 bank->base, address, cfi_info->max_buf_write_size);
1604 return ERROR_FLASH_OPERATION_FAILED;
1605 }
1606 switch (bank->chip_width)
1607 {
1608 case 4 : bufferwsize = buffersize / 4; break;
1609 case 2 : bufferwsize = buffersize / 2; break;
1610 case 1 : bufferwsize = buffersize; break;
1611 default:
1612 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1613 return ERROR_FLASH_OPERATION_FAILED;
1614 }
1615
1616 bufferwsize/=(bank->bus_width / bank->chip_width);
1617
1618
1619 /* Check for valid size */
1620 if (wordcount > bufferwsize)
1621 {
1622 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32 , wordcount, buffersize);
1623 return ERROR_FLASH_OPERATION_FAILED;
1624 }
1625
1626 /* Write to flash buffer */
1627 cfi_intel_clear_status_register(bank);
1628
1629 /* Initiate buffer operation _*/
1630 cfi_command(bank, 0xE8, command);
1631 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1632 {
1633 return retval;
1634 }
1635 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1636 {
1637 cfi_command(bank, 0xff, command);
1638 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1639 {
1640 return retval;
1641 }
1642
1643 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1644 return ERROR_FLASH_OPERATION_FAILED;
1645 }
1646
1647 /* Write buffer wordcount-1 and data words */
1648 cfi_command(bank, bufferwsize-1, command);
1649 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1650 {
1651 return retval;
1652 }
1653
1654 if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1655 {
1656 return retval;
1657 }
1658
1659 /* Commit write operation */
1660 cfi_command(bank, 0xd0, command);
1661 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1662 {
1663 return retval;
1664 }
1665 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1666 {
1667 cfi_command(bank, 0xff, command);
1668 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1669 {
1670 return retval;
1671 }
1672
1673 LOG_ERROR("Buffer write at base 0x%" PRIx32 ", address %" PRIx32 " failed.", bank->base, address);
1674 return ERROR_FLASH_OPERATION_FAILED;
1675 }
1676
1677 return ERROR_OK;
1678 }
1679
1680 static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1681 {
1682 int retval;
1683 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1684 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1685 struct target *target = bank->target;
1686 uint8_t command[8];
1687
1688 cfi_command(bank, 0xaa, command);
1689 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1690 {
1691 return retval;
1692 }
1693
1694 cfi_command(bank, 0x55, command);
1695 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1696 {
1697 return retval;
1698 }
1699
1700 cfi_command(bank, 0xa0, command);
1701 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1702 {
1703 return retval;
1704 }
1705
1706 if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1707 {
1708 return retval;
1709 }
1710
1711 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1712 {
1713 cfi_command(bank, 0xf0, command);
1714 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1715 {
1716 return retval;
1717 }
1718
1719 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address %" PRIx32 , bank->base, address);
1720 return ERROR_FLASH_OPERATION_FAILED;
1721 }
1722
1723 return ERROR_OK;
1724 }
1725
1726 static int cfi_spansion_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1727 {
1728 int retval;
1729 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1730 struct target *target = bank->target;
1731 uint8_t command[8];
1732 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1733
1734 /* Calculate buffer size and boundary mask */
1735 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1736 uint32_t buffermask = buffersize-1;
1737 uint32_t bufferwsize;
1738
1739 /* Check for valid range */
1740 if (address & buffermask)
1741 {
1742 LOG_ERROR("Write address at base 0x%" PRIx32 ", address %" PRIx32 " not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1743 return ERROR_FLASH_OPERATION_FAILED;
1744 }
1745 switch (bank->chip_width)
1746 {
1747 case 4 : bufferwsize = buffersize / 4; break;
1748 case 2 : bufferwsize = buffersize / 2; break;
1749 case 1 : bufferwsize = buffersize; break;
1750 default:
1751 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1752 return ERROR_FLASH_OPERATION_FAILED;
1753 }
1754
1755 bufferwsize/=(bank->bus_width / bank->chip_width);
1756
1757 /* Check for valid size */
1758 if (wordcount > bufferwsize)
1759 {
1760 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32, wordcount, buffersize);
1761 return ERROR_FLASH_OPERATION_FAILED;
1762 }
1763
1764 // Unlock
1765 cfi_command(bank, 0xaa, command);
1766 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1767 {
1768 return retval;
1769 }
1770
1771 cfi_command(bank, 0x55, command);
1772 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1773 {
1774 return retval;
1775 }
1776
1777 // Buffer load command
1778 cfi_command(bank, 0x25, command);
1779 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1780 {
1781 return retval;
1782 }
1783
1784 /* Write buffer wordcount-1 and data words */
1785 cfi_command(bank, bufferwsize-1, command);
1786 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1787 {
1788 return retval;
1789 }
1790
1791 if ((retval = target_write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1792 {
1793 return retval;
1794 }
1795
1796 /* Commit write operation */
1797 cfi_command(bank, 0x29, command);
1798 if ((retval = target_write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1799 {
1800 return retval;
1801 }
1802
1803 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1804 {
1805 cfi_command(bank, 0xf0, command);
1806 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1807 {
1808 return retval;
1809 }
1810
1811 LOG_ERROR("couldn't write block at base 0x%" PRIx32 ", address %" PRIx32 ", size %" PRIx32 , bank->base, address, bufferwsize);
1812 return ERROR_FLASH_OPERATION_FAILED;
1813 }
1814
1815 return ERROR_OK;
1816 }
1817
1818 static int cfi_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1819 {
1820 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1821
1822 switch (cfi_info->pri_id)
1823 {
1824 case 1:
1825 case 3:
1826 return cfi_intel_write_word(bank, word, address);
1827 break;
1828 case 2:
1829 return cfi_spansion_write_word(bank, word, address);
1830 break;
1831 default:
1832 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1833 break;
1834 }
1835
1836 return ERROR_FLASH_OPERATION_FAILED;
1837 }
1838
1839 static int cfi_write_words(struct flash_bank *bank, uint8_t *word, uint32_t wordcount, uint32_t address)
1840 {
1841 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1842
1843 switch (cfi_info->pri_id)
1844 {
1845 case 1:
1846 case 3:
1847 return cfi_intel_write_words(bank, word, wordcount, address);
1848 break;
1849 case 2:
1850 return cfi_spansion_write_words(bank, word, wordcount, address);
1851 break;
1852 default:
1853 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1854 break;
1855 }
1856
1857 return ERROR_FLASH_OPERATION_FAILED;
1858 }
1859
1860 int cfi_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
1861 {
1862 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1863 struct target *target = bank->target;
1864 uint32_t address = bank->base + offset; /* address of first byte to be programmed */
1865 uint32_t write_p, copy_p;
1866 int align; /* number of unaligned bytes */
1867 int blk_count; /* number of bus_width bytes for block copy */
1868 uint8_t current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1869 int i;
1870 int retval;
1871
1872 if (bank->target->state != TARGET_HALTED)
1873 {
1874 LOG_ERROR("Target not halted");
1875 return ERROR_TARGET_NOT_HALTED;
1876 }
1877
1878 if (offset + count > bank->size)
1879 return ERROR_FLASH_DST_OUT_OF_BANK;
1880
1881 if (cfi_info->qry[0] != 'Q')
1882 return ERROR_FLASH_BANK_NOT_PROBED;
1883
1884 /* start at the first byte of the first word (bus_width size) */
1885 write_p = address & ~(bank->bus_width - 1);
1886 if ((align = address - write_p) != 0)
1887 {
1888 LOG_INFO("Fixup %d unaligned head bytes", align);
1889
1890 for (i = 0; i < bank->bus_width; i++)
1891 current_word[i] = 0;
1892 copy_p = write_p;
1893
1894 /* copy bytes before the first write address */
1895 for (i = 0; i < align; ++i, ++copy_p)
1896 {
1897 uint8_t byte;
1898 if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1899 {
1900 return retval;
1901 }
1902 cfi_add_byte(bank, current_word, byte);
1903 }
1904
1905 /* add bytes from the buffer */
1906 for (; (i < bank->bus_width) && (count > 0); i++)
1907 {
1908 cfi_add_byte(bank, current_word, *buffer++);
1909 count--;
1910 copy_p++;
1911 }
1912
1913 /* if the buffer is already finished, copy bytes after the last write address */
1914 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1915 {
1916 uint8_t byte;
1917 if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1918 {
1919 return retval;
1920 }
1921 cfi_add_byte(bank, current_word, byte);
1922 }
1923
1924 retval = cfi_write_word(bank, current_word, write_p);
1925 if (retval != ERROR_OK)
1926 return retval;
1927 write_p = copy_p;
1928 }
1929
1930 /* handle blocks of bus_size aligned bytes */
1931 blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1932 switch (cfi_info->pri_id)
1933 {
1934 /* try block writes (fails without working area) */
1935 case 1:
1936 case 3:
1937 retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1938 break;
1939 case 2:
1940 retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1941 break;
1942 default:
1943 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1944 retval = ERROR_FLASH_OPERATION_FAILED;
1945 break;
1946 }
1947 if (retval == ERROR_OK)
1948 {
1949 /* Increment pointers and decrease count on succesful block write */
1950 buffer += blk_count;
1951 write_p += blk_count;
1952 count -= blk_count;
1953 }
1954 else
1955 {
1956 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1957 {
1958 //adjust buffersize for chip width
1959 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1960 uint32_t buffermask = buffersize-1;
1961 uint32_t bufferwsize;
1962
1963 switch (bank->chip_width)
1964 {
1965 case 4 : bufferwsize = buffersize / 4; break;
1966 case 2 : bufferwsize = buffersize / 2; break;
1967 case 1 : bufferwsize = buffersize; break;
1968 default:
1969 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1970 return ERROR_FLASH_OPERATION_FAILED;
1971 }
1972
1973 bufferwsize/=(bank->bus_width / bank->chip_width);
1974
1975 /* fall back to memory writes */
1976 while (count >= (uint32_t)bank->bus_width)
1977 {
1978 int fallback;
1979 if ((write_p & 0xff) == 0)
1980 {
1981 LOG_INFO("Programming at %08" PRIx32 ", count %08" PRIx32 " bytes remaining", write_p, count);
1982 }
1983 fallback = 1;
1984 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1985 {
1986 retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1987 if (retval == ERROR_OK)
1988 {
1989 buffer += buffersize;
1990 write_p += buffersize;
1991 count -= buffersize;
1992 fallback = 0;
1993 }
1994 }
1995 /* try the slow way? */
1996 if (fallback)
1997 {
1998 for (i = 0; i < bank->bus_width; i++)
1999 current_word[i] = 0;
2000
2001 for (i = 0; i < bank->bus_width; i++)
2002 {
2003 cfi_add_byte(bank, current_word, *buffer++);
2004 }
2005
2006 retval = cfi_write_word(bank, current_word, write_p);
2007 if (retval != ERROR_OK)
2008 return retval;
2009
2010 write_p += bank->bus_width;
2011 count -= bank->bus_width;
2012 }
2013 }
2014 }
2015 else
2016 return retval;
2017 }
2018
2019 /* return to read array mode, so we can read from flash again for padding */
2020 cfi_command(bank, 0xf0, current_word);
2021 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2022 {
2023 return retval;
2024 }
2025 cfi_command(bank, 0xff, current_word);
2026 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2027 {
2028 return retval;
2029 }
2030
2031 /* handle unaligned tail bytes */
2032 if (count > 0)
2033 {
2034 LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
2035
2036 copy_p = write_p;
2037 for (i = 0; i < bank->bus_width; i++)
2038 current_word[i] = 0;
2039
2040 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
2041 {
2042 cfi_add_byte(bank, current_word, *buffer++);
2043 count--;
2044 }
2045 for (; i < bank->bus_width; ++i, ++copy_p)
2046 {
2047 uint8_t byte;
2048 if ((retval = target_read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
2049 {
2050 return retval;
2051 }
2052 cfi_add_byte(bank, current_word, byte);
2053 }
2054 retval = cfi_write_word(bank, current_word, write_p);
2055 if (retval != ERROR_OK)
2056 return retval;
2057 }
2058
2059 /* return to read array mode */
2060 cfi_command(bank, 0xf0, current_word);
2061 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2062 {
2063 return retval;
2064 }
2065 cfi_command(bank, 0xff, current_word);
2066 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
2067 }
2068
2069 static void cfi_fixup_atmel_reversed_erase_regions(struct flash_bank *bank, void *param)
2070 {
2071 (void) param;
2072 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2073 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2074
2075 pri_ext->_reversed_geometry = 1;
2076 }
2077
2078 static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param)
2079 {
2080 int i;
2081 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2082 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2083 (void) param;
2084
2085 if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2086 {
2087 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2088
2089 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2090 {
2091 int j = (cfi_info->num_erase_regions - 1) - i;
2092 uint32_t swap;
2093
2094 swap = cfi_info->erase_region_info[i];
2095 cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2096 cfi_info->erase_region_info[j] = swap;
2097 }
2098 }
2099 }
2100
2101 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param)
2102 {
2103 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2104 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2105 struct cfi_unlock_addresses *unlock_addresses = param;
2106
2107 pri_ext->_unlock1 = unlock_addresses->unlock1;
2108 pri_ext->_unlock2 = unlock_addresses->unlock2;
2109 }
2110
2111
2112 static int cfi_query_string(struct flash_bank *bank, int address)
2113 {
2114 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2115 struct target *target = bank->target;
2116 int retval;
2117 uint8_t command[8];
2118
2119 cfi_command(bank, 0x98, command);
2120 if ((retval = target_write_memory(target, flash_address(bank, 0, address), bank->bus_width, 1, command)) != ERROR_OK)
2121 {
2122 return retval;
2123 }
2124
2125 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
2126 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
2127 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
2128
2129 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2130
2131 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2132 {
2133 cfi_command(bank, 0xf0, command);
2134 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2135 {
2136 return retval;
2137 }
2138 cfi_command(bank, 0xff, command);
2139 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2140 {
2141 return retval;
2142 }
2143 LOG_ERROR("Could not probe bank: no QRY");
2144 return ERROR_FLASH_BANK_INVALID;
2145 }
2146
2147 return ERROR_OK;
2148 }
2149
2150 static int cfi_probe(struct flash_bank *bank)
2151 {
2152 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2153 struct target *target = bank->target;
2154 uint8_t command[8];
2155 int num_sectors = 0;
2156 int i;
2157 int sector = 0;
2158 uint32_t unlock1 = 0x555;
2159 uint32_t unlock2 = 0x2aa;
2160 int retval;
2161
2162 if (bank->target->state != TARGET_HALTED)
2163 {
2164 LOG_ERROR("Target not halted");
2165 return ERROR_TARGET_NOT_HALTED;
2166 }
2167
2168 cfi_info->probed = 0;
2169
2170 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2171 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2172 */
2173 if (cfi_info->jedec_probe)
2174 {
2175 unlock1 = 0x5555;
2176 unlock2 = 0x2aaa;
2177 }
2178
2179 /* switch to read identifier codes mode ("AUTOSELECT") */
2180 cfi_command(bank, 0xaa, command);
2181 if ((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2182 {
2183 return retval;
2184 }
2185 cfi_command(bank, 0x55, command);
2186 if ((retval = target_write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2187 {
2188 return retval;
2189 }
2190 cfi_command(bank, 0x90, command);
2191 if ((retval = target_write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2192 {
2193 return retval;
2194 }
2195
2196 if (bank->chip_width == 1)
2197 {
2198 uint8_t manufacturer, device_id;
2199 if ((retval = target_read_u8(target, flash_address(bank, 0, 0x00), &manufacturer)) != ERROR_OK)
2200 {
2201 return retval;
2202 }
2203 if ((retval = target_read_u8(target, flash_address(bank, 0, 0x01), &device_id)) != ERROR_OK)
2204 {
2205 return retval;
2206 }
2207 cfi_info->manufacturer = manufacturer;
2208 cfi_info->device_id = device_id;
2209 }
2210 else if (bank->chip_width == 2)
2211 {
2212 if ((retval = target_read_u16(target, flash_address(bank, 0, 0x00), &cfi_info->manufacturer)) != ERROR_OK)
2213 {
2214 return retval;
2215 }
2216 if ((retval = target_read_u16(target, flash_address(bank, 0, 0x01), &cfi_info->device_id)) != ERROR_OK)
2217 {
2218 return retval;
2219 }
2220 }
2221
2222 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2223 /* switch back to read array mode */
2224 cfi_command(bank, 0xf0, command);
2225 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2226 {
2227 return retval;
2228 }
2229 cfi_command(bank, 0xff, command);
2230 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2231 {
2232 return retval;
2233 }
2234
2235 /* check device/manufacturer ID for known non-CFI flashes. */
2236 cfi_fixup_non_cfi(bank);
2237
2238 /* query only if this is a CFI compatible flash,
2239 * otherwise the relevant info has already been filled in
2240 */
2241 if (cfi_info->not_cfi == 0)
2242 {
2243 int retval;
2244
2245 /* enter CFI query mode
2246 * according to JEDEC Standard No. 68.01,
2247 * a single bus sequence with address = 0x55, data = 0x98 should put
2248 * the device into CFI query mode.
2249 *
2250 * SST flashes clearly violate this, and we will consider them incompatbile for now
2251 */
2252
2253 retval = cfi_query_string(bank, 0x55);
2254 if (retval != ERROR_OK)
2255 {
2256 /*
2257 * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2258 * be harmless enough:
2259 *
2260 * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2261 */
2262 LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2263 retval = cfi_query_string(bank, 0x555);
2264 }
2265 if (retval != ERROR_OK)
2266 return retval;
2267
2268 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
2269 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
2270 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
2271 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
2272
2273 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2274
2275 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
2276 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
2277 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
2278 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
2279 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
2280 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
2281 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
2282 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
2283 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
2284 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
2285 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
2286 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
2287
2288 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
2289 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2290 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2291 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2292 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2293 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2294 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2295 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2296 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2297 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2298 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2299
2300 cfi_info->dev_size = 1 << cfi_query_u8(bank, 0, 0x27);
2301 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
2302 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
2303 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
2304
2305 LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2306
2307 if (cfi_info->num_erase_regions)
2308 {
2309 cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2310 for (i = 0; i < cfi_info->num_erase_regions; i++)
2311 {
2312 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2313 LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
2314 i,
2315 (cfi_info->erase_region_info[i] & 0xffff) + 1,
2316 (cfi_info->erase_region_info[i] >> 16) * 256);
2317 }
2318 }
2319 else
2320 {
2321 cfi_info->erase_region_info = NULL;
2322 }
2323
2324 /* We need to read the primary algorithm extended query table before calculating
2325 * the sector layout to be able to apply fixups
2326 */
2327 switch (cfi_info->pri_id)
2328 {
2329 /* Intel command set (standard and extended) */
2330 case 0x0001:
2331 case 0x0003:
2332 cfi_read_intel_pri_ext(bank);
2333 break;
2334 /* AMD/Spansion, Atmel, ... command set */
2335 case 0x0002:
2336 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2337 cfi_read_0002_pri_ext(bank);
2338 break;
2339 default:
2340 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2341 break;
2342 }
2343
2344 /* return to read array mode
2345 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2346 */
2347 cfi_command(bank, 0xf0, command);
2348 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2349 {
2350 return retval;
2351 }
2352 cfi_command(bank, 0xff, command);
2353 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2354 {
2355 return retval;
2356 }
2357 } /* end CFI case */
2358
2359 /* apply fixups depending on the primary command set */
2360 switch (cfi_info->pri_id)
2361 {
2362 /* Intel command set (standard and extended) */
2363 case 0x0001:
2364 case 0x0003:
2365 cfi_fixup(bank, cfi_0001_fixups);
2366 break;
2367 /* AMD/Spansion, Atmel, ... command set */
2368 case 0x0002:
2369 cfi_fixup(bank, cfi_0002_fixups);
2370 break;
2371 default:
2372 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2373 break;
2374 }
2375
2376 if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2377 {
2378 LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32 " size flash was found", bank->size, cfi_info->dev_size);
2379 }
2380
2381 if (cfi_info->num_erase_regions == 0)
2382 {
2383 /* a device might have only one erase block, spanning the whole device */
2384 bank->num_sectors = 1;
2385 bank->sectors = malloc(sizeof(struct flash_sector));
2386
2387 bank->sectors[sector].offset = 0x0;
2388 bank->sectors[sector].size = bank->size;
2389 bank->sectors[sector].is_erased = -1;
2390 bank->sectors[sector].is_protected = -1;
2391 }
2392 else
2393 {
2394 uint32_t offset = 0;
2395
2396 for (i = 0; i < cfi_info->num_erase_regions; i++)
2397 {
2398 num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2399 }
2400
2401 bank->num_sectors = num_sectors;
2402 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
2403
2404 for (i = 0; i < cfi_info->num_erase_regions; i++)
2405 {
2406 uint32_t j;
2407 for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2408 {
2409 bank->sectors[sector].offset = offset;
2410 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2411 offset += bank->sectors[sector].size;
2412 bank->sectors[sector].is_erased = -1;
2413 bank->sectors[sector].is_protected = -1;
2414 sector++;
2415 }
2416 }
2417 if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width))
2418 {
2419 LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
2420 (cfi_info->dev_size * bank->bus_width / bank->chip_width), offset);
2421 }
2422 }
2423
2424 cfi_info->probed = 1;
2425
2426 return ERROR_OK;
2427 }
2428
2429 static int cfi_auto_probe(struct flash_bank *bank)
2430 {
2431 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2432 if (cfi_info->probed)
2433 return ERROR_OK;
2434 return cfi_probe(bank);
2435 }
2436
2437
2438 static int cfi_intel_protect_check(struct flash_bank *bank)
2439 {
2440 int retval;
2441 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2442 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
2443 struct target *target = bank->target;
2444 uint8_t command[CFI_MAX_BUS_WIDTH];
2445 int i;
2446
2447 /* check if block lock bits are supported on this device */
2448 if (!(pri_ext->blk_status_reg_mask & 0x1))
2449 return ERROR_FLASH_OPERATION_FAILED;
2450
2451 cfi_command(bank, 0x90, command);
2452 if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2453 {
2454 return retval;
2455 }
2456
2457 for (i = 0; i < bank->num_sectors; i++)
2458 {
2459 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2460
2461 if (block_status & 1)
2462 bank->sectors[i].is_protected = 1;
2463 else
2464 bank->sectors[i].is_protected = 0;
2465 }
2466
2467 cfi_command(bank, 0xff, command);
2468 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2469 }
2470
2471 static int cfi_spansion_protect_check(struct flash_bank *bank)
2472 {
2473 int retval;
2474 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2475 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2476 struct target *target = bank->target;
2477 uint8_t command[8];
2478 int i;
2479
2480 cfi_command(bank, 0xaa, command);
2481 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2482 {
2483 return retval;
2484 }
2485
2486 cfi_command(bank, 0x55, command);
2487 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2488 {
2489 return retval;
2490 }
2491
2492 cfi_command(bank, 0x90, command);
2493 if ((retval = target_write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2494 {
2495 return retval;
2496 }
2497
2498 for (i = 0; i < bank->num_sectors; i++)
2499 {
2500 uint8_t block_status = cfi_get_u8(bank, i, 0x2);
2501
2502 if (block_status & 1)
2503 bank->sectors[i].is_protected = 1;
2504 else
2505 bank->sectors[i].is_protected = 0;
2506 }
2507
2508 cfi_command(bank, 0xf0, command);
2509 return target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2510 }
2511
2512 static int cfi_protect_check(struct flash_bank *bank)
2513 {
2514 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2515
2516 if (bank->target->state != TARGET_HALTED)
2517 {
2518 LOG_ERROR("Target not halted");
2519 return ERROR_TARGET_NOT_HALTED;
2520 }
2521
2522 if (cfi_info->qry[0] != 'Q')
2523 return ERROR_FLASH_BANK_NOT_PROBED;
2524
2525 switch (cfi_info->pri_id)
2526 {
2527 case 1:
2528 case 3:
2529 return cfi_intel_protect_check(bank);
2530 break;
2531 case 2:
2532 return cfi_spansion_protect_check(bank);
2533 break;
2534 default:
2535 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2536 break;
2537 }
2538
2539 return ERROR_OK;
2540 }
2541
2542 static int cfi_info(struct flash_bank *bank, char *buf, int buf_size)
2543 {
2544 int printed;
2545 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2546
2547 if (cfi_info->qry[0] == (char)-1)
2548 {
2549 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2550 return ERROR_OK;
2551 }
2552
2553 if (cfi_info->not_cfi == 0)
2554 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2555 else
2556 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2557 buf += printed;
2558 buf_size -= printed;
2559
2560 printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2561 cfi_info->manufacturer, cfi_info->device_id);
2562 buf += printed;
2563 buf_size -= printed;
2564
2565 if (cfi_info->not_cfi == 0)
2566 {
2567 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2568 buf += printed;
2569 buf_size -= printed;
2570
2571 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2572 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2573 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2574 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2575 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2576 buf += printed;
2577 buf_size -= printed;
2578
2579 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2580 1 << cfi_info->word_write_timeout_typ,
2581 1 << cfi_info->buf_write_timeout_typ,
2582 1 << cfi_info->block_erase_timeout_typ,
2583 1 << cfi_info->chip_erase_timeout_typ);
2584 buf += printed;
2585 buf_size -= printed;
2586
2587 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2588 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2589 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2590 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2591 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2592 buf += printed;
2593 buf_size -= printed;
2594
2595 printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: %x\n",
2596 cfi_info->dev_size,
2597 cfi_info->interface_desc,
2598 1 << cfi_info->max_buf_write_size);
2599 buf += printed;
2600 buf_size -= printed;
2601
2602 switch (cfi_info->pri_id)
2603 {
2604 case 1:
2605 case 3:
2606 cfi_intel_info(bank, buf, buf_size);
2607 break;
2608 case 2:
2609 cfi_spansion_info(bank, buf, buf_size);
2610 break;
2611 default:
2612 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2613 break;
2614 }
2615 }
2616
2617 return ERROR_OK;
2618 }
2619
2620 struct flash_driver cfi_flash = {
2621 .name = "cfi",
2622 .flash_bank_command = &cfi_flash_bank_command,
2623 .erase = &cfi_erase,
2624 .protect = &cfi_protect,
2625 .write = &cfi_write,
2626 .probe = &cfi_probe,
2627 .auto_probe = &cfi_auto_probe,
2628 .erase_check = &default_flash_blank_check,
2629 .protect_check = &cfi_protect_check,
2630 .info = &cfi_info,
2631 };
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