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opendous: Inhibit unnecessary state transitions
[openocd.git] / src / flash / nor / efm32.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 * *
11 * Copyright (C) 2013 by Roman Dmitrienko *
12 * me@iamroman.org *
13 *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
28 ***************************************************************************/
29
30 #ifdef HAVE_CONFIG_H
31 #include "config.h"
32 #endif
33
34 #include "imp.h"
35 #include <helper/binarybuffer.h>
36 #include <target/algorithm.h>
37 #include <target/armv7m.h>
38 #include <target/cortex_m.h>
39
40 /* keep family IDs in decimal */
41 #define EFM_FAMILY_ID_GECKO 71
42 #define EFM_FAMILY_ID_GIANT_GECKO 72
43 #define EFM_FAMILY_ID_TINY_GECKO 73
44 #define EFM_FAMILY_ID_LEOPARD_GECKO 74
45
46 #define EFM32_FLASH_ERASE_TMO 100
47 #define EFM32_FLASH_WDATAREADY_TMO 100
48 #define EFM32_FLASH_WRITE_TMO 100
49
50 /* size in bytes, not words; must fit all Gecko devices */
51 #define LOCKBITS_PAGE_SZ 512
52
53 #define EFM32_MSC_INFO_BASE 0x0fe00000
54
55 #define EFM32_MSC_USER_DATA EFM32_MSC_INFO_BASE
56 #define EFM32_MSC_LOCK_BITS (EFM32_MSC_INFO_BASE+0x4000)
57 #define EFM32_MSC_DEV_INFO (EFM32_MSC_INFO_BASE+0x8000)
58
59 /* PAGE_SIZE is only present in Leopard and Giant Gecko MCUs */
60 #define EFM32_MSC_DI_PAGE_SIZE (EFM32_MSC_DEV_INFO+0x1e7)
61 #define EFM32_MSC_DI_FLASH_SZ (EFM32_MSC_DEV_INFO+0x1f8)
62 #define EFM32_MSC_DI_RAM_SZ (EFM32_MSC_DEV_INFO+0x1fa)
63 #define EFM32_MSC_DI_PART_NUM (EFM32_MSC_DEV_INFO+0x1fc)
64 #define EFM32_MSC_DI_PART_FAMILY (EFM32_MSC_DEV_INFO+0x1fe)
65 #define EFM32_MSC_DI_PROD_REV (EFM32_MSC_DEV_INFO+0x1ff)
66
67 #define EFM32_MSC_REGBASE 0x400c0000
68 #define EFM32_MSC_WRITECTRL (EFM32_MSC_REGBASE+0x008)
69 #define EFM32_MSC_WRITECTRL_WREN_MASK 0x1
70 #define EFM32_MSC_WRITECMD (EFM32_MSC_REGBASE+0x00c)
71 #define EFM32_MSC_WRITECMD_LADDRIM_MASK 0x1
72 #define EFM32_MSC_WRITECMD_ERASEPAGE_MASK 0x2
73 #define EFM32_MSC_WRITECMD_WRITEONCE_MASK 0x8
74 #define EFM32_MSC_ADDRB (EFM32_MSC_REGBASE+0x010)
75 #define EFM32_MSC_WDATA (EFM32_MSC_REGBASE+0x018)
76 #define EFM32_MSC_STATUS (EFM32_MSC_REGBASE+0x01c)
77 #define EFM32_MSC_STATUS_BUSY_MASK 0x1
78 #define EFM32_MSC_STATUS_LOCKED_MASK 0x2
79 #define EFM32_MSC_STATUS_INVADDR_MASK 0x4
80 #define EFM32_MSC_STATUS_WDATAREADY_MASK 0x8
81 #define EFM32_MSC_STATUS_WORDTIMEOUT_MASK 0x10
82 #define EFM32_MSC_STATUS_ERASEABORTED_MASK 0x20
83 #define EFM32_MSC_LOCK (EFM32_MSC_REGBASE+0x03c)
84 #define EFM32_MSC_LOCK_LOCKKEY 0x1b71
85
86 struct efm32x_flash_bank {
87 int probed;
88 uint8_t lb_page[LOCKBITS_PAGE_SZ];
89 };
90
91 struct efm32_info {
92 uint16_t flash_sz_kib;
93 uint16_t ram_sz_kib;
94 uint16_t part_num;
95 uint8_t part_family;
96 uint8_t prod_rev;
97 uint16_t page_size;
98 };
99
100 static int efm32x_write(struct flash_bank *bank, uint8_t *buffer,
101 uint32_t offset, uint32_t count);
102
103 static int efm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_sz)
104 {
105 return target_read_u16(bank->target, EFM32_MSC_DI_FLASH_SZ, flash_sz);
106 }
107
108 static int efm32x_get_ram_size(struct flash_bank *bank, uint16_t *ram_sz)
109 {
110 return target_read_u16(bank->target, EFM32_MSC_DI_RAM_SZ, ram_sz);
111 }
112
113 static int efm32x_get_part_num(struct flash_bank *bank, uint16_t *pnum)
114 {
115 return target_read_u16(bank->target, EFM32_MSC_DI_PART_NUM, pnum);
116 }
117
118 static int efm32x_get_part_family(struct flash_bank *bank, uint8_t *pfamily)
119 {
120 return target_read_u8(bank->target, EFM32_MSC_DI_PART_FAMILY, pfamily);
121 }
122
123 static int efm32x_get_prod_rev(struct flash_bank *bank, uint8_t *prev)
124 {
125 return target_read_u8(bank->target, EFM32_MSC_DI_PROD_REV, prev);
126 }
127
128 static int efm32x_read_info(struct flash_bank *bank,
129 struct efm32_info *efm32_info)
130 {
131 int ret;
132 uint32_t cpuid = 0;
133
134 memset(efm32_info, 0, sizeof(struct efm32_info));
135
136 ret = target_read_u32(bank->target, CPUID, &cpuid);
137 if (ERROR_OK != ret)
138 return ret;
139
140 if (((cpuid >> 4) & 0xfff) == 0xc23) {
141 /* Cortex M3 device */
142 } else {
143 LOG_ERROR("Target is not CortexM3");
144 return ERROR_FAIL;
145 }
146
147 ret = efm32x_get_flash_size(bank, &(efm32_info->flash_sz_kib));
148 if (ERROR_OK != ret)
149 return ret;
150
151 ret = efm32x_get_ram_size(bank, &(efm32_info->ram_sz_kib));
152 if (ERROR_OK != ret)
153 return ret;
154
155 ret = efm32x_get_part_num(bank, &(efm32_info->part_num));
156 if (ERROR_OK != ret)
157 return ret;
158
159 ret = efm32x_get_part_family(bank, &(efm32_info->part_family));
160 if (ERROR_OK != ret)
161 return ret;
162
163 ret = efm32x_get_prod_rev(bank, &(efm32_info->prod_rev));
164 if (ERROR_OK != ret)
165 return ret;
166
167 if (EFM_FAMILY_ID_GECKO == efm32_info->part_family ||
168 EFM_FAMILY_ID_TINY_GECKO == efm32_info->part_family)
169 efm32_info->page_size = 512;
170 else if (EFM_FAMILY_ID_GIANT_GECKO == efm32_info->part_family ||
171 EFM_FAMILY_ID_LEOPARD_GECKO == efm32_info->part_family) {
172 uint8_t pg_size = 0;
173
174 ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
175 &pg_size);
176 if (ERROR_OK != ret)
177 return ret;
178
179 efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
180
181 if ((2048 != efm32_info->page_size) &&
182 (4096 != efm32_info->page_size)) {
183 LOG_ERROR("Invalid page size %u", efm32_info->page_size);
184 return ERROR_FAIL;
185 }
186 } else {
187 LOG_ERROR("Unknown MCU family %d", efm32_info->part_family);
188 return ERROR_FAIL;
189 }
190
191 return ERROR_OK;
192 }
193
194 /* flash bank efm32 <base> <size> 0 0 <target#>
195 */
196 FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command)
197 {
198 struct efm32x_flash_bank *efm32x_info;
199
200 if (CMD_ARGC < 6)
201 return ERROR_COMMAND_SYNTAX_ERROR;
202
203 efm32x_info = malloc(sizeof(struct efm32x_flash_bank));
204
205 bank->driver_priv = efm32x_info;
206 efm32x_info->probed = 0;
207 memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
208
209 return ERROR_OK;
210 }
211
212 /* set or reset given bits in a register */
213 static int efm32x_set_reg_bits(struct flash_bank *bank, uint32_t reg,
214 uint32_t bitmask, int set)
215 {
216 int ret = 0;
217 uint32_t reg_val = 0;
218
219 ret = target_read_u32(bank->target, reg, &reg_val);
220 if (ERROR_OK != ret)
221 return ret;
222
223 if (set)
224 reg_val |= bitmask;
225 else
226 reg_val &= ~bitmask;
227
228 return target_write_u32(bank->target, reg, reg_val);
229 }
230
231 static int efm32x_set_wren(struct flash_bank *bank, int write_enable)
232 {
233 return efm32x_set_reg_bits(bank, EFM32_MSC_WRITECTRL,
234 EFM32_MSC_WRITECTRL_WREN_MASK, write_enable);
235 }
236
237 static int efm32x_msc_lock(struct flash_bank *bank, int lock)
238 {
239 return target_write_u32(bank->target, EFM32_MSC_LOCK,
240 (lock ? 0 : EFM32_MSC_LOCK_LOCKKEY));
241 }
242
243 static int efm32x_wait_status(struct flash_bank *bank, int timeout,
244 uint32_t wait_mask, int wait_for_set)
245 {
246 int ret = 0;
247 uint32_t status = 0;
248
249 while (1) {
250 ret = target_read_u32(bank->target, EFM32_MSC_STATUS, &status);
251 if (ERROR_OK != ret)
252 break;
253
254 LOG_DEBUG("status: 0x%" PRIx32 "", status);
255
256 if (((status & wait_mask) == 0) && (0 == wait_for_set))
257 break;
258 else if (((status & wait_mask) != 0) && wait_for_set)
259 break;
260
261 if (timeout-- <= 0) {
262 LOG_ERROR("timed out waiting for MSC status");
263 return ERROR_FAIL;
264 }
265
266 alive_sleep(1);
267 }
268
269 if (status & EFM32_MSC_STATUS_ERASEABORTED_MASK)
270 LOG_WARNING("page erase was aborted");
271
272 return ret;
273 }
274
275 static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr)
276 {
277 /* this function DOES NOT set WREN; must be set already */
278 /* 1. write address to ADDRB
279 2. write LADDRIM
280 3. check status (INVADDR, LOCKED)
281 4. write ERASEPAGE
282 5. wait until !STATUS_BUSY
283 */
284 int ret = 0;
285 uint32_t status = 0;
286
287 LOG_DEBUG("erasing flash page at 0x%08x", addr);
288
289 ret = target_write_u32(bank->target, EFM32_MSC_ADDRB, addr);
290 if (ERROR_OK != ret)
291 return ret;
292
293 ret = efm32x_set_reg_bits(bank, EFM32_MSC_WRITECMD,
294 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
295 if (ERROR_OK != ret)
296 return ret;
297
298 ret = target_read_u32(bank->target, EFM32_MSC_STATUS, &status);
299 if (ERROR_OK != ret)
300 return ret;
301
302 LOG_DEBUG("status 0x%x", status);
303
304 if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
305 LOG_ERROR("Page is locked");
306 return ERROR_FAIL;
307 } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
308 LOG_ERROR("Invalid address 0x%x", addr);
309 return ERROR_FAIL;
310 }
311
312 ret = efm32x_set_reg_bits(bank, EFM32_MSC_WRITECMD,
313 EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
314 if (ERROR_OK != ret)
315 return ret;
316
317 return efm32x_wait_status(bank, EFM32_FLASH_ERASE_TMO,
318 EFM32_MSC_STATUS_BUSY_MASK, 0);
319 }
320
321 static int efm32x_erase(struct flash_bank *bank, int first, int last)
322 {
323 struct target *target = bank->target;
324 int i = 0;
325 int ret = 0;
326
327 if (TARGET_HALTED != target->state) {
328 LOG_ERROR("Target not halted");
329 return ERROR_TARGET_NOT_HALTED;
330 }
331
332 efm32x_msc_lock(bank, 0);
333 ret = efm32x_set_wren(bank, 1);
334 if (ERROR_OK != ret) {
335 LOG_ERROR("Failed to enable MSC write");
336 return ret;
337 }
338
339 for (i = first; i <= last; i++) {
340 ret = efm32x_erase_page(bank, bank->sectors[i].offset);
341 if (ERROR_OK != ret)
342 LOG_ERROR("Failed to erase page %d", i);
343 }
344
345 ret = efm32x_set_wren(bank, 0);
346 efm32x_msc_lock(bank, 1);
347
348 return ret;
349 }
350
351 static int efm32x_read_lock_data(struct flash_bank *bank)
352 {
353 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
354 struct target *target = bank->target;
355 int i = 0;
356 int data_size = 0;
357 uint32_t *ptr = NULL;
358 int ret = 0;
359
360 assert(!(bank->num_sectors & 0x1f));
361
362 data_size = bank->num_sectors / 8; /* number of data bytes */
363 data_size /= 4; /* ...and data dwords */
364
365 ptr = (uint32_t *)efm32x_info->lb_page;
366
367 for (i = 0; i < data_size; i++, ptr++) {
368 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+i*4, ptr);
369 if (ERROR_OK != ret) {
370 LOG_ERROR("Failed to read PLW %d", i);
371 return ret;
372 }
373 }
374
375 /* also, read ULW, DLW and MLW */
376
377 /* ULW, word 126 */
378 ptr = ((uint32_t *)efm32x_info->lb_page) + 126;
379 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+126*4, ptr);
380 if (ERROR_OK != ret) {
381 LOG_ERROR("Failed to read ULW");
382 return ret;
383 }
384
385 /* DLW, word 127 */
386 ptr = ((uint32_t *)efm32x_info->lb_page) + 127;
387 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+127*4, ptr);
388 if (ERROR_OK != ret) {
389 LOG_ERROR("Failed to read DLW");
390 return ret;
391 }
392
393 /* MLW, word 125, present in GG and LG */
394 ptr = ((uint32_t *)efm32x_info->lb_page) + 125;
395 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+125*4, ptr);
396 if (ERROR_OK != ret) {
397 LOG_ERROR("Failed to read MLW");
398 return ret;
399 }
400
401 return ERROR_OK;
402 }
403
404 static int efm32x_write_lock_data(struct flash_bank *bank)
405 {
406 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
407 int ret = 0;
408
409 ret = efm32x_erase_page(bank, EFM32_MSC_LOCK_BITS);
410 if (ERROR_OK != ret) {
411 LOG_ERROR("Failed to erase LB page");
412 return ret;
413 }
414
415 return efm32x_write(bank, efm32x_info->lb_page, EFM32_MSC_LOCK_BITS,
416 LOCKBITS_PAGE_SZ);
417 }
418
419 static int efm32x_get_page_lock(struct flash_bank *bank, size_t page)
420 {
421 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
422 uint32_t dw = ((uint32_t *)efm32x_info->lb_page)[page >> 5];
423 uint32_t mask = 0;
424
425 mask = 1 << (page & 0x1f);
426
427 return (dw & mask) ? 0 : 1;
428 }
429
430 static int efm32x_set_page_lock(struct flash_bank *bank, size_t page, int set)
431 {
432 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
433 uint32_t *dw = &((uint32_t *)efm32x_info->lb_page)[page >> 5];
434 uint32_t mask = 0;
435
436 mask = 1 << (page & 0x1f);
437
438 if (!set)
439 *dw |= mask;
440 else
441 *dw &= ~mask;
442
443 return ERROR_OK;
444 }
445
446 static int efm32x_protect(struct flash_bank *bank, int set, int first, int last)
447 {
448 struct target *target = bank->target;
449 int i = 0;
450 int ret = 0;
451
452 if (!set) {
453 LOG_ERROR("Erase device data to reset page locks");
454 return ERROR_FAIL;
455 }
456
457 if (target->state != TARGET_HALTED) {
458 LOG_ERROR("Target not halted");
459 return ERROR_TARGET_NOT_HALTED;
460 }
461
462 for (i = first; i <= last; i++) {
463 ret = efm32x_set_page_lock(bank, i, set);
464 if (ERROR_OK != ret) {
465 LOG_ERROR("Failed to set lock on page %d", i);
466 return ret;
467 }
468 }
469
470 ret = efm32x_write_lock_data(bank);
471 if (ERROR_OK != ret) {
472 LOG_ERROR("Failed to write LB page");
473 return ret;
474 }
475
476 return ERROR_OK;
477 }
478
479 static int efm32x_write_block(struct flash_bank *bank, uint8_t *buf,
480 uint32_t offset, uint32_t count)
481 {
482 struct target *target = bank->target;
483 uint32_t buffer_size = 16384;
484 struct working_area *write_algorithm;
485 struct working_area *source;
486 uint32_t address = bank->base + offset;
487 struct reg_param reg_params[5];
488 struct armv7m_algorithm armv7m_info;
489 int ret = ERROR_OK;
490
491 /* see contrib/loaders/flash/efm32.S for src */
492 static const uint8_t efm32x_flash_write_code[] = {
493 /* #define EFM32_MSC_WRITECTRL_OFFSET 0x008 */
494 /* #define EFM32_MSC_WRITECMD_OFFSET 0x00c */
495 /* #define EFM32_MSC_ADDRB_OFFSET 0x010 */
496 /* #define EFM32_MSC_WDATA_OFFSET 0x018 */
497 /* #define EFM32_MSC_STATUS_OFFSET 0x01c */
498 /* #define EFM32_MSC_LOCK_OFFSET 0x03c */
499
500 0x15, 0x4e, /* ldr r6, =#0x1b71 */
501 0xc6, 0x63, /* str r6, [r0, #EFM32_MSC_LOCK_OFFSET] */
502 0x01, 0x26, /* movs r6, #1 */
503 0x86, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET] */
504
505 /* wait_fifo: */
506 0x16, 0x68, /* ldr r6, [r2, #0] */
507 0x00, 0x2e, /* cmp r6, #0 */
508 0x22, 0xd0, /* beq exit */
509 0x55, 0x68, /* ldr r5, [r2, #4] */
510 0xb5, 0x42, /* cmp r5, r6 */
511 0xf9, 0xd0, /* beq wait_fifo */
512
513 0x04, 0x61, /* str r4, [r0, #EFM32_MSC_ADDRB_OFFSET] */
514 0x01, 0x26, /* movs r6, #1 */
515 0xc6, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
516 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
517 0x06, 0x27, /* movs r7, #6 */
518 0x3e, 0x42, /* tst r6, r7 */
519 0x16, 0xd1, /* bne error */
520
521 /* wait_wdataready: */
522 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
523 0x08, 0x27, /* movs r7, #8 */
524 0x3e, 0x42, /* tst r6, r7 */
525 0xfb, 0xd0, /* beq wait_wdataready */
526
527 0x2e, 0x68, /* ldr r6, [r5] */
528 0x86, 0x61, /* str r6, [r0, #EFM32_MSC_WDATA_OFFSET] */
529 0x08, 0x26, /* movs r6, #8 */
530 0xc6, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
531
532 0x04, 0x35, /* adds r5, #4 */
533 0x04, 0x34, /* adds r4, #4 */
534
535 /* busy: */
536 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
537 0x01, 0x27, /* movs r7, #1 */
538 0x3e, 0x42, /* tst r6, r7 */
539 0xfb, 0xd1, /* bne busy */
540
541 0x9d, 0x42, /* cmp r5, r3 */
542 0x01, 0xd3, /* bcc no_wrap */
543 0x15, 0x46, /* mov r5, r2 */
544 0x08, 0x35, /* adds r5, #8 */
545
546 /* no_wrap: */
547 0x55, 0x60, /* str r5, [r2, #4] */
548 0x01, 0x39, /* subs r1, r1, #1 */
549 0x00, 0x29, /* cmp r1, #0 */
550 0x02, 0xd0, /* beq exit */
551 0xdb, 0xe7, /* b wait_fifo */
552
553 /* error: */
554 0x00, 0x20, /* movs r0, #0 */
555 0x50, 0x60, /* str r0, [r2, #4] */
556
557 /* exit: */
558 0x30, 0x46, /* mov r0, r6 */
559 0x00, 0xbe, /* bkpt #0 */
560
561 /* LOCKKEY */
562 0x71, 0x1b, 0x00, 0x00
563 };
564
565 /* flash write code */
566 if (target_alloc_working_area(target, sizeof(efm32x_flash_write_code),
567 &write_algorithm) != ERROR_OK) {
568 LOG_WARNING("no working area available, can't do block memory writes");
569 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
570 };
571
572 ret = target_write_buffer(target, write_algorithm->address,
573 sizeof(efm32x_flash_write_code),
574 (uint8_t *)efm32x_flash_write_code);
575 if (ret != ERROR_OK)
576 return ret;
577
578 /* memory buffer */
579 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
580 buffer_size /= 2;
581 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
582 if (buffer_size <= 256) {
583 /* we already allocated the writing code, but failed to get a
584 * buffer, free the algorithm */
585 target_free_working_area(target, write_algorithm);
586
587 LOG_WARNING("no large enough working area available, can't do block memory writes");
588 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
589 }
590 };
591
592 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
593 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (word-32bit) */
594 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
595 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
596 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
597
598 buf_set_u32(reg_params[0].value, 0, 32, EFM32_MSC_REGBASE);
599 buf_set_u32(reg_params[1].value, 0, 32, count);
600 buf_set_u32(reg_params[2].value, 0, 32, source->address);
601 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
602 buf_set_u32(reg_params[4].value, 0, 32, address);
603
604 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
605 armv7m_info.core_mode = ARMV7M_MODE_ANY;
606
607 ret = target_run_flash_async_algorithm(target, buf, count, 4,
608 0, NULL,
609 5, reg_params,
610 source->address, source->size,
611 write_algorithm->address, 0,
612 &armv7m_info);
613
614 if (ret == ERROR_FLASH_OPERATION_FAILED) {
615 LOG_ERROR("flash write failed at address 0x%"PRIx32,
616 buf_get_u32(reg_params[4].value, 0, 32));
617
618 if (buf_get_u32(reg_params[0].value, 0, 32) &
619 EFM32_MSC_STATUS_LOCKED_MASK) {
620 LOG_ERROR("flash memory write protected");
621 }
622
623 if (buf_get_u32(reg_params[0].value, 0, 32) &
624 EFM32_MSC_STATUS_INVADDR_MASK) {
625 LOG_ERROR("invalid flash memory write address");
626 }
627 }
628
629 target_free_working_area(target, source);
630 target_free_working_area(target, write_algorithm);
631
632 destroy_reg_param(&reg_params[0]);
633 destroy_reg_param(&reg_params[1]);
634 destroy_reg_param(&reg_params[2]);
635 destroy_reg_param(&reg_params[3]);
636 destroy_reg_param(&reg_params[4]);
637
638 return ret;
639 }
640
641 static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
642 uint32_t val)
643 {
644 /* this function DOES NOT set WREN; must be set already */
645 /* 1. write address to ADDRB
646 2. write LADDRIM
647 3. check status (INVADDR, LOCKED)
648 4. wait for WDATAREADY
649 5. write data to WDATA
650 6. write WRITECMD_WRITEONCE to WRITECMD
651 7. wait until !STATUS_BUSY
652 */
653
654 /* FIXME: EFM32G ref states (7.3.2) that writes should be
655 * performed twice per dword */
656
657 int ret = 0;
658 uint32_t status = 0;
659
660 /* if not called, GDB errors will be reported during large writes */
661 keep_alive();
662
663 ret = target_write_u32(bank->target, EFM32_MSC_ADDRB, addr);
664 if (ERROR_OK != ret)
665 return ret;
666
667 ret = efm32x_set_reg_bits(bank, EFM32_MSC_WRITECMD,
668 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
669 if (ERROR_OK != ret)
670 return ret;
671
672 ret = target_read_u32(bank->target, EFM32_MSC_STATUS, &status);
673 if (ERROR_OK != ret)
674 return ret;
675
676 LOG_DEBUG("status 0x%x", status);
677
678 if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
679 LOG_ERROR("Page is locked");
680 return ERROR_FAIL;
681 } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
682 LOG_ERROR("Invalid address 0x%x", addr);
683 return ERROR_FAIL;
684 }
685
686 ret = efm32x_wait_status(bank, EFM32_FLASH_WDATAREADY_TMO,
687 EFM32_MSC_STATUS_WDATAREADY_MASK, 1);
688 if (ERROR_OK != ret) {
689 LOG_ERROR("Wait for WDATAREADY failed");
690 return ret;
691 }
692
693 ret = target_write_u32(bank->target, EFM32_MSC_WDATA, val);
694 if (ERROR_OK != ret) {
695 LOG_ERROR("WDATA write failed");
696 return ret;
697 }
698
699 ret = target_write_u32(bank->target, EFM32_MSC_WRITECMD,
700 EFM32_MSC_WRITECMD_WRITEONCE_MASK);
701 if (ERROR_OK != ret) {
702 LOG_ERROR("WRITECMD write failed");
703 return ret;
704 }
705
706 ret = efm32x_wait_status(bank, EFM32_FLASH_WRITE_TMO,
707 EFM32_MSC_STATUS_BUSY_MASK, 0);
708 if (ERROR_OK != ret) {
709 LOG_ERROR("Wait for BUSY failed");
710 return ret;
711 }
712
713 return ERROR_OK;
714 }
715
716 static int efm32x_write(struct flash_bank *bank, uint8_t *buffer,
717 uint32_t offset, uint32_t count)
718 {
719 struct target *target = bank->target;
720 uint8_t *new_buffer = NULL;
721
722 if (target->state != TARGET_HALTED) {
723 LOG_ERROR("Target not halted");
724 return ERROR_TARGET_NOT_HALTED;
725 }
726
727 if (offset & 0x3) {
728 LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte "
729 "alignment", offset);
730 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
731 }
732
733 if (count & 0x3) {
734 uint32_t old_count = count;
735 count = (old_count | 3) + 1;
736 new_buffer = malloc(count);
737 if (new_buffer == NULL) {
738 LOG_ERROR("odd number of bytes to write and no memory "
739 "for padding buffer");
740 return ERROR_FAIL;
741 }
742 LOG_INFO("odd number of bytes to write (%d), extending to %d "
743 "and padding with 0xff", old_count, count);
744 memset(buffer, 0xff, count);
745 buffer = memcpy(new_buffer, buffer, old_count);
746 }
747
748 uint32_t words_remaining = count / 4;
749 int retval, retval2;
750
751 /* unlock flash registers */
752 efm32x_msc_lock(bank, 0);
753 retval = efm32x_set_wren(bank, 1);
754 if (retval != ERROR_OK)
755 goto cleanup;
756
757 /* try using a block write */
758 retval = efm32x_write_block(bank, buffer, offset, words_remaining);
759
760 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
761 /* if block write failed (no sufficient working area),
762 * we use normal (slow) single word accesses */
763 LOG_WARNING("couldn't use block writes, falling back to single "
764 "memory accesses");
765
766 while (words_remaining > 0) {
767 uint32_t value;
768 memcpy(&value, buffer, sizeof(uint32_t));
769
770 retval = efm32x_write_word(bank, offset, value);
771 if (retval != ERROR_OK)
772 goto reset_pg_and_lock;
773
774 words_remaining--;
775 buffer += 4;
776 offset += 4;
777 }
778 }
779
780 reset_pg_and_lock:
781 retval2 = efm32x_set_wren(bank, 0);
782 efm32x_msc_lock(bank, 1);
783 if (retval == ERROR_OK)
784 retval = retval2;
785
786 cleanup:
787 if (new_buffer)
788 free(new_buffer);
789
790 return retval;
791 }
792
793 static int efm32x_probe(struct flash_bank *bank)
794 {
795 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
796 struct efm32_info efm32_mcu_info;
797 int ret;
798 int i;
799 uint32_t base_address = 0x00000000;
800
801 efm32x_info->probed = 0;
802 memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
803
804 ret = efm32x_read_info(bank, &efm32_mcu_info);
805 if (ERROR_OK != ret)
806 return ret;
807
808 switch (efm32_mcu_info.part_family) {
809 case EFM_FAMILY_ID_GECKO:
810 LOG_INFO("Gecko MCU detected");
811 break;
812 case EFM_FAMILY_ID_GIANT_GECKO:
813 LOG_INFO("Giant Gecko MCU detected");
814 break;
815 case EFM_FAMILY_ID_TINY_GECKO:
816 LOG_INFO("Tiny Gecko MCU detected");
817 break;
818 case EFM_FAMILY_ID_LEOPARD_GECKO:
819 LOG_INFO("Leopard Gecko MCU detected");
820 break;
821 default:
822 LOG_ERROR("Unsupported MCU family %d",
823 efm32_mcu_info.part_family);
824 return ERROR_FAIL;
825 }
826
827 LOG_INFO("flash size = %dkbytes", efm32_mcu_info.flash_sz_kib);
828 LOG_INFO("flash page size = %dbytes", efm32_mcu_info.page_size);
829
830 assert(0 != efm32_mcu_info.page_size);
831
832 int num_pages = efm32_mcu_info.flash_sz_kib * 1024 /
833 efm32_mcu_info.page_size;
834
835 assert(num_pages > 0);
836
837 if (bank->sectors) {
838 free(bank->sectors);
839 bank->sectors = NULL;
840 }
841
842 bank->base = base_address;
843 bank->size = (num_pages * efm32_mcu_info.page_size);
844 bank->num_sectors = num_pages;
845
846 ret = efm32x_read_lock_data(bank);
847 if (ERROR_OK != ret) {
848 LOG_ERROR("Failed to read LB data");
849 return ret;
850 }
851
852 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
853
854 for (i = 0; i < num_pages; i++) {
855 bank->sectors[i].offset = i * efm32_mcu_info.page_size;
856 bank->sectors[i].size = efm32_mcu_info.page_size;
857 bank->sectors[i].is_erased = -1;
858 bank->sectors[i].is_protected = 1;
859 }
860
861 efm32x_info->probed = 1;
862
863 return ERROR_OK;
864 }
865
866 static int efm32x_auto_probe(struct flash_bank *bank)
867 {
868 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
869 if (efm32x_info->probed)
870 return ERROR_OK;
871 return efm32x_probe(bank);
872 }
873
874 static int efm32x_protect_check(struct flash_bank *bank)
875 {
876 struct target *target = bank->target;
877 int ret = 0;
878 int i = 0;
879
880 if (target->state != TARGET_HALTED) {
881 LOG_ERROR("Target not halted");
882 return ERROR_TARGET_NOT_HALTED;
883 }
884
885 ret = efm32x_read_lock_data(bank);
886 if (ERROR_OK != ret) {
887 LOG_ERROR("Failed to read LB data");
888 return ret;
889 }
890
891 assert(NULL != bank->sectors);
892
893 for (i = 0; i < bank->num_sectors; i++)
894 bank->sectors[i].is_protected = efm32x_get_page_lock(bank, i);
895
896 return ERROR_OK;
897 }
898
899 static int get_efm32x_info(struct flash_bank *bank, char *buf, int buf_size)
900 {
901 struct efm32_info info;
902 int ret = 0;
903 int printed = 0;
904
905 ret = efm32x_read_info(bank, &info);
906 if (ERROR_OK != ret) {
907 LOG_ERROR("Failed to read EFM32 info");
908 return ret;
909 }
910
911 printed = snprintf(buf, buf_size, "EFM32 ");
912 buf += printed;
913 buf_size -= printed;
914
915 if (0 >= buf_size)
916 return ERROR_BUF_TOO_SMALL;
917
918 switch (info.part_family) {
919 case EFM_FAMILY_ID_GECKO:
920 printed = snprintf(buf, buf_size, "Gecko");
921 break;
922 case EFM_FAMILY_ID_GIANT_GECKO:
923 printed = snprintf(buf, buf_size, "Giant Gecko");
924 break;
925 case EFM_FAMILY_ID_TINY_GECKO:
926 printed = snprintf(buf, buf_size, "Tiny Gecko");
927 break;
928 case EFM_FAMILY_ID_LEOPARD_GECKO:
929 printed = snprintf(buf, buf_size, "Leopard Gecko");
930 break;
931 }
932
933 buf += printed;
934 buf_size -= printed;
935
936 if (0 >= buf_size)
937 return ERROR_BUF_TOO_SMALL;
938
939 printed = snprintf(buf, buf_size, " - Rev: %d", info.prod_rev);
940 buf += printed;
941 buf_size -= printed;
942
943 if (0 >= buf_size)
944 return ERROR_BUF_TOO_SMALL;
945
946 return ERROR_OK;
947 }
948
949 static const struct command_registration efm32x_exec_command_handlers[] = {
950 COMMAND_REGISTRATION_DONE
951 };
952
953 static const struct command_registration efm32x_command_handlers[] = {
954 {
955 .name = "efm32",
956 .mode = COMMAND_ANY,
957 .help = "efm32 flash command group",
958 .usage = "",
959 .chain = efm32x_exec_command_handlers,
960 },
961 COMMAND_REGISTRATION_DONE
962 };
963
964 struct flash_driver efm32_flash = {
965 .name = "efm32",
966 .commands = efm32x_command_handlers,
967 .flash_bank_command = efm32x_flash_bank_command,
968 .erase = efm32x_erase,
969 .protect = efm32x_protect,
970 .write = efm32x_write,
971 .read = default_flash_read,
972 .probe = efm32x_probe,
973 .auto_probe = efm32x_auto_probe,
974 .erase_check = default_flash_blank_check,
975 .protect_check = efm32x_protect_check,
976 .info = get_efm32x_info,
977 };
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