Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
flash: efm32: add support for EFR-familty (e.g. bluegecko)
[openocd.git] / src / flash / nor / efm32.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 * *
11 * Copyright (C) 2013 by Roman Dmitrienko *
12 * me@iamroman.org *
13 * *
14 * Copyright (C) 2014 Nemui Trinomius *
15 * nemuisan_kawausogasuki@live.jp *
16 * *
17 * This program is free software; you can redistribute it and/or modify *
18 * it under the terms of the GNU General Public License as published by *
19 * the Free Software Foundation; either version 2 of the License, or *
20 * (at your option) any later version. *
21 * *
22 * This program is distributed in the hope that it will be useful, *
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
25 * GNU General Public License for more details. *
26 * *
27 * You should have received a copy of the GNU General Public License *
28 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
29 ***************************************************************************/
30
31 #ifdef HAVE_CONFIG_H
32 #include "config.h"
33 #endif
34
35 #include "imp.h"
36 #include <helper/binarybuffer.h>
37 #include <target/algorithm.h>
38 #include <target/armv7m.h>
39 #include <target/cortex_m.h>
40
41 /* keep family IDs in decimal */
42 #define EFM_FAMILY_ID_GECKO 71
43 #define EFM_FAMILY_ID_GIANT_GECKO 72
44 #define EFM_FAMILY_ID_TINY_GECKO 73
45 #define EFM_FAMILY_ID_LEOPARD_GECKO 74
46 #define EFM_FAMILY_ID_WONDER_GECKO 75
47 #define EFM_FAMILY_ID_ZERO_GECKO 76
48 #define EFM_FAMILY_ID_HAPPY_GECKO 77
49 #define EZR_FAMILY_ID_WONDER_GECKO 120
50 #define EZR_FAMILY_ID_LEOPARD_GECKO 121
51 #define EZR_FAMILY_ID_HAPPY_GECKO 122
52 #define EFR_FAMILY_ID_MIGHTY_GECKO 16
53 #define EFR_FAMILY_ID_BLUE_GECKO 20
54
55 #define EFM32_FLASH_ERASE_TMO 100
56 #define EFM32_FLASH_WDATAREADY_TMO 100
57 #define EFM32_FLASH_WRITE_TMO 100
58
59 /* size in bytes, not words; must fit all Gecko devices */
60 #define LOCKBITS_PAGE_SZ 512
61
62 #define EFM32_MSC_INFO_BASE 0x0fe00000
63
64 #define EFM32_MSC_USER_DATA EFM32_MSC_INFO_BASE
65 #define EFM32_MSC_LOCK_BITS (EFM32_MSC_INFO_BASE+0x4000)
66 #define EFM32_MSC_DEV_INFO (EFM32_MSC_INFO_BASE+0x8000)
67
68 /* PAGE_SIZE is only present in Leopard, Giant and Wonder Gecko MCUs */
69 #define EFM32_MSC_DI_PAGE_SIZE (EFM32_MSC_DEV_INFO+0x1e7)
70 #define EFM32_MSC_DI_FLASH_SZ (EFM32_MSC_DEV_INFO+0x1f8)
71 #define EFM32_MSC_DI_RAM_SZ (EFM32_MSC_DEV_INFO+0x1fa)
72 #define EFM32_MSC_DI_PART_NUM (EFM32_MSC_DEV_INFO+0x1fc)
73 #define EFM32_MSC_DI_PART_FAMILY (EFM32_MSC_DEV_INFO+0x1fe)
74 #define EFM32_MSC_DI_PROD_REV (EFM32_MSC_DEV_INFO+0x1ff)
75
76 #define EFM32_MSC_REGBASE 0x400c0000
77 #define EFR32_MSC_REGBASE 0x400e0000
78 #define EFM32_MSC_REG_WRITECTRL 0x008
79 #define EFM32_MSC_WRITECTRL_WREN_MASK 0x1
80 #define EFM32_MSC_REG_WRITECMD 0x00c
81 #define EFM32_MSC_WRITECMD_LADDRIM_MASK 0x1
82 #define EFM32_MSC_WRITECMD_ERASEPAGE_MASK 0x2
83 #define EFM32_MSC_WRITECMD_WRITEONCE_MASK 0x8
84 #define EFM32_MSC_REG_ADDRB 0x010
85 #define EFM32_MSC_REG_WDATA 0x018
86 #define EFM32_MSC_REG_STATUS 0x01c
87 #define EFM32_MSC_STATUS_BUSY_MASK 0x1
88 #define EFM32_MSC_STATUS_LOCKED_MASK 0x2
89 #define EFM32_MSC_STATUS_INVADDR_MASK 0x4
90 #define EFM32_MSC_STATUS_WDATAREADY_MASK 0x8
91 #define EFM32_MSC_STATUS_WORDTIMEOUT_MASK 0x10
92 #define EFM32_MSC_STATUS_ERASEABORTED_MASK 0x20
93 #define EFM32_MSC_REG_LOCK 0x03c
94 #define EFR32_MSC_REG_LOCK 0x040
95 #define EFM32_MSC_LOCK_LOCKKEY 0x1b71
96
97 struct efm32x_flash_bank {
98 int probed;
99 uint32_t lb_page[LOCKBITS_PAGE_SZ/4];
100 uint32_t reg_base;
101 uint32_t reg_lock;
102 };
103
104 struct efm32_info {
105 uint16_t flash_sz_kib;
106 uint16_t ram_sz_kib;
107 uint16_t part_num;
108 uint8_t part_family;
109 uint8_t prod_rev;
110 uint16_t page_size;
111 };
112
113 static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
114 uint32_t offset, uint32_t count);
115
116 static int efm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_sz)
117 {
118 return target_read_u16(bank->target, EFM32_MSC_DI_FLASH_SZ, flash_sz);
119 }
120
121 static int efm32x_get_ram_size(struct flash_bank *bank, uint16_t *ram_sz)
122 {
123 return target_read_u16(bank->target, EFM32_MSC_DI_RAM_SZ, ram_sz);
124 }
125
126 static int efm32x_get_part_num(struct flash_bank *bank, uint16_t *pnum)
127 {
128 return target_read_u16(bank->target, EFM32_MSC_DI_PART_NUM, pnum);
129 }
130
131 static int efm32x_get_part_family(struct flash_bank *bank, uint8_t *pfamily)
132 {
133 return target_read_u8(bank->target, EFM32_MSC_DI_PART_FAMILY, pfamily);
134 }
135
136 static int efm32x_get_prod_rev(struct flash_bank *bank, uint8_t *prev)
137 {
138 return target_read_u8(bank->target, EFM32_MSC_DI_PROD_REV, prev);
139 }
140
141 static int efm32x_read_reg_u32(struct flash_bank *bank, target_addr_t offset,
142 uint32_t *value)
143 {
144 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
145 uint32_t base = efm32x_info->reg_base;
146
147 return target_read_u32(bank->target, base + offset, value);
148 }
149
150 static int efm32x_write_reg_u32(struct flash_bank *bank, target_addr_t offset,
151 uint32_t value)
152 {
153 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
154 uint32_t base = efm32x_info->reg_base;
155
156 return target_write_u32(bank->target, base + offset, value);
157 }
158
159 static int efm32x_read_info(struct flash_bank *bank,
160 struct efm32_info *efm32_info)
161 {
162 int ret;
163 uint32_t cpuid = 0;
164 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
165
166 memset(efm32_info, 0, sizeof(struct efm32_info));
167
168 ret = target_read_u32(bank->target, CPUID, &cpuid);
169 if (ERROR_OK != ret)
170 return ret;
171
172 if (((cpuid >> 4) & 0xfff) == 0xc23) {
173 /* Cortex-M3 device */
174 } else if (((cpuid >> 4) & 0xfff) == 0xc24) {
175 /* Cortex-M4 device (WONDER GECKO) */
176 } else if (((cpuid >> 4) & 0xfff) == 0xc60) {
177 /* Cortex-M0+ device */
178 } else {
179 LOG_ERROR("Target is not Cortex-Mx Device");
180 return ERROR_FAIL;
181 }
182
183 ret = efm32x_get_flash_size(bank, &(efm32_info->flash_sz_kib));
184 if (ERROR_OK != ret)
185 return ret;
186
187 ret = efm32x_get_ram_size(bank, &(efm32_info->ram_sz_kib));
188 if (ERROR_OK != ret)
189 return ret;
190
191 ret = efm32x_get_part_num(bank, &(efm32_info->part_num));
192 if (ERROR_OK != ret)
193 return ret;
194
195 ret = efm32x_get_part_family(bank, &(efm32_info->part_family));
196 if (ERROR_OK != ret)
197 return ret;
198
199 ret = efm32x_get_prod_rev(bank, &(efm32_info->prod_rev));
200 if (ERROR_OK != ret)
201 return ret;
202
203 if (EFR_FAMILY_ID_BLUE_GECKO == efm32_info->part_family ||
204 EFR_FAMILY_ID_MIGHTY_GECKO == efm32_info->part_family) {
205 efm32x_info->reg_base = EFR32_MSC_REGBASE;
206 efm32x_info->reg_lock = EFR32_MSC_REG_LOCK;
207 } else {
208 efm32x_info->reg_base = EFM32_MSC_REGBASE;
209 efm32x_info->reg_lock = EFM32_MSC_REG_LOCK;
210 }
211
212 if (EFM_FAMILY_ID_GECKO == efm32_info->part_family ||
213 EFM_FAMILY_ID_TINY_GECKO == efm32_info->part_family)
214 efm32_info->page_size = 512;
215 else if (EFM_FAMILY_ID_ZERO_GECKO == efm32_info->part_family ||
216 EFM_FAMILY_ID_HAPPY_GECKO == efm32_info->part_family ||
217 EZR_FAMILY_ID_HAPPY_GECKO == efm32_info->part_family)
218 efm32_info->page_size = 1024;
219 else if (EFM_FAMILY_ID_GIANT_GECKO == efm32_info->part_family ||
220 EFM_FAMILY_ID_LEOPARD_GECKO == efm32_info->part_family) {
221 if (efm32_info->prod_rev >= 18) {
222 uint8_t pg_size = 0;
223 ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
224 &pg_size);
225 if (ERROR_OK != ret)
226 return ret;
227
228 efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
229 } else {
230 /* EFM32 GG/LG errata: MEM_INFO_PAGE_SIZE is invalid
231 for MCUs with PROD_REV < 18 */
232 if (efm32_info->flash_sz_kib < 512)
233 efm32_info->page_size = 2048;
234 else
235 efm32_info->page_size = 4096;
236 }
237
238 if ((2048 != efm32_info->page_size) &&
239 (4096 != efm32_info->page_size)) {
240 LOG_ERROR("Invalid page size %u", efm32_info->page_size);
241 return ERROR_FAIL;
242 }
243 } else if (EFM_FAMILY_ID_WONDER_GECKO == efm32_info->part_family ||
244 EZR_FAMILY_ID_WONDER_GECKO == efm32_info->part_family ||
245 EZR_FAMILY_ID_LEOPARD_GECKO == efm32_info->part_family ||
246 EFR_FAMILY_ID_BLUE_GECKO == efm32_info->part_family ||
247 EFR_FAMILY_ID_MIGHTY_GECKO == efm32_info->part_family) {
248 uint8_t pg_size = 0;
249 ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
250 &pg_size);
251 if (ERROR_OK != ret)
252 return ret;
253
254 efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
255 if (2048 != efm32_info->page_size) {
256 LOG_ERROR("Invalid page size %u", efm32_info->page_size);
257 return ERROR_FAIL;
258 }
259 } else {
260 LOG_ERROR("Unknown MCU family %d", efm32_info->part_family);
261 return ERROR_FAIL;
262 }
263
264 return ERROR_OK;
265 }
266
267 /*
268 * Helper to create a human friendly string describing a part
269 */
270 static int efm32x_decode_info(struct efm32_info *info, char *buf, int buf_size)
271 {
272 int printed = 0;
273
274 switch (info->part_family) {
275 case EZR_FAMILY_ID_WONDER_GECKO:
276 case EZR_FAMILY_ID_LEOPARD_GECKO:
277 case EZR_FAMILY_ID_HAPPY_GECKO:
278 printed = snprintf(buf, buf_size, "EZR32 ");
279 break;
280 case EFR_FAMILY_ID_MIGHTY_GECKO:
281 case EFR_FAMILY_ID_BLUE_GECKO:
282 printed = snprintf(buf, buf_size, "EFR32 ");
283 break;
284 default:
285 printed = snprintf(buf, buf_size, "EFM32 ");
286 }
287
288 buf += printed;
289 buf_size -= printed;
290
291 if (0 >= buf_size)
292 return ERROR_BUF_TOO_SMALL;
293
294 switch (info->part_family) {
295 case EFM_FAMILY_ID_GECKO:
296 printed = snprintf(buf, buf_size, "Gecko");
297 break;
298 case EFM_FAMILY_ID_GIANT_GECKO:
299 printed = snprintf(buf, buf_size, "Giant Gecko");
300 break;
301 case EFM_FAMILY_ID_TINY_GECKO:
302 printed = snprintf(buf, buf_size, "Tiny Gecko");
303 break;
304 case EFM_FAMILY_ID_LEOPARD_GECKO:
305 case EZR_FAMILY_ID_LEOPARD_GECKO:
306 printed = snprintf(buf, buf_size, "Leopard Gecko");
307 break;
308 case EFM_FAMILY_ID_WONDER_GECKO:
309 case EZR_FAMILY_ID_WONDER_GECKO:
310 printed = snprintf(buf, buf_size, "Wonder Gecko");
311 break;
312 case EFM_FAMILY_ID_ZERO_GECKO:
313 printed = snprintf(buf, buf_size, "Zero Gecko");
314 break;
315 case EFM_FAMILY_ID_HAPPY_GECKO:
316 case EZR_FAMILY_ID_HAPPY_GECKO:
317 printed = snprintf(buf, buf_size, "Happy Gecko");
318 break;
319 case EFR_FAMILY_ID_BLUE_GECKO:
320 printed = snprintf(buf, buf_size, "Blue Gecko");
321 break;
322 case EFR_FAMILY_ID_MIGHTY_GECKO:
323 printed = snprintf(buf, buf_size, "Mighty Gecko");
324 break;
325 }
326
327 buf += printed;
328 buf_size -= printed;
329
330 if (0 >= buf_size)
331 return ERROR_BUF_TOO_SMALL;
332
333 printed = snprintf(buf, buf_size, " - Rev: %d", info->prod_rev);
334 buf += printed;
335 buf_size -= printed;
336
337 if (0 >= buf_size)
338 return ERROR_BUF_TOO_SMALL;
339
340 return ERROR_OK;
341 }
342
343 /* flash bank efm32 <base> <size> 0 0 <target#>
344 */
345 FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command)
346 {
347 struct efm32x_flash_bank *efm32x_info;
348
349 if (CMD_ARGC < 6)
350 return ERROR_COMMAND_SYNTAX_ERROR;
351
352 efm32x_info = malloc(sizeof(struct efm32x_flash_bank));
353
354 bank->driver_priv = efm32x_info;
355 efm32x_info->probed = 0;
356 memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
357
358 return ERROR_OK;
359 }
360
361 /* set or reset given bits in a register */
362 static int efm32x_set_reg_bits(struct flash_bank *bank, uint32_t reg,
363 uint32_t bitmask, int set)
364 {
365 int ret = 0;
366 uint32_t reg_val = 0;
367
368 ret = efm32x_read_reg_u32(bank, reg, &reg_val);
369 if (ERROR_OK != ret)
370 return ret;
371
372 if (set)
373 reg_val |= bitmask;
374 else
375 reg_val &= ~bitmask;
376
377 return efm32x_write_reg_u32(bank, reg, reg_val);
378 }
379
380 static int efm32x_set_wren(struct flash_bank *bank, int write_enable)
381 {
382 return efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECTRL,
383 EFM32_MSC_WRITECTRL_WREN_MASK, write_enable);
384 }
385
386 static int efm32x_msc_lock(struct flash_bank *bank, int lock)
387 {
388 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
389 return efm32x_write_reg_u32(bank, efm32x_info->reg_lock,
390 (lock ? 0 : EFM32_MSC_LOCK_LOCKKEY));
391 }
392
393 static int efm32x_wait_status(struct flash_bank *bank, int timeout,
394 uint32_t wait_mask, int wait_for_set)
395 {
396 int ret = 0;
397 uint32_t status = 0;
398
399 while (1) {
400 ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
401 if (ERROR_OK != ret)
402 break;
403
404 LOG_DEBUG("status: 0x%" PRIx32 "", status);
405
406 if (((status & wait_mask) == 0) && (0 == wait_for_set))
407 break;
408 else if (((status & wait_mask) != 0) && wait_for_set)
409 break;
410
411 if (timeout-- <= 0) {
412 LOG_ERROR("timed out waiting for MSC status");
413 return ERROR_FAIL;
414 }
415
416 alive_sleep(1);
417 }
418
419 if (status & EFM32_MSC_STATUS_ERASEABORTED_MASK)
420 LOG_WARNING("page erase was aborted");
421
422 return ret;
423 }
424
425 static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr)
426 {
427 /* this function DOES NOT set WREN; must be set already */
428 /* 1. write address to ADDRB
429 2. write LADDRIM
430 3. check status (INVADDR, LOCKED)
431 4. write ERASEPAGE
432 5. wait until !STATUS_BUSY
433 */
434 int ret = 0;
435 uint32_t status = 0;
436
437 LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr);
438
439 ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
440 if (ERROR_OK != ret)
441 return ret;
442
443 ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
444 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
445 if (ERROR_OK != ret)
446 return ret;
447
448 ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
449 if (ERROR_OK != ret)
450 return ret;
451
452 LOG_DEBUG("status 0x%" PRIx32, status);
453
454 if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
455 LOG_ERROR("Page is locked");
456 return ERROR_FAIL;
457 } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
458 LOG_ERROR("Invalid address 0x%" PRIx32, addr);
459 return ERROR_FAIL;
460 }
461
462 ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
463 EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
464 if (ERROR_OK != ret)
465 return ret;
466
467 return efm32x_wait_status(bank, EFM32_FLASH_ERASE_TMO,
468 EFM32_MSC_STATUS_BUSY_MASK, 0);
469 }
470
471 static int efm32x_erase(struct flash_bank *bank, int first, int last)
472 {
473 struct target *target = bank->target;
474 int i = 0;
475 int ret = 0;
476
477 if (TARGET_HALTED != target->state) {
478 LOG_ERROR("Target not halted");
479 return ERROR_TARGET_NOT_HALTED;
480 }
481
482 efm32x_msc_lock(bank, 0);
483 ret = efm32x_set_wren(bank, 1);
484 if (ERROR_OK != ret) {
485 LOG_ERROR("Failed to enable MSC write");
486 return ret;
487 }
488
489 for (i = first; i <= last; i++) {
490 ret = efm32x_erase_page(bank, bank->sectors[i].offset);
491 if (ERROR_OK != ret)
492 LOG_ERROR("Failed to erase page %d", i);
493 }
494
495 ret = efm32x_set_wren(bank, 0);
496 efm32x_msc_lock(bank, 1);
497
498 return ret;
499 }
500
501 static int efm32x_read_lock_data(struct flash_bank *bank)
502 {
503 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
504 struct target *target = bank->target;
505 int i = 0;
506 int data_size = 0;
507 uint32_t *ptr = NULL;
508 int ret = 0;
509
510 assert(bank->num_sectors > 0);
511
512 /* calculate the number of 32-bit words to read (one lock bit per sector) */
513 data_size = (bank->num_sectors + 31) / 32;
514
515 ptr = efm32x_info->lb_page;
516
517 for (i = 0; i < data_size; i++, ptr++) {
518 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+i*4, ptr);
519 if (ERROR_OK != ret) {
520 LOG_ERROR("Failed to read PLW %d", i);
521 return ret;
522 }
523 }
524
525 /* also, read ULW, DLW and MLW */
526
527 /* ULW, word 126 */
528 ptr = efm32x_info->lb_page + 126;
529 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+126*4, ptr);
530 if (ERROR_OK != ret) {
531 LOG_ERROR("Failed to read ULW");
532 return ret;
533 }
534
535 /* DLW, word 127 */
536 ptr = efm32x_info->lb_page + 127;
537 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+127*4, ptr);
538 if (ERROR_OK != ret) {
539 LOG_ERROR("Failed to read DLW");
540 return ret;
541 }
542
543 /* MLW, word 125, present in GG and LG */
544 ptr = efm32x_info->lb_page + 125;
545 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+125*4, ptr);
546 if (ERROR_OK != ret) {
547 LOG_ERROR("Failed to read MLW");
548 return ret;
549 }
550
551 return ERROR_OK;
552 }
553
554 static int efm32x_write_lock_data(struct flash_bank *bank)
555 {
556 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
557 int ret = 0;
558
559 ret = efm32x_erase_page(bank, EFM32_MSC_LOCK_BITS);
560 if (ERROR_OK != ret) {
561 LOG_ERROR("Failed to erase LB page");
562 return ret;
563 }
564
565 return efm32x_write(bank, (uint8_t *)efm32x_info->lb_page, EFM32_MSC_LOCK_BITS,
566 LOCKBITS_PAGE_SZ);
567 }
568
569 static int efm32x_get_page_lock(struct flash_bank *bank, size_t page)
570 {
571 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
572 uint32_t dw = efm32x_info->lb_page[page >> 5];
573 uint32_t mask = 0;
574
575 mask = 1 << (page & 0x1f);
576
577 return (dw & mask) ? 0 : 1;
578 }
579
580 static int efm32x_set_page_lock(struct flash_bank *bank, size_t page, int set)
581 {
582 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
583 uint32_t *dw = &efm32x_info->lb_page[page >> 5];
584 uint32_t mask = 0;
585
586 mask = 1 << (page & 0x1f);
587
588 if (!set)
589 *dw |= mask;
590 else
591 *dw &= ~mask;
592
593 return ERROR_OK;
594 }
595
596 static int efm32x_protect(struct flash_bank *bank, int set, int first, int last)
597 {
598 struct target *target = bank->target;
599 int i = 0;
600 int ret = 0;
601
602 if (!set) {
603 LOG_ERROR("Erase device data to reset page locks");
604 return ERROR_FAIL;
605 }
606
607 if (target->state != TARGET_HALTED) {
608 LOG_ERROR("Target not halted");
609 return ERROR_TARGET_NOT_HALTED;
610 }
611
612 for (i = first; i <= last; i++) {
613 ret = efm32x_set_page_lock(bank, i, set);
614 if (ERROR_OK != ret) {
615 LOG_ERROR("Failed to set lock on page %d", i);
616 return ret;
617 }
618 }
619
620 ret = efm32x_write_lock_data(bank);
621 if (ERROR_OK != ret) {
622 LOG_ERROR("Failed to write LB page");
623 return ret;
624 }
625
626 return ERROR_OK;
627 }
628
629 static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
630 uint32_t offset, uint32_t count)
631 {
632 struct target *target = bank->target;
633 uint32_t buffer_size = 16384;
634 struct working_area *write_algorithm;
635 struct working_area *source;
636 uint32_t address = bank->base + offset;
637 struct reg_param reg_params[5];
638 struct armv7m_algorithm armv7m_info;
639 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
640 int ret = ERROR_OK;
641
642 /* see contrib/loaders/flash/efm32.S for src */
643 static const uint8_t efm32x_flash_write_code[] = {
644 /* #define EFM32_MSC_WRITECTRL_OFFSET 0x008 */
645 /* #define EFM32_MSC_WRITECMD_OFFSET 0x00c */
646 /* #define EFM32_MSC_ADDRB_OFFSET 0x010 */
647 /* #define EFM32_MSC_WDATA_OFFSET 0x018 */
648 /* #define EFM32_MSC_STATUS_OFFSET 0x01c */
649
650 0x01, 0x26, /* movs r6, #1 */
651 0x86, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET] */
652
653 /* wait_fifo: */
654 0x16, 0x68, /* ldr r6, [r2, #0] */
655 0x00, 0x2e, /* cmp r6, #0 */
656 0x22, 0xd0, /* beq exit */
657 0x55, 0x68, /* ldr r5, [r2, #4] */
658 0xb5, 0x42, /* cmp r5, r6 */
659 0xf9, 0xd0, /* beq wait_fifo */
660
661 0x04, 0x61, /* str r4, [r0, #EFM32_MSC_ADDRB_OFFSET] */
662 0x01, 0x26, /* movs r6, #1 */
663 0xc6, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
664 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
665 0x06, 0x27, /* movs r7, #6 */
666 0x3e, 0x42, /* tst r6, r7 */
667 0x16, 0xd1, /* bne error */
668
669 /* wait_wdataready: */
670 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
671 0x08, 0x27, /* movs r7, #8 */
672 0x3e, 0x42, /* tst r6, r7 */
673 0xfb, 0xd0, /* beq wait_wdataready */
674
675 0x2e, 0x68, /* ldr r6, [r5] */
676 0x86, 0x61, /* str r6, [r0, #EFM32_MSC_WDATA_OFFSET] */
677 0x08, 0x26, /* movs r6, #8 */
678 0xc6, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
679
680 0x04, 0x35, /* adds r5, #4 */
681 0x04, 0x34, /* adds r4, #4 */
682
683 /* busy: */
684 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
685 0x01, 0x27, /* movs r7, #1 */
686 0x3e, 0x42, /* tst r6, r7 */
687 0xfb, 0xd1, /* bne busy */
688
689 0x9d, 0x42, /* cmp r5, r3 */
690 0x01, 0xd3, /* bcc no_wrap */
691 0x15, 0x46, /* mov r5, r2 */
692 0x08, 0x35, /* adds r5, #8 */
693
694 /* no_wrap: */
695 0x55, 0x60, /* str r5, [r2, #4] */
696 0x01, 0x39, /* subs r1, r1, #1 */
697 0x00, 0x29, /* cmp r1, #0 */
698 0x02, 0xd0, /* beq exit */
699 0xdb, 0xe7, /* b wait_fifo */
700
701 /* error: */
702 0x00, 0x20, /* movs r0, #0 */
703 0x50, 0x60, /* str r0, [r2, #4] */
704
705 /* exit: */
706 0x30, 0x46, /* mov r0, r6 */
707 0x00, 0xbe, /* bkpt #0 */
708 };
709
710
711 /* flash write code */
712 if (target_alloc_working_area(target, sizeof(efm32x_flash_write_code),
713 &write_algorithm) != ERROR_OK) {
714 LOG_WARNING("no working area available, can't do block memory writes");
715 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
716 }
717
718 ret = target_write_buffer(target, write_algorithm->address,
719 sizeof(efm32x_flash_write_code), efm32x_flash_write_code);
720 if (ret != ERROR_OK)
721 return ret;
722
723 /* memory buffer */
724 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
725 buffer_size /= 2;
726 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
727 if (buffer_size <= 256) {
728 /* we already allocated the writing code, but failed to get a
729 * buffer, free the algorithm */
730 target_free_working_area(target, write_algorithm);
731
732 LOG_WARNING("no large enough working area available, can't do block memory writes");
733 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
734 }
735 }
736
737 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
738 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (word-32bit) */
739 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
740 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
741 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
742
743 buf_set_u32(reg_params[0].value, 0, 32, efm32x_info->reg_base);
744 buf_set_u32(reg_params[1].value, 0, 32, count);
745 buf_set_u32(reg_params[2].value, 0, 32, source->address);
746 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
747 buf_set_u32(reg_params[4].value, 0, 32, address);
748
749 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
750 armv7m_info.core_mode = ARM_MODE_THREAD;
751
752 ret = target_run_flash_async_algorithm(target, buf, count, 4,
753 0, NULL,
754 5, reg_params,
755 source->address, source->size,
756 write_algorithm->address, 0,
757 &armv7m_info);
758
759 if (ret == ERROR_FLASH_OPERATION_FAILED) {
760 LOG_ERROR("flash write failed at address 0x%"PRIx32,
761 buf_get_u32(reg_params[4].value, 0, 32));
762
763 if (buf_get_u32(reg_params[0].value, 0, 32) &
764 EFM32_MSC_STATUS_LOCKED_MASK) {
765 LOG_ERROR("flash memory write protected");
766 }
767
768 if (buf_get_u32(reg_params[0].value, 0, 32) &
769 EFM32_MSC_STATUS_INVADDR_MASK) {
770 LOG_ERROR("invalid flash memory write address");
771 }
772 }
773
774 target_free_working_area(target, source);
775 target_free_working_area(target, write_algorithm);
776
777 destroy_reg_param(&reg_params[0]);
778 destroy_reg_param(&reg_params[1]);
779 destroy_reg_param(&reg_params[2]);
780 destroy_reg_param(&reg_params[3]);
781 destroy_reg_param(&reg_params[4]);
782
783 return ret;
784 }
785
786 static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
787 uint32_t val)
788 {
789 /* this function DOES NOT set WREN; must be set already */
790 /* 1. write address to ADDRB
791 2. write LADDRIM
792 3. check status (INVADDR, LOCKED)
793 4. wait for WDATAREADY
794 5. write data to WDATA
795 6. write WRITECMD_WRITEONCE to WRITECMD
796 7. wait until !STATUS_BUSY
797 */
798
799 /* FIXME: EFM32G ref states (7.3.2) that writes should be
800 * performed twice per dword */
801
802 int ret = 0;
803 uint32_t status = 0;
804
805 /* if not called, GDB errors will be reported during large writes */
806 keep_alive();
807
808 ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
809 if (ERROR_OK != ret)
810 return ret;
811
812 ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
813 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
814 if (ERROR_OK != ret)
815 return ret;
816
817 ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
818 if (ERROR_OK != ret)
819 return ret;
820
821 LOG_DEBUG("status 0x%" PRIx32, status);
822
823 if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
824 LOG_ERROR("Page is locked");
825 return ERROR_FAIL;
826 } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
827 LOG_ERROR("Invalid address 0x%" PRIx32, addr);
828 return ERROR_FAIL;
829 }
830
831 ret = efm32x_wait_status(bank, EFM32_FLASH_WDATAREADY_TMO,
832 EFM32_MSC_STATUS_WDATAREADY_MASK, 1);
833 if (ERROR_OK != ret) {
834 LOG_ERROR("Wait for WDATAREADY failed");
835 return ret;
836 }
837
838 ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WDATA, val);
839 if (ERROR_OK != ret) {
840 LOG_ERROR("WDATA write failed");
841 return ret;
842 }
843
844 ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WRITECMD,
845 EFM32_MSC_WRITECMD_WRITEONCE_MASK);
846 if (ERROR_OK != ret) {
847 LOG_ERROR("WRITECMD write failed");
848 return ret;
849 }
850
851 ret = efm32x_wait_status(bank, EFM32_FLASH_WRITE_TMO,
852 EFM32_MSC_STATUS_BUSY_MASK, 0);
853 if (ERROR_OK != ret) {
854 LOG_ERROR("Wait for BUSY failed");
855 return ret;
856 }
857
858 return ERROR_OK;
859 }
860
861 static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
862 uint32_t offset, uint32_t count)
863 {
864 struct target *target = bank->target;
865 uint8_t *new_buffer = NULL;
866
867 if (target->state != TARGET_HALTED) {
868 LOG_ERROR("Target not halted");
869 return ERROR_TARGET_NOT_HALTED;
870 }
871
872 if (offset & 0x3) {
873 LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte "
874 "alignment", offset);
875 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
876 }
877
878 if (count & 0x3) {
879 uint32_t old_count = count;
880 count = (old_count | 3) + 1;
881 new_buffer = malloc(count);
882 if (new_buffer == NULL) {
883 LOG_ERROR("odd number of bytes to write and no memory "
884 "for padding buffer");
885 return ERROR_FAIL;
886 }
887 LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " "
888 "and padding with 0xff", old_count, count);
889 memset(new_buffer, 0xff, count);
890 buffer = memcpy(new_buffer, buffer, old_count);
891 }
892
893 uint32_t words_remaining = count / 4;
894 int retval, retval2;
895
896 /* unlock flash registers */
897 efm32x_msc_lock(bank, 0);
898 retval = efm32x_set_wren(bank, 1);
899 if (retval != ERROR_OK)
900 goto cleanup;
901
902 /* try using a block write */
903 retval = efm32x_write_block(bank, buffer, offset, words_remaining);
904
905 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
906 /* if block write failed (no sufficient working area),
907 * we use normal (slow) single word accesses */
908 LOG_WARNING("couldn't use block writes, falling back to single "
909 "memory accesses");
910
911 while (words_remaining > 0) {
912 uint32_t value;
913 memcpy(&value, buffer, sizeof(uint32_t));
914
915 retval = efm32x_write_word(bank, offset, value);
916 if (retval != ERROR_OK)
917 goto reset_pg_and_lock;
918
919 words_remaining--;
920 buffer += 4;
921 offset += 4;
922 }
923 }
924
925 reset_pg_and_lock:
926 retval2 = efm32x_set_wren(bank, 0);
927 efm32x_msc_lock(bank, 1);
928 if (retval == ERROR_OK)
929 retval = retval2;
930
931 cleanup:
932 if (new_buffer)
933 free(new_buffer);
934
935 return retval;
936 }
937
938 static int efm32x_probe(struct flash_bank *bank)
939 {
940 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
941 struct efm32_info efm32_mcu_info;
942 int ret;
943 int i;
944 uint32_t base_address = 0x00000000;
945 char buf[256];
946
947 efm32x_info->probed = 0;
948 memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
949
950 ret = efm32x_read_info(bank, &efm32_mcu_info);
951 if (ERROR_OK != ret)
952 return ret;
953
954 ret = efm32x_decode_info(&efm32_mcu_info, buf, sizeof(buf));
955 if (ERROR_OK != ret)
956 return ret;
957
958 LOG_INFO("detected part: %s", buf);
959 LOG_INFO("flash size = %dkbytes", efm32_mcu_info.flash_sz_kib);
960 LOG_INFO("flash page size = %dbytes", efm32_mcu_info.page_size);
961
962 assert(0 != efm32_mcu_info.page_size);
963
964 int num_pages = efm32_mcu_info.flash_sz_kib * 1024 /
965 efm32_mcu_info.page_size;
966
967 assert(num_pages > 0);
968
969 if (bank->sectors) {
970 free(bank->sectors);
971 bank->sectors = NULL;
972 }
973
974 bank->base = base_address;
975 bank->size = (num_pages * efm32_mcu_info.page_size);
976 bank->num_sectors = num_pages;
977
978 ret = efm32x_read_lock_data(bank);
979 if (ERROR_OK != ret) {
980 LOG_ERROR("Failed to read LB data");
981 return ret;
982 }
983
984 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
985
986 for (i = 0; i < num_pages; i++) {
987 bank->sectors[i].offset = i * efm32_mcu_info.page_size;
988 bank->sectors[i].size = efm32_mcu_info.page_size;
989 bank->sectors[i].is_erased = -1;
990 bank->sectors[i].is_protected = 1;
991 }
992
993 efm32x_info->probed = 1;
994
995 return ERROR_OK;
996 }
997
998 static int efm32x_auto_probe(struct flash_bank *bank)
999 {
1000 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
1001 if (efm32x_info->probed)
1002 return ERROR_OK;
1003 return efm32x_probe(bank);
1004 }
1005
1006 static int efm32x_protect_check(struct flash_bank *bank)
1007 {
1008 struct target *target = bank->target;
1009 int ret = 0;
1010 int i = 0;
1011
1012 if (target->state != TARGET_HALTED) {
1013 LOG_ERROR("Target not halted");
1014 return ERROR_TARGET_NOT_HALTED;
1015 }
1016
1017 ret = efm32x_read_lock_data(bank);
1018 if (ERROR_OK != ret) {
1019 LOG_ERROR("Failed to read LB data");
1020 return ret;
1021 }
1022
1023 assert(NULL != bank->sectors);
1024
1025 for (i = 0; i < bank->num_sectors; i++)
1026 bank->sectors[i].is_protected = efm32x_get_page_lock(bank, i);
1027
1028 return ERROR_OK;
1029 }
1030
1031 static int get_efm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1032 {
1033 struct efm32_info info;
1034 int ret = 0;
1035
1036 ret = efm32x_read_info(bank, &info);
1037 if (ERROR_OK != ret) {
1038 LOG_ERROR("Failed to read EFM32 info");
1039 return ret;
1040 }
1041
1042 return efm32x_decode_info(&info, buf, buf_size);
1043 }
1044
1045 COMMAND_HANDLER(efm32x_handle_debuglock_command)
1046 {
1047 struct target *target = NULL;
1048
1049 if (CMD_ARGC < 1)
1050 return ERROR_COMMAND_SYNTAX_ERROR;
1051
1052 struct flash_bank *bank;
1053 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1054 if (ERROR_OK != retval)
1055 return retval;
1056
1057 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
1058
1059 target = bank->target;
1060
1061 if (target->state != TARGET_HALTED) {
1062 LOG_ERROR("Target not halted");
1063 return ERROR_TARGET_NOT_HALTED;
1064 }
1065
1066 uint32_t *ptr;
1067 ptr = efm32x_info->lb_page + 127;
1068 *ptr = 0;
1069
1070 retval = efm32x_write_lock_data(bank);
1071 if (ERROR_OK != retval) {
1072 LOG_ERROR("Failed to write LB page");
1073 return retval;
1074 }
1075
1076 command_print(CMD_CTX, "efm32x debug interface locked, reset the device to apply");
1077
1078 return ERROR_OK;
1079 }
1080
1081 static const struct command_registration efm32x_exec_command_handlers[] = {
1082 {
1083 .name = "debuglock",
1084 .handler = efm32x_handle_debuglock_command,
1085 .mode = COMMAND_EXEC,
1086 .usage = "bank_id",
1087 .help = "Lock the debug interface of the device.",
1088 },
1089 COMMAND_REGISTRATION_DONE
1090 };
1091
1092 static const struct command_registration efm32x_command_handlers[] = {
1093 {
1094 .name = "efm32",
1095 .mode = COMMAND_ANY,
1096 .help = "efm32 flash command group",
1097 .usage = "",
1098 .chain = efm32x_exec_command_handlers,
1099 },
1100 COMMAND_REGISTRATION_DONE
1101 };
1102
1103 struct flash_driver efm32_flash = {
1104 .name = "efm32",
1105 .commands = efm32x_command_handlers,
1106 .flash_bank_command = efm32x_flash_bank_command,
1107 .erase = efm32x_erase,
1108 .protect = efm32x_protect,
1109 .write = efm32x_write,
1110 .read = default_flash_read,
1111 .probe = efm32x_probe,
1112 .auto_probe = efm32x_auto_probe,
1113 .erase_check = default_flash_blank_check,
1114 .protect_check = efm32x_protect_check,
1115 .info = get_efm32x_info,
1116 };
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)