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[openocd.git] / src / flash / nor / efm32.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 * *
11 * Copyright (C) 2013 by Roman Dmitrienko *
12 * me@iamroman.org *
13 * *
14 * Copyright (C) 2014 Nemui Trinomius *
15 * nemuisan_kawausogasuki@live.jp *
16 * *
17 * This program is free software; you can redistribute it and/or modify *
18 * it under the terms of the GNU General Public License as published by *
19 * the Free Software Foundation; either version 2 of the License, or *
20 * (at your option) any later version. *
21 * *
22 * This program is distributed in the hope that it will be useful, *
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
25 * GNU General Public License for more details. *
26 * *
27 * You should have received a copy of the GNU General Public License *
28 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
29 ***************************************************************************/
30
31 #ifdef HAVE_CONFIG_H
32 #include "config.h"
33 #endif
34
35 #include "imp.h"
36 #include <helper/binarybuffer.h>
37 #include <target/algorithm.h>
38 #include <target/armv7m.h>
39 #include <target/cortex_m.h>
40
41 #define EFM_FAMILY_ID_GIANT_GECKO 72
42 #define EFM_FAMILY_ID_LEOPARD_GECKO 74
43
44 #define EFM32_FLASH_ERASE_TMO 100
45 #define EFM32_FLASH_WDATAREADY_TMO 100
46 #define EFM32_FLASH_WRITE_TMO 100
47
48 /* size in bytes, not words; must fit all Gecko devices */
49 #define LOCKBITS_PAGE_SZ 512
50
51 #define EFM32_MSC_INFO_BASE 0x0fe00000
52
53 #define EFM32_MSC_USER_DATA EFM32_MSC_INFO_BASE
54 #define EFM32_MSC_LOCK_BITS (EFM32_MSC_INFO_BASE+0x4000)
55 #define EFM32_MSC_DEV_INFO (EFM32_MSC_INFO_BASE+0x8000)
56
57 /* PAGE_SIZE is not present in Zero, Happy and the original Gecko MCU */
58 #define EFM32_MSC_DI_PAGE_SIZE (EFM32_MSC_DEV_INFO+0x1e7)
59 #define EFM32_MSC_DI_FLASH_SZ (EFM32_MSC_DEV_INFO+0x1f8)
60 #define EFM32_MSC_DI_RAM_SZ (EFM32_MSC_DEV_INFO+0x1fa)
61 #define EFM32_MSC_DI_PART_NUM (EFM32_MSC_DEV_INFO+0x1fc)
62 #define EFM32_MSC_DI_PART_FAMILY (EFM32_MSC_DEV_INFO+0x1fe)
63 #define EFM32_MSC_DI_PROD_REV (EFM32_MSC_DEV_INFO+0x1ff)
64
65 #define EFM32_MSC_REGBASE 0x400c0000
66 #define EFM32_MSC_REGBASE_SERIES1 0x400e0000
67 #define EFM32_MSC_REG_WRITECTRL 0x008
68 #define EFM32_MSC_WRITECTRL_WREN_MASK 0x1
69 #define EFM32_MSC_REG_WRITECMD 0x00c
70 #define EFM32_MSC_WRITECMD_LADDRIM_MASK 0x1
71 #define EFM32_MSC_WRITECMD_ERASEPAGE_MASK 0x2
72 #define EFM32_MSC_WRITECMD_WRITEONCE_MASK 0x8
73 #define EFM32_MSC_REG_ADDRB 0x010
74 #define EFM32_MSC_REG_WDATA 0x018
75 #define EFM32_MSC_REG_STATUS 0x01c
76 #define EFM32_MSC_STATUS_BUSY_MASK 0x1
77 #define EFM32_MSC_STATUS_LOCKED_MASK 0x2
78 #define EFM32_MSC_STATUS_INVADDR_MASK 0x4
79 #define EFM32_MSC_STATUS_WDATAREADY_MASK 0x8
80 #define EFM32_MSC_STATUS_WORDTIMEOUT_MASK 0x10
81 #define EFM32_MSC_STATUS_ERASEABORTED_MASK 0x20
82 #define EFM32_MSC_REG_LOCK 0x03c
83 #define EFM32_MSC_REG_LOCK_SERIES1 0x040
84 #define EFM32_MSC_LOCK_LOCKKEY 0x1b71
85
86 struct efm32_family_data {
87 int family_id;
88 const char *name;
89
90 /* EFM32 series (EFM32LG995F is the "old" series 0, while EFR32MG12P132
91 is the "new" series 1). Determines location of MSC registers. */
92 int series;
93
94 /* Page size in bytes, or 0 to read from EFM32_MSC_DI_PAGE_SIZE */
95 int page_size;
96
97 /* MSC register base address, or 0 to use default */
98 uint32_t msc_regbase;
99 };
100
101 struct efm32x_flash_bank {
102 bool probed;
103 uint32_t lb_page[LOCKBITS_PAGE_SZ/4];
104 uint32_t reg_base;
105 uint32_t reg_lock;
106 };
107
108 struct efm32_info {
109 const struct efm32_family_data *family_data;
110 uint16_t flash_sz_kib;
111 uint16_t ram_sz_kib;
112 uint16_t part_num;
113 uint8_t part_family;
114 uint8_t prod_rev;
115 uint16_t page_size;
116 };
117
118 static const struct efm32_family_data efm32_families[] = {
119 { 16, "EFR32MG1P Mighty", .series = 1 },
120 { 17, "EFR32MG1B Mighty", .series = 1 },
121 { 18, "EFR32MG1V Mighty", .series = 1 },
122 { 19, "EFR32BG1P Blue", .series = 1 },
123 { 20, "EFR32BG1B Blue", .series = 1 },
124 { 21, "EFR32BG1V Blue", .series = 1 },
125 { 25, "EFR32FG1P Flex", .series = 1 },
126 { 26, "EFR32FG1B Flex", .series = 1 },
127 { 27, "EFR32FG1V Flex", .series = 1 },
128 { 28, "EFR32MG2P Mighty", .series = 1 },
129 { 29, "EFR32MG2B Mighty", .series = 1 },
130 { 30, "EFR32MG2V Mighty", .series = 1 },
131 { 31, "EFR32BG12P Blue", .series = 1 },
132 { 32, "EFR32BG12B Blue", .series = 1 },
133 { 33, "EFR32BG12V Blue", .series = 1 },
134 { 37, "EFR32FG12P Flex", .series = 1 },
135 { 38, "EFR32FG12B Flex", .series = 1 },
136 { 39, "EFR32FG12V Flex", .series = 1 },
137 { 40, "EFR32MG13P Mighty", .series = 1 },
138 { 41, "EFR32MG13B Mighty", .series = 1 },
139 { 42, "EFR32MG13V Mighty", .series = 1 },
140 { 43, "EFR32BG13P Blue", .series = 1 },
141 { 44, "EFR32BG13B Blue", .series = 1 },
142 { 45, "EFR32BG13V Blue", .series = 1 },
143 { 46, "EFR32ZG13P Zen", .series = 1 },
144 { 49, "EFR32FG13P Flex", .series = 1 },
145 { 50, "EFR32FG13B Flex", .series = 1 },
146 { 51, "EFR32FG13V Flex", .series = 1 },
147 { 52, "EFR32MG14P Mighty", .series = 1 },
148 { 53, "EFR32MG14B Mighty", .series = 1 },
149 { 54, "EFR32MG14V Mighty", .series = 1 },
150 { 55, "EFR32BG14P Blue", .series = 1 },
151 { 56, "EFR32BG14B Blue", .series = 1 },
152 { 57, "EFR32BG14V Blue", .series = 1 },
153 { 58, "EFR32ZG14P Zen", .series = 1 },
154 { 61, "EFR32FG14P Flex", .series = 1 },
155 { 62, "EFR32FG14B Flex", .series = 1 },
156 { 63, "EFR32FG14V Flex", .series = 1 },
157 { 71, "EFM32G", .series = 0, .page_size = 512 },
158 { 72, "EFM32GG Giant", .series = 0 },
159 { 73, "EFM32TG Tiny", .series = 0, .page_size = 512 },
160 { 74, "EFM32LG Leopard", .series = 0 },
161 { 75, "EFM32WG Wonder", .series = 0 },
162 { 76, "EFM32ZG Zero", .series = 0, .page_size = 1024 },
163 { 77, "EFM32HG Happy", .series = 0, .page_size = 1024 },
164 { 81, "EFM32PG1B Pearl", .series = 1 },
165 { 83, "EFM32JG1B Jade", .series = 1 },
166 { 85, "EFM32PG12B Pearl", .series = 1 },
167 { 87, "EFM32JG12B Jade", .series = 1 },
168 { 89, "EFM32PG13B Pearl", .series = 1 },
169 { 91, "EFM32JG13B Jade", .series = 1 },
170 { 100, "EFM32GG11B Giant", .series = 1, .msc_regbase = 0x40000000 },
171 { 103, "EFM32TG11B Tiny", .series = 1, .msc_regbase = 0x40000000 },
172 { 106, "EFM32GG12B Giant", .series = 1, .msc_regbase = 0x40000000 },
173 { 120, "EZR32WG Wonder", .series = 0 },
174 { 121, "EZR32LG Leopard", .series = 0 },
175 { 122, "EZR32HG Happy", .series = 0, .page_size = 1024 },
176 };
177
178
179 static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
180 uint32_t offset, uint32_t count);
181
182 static int efm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_sz)
183 {
184 return target_read_u16(bank->target, EFM32_MSC_DI_FLASH_SZ, flash_sz);
185 }
186
187 static int efm32x_get_ram_size(struct flash_bank *bank, uint16_t *ram_sz)
188 {
189 return target_read_u16(bank->target, EFM32_MSC_DI_RAM_SZ, ram_sz);
190 }
191
192 static int efm32x_get_part_num(struct flash_bank *bank, uint16_t *pnum)
193 {
194 return target_read_u16(bank->target, EFM32_MSC_DI_PART_NUM, pnum);
195 }
196
197 static int efm32x_get_part_family(struct flash_bank *bank, uint8_t *pfamily)
198 {
199 return target_read_u8(bank->target, EFM32_MSC_DI_PART_FAMILY, pfamily);
200 }
201
202 static int efm32x_get_prod_rev(struct flash_bank *bank, uint8_t *prev)
203 {
204 return target_read_u8(bank->target, EFM32_MSC_DI_PROD_REV, prev);
205 }
206
207 static int efm32x_read_reg_u32(struct flash_bank *bank, target_addr_t offset,
208 uint32_t *value)
209 {
210 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
211 uint32_t base = efm32x_info->reg_base;
212
213 return target_read_u32(bank->target, base + offset, value);
214 }
215
216 static int efm32x_write_reg_u32(struct flash_bank *bank, target_addr_t offset,
217 uint32_t value)
218 {
219 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
220 uint32_t base = efm32x_info->reg_base;
221
222 return target_write_u32(bank->target, base + offset, value);
223 }
224
225 static int efm32x_read_info(struct flash_bank *bank,
226 struct efm32_info *efm32_info)
227 {
228 int ret;
229 uint32_t cpuid = 0;
230 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
231
232 memset(efm32_info, 0, sizeof(struct efm32_info));
233
234 ret = target_read_u32(bank->target, CPUID, &cpuid);
235 if (ret != ERROR_OK)
236 return ret;
237
238 if (((cpuid >> 4) & 0xfff) == 0xc23) {
239 /* Cortex-M3 device */
240 } else if (((cpuid >> 4) & 0xfff) == 0xc24) {
241 /* Cortex-M4 device (WONDER GECKO) */
242 } else if (((cpuid >> 4) & 0xfff) == 0xc60) {
243 /* Cortex-M0+ device */
244 } else {
245 LOG_ERROR("Target is not Cortex-Mx Device");
246 return ERROR_FAIL;
247 }
248
249 ret = efm32x_get_flash_size(bank, &(efm32_info->flash_sz_kib));
250 if (ret != ERROR_OK)
251 return ret;
252
253 ret = efm32x_get_ram_size(bank, &(efm32_info->ram_sz_kib));
254 if (ret != ERROR_OK)
255 return ret;
256
257 ret = efm32x_get_part_num(bank, &(efm32_info->part_num));
258 if (ret != ERROR_OK)
259 return ret;
260
261 ret = efm32x_get_part_family(bank, &(efm32_info->part_family));
262 if (ret != ERROR_OK)
263 return ret;
264
265 ret = efm32x_get_prod_rev(bank, &(efm32_info->prod_rev));
266 if (ret != ERROR_OK)
267 return ret;
268
269 for (size_t i = 0; i < ARRAY_SIZE(efm32_families); i++) {
270 if (efm32_families[i].family_id == efm32_info->part_family)
271 efm32_info->family_data = &efm32_families[i];
272 }
273
274 if (!efm32_info->family_data) {
275 LOG_ERROR("Unknown MCU family %d", efm32_info->part_family);
276 return ERROR_FAIL;
277 }
278
279 switch (efm32_info->family_data->series) {
280 case 0:
281 efm32x_info->reg_base = EFM32_MSC_REGBASE;
282 efm32x_info->reg_lock = EFM32_MSC_REG_LOCK;
283 break;
284 case 1:
285 efm32x_info->reg_base = EFM32_MSC_REGBASE_SERIES1;
286 efm32x_info->reg_lock = EFM32_MSC_REG_LOCK_SERIES1;
287 break;
288 }
289
290 if (efm32_info->family_data->msc_regbase != 0)
291 efm32x_info->reg_base = efm32_info->family_data->msc_regbase;
292
293 if (efm32_info->family_data->page_size != 0) {
294 efm32_info->page_size = efm32_info->family_data->page_size;
295 } else {
296 uint8_t pg_size = 0;
297 ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
298 &pg_size);
299 if (ret != ERROR_OK)
300 return ret;
301
302 efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
303
304 if (efm32_info->part_family == EFM_FAMILY_ID_GIANT_GECKO ||
305 efm32_info->part_family == EFM_FAMILY_ID_LEOPARD_GECKO) {
306 /* Giant or Leopard Gecko */
307 if (efm32_info->prod_rev < 18) {
308 /* EFM32 GG/LG errata: MEM_INFO_PAGE_SIZE is invalid
309 for MCUs with PROD_REV < 18 */
310 if (efm32_info->flash_sz_kib < 512)
311 efm32_info->page_size = 2048;
312 else
313 efm32_info->page_size = 4096;
314 }
315 }
316
317 if ((efm32_info->page_size != 2048) &&
318 (efm32_info->page_size != 4096)) {
319 LOG_ERROR("Invalid page size %u", efm32_info->page_size);
320 return ERROR_FAIL;
321 }
322 }
323
324 return ERROR_OK;
325 }
326
327 /* flash bank efm32 <base> <size> 0 0 <target#> */
328 FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command)
329 {
330 struct efm32x_flash_bank *efm32x_info;
331
332 if (CMD_ARGC < 6)
333 return ERROR_COMMAND_SYNTAX_ERROR;
334
335 efm32x_info = malloc(sizeof(struct efm32x_flash_bank));
336
337 bank->driver_priv = efm32x_info;
338 efm32x_info->probed = false;
339 memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
340
341 return ERROR_OK;
342 }
343
344 /* set or reset given bits in a register */
345 static int efm32x_set_reg_bits(struct flash_bank *bank, uint32_t reg,
346 uint32_t bitmask, int set)
347 {
348 int ret = 0;
349 uint32_t reg_val = 0;
350
351 ret = efm32x_read_reg_u32(bank, reg, &reg_val);
352 if (ret != ERROR_OK)
353 return ret;
354
355 if (set)
356 reg_val |= bitmask;
357 else
358 reg_val &= ~bitmask;
359
360 return efm32x_write_reg_u32(bank, reg, reg_val);
361 }
362
363 static int efm32x_set_wren(struct flash_bank *bank, int write_enable)
364 {
365 return efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECTRL,
366 EFM32_MSC_WRITECTRL_WREN_MASK, write_enable);
367 }
368
369 static int efm32x_msc_lock(struct flash_bank *bank, int lock)
370 {
371 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
372 return efm32x_write_reg_u32(bank, efm32x_info->reg_lock,
373 (lock ? 0 : EFM32_MSC_LOCK_LOCKKEY));
374 }
375
376 static int efm32x_wait_status(struct flash_bank *bank, int timeout,
377 uint32_t wait_mask, int wait_for_set)
378 {
379 int ret = 0;
380 uint32_t status = 0;
381
382 while (1) {
383 ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
384 if (ret != ERROR_OK)
385 break;
386
387 LOG_DEBUG("status: 0x%" PRIx32 "", status);
388
389 if (((status & wait_mask) == 0) && (wait_for_set == 0))
390 break;
391 else if (((status & wait_mask) != 0) && wait_for_set)
392 break;
393
394 if (timeout-- <= 0) {
395 LOG_ERROR("timed out waiting for MSC status");
396 return ERROR_FAIL;
397 }
398
399 alive_sleep(1);
400 }
401
402 if (status & EFM32_MSC_STATUS_ERASEABORTED_MASK)
403 LOG_WARNING("page erase was aborted");
404
405 return ret;
406 }
407
408 static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr)
409 {
410 /* this function DOES NOT set WREN; must be set already */
411 /* 1. write address to ADDRB
412 2. write LADDRIM
413 3. check status (INVADDR, LOCKED)
414 4. write ERASEPAGE
415 5. wait until !STATUS_BUSY
416 */
417 int ret = 0;
418 uint32_t status = 0;
419 addr += bank->base;
420 LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr);
421
422 ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
423 if (ret != ERROR_OK)
424 return ret;
425
426 ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
427 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
428 if (ret != ERROR_OK)
429 return ret;
430
431 ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
432 if (ret != ERROR_OK)
433 return ret;
434
435 LOG_DEBUG("status 0x%" PRIx32, status);
436
437 if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
438 LOG_ERROR("Page is locked");
439 return ERROR_FAIL;
440 } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
441 LOG_ERROR("Invalid address 0x%" PRIx32, addr);
442 return ERROR_FAIL;
443 }
444
445 ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
446 EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
447 if (ret != ERROR_OK)
448 return ret;
449
450 return efm32x_wait_status(bank, EFM32_FLASH_ERASE_TMO,
451 EFM32_MSC_STATUS_BUSY_MASK, 0);
452 }
453
454 static int efm32x_erase(struct flash_bank *bank, unsigned int first,
455 unsigned int last)
456 {
457 struct target *target = bank->target;
458 int ret = 0;
459
460 if (target->state != TARGET_HALTED) {
461 LOG_ERROR("Target not halted");
462 return ERROR_TARGET_NOT_HALTED;
463 }
464
465 efm32x_msc_lock(bank, 0);
466 ret = efm32x_set_wren(bank, 1);
467 if (ret != ERROR_OK) {
468 LOG_ERROR("Failed to enable MSC write");
469 return ret;
470 }
471
472 for (unsigned int i = first; i <= last; i++) {
473 ret = efm32x_erase_page(bank, bank->sectors[i].offset);
474 if (ret != ERROR_OK)
475 LOG_ERROR("Failed to erase page %d", i);
476 }
477
478 ret = efm32x_set_wren(bank, 0);
479 efm32x_msc_lock(bank, 1);
480
481 return ret;
482 }
483
484 static int efm32x_read_lock_data(struct flash_bank *bank)
485 {
486 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
487 struct target *target = bank->target;
488 int data_size = 0;
489 uint32_t *ptr = NULL;
490 int ret = 0;
491
492 assert(bank->num_sectors > 0);
493
494 /* calculate the number of 32-bit words to read (one lock bit per sector) */
495 data_size = (bank->num_sectors + 31) / 32;
496
497 ptr = efm32x_info->lb_page;
498
499 for (int i = 0; i < data_size; i++, ptr++) {
500 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+i*4, ptr);
501 if (ret != ERROR_OK) {
502 LOG_ERROR("Failed to read PLW %d", i);
503 return ret;
504 }
505 }
506
507 /* also, read ULW, DLW, MLW, ALW and CLW words */
508
509 /* ULW, word 126 */
510 ptr = efm32x_info->lb_page + 126;
511 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+126*4, ptr);
512 if (ret != ERROR_OK) {
513 LOG_ERROR("Failed to read ULW");
514 return ret;
515 }
516
517 /* DLW, word 127 */
518 ptr = efm32x_info->lb_page + 127;
519 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+127*4, ptr);
520 if (ret != ERROR_OK) {
521 LOG_ERROR("Failed to read DLW");
522 return ret;
523 }
524
525 /* MLW, word 125, present in GG, LG, PG, JG, EFR32 */
526 ptr = efm32x_info->lb_page + 125;
527 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+125*4, ptr);
528 if (ret != ERROR_OK) {
529 LOG_ERROR("Failed to read MLW");
530 return ret;
531 }
532
533 /* ALW, word 124, present in GG, LG, PG, JG, EFR32 */
534 ptr = efm32x_info->lb_page + 124;
535 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+124*4, ptr);
536 if (ret != ERROR_OK) {
537 LOG_ERROR("Failed to read ALW");
538 return ret;
539 }
540
541 /* CLW1, word 123, present in EFR32 */
542 ptr = efm32x_info->lb_page + 123;
543 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+123*4, ptr);
544 if (ret != ERROR_OK) {
545 LOG_ERROR("Failed to read CLW1");
546 return ret;
547 }
548
549 /* CLW0, word 122, present in GG, LG, PG, JG, EFR32 */
550 ptr = efm32x_info->lb_page + 122;
551 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+122*4, ptr);
552 if (ret != ERROR_OK) {
553 LOG_ERROR("Failed to read CLW0");
554 return ret;
555 }
556
557 return ERROR_OK;
558 }
559
560 static int efm32x_write_lock_data(struct flash_bank *bank)
561 {
562 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
563 int ret = 0;
564
565 ret = efm32x_erase_page(bank, EFM32_MSC_LOCK_BITS);
566 if (ret != ERROR_OK) {
567 LOG_ERROR("Failed to erase LB page");
568 return ret;
569 }
570
571 return efm32x_write(bank, (uint8_t *)efm32x_info->lb_page, EFM32_MSC_LOCK_BITS,
572 LOCKBITS_PAGE_SZ);
573 }
574
575 static int efm32x_get_page_lock(struct flash_bank *bank, size_t page)
576 {
577 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
578 uint32_t dw = efm32x_info->lb_page[page >> 5];
579 uint32_t mask = 0;
580
581 mask = 1 << (page & 0x1f);
582
583 return (dw & mask) ? 0 : 1;
584 }
585
586 static int efm32x_set_page_lock(struct flash_bank *bank, size_t page, int set)
587 {
588 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
589 uint32_t *dw = &efm32x_info->lb_page[page >> 5];
590 uint32_t mask = 0;
591
592 mask = 1 << (page & 0x1f);
593
594 if (!set)
595 *dw |= mask;
596 else
597 *dw &= ~mask;
598
599 return ERROR_OK;
600 }
601
602 static int efm32x_protect(struct flash_bank *bank, int set, unsigned int first,
603 unsigned int last)
604 {
605 struct target *target = bank->target;
606 int ret = 0;
607
608 if (!set) {
609 LOG_ERROR("Erase device data to reset page locks");
610 return ERROR_FAIL;
611 }
612
613 if (target->state != TARGET_HALTED) {
614 LOG_ERROR("Target not halted");
615 return ERROR_TARGET_NOT_HALTED;
616 }
617
618 for (unsigned int i = first; i <= last; i++) {
619 ret = efm32x_set_page_lock(bank, i, set);
620 if (ret != ERROR_OK) {
621 LOG_ERROR("Failed to set lock on page %d", i);
622 return ret;
623 }
624 }
625
626 ret = efm32x_write_lock_data(bank);
627 if (ret != ERROR_OK) {
628 LOG_ERROR("Failed to write LB page");
629 return ret;
630 }
631
632 return ERROR_OK;
633 }
634
635 static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
636 uint32_t offset, uint32_t count)
637 {
638 struct target *target = bank->target;
639 uint32_t buffer_size = 16384;
640 struct working_area *write_algorithm;
641 struct working_area *source;
642 uint32_t address = bank->base + offset;
643 struct reg_param reg_params[5];
644 struct armv7m_algorithm armv7m_info;
645 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
646 int ret = ERROR_OK;
647
648 /* see contrib/loaders/flash/efm32.S for src */
649 static const uint8_t efm32x_flash_write_code[] = {
650 /* #define EFM32_MSC_WRITECTRL_OFFSET 0x008 */
651 /* #define EFM32_MSC_WRITECMD_OFFSET 0x00c */
652 /* #define EFM32_MSC_ADDRB_OFFSET 0x010 */
653 /* #define EFM32_MSC_WDATA_OFFSET 0x018 */
654 /* #define EFM32_MSC_STATUS_OFFSET 0x01c */
655
656 0x01, 0x26, /* movs r6, #1 */
657 0x86, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET] */
658
659 /* wait_fifo: */
660 0x16, 0x68, /* ldr r6, [r2, #0] */
661 0x00, 0x2e, /* cmp r6, #0 */
662 0x22, 0xd0, /* beq exit */
663 0x55, 0x68, /* ldr r5, [r2, #4] */
664 0xb5, 0x42, /* cmp r5, r6 */
665 0xf9, 0xd0, /* beq wait_fifo */
666
667 0x04, 0x61, /* str r4, [r0, #EFM32_MSC_ADDRB_OFFSET] */
668 0x01, 0x26, /* movs r6, #1 */
669 0xc6, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
670 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
671 0x06, 0x27, /* movs r7, #6 */
672 0x3e, 0x42, /* tst r6, r7 */
673 0x16, 0xd1, /* bne error */
674
675 /* wait_wdataready: */
676 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
677 0x08, 0x27, /* movs r7, #8 */
678 0x3e, 0x42, /* tst r6, r7 */
679 0xfb, 0xd0, /* beq wait_wdataready */
680
681 0x2e, 0x68, /* ldr r6, [r5] */
682 0x86, 0x61, /* str r6, [r0, #EFM32_MSC_WDATA_OFFSET] */
683 0x08, 0x26, /* movs r6, #8 */
684 0xc6, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
685
686 0x04, 0x35, /* adds r5, #4 */
687 0x04, 0x34, /* adds r4, #4 */
688
689 /* busy: */
690 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
691 0x01, 0x27, /* movs r7, #1 */
692 0x3e, 0x42, /* tst r6, r7 */
693 0xfb, 0xd1, /* bne busy */
694
695 0x9d, 0x42, /* cmp r5, r3 */
696 0x01, 0xd3, /* bcc no_wrap */
697 0x15, 0x46, /* mov r5, r2 */
698 0x08, 0x35, /* adds r5, #8 */
699
700 /* no_wrap: */
701 0x55, 0x60, /* str r5, [r2, #4] */
702 0x01, 0x39, /* subs r1, r1, #1 */
703 0x00, 0x29, /* cmp r1, #0 */
704 0x02, 0xd0, /* beq exit */
705 0xdb, 0xe7, /* b wait_fifo */
706
707 /* error: */
708 0x00, 0x20, /* movs r0, #0 */
709 0x50, 0x60, /* str r0, [r2, #4] */
710
711 /* exit: */
712 0x30, 0x46, /* mov r0, r6 */
713 0x00, 0xbe, /* bkpt #0 */
714 };
715
716
717 /* flash write code */
718 if (target_alloc_working_area(target, sizeof(efm32x_flash_write_code),
719 &write_algorithm) != ERROR_OK) {
720 LOG_WARNING("no working area available, can't do block memory writes");
721 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
722 }
723
724 ret = target_write_buffer(target, write_algorithm->address,
725 sizeof(efm32x_flash_write_code), efm32x_flash_write_code);
726 if (ret != ERROR_OK)
727 return ret;
728
729 /* memory buffer */
730 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
731 buffer_size /= 2;
732 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
733 if (buffer_size <= 256) {
734 /* we already allocated the writing code, but failed to get a
735 * buffer, free the algorithm */
736 target_free_working_area(target, write_algorithm);
737
738 LOG_WARNING("no large enough working area available, can't do block memory writes");
739 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
740 }
741 }
742
743 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
744 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (word-32bit) */
745 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
746 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
747 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
748
749 buf_set_u32(reg_params[0].value, 0, 32, efm32x_info->reg_base);
750 buf_set_u32(reg_params[1].value, 0, 32, count);
751 buf_set_u32(reg_params[2].value, 0, 32, source->address);
752 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
753 buf_set_u32(reg_params[4].value, 0, 32, address);
754
755 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
756 armv7m_info.core_mode = ARM_MODE_THREAD;
757
758 ret = target_run_flash_async_algorithm(target, buf, count, 4,
759 0, NULL,
760 5, reg_params,
761 source->address, source->size,
762 write_algorithm->address, 0,
763 &armv7m_info);
764
765 if (ret == ERROR_FLASH_OPERATION_FAILED) {
766 LOG_ERROR("flash write failed at address 0x%"PRIx32,
767 buf_get_u32(reg_params[4].value, 0, 32));
768
769 if (buf_get_u32(reg_params[0].value, 0, 32) &
770 EFM32_MSC_STATUS_LOCKED_MASK) {
771 LOG_ERROR("flash memory write protected");
772 }
773
774 if (buf_get_u32(reg_params[0].value, 0, 32) &
775 EFM32_MSC_STATUS_INVADDR_MASK) {
776 LOG_ERROR("invalid flash memory write address");
777 }
778 }
779
780 target_free_working_area(target, source);
781 target_free_working_area(target, write_algorithm);
782
783 destroy_reg_param(&reg_params[0]);
784 destroy_reg_param(&reg_params[1]);
785 destroy_reg_param(&reg_params[2]);
786 destroy_reg_param(&reg_params[3]);
787 destroy_reg_param(&reg_params[4]);
788
789 return ret;
790 }
791
792 static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
793 uint32_t val)
794 {
795 /* this function DOES NOT set WREN; must be set already */
796 /* 1. write address to ADDRB
797 2. write LADDRIM
798 3. check status (INVADDR, LOCKED)
799 4. wait for WDATAREADY
800 5. write data to WDATA
801 6. write WRITECMD_WRITEONCE to WRITECMD
802 7. wait until !STATUS_BUSY
803 */
804
805 /* FIXME: EFM32G ref states (7.3.2) that writes should be
806 * performed twice per dword */
807
808 int ret = 0;
809 uint32_t status = 0;
810
811 /* if not called, GDB errors will be reported during large writes */
812 keep_alive();
813
814 ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
815 if (ret != ERROR_OK)
816 return ret;
817
818 ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
819 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
820 if (ret != ERROR_OK)
821 return ret;
822
823 ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
824 if (ret != ERROR_OK)
825 return ret;
826
827 LOG_DEBUG("status 0x%" PRIx32, status);
828
829 if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
830 LOG_ERROR("Page is locked");
831 return ERROR_FAIL;
832 } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
833 LOG_ERROR("Invalid address 0x%" PRIx32, addr);
834 return ERROR_FAIL;
835 }
836
837 ret = efm32x_wait_status(bank, EFM32_FLASH_WDATAREADY_TMO,
838 EFM32_MSC_STATUS_WDATAREADY_MASK, 1);
839 if (ret != ERROR_OK) {
840 LOG_ERROR("Wait for WDATAREADY failed");
841 return ret;
842 }
843
844 ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WDATA, val);
845 if (ret != ERROR_OK) {
846 LOG_ERROR("WDATA write failed");
847 return ret;
848 }
849
850 ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WRITECMD,
851 EFM32_MSC_WRITECMD_WRITEONCE_MASK);
852 if (ret != ERROR_OK) {
853 LOG_ERROR("WRITECMD write failed");
854 return ret;
855 }
856
857 ret = efm32x_wait_status(bank, EFM32_FLASH_WRITE_TMO,
858 EFM32_MSC_STATUS_BUSY_MASK, 0);
859 if (ret != ERROR_OK) {
860 LOG_ERROR("Wait for BUSY failed");
861 return ret;
862 }
863
864 return ERROR_OK;
865 }
866
867 static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
868 uint32_t offset, uint32_t count)
869 {
870 struct target *target = bank->target;
871 uint8_t *new_buffer = NULL;
872
873 if (target->state != TARGET_HALTED) {
874 LOG_ERROR("Target not halted");
875 return ERROR_TARGET_NOT_HALTED;
876 }
877
878 if (offset & 0x3) {
879 LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte "
880 "alignment", offset);
881 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
882 }
883
884 if (count & 0x3) {
885 uint32_t old_count = count;
886 count = (old_count | 3) + 1;
887 new_buffer = malloc(count);
888 if (!new_buffer) {
889 LOG_ERROR("odd number of bytes to write and no memory "
890 "for padding buffer");
891 return ERROR_FAIL;
892 }
893 LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " "
894 "and padding with 0xff", old_count, count);
895 memset(new_buffer, 0xff, count);
896 buffer = memcpy(new_buffer, buffer, old_count);
897 }
898
899 uint32_t words_remaining = count / 4;
900 int retval, retval2;
901
902 /* unlock flash registers */
903 efm32x_msc_lock(bank, 0);
904 retval = efm32x_set_wren(bank, 1);
905 if (retval != ERROR_OK)
906 goto cleanup;
907
908 /* try using a block write */
909 retval = efm32x_write_block(bank, buffer, offset, words_remaining);
910
911 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
912 /* if block write failed (no sufficient working area),
913 * we use normal (slow) single word accesses */
914 LOG_WARNING("couldn't use block writes, falling back to single "
915 "memory accesses");
916
917 while (words_remaining > 0) {
918 uint32_t value;
919 memcpy(&value, buffer, sizeof(uint32_t));
920
921 retval = efm32x_write_word(bank, offset, value);
922 if (retval != ERROR_OK)
923 goto reset_pg_and_lock;
924
925 words_remaining--;
926 buffer += 4;
927 offset += 4;
928 }
929 }
930
931 reset_pg_and_lock:
932 retval2 = efm32x_set_wren(bank, 0);
933 efm32x_msc_lock(bank, 1);
934 if (retval == ERROR_OK)
935 retval = retval2;
936
937 cleanup:
938 free(new_buffer);
939 return retval;
940 }
941
942 static int efm32x_probe(struct flash_bank *bank)
943 {
944 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
945 struct efm32_info efm32_mcu_info;
946 int ret;
947 uint32_t base_address = 0x00000000;
948
949 efm32x_info->probed = false;
950 memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
951
952 ret = efm32x_read_info(bank, &efm32_mcu_info);
953 if (ret != ERROR_OK)
954 return ret;
955
956 LOG_INFO("detected part: %s Gecko, rev %d",
957 efm32_mcu_info.family_data->name, efm32_mcu_info.prod_rev);
958 LOG_INFO("flash size = %dkbytes", efm32_mcu_info.flash_sz_kib);
959 LOG_INFO("flash page size = %dbytes", efm32_mcu_info.page_size);
960
961 assert(efm32_mcu_info.page_size != 0);
962
963 int num_pages = efm32_mcu_info.flash_sz_kib * 1024 /
964 efm32_mcu_info.page_size;
965
966 assert(num_pages > 0);
967
968 free(bank->sectors);
969 bank->sectors = NULL;
970
971 bank->base = base_address;
972 bank->size = (num_pages * efm32_mcu_info.page_size);
973 bank->num_sectors = num_pages;
974
975 ret = efm32x_read_lock_data(bank);
976 if (ret != ERROR_OK) {
977 LOG_ERROR("Failed to read LB data");
978 return ret;
979 }
980
981 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
982
983 for (int i = 0; i < num_pages; i++) {
984 bank->sectors[i].offset = i * efm32_mcu_info.page_size;
985 bank->sectors[i].size = efm32_mcu_info.page_size;
986 bank->sectors[i].is_erased = -1;
987 bank->sectors[i].is_protected = 1;
988 }
989
990 efm32x_info->probed = true;
991
992 return ERROR_OK;
993 }
994
995 static int efm32x_auto_probe(struct flash_bank *bank)
996 {
997 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
998 if (efm32x_info->probed)
999 return ERROR_OK;
1000 return efm32x_probe(bank);
1001 }
1002
1003 static int efm32x_protect_check(struct flash_bank *bank)
1004 {
1005 struct target *target = bank->target;
1006 int ret = 0;
1007
1008 if (target->state != TARGET_HALTED) {
1009 LOG_ERROR("Target not halted");
1010 return ERROR_TARGET_NOT_HALTED;
1011 }
1012
1013 ret = efm32x_read_lock_data(bank);
1014 if (ret != ERROR_OK) {
1015 LOG_ERROR("Failed to read LB data");
1016 return ret;
1017 }
1018
1019 assert(bank->sectors);
1020
1021 for (unsigned int i = 0; i < bank->num_sectors; i++)
1022 bank->sectors[i].is_protected = efm32x_get_page_lock(bank, i);
1023
1024 return ERROR_OK;
1025 }
1026
1027 static int get_efm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
1028 {
1029 struct efm32_info info;
1030 int ret;
1031
1032 ret = efm32x_read_info(bank, &info);
1033 if (ret != ERROR_OK) {
1034 LOG_ERROR("Failed to read EFM32 info");
1035 return ret;
1036 }
1037
1038 command_print_sameline(cmd, "%s Gecko, rev %d", info.family_data->name, info.prod_rev);
1039 return ERROR_OK;
1040 }
1041
1042 COMMAND_HANDLER(efm32x_handle_debuglock_command)
1043 {
1044 struct target *target = NULL;
1045
1046 if (CMD_ARGC < 1)
1047 return ERROR_COMMAND_SYNTAX_ERROR;
1048
1049 struct flash_bank *bank;
1050 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1051 if (retval != ERROR_OK)
1052 return retval;
1053
1054 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
1055
1056 target = bank->target;
1057
1058 if (target->state != TARGET_HALTED) {
1059 LOG_ERROR("Target not halted");
1060 return ERROR_TARGET_NOT_HALTED;
1061 }
1062
1063 uint32_t *ptr;
1064 ptr = efm32x_info->lb_page + 127;
1065 *ptr = 0;
1066
1067 retval = efm32x_write_lock_data(bank);
1068 if (retval != ERROR_OK) {
1069 LOG_ERROR("Failed to write LB page");
1070 return retval;
1071 }
1072
1073 command_print(CMD, "efm32x debug interface locked, reset the device to apply");
1074
1075 return ERROR_OK;
1076 }
1077
1078 static const struct command_registration efm32x_exec_command_handlers[] = {
1079 {
1080 .name = "debuglock",
1081 .handler = efm32x_handle_debuglock_command,
1082 .mode = COMMAND_EXEC,
1083 .usage = "bank_id",
1084 .help = "Lock the debug interface of the device.",
1085 },
1086 COMMAND_REGISTRATION_DONE
1087 };
1088
1089 static const struct command_registration efm32x_command_handlers[] = {
1090 {
1091 .name = "efm32",
1092 .mode = COMMAND_ANY,
1093 .help = "efm32 flash command group",
1094 .usage = "",
1095 .chain = efm32x_exec_command_handlers,
1096 },
1097 COMMAND_REGISTRATION_DONE
1098 };
1099
1100 const struct flash_driver efm32_flash = {
1101 .name = "efm32",
1102 .commands = efm32x_command_handlers,
1103 .flash_bank_command = efm32x_flash_bank_command,
1104 .erase = efm32x_erase,
1105 .protect = efm32x_protect,
1106 .write = efm32x_write,
1107 .read = default_flash_read,
1108 .probe = efm32x_probe,
1109 .auto_probe = efm32x_auto_probe,
1110 .erase_check = default_flash_blank_check,
1111 .protect_check = efm32x_protect_check,
1112 .info = get_efm32x_info,
1113 .free_driver_priv = default_flash_free_driver_priv,
1114 };
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