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[openocd.git] / src / flash / nor / kinetis.c
1 /***************************************************************************
2 * Copyright (C) 2011 by Mathias Kuester *
3 * kesmtp@freenet.de *
4 * *
5 * Copyright (C) 2011 sleep(5) ltd *
6 * tomas@sleepfive.com *
7 * *
8 * Copyright (C) 2012 by Christopher D. Kilgour *
9 * techie at whiterocker.com *
10 * *
11 * Copyright (C) 2013 Nemui Trinomius *
12 * nemuisan_kawausogasuki@live.jp *
13 * *
14 * Copyright (C) 2015 Tomas Vanek *
15 * vanekt@fbl.cz *
16 * *
17 * This program is free software; you can redistribute it and/or modify *
18 * it under the terms of the GNU General Public License as published by *
19 * the Free Software Foundation; either version 2 of the License, or *
20 * (at your option) any later version. *
21 * *
22 * This program is distributed in the hope that it will be useful, *
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
25 * GNU General Public License for more details. *
26 * *
27 * You should have received a copy of the GNU General Public License *
28 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
29 ***************************************************************************/
30
31 #ifdef HAVE_CONFIG_H
32 #include "config.h"
33 #endif
34
35 #include "jtag/interface.h"
36 #include "imp.h"
37 #include <helper/binarybuffer.h>
38 #include <helper/time_support.h>
39 #include <target/target_type.h>
40 #include <target/algorithm.h>
41 #include <target/armv7m.h>
42 #include <target/cortex_m.h>
43
44 /*
45 * Implementation Notes
46 *
47 * The persistent memories in the Kinetis chip families K10 through
48 * K70 are all manipulated with the Flash Memory Module. Some
49 * variants call this module the FTFE, others call it the FTFL. To
50 * indicate that both are considered here, we use FTFX.
51 *
52 * Within the module, according to the chip variant, the persistent
53 * memory is divided into what Freescale terms Program Flash, FlexNVM,
54 * and FlexRAM. All chip variants have Program Flash. Some chip
55 * variants also have FlexNVM and FlexRAM, which always appear
56 * together.
57 *
58 * A given Kinetis chip may have 1, 2 or 4 blocks of flash. Here we map
59 * each block to a separate bank. Each block size varies by chip and
60 * may be determined by the read-only SIM_FCFG1 register. The sector
61 * size within each bank/block varies by chip, and may be 1, 2 or 4k.
62 * The sector size may be different for flash and FlexNVM.
63 *
64 * The first half of the flash (1 or 2 blocks) is always Program Flash
65 * and always starts at address 0x00000000. The "PFLSH" flag, bit 23
66 * of the read-only SIM_FCFG2 register, determines whether the second
67 * half of the flash is also Program Flash or FlexNVM+FlexRAM. When
68 * PFLSH is set, the second from the first half. When PFLSH is clear,
69 * the second half of flash is FlexNVM and always starts at address
70 * 0x10000000. FlexRAM, which is also present when PFLSH is clear,
71 * always starts at address 0x14000000.
72 *
73 * The Flash Memory Module provides a register set where flash
74 * commands are loaded to perform flash operations like erase and
75 * program. Different commands are available depending on whether
76 * Program Flash or FlexNVM/FlexRAM is being manipulated. Although
77 * the commands used are quite consistent between flash blocks, the
78 * parameters they accept differ according to the flash sector size.
79 *
80 */
81
82 /* Addressess */
83 #define FCF_ADDRESS 0x00000400
84 #define FCF_FPROT 0x8
85 #define FCF_FSEC 0xc
86 #define FCF_FOPT 0xd
87 #define FCF_FDPROT 0xf
88 #define FCF_SIZE 0x10
89
90 #define FLEXRAM 0x14000000
91
92 #define FMC_PFB01CR 0x4001f004
93 #define FTFx_FSTAT 0x40020000
94 #define FTFx_FCNFG 0x40020001
95 #define FTFx_FCCOB3 0x40020004
96 #define FTFx_FPROT3 0x40020010
97 #define FTFx_FDPROT 0x40020017
98 #define SIM_SDID 0x40048024
99 #define SIM_SOPT1 0x40047000
100 #define SIM_FCFG1 0x4004804c
101 #define SIM_FCFG2 0x40048050
102 #define WDOG_STCTRH 0x40052000
103 #define SMC_PMCTRL 0x4007E001
104 #define SMC_PMSTAT 0x4007E003
105
106 /* Values */
107 #define PM_STAT_RUN 0x01
108 #define PM_STAT_VLPR 0x04
109 #define PM_CTRL_RUNM_RUN 0x00
110
111 /* Commands */
112 #define FTFx_CMD_BLOCKSTAT 0x00
113 #define FTFx_CMD_SECTSTAT 0x01
114 #define FTFx_CMD_LWORDPROG 0x06
115 #define FTFx_CMD_SECTERASE 0x09
116 #define FTFx_CMD_SECTWRITE 0x0b
117 #define FTFx_CMD_MASSERASE 0x44
118 #define FTFx_CMD_PGMPART 0x80
119 #define FTFx_CMD_SETFLEXRAM 0x81
120
121 /* The older Kinetis K series uses the following SDID layout :
122 * Bit 31-16 : 0
123 * Bit 15-12 : REVID
124 * Bit 11-7 : DIEID
125 * Bit 6-4 : FAMID
126 * Bit 3-0 : PINID
127 *
128 * The newer Kinetis series uses the following SDID layout :
129 * Bit 31-28 : FAMID
130 * Bit 27-24 : SUBFAMID
131 * Bit 23-20 : SERIESID
132 * Bit 19-16 : SRAMSIZE
133 * Bit 15-12 : REVID
134 * Bit 6-4 : Reserved (0)
135 * Bit 3-0 : PINID
136 *
137 * We assume that if bits 31-16 are 0 then it's an older
138 * K-series MCU.
139 */
140
141 #define KINETIS_SOPT1_RAMSIZE_MASK 0x0000F000
142 #define KINETIS_SOPT1_RAMSIZE_K24FN1M 0x0000B000
143
144 #define KINETIS_SDID_K_SERIES_MASK 0x0000FFFF
145
146 #define KINETIS_SDID_DIEID_MASK 0x00000F80
147
148 #define KINETIS_SDID_DIEID_K22FN128 0x00000680 /* smaller pflash with FTFA */
149 #define KINETIS_SDID_DIEID_K22FN256 0x00000A80
150 #define KINETIS_SDID_DIEID_K22FN512 0x00000E80
151 #define KINETIS_SDID_DIEID_K24FN256 0x00000700
152
153 #define KINETIS_SDID_DIEID_K24FN1M 0x00000300 /* Detect Errata 7534 */
154
155 /* We can't rely solely on the FAMID field to determine the MCU
156 * type since some FAMID values identify multiple MCUs with
157 * different flash sector sizes (K20 and K22 for instance).
158 * Therefore we combine it with the DIEID bits which may possibly
159 * break if Freescale bumps the DIEID for a particular MCU. */
160 #define KINETIS_K_SDID_TYPE_MASK 0x00000FF0
161 #define KINETIS_K_SDID_K10_M50 0x00000000
162 #define KINETIS_K_SDID_K10_M72 0x00000080
163 #define KINETIS_K_SDID_K10_M100 0x00000100
164 #define KINETIS_K_SDID_K10_M120 0x00000180
165 #define KINETIS_K_SDID_K11 0x00000220
166 #define KINETIS_K_SDID_K12 0x00000200
167 #define KINETIS_K_SDID_K20_M50 0x00000010
168 #define KINETIS_K_SDID_K20_M72 0x00000090
169 #define KINETIS_K_SDID_K20_M100 0x00000110
170 #define KINETIS_K_SDID_K20_M120 0x00000190
171 #define KINETIS_K_SDID_K21_M50 0x00000230
172 #define KINETIS_K_SDID_K21_M120 0x00000330
173 #define KINETIS_K_SDID_K22_M50 0x00000210
174 #define KINETIS_K_SDID_K22_M120 0x00000310
175 #define KINETIS_K_SDID_K30_M72 0x000000A0
176 #define KINETIS_K_SDID_K30_M100 0x00000120
177 #define KINETIS_K_SDID_K40_M72 0x000000B0
178 #define KINETIS_K_SDID_K40_M100 0x00000130
179 #define KINETIS_K_SDID_K50_M72 0x000000E0
180 #define KINETIS_K_SDID_K51_M72 0x000000F0
181 #define KINETIS_K_SDID_K53 0x00000170
182 #define KINETIS_K_SDID_K60_M100 0x00000140
183 #define KINETIS_K_SDID_K60_M150 0x000001C0
184 #define KINETIS_K_SDID_K70_M150 0x000001D0
185
186 #define KINETIS_SDID_SERIESID_MASK 0x00F00000
187 #define KINETIS_SDID_SERIESID_K 0x00000000
188 #define KINETIS_SDID_SERIESID_KL 0x00100000
189 #define KINETIS_SDID_SERIESID_KW 0x00500000
190 #define KINETIS_SDID_SERIESID_KV 0x00600000
191
192 #define KINETIS_SDID_SUBFAMID_MASK 0x0F000000
193 #define KINETIS_SDID_SUBFAMID_KX0 0x00000000
194 #define KINETIS_SDID_SUBFAMID_KX1 0x01000000
195 #define KINETIS_SDID_SUBFAMID_KX2 0x02000000
196 #define KINETIS_SDID_SUBFAMID_KX3 0x03000000
197 #define KINETIS_SDID_SUBFAMID_KX4 0x04000000
198 #define KINETIS_SDID_SUBFAMID_KX5 0x05000000
199 #define KINETIS_SDID_SUBFAMID_KX6 0x06000000
200
201 #define KINETIS_SDID_FAMILYID_MASK 0xF0000000
202 #define KINETIS_SDID_FAMILYID_K0X 0x00000000
203 #define KINETIS_SDID_FAMILYID_K1X 0x10000000
204 #define KINETIS_SDID_FAMILYID_K2X 0x20000000
205 #define KINETIS_SDID_FAMILYID_K3X 0x30000000
206 #define KINETIS_SDID_FAMILYID_K4X 0x40000000
207 #define KINETIS_SDID_FAMILYID_K6X 0x60000000
208 #define KINETIS_SDID_FAMILYID_K7X 0x70000000
209
210 struct kinetis_flash_bank {
211 bool probed;
212 uint32_t sector_size;
213 uint32_t max_flash_prog_size;
214 uint32_t protection_size;
215 uint32_t prog_base; /* base address for FTFx operations */
216 /* same as bank->base for pflash, differs for FlexNVM */
217 uint32_t protection_block; /* number of first protection block in this bank */
218
219 uint32_t sim_sdid;
220 uint32_t sim_fcfg1;
221 uint32_t sim_fcfg2;
222
223 enum {
224 FC_AUTO = 0,
225 FC_PFLASH,
226 FC_FLEX_NVM,
227 FC_FLEX_RAM,
228 } flash_class;
229
230 enum {
231 FS_PROGRAM_SECTOR = 1,
232 FS_PROGRAM_LONGWORD = 2,
233 FS_PROGRAM_PHRASE = 4, /* Unsupported */
234 FS_INVALIDATE_CACHE = 8,
235 } flash_support;
236 };
237
238 #define MDM_AP 1
239
240 #define MDM_REG_STAT 0x00
241 #define MDM_REG_CTRL 0x04
242 #define MDM_REG_ID 0xfc
243
244 #define MDM_STAT_FMEACK (1<<0)
245 #define MDM_STAT_FREADY (1<<1)
246 #define MDM_STAT_SYSSEC (1<<2)
247 #define MDM_STAT_SYSRES (1<<3)
248 #define MDM_STAT_FMEEN (1<<5)
249 #define MDM_STAT_BACKDOOREN (1<<6)
250 #define MDM_STAT_LPEN (1<<7)
251 #define MDM_STAT_VLPEN (1<<8)
252 #define MDM_STAT_LLSMODEXIT (1<<9)
253 #define MDM_STAT_VLLSXMODEXIT (1<<10)
254 #define MDM_STAT_CORE_HALTED (1<<16)
255 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
256 #define MDM_STAT_CORESLEEPING (1<<18)
257
258 #define MDM_CTRL_FMEIP (1<<0)
259 #define MDM_CTRL_DBG_DIS (1<<1)
260 #define MDM_CTRL_DBG_REQ (1<<2)
261 #define MDM_CTRL_SYS_RES_REQ (1<<3)
262 #define MDM_CTRL_CORE_HOLD_RES (1<<4)
263 #define MDM_CTRL_VLLSX_DBG_REQ (1<<5)
264 #define MDM_CTRL_VLLSX_DBG_ACK (1<<6)
265 #define MDM_CTRL_VLLSX_STAT_ACK (1<<7)
266
267 #define MDM_ACCESS_TIMEOUT 500 /* msec */
268
269
270 static bool allow_fcf_writes;
271 static uint8_t fcf_fopt = 0xff;
272
273
274 struct flash_driver kinetis_flash;
275 static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
276 uint32_t offset, uint32_t count);
277 static int kinetis_auto_probe(struct flash_bank *bank);
278
279
280 static int kinetis_mdm_write_register(struct adiv5_dap *dap, unsigned reg, uint32_t value)
281 {
282 int retval;
283 LOG_DEBUG("MDM_REG[0x%02x] <- %08" PRIX32, reg, value);
284
285 retval = dap_queue_ap_write(dap_ap(dap, MDM_AP), reg, value);
286 if (retval != ERROR_OK) {
287 LOG_DEBUG("MDM: failed to queue a write request");
288 return retval;
289 }
290
291 retval = dap_run(dap);
292 if (retval != ERROR_OK) {
293 LOG_DEBUG("MDM: dap_run failed");
294 return retval;
295 }
296
297
298 return ERROR_OK;
299 }
300
301 static int kinetis_mdm_read_register(struct adiv5_dap *dap, unsigned reg, uint32_t *result)
302 {
303 int retval;
304
305 retval = dap_queue_ap_read(dap_ap(dap, MDM_AP), reg, result);
306 if (retval != ERROR_OK) {
307 LOG_DEBUG("MDM: failed to queue a read request");
308 return retval;
309 }
310
311 retval = dap_run(dap);
312 if (retval != ERROR_OK) {
313 LOG_DEBUG("MDM: dap_run failed");
314 return retval;
315 }
316
317 LOG_DEBUG("MDM_REG[0x%02x]: %08" PRIX32, reg, *result);
318 return ERROR_OK;
319 }
320
321 static int kinetis_mdm_poll_register(struct adiv5_dap *dap, unsigned reg,
322 uint32_t mask, uint32_t value, uint32_t timeout_ms)
323 {
324 uint32_t val;
325 int retval;
326 int64_t ms_timeout = timeval_ms() + timeout_ms;
327
328 do {
329 retval = kinetis_mdm_read_register(dap, reg, &val);
330 if (retval != ERROR_OK || (val & mask) == value)
331 return retval;
332
333 alive_sleep(1);
334 } while (timeval_ms() < ms_timeout);
335
336 LOG_DEBUG("MDM: polling timed out");
337 return ERROR_FAIL;
338 }
339
340 /*
341 * This command can be used to break a watchdog reset loop when
342 * connecting to an unsecured target. Unlike other commands, halt will
343 * automatically retry as it does not know how far into the boot process
344 * it is when the command is called.
345 */
346 COMMAND_HANDLER(kinetis_mdm_halt)
347 {
348 struct target *target = get_current_target(CMD_CTX);
349 struct cortex_m_common *cortex_m = target_to_cm(target);
350 struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
351 int retval;
352 int tries = 0;
353 uint32_t stat;
354 int64_t ms_timeout = timeval_ms() + MDM_ACCESS_TIMEOUT;
355
356 if (!dap) {
357 LOG_ERROR("Cannot perform halt with a high-level adapter");
358 return ERROR_FAIL;
359 }
360
361 while (true) {
362 tries++;
363
364 kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_CORE_HOLD_RES);
365
366 alive_sleep(1);
367
368 retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &stat);
369 if (retval != ERROR_OK) {
370 LOG_DEBUG("MDM: failed to read MDM_REG_STAT");
371 continue;
372 }
373
374 /* Repeat setting MDM_CTRL_CORE_HOLD_RES until system is out of
375 * reset with flash ready and without security
376 */
377 if ((stat & (MDM_STAT_FREADY | MDM_STAT_SYSSEC | MDM_STAT_SYSRES))
378 == (MDM_STAT_FREADY | MDM_STAT_SYSRES))
379 break;
380
381 if (timeval_ms() >= ms_timeout) {
382 LOG_ERROR("MDM: halt timed out");
383 return ERROR_FAIL;
384 }
385 }
386
387 LOG_DEBUG("MDM: halt succeded after %d attempts.", tries);
388
389 target_poll(target);
390 /* enable polling in case kinetis_check_flash_security_status disabled it */
391 jtag_poll_set_enabled(true);
392
393 alive_sleep(100);
394
395 target->reset_halt = true;
396 target->type->assert_reset(target);
397
398 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
399 if (retval != ERROR_OK) {
400 LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
401 return retval;
402 }
403
404 target->type->deassert_reset(target);
405
406 return ERROR_OK;
407 }
408
409 COMMAND_HANDLER(kinetis_mdm_reset)
410 {
411 struct target *target = get_current_target(CMD_CTX);
412 struct cortex_m_common *cortex_m = target_to_cm(target);
413 struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
414 int retval;
415
416 if (!dap) {
417 LOG_ERROR("Cannot perform reset with a high-level adapter");
418 return ERROR_FAIL;
419 }
420
421 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_SYS_RES_REQ);
422 if (retval != ERROR_OK) {
423 LOG_ERROR("MDM: failed to write MDM_REG_CTRL");
424 return retval;
425 }
426
427 retval = kinetis_mdm_poll_register(dap, MDM_REG_STAT, MDM_STAT_SYSRES, 0, 500);
428 if (retval != ERROR_OK) {
429 LOG_ERROR("MDM: failed to assert reset");
430 return retval;
431 }
432
433 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
434 if (retval != ERROR_OK) {
435 LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
436 return retval;
437 }
438
439 return ERROR_OK;
440 }
441
442 /*
443 * This function implements the procedure to mass erase the flash via
444 * SWD/JTAG on Kinetis K and L series of devices as it is described in
445 * AN4835 "Production Flash Programming Best Practices for Kinetis K-
446 * and L-series MCUs" Section 4.2.1. To prevent a watchdog reset loop,
447 * the core remains halted after this function completes as suggested
448 * by the application note.
449 */
450 COMMAND_HANDLER(kinetis_mdm_mass_erase)
451 {
452 struct target *target = get_current_target(CMD_CTX);
453 struct cortex_m_common *cortex_m = target_to_cm(target);
454 struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
455
456 if (!dap) {
457 LOG_ERROR("Cannot perform mass erase with a high-level adapter");
458 return ERROR_FAIL;
459 }
460
461 int retval;
462
463 /*
464 * ... Power on the processor, or if power has already been
465 * applied, assert the RESET pin to reset the processor. For
466 * devices that do not have a RESET pin, write the System
467 * Reset Request bit in the MDM-AP control register after
468 * establishing communication...
469 */
470
471 /* assert SRST if configured */
472 bool has_srst = jtag_get_reset_config() & RESET_HAS_SRST;
473 if (has_srst)
474 adapter_assert_reset();
475
476 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_SYS_RES_REQ);
477 if (retval != ERROR_OK && !has_srst) {
478 LOG_ERROR("MDM: failed to assert reset");
479 goto deassert_reset_and_exit;
480 }
481
482 /*
483 * ... Read the MDM-AP status register repeatedly and wait for
484 * stable conditions suitable for mass erase:
485 * - mass erase is enabled
486 * - flash is ready
487 * - reset is finished
488 *
489 * Mass erase is started as soon as all conditions are met in 32
490 * subsequent status reads.
491 *
492 * In case of not stable conditions (RESET/WDOG loop in secured device)
493 * the user is asked for manual pressing of RESET button
494 * as a last resort.
495 */
496 int cnt_mass_erase_disabled = 0;
497 int cnt_ready = 0;
498 int64_t ms_start = timeval_ms();
499 bool man_reset_requested = false;
500
501 do {
502 uint32_t stat = 0;
503 int64_t ms_elapsed = timeval_ms() - ms_start;
504
505 if (!man_reset_requested && ms_elapsed > 100) {
506 LOG_INFO("MDM: Press RESET button now if possible.");
507 man_reset_requested = true;
508 }
509
510 if (ms_elapsed > 3000) {
511 LOG_ERROR("MDM: waiting for mass erase conditions timed out.");
512 LOG_INFO("Mass erase of a secured MCU is not possible without hardware reset.");
513 LOG_INFO("Connect SRST, use 'reset_config srst_only' and retry.");
514 goto deassert_reset_and_exit;
515 }
516 retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &stat);
517 if (retval != ERROR_OK) {
518 cnt_ready = 0;
519 continue;
520 }
521
522 if (!(stat & MDM_STAT_FMEEN)) {
523 cnt_ready = 0;
524 cnt_mass_erase_disabled++;
525 if (cnt_mass_erase_disabled > 10) {
526 LOG_ERROR("MDM: mass erase is disabled");
527 goto deassert_reset_and_exit;
528 }
529 continue;
530 }
531
532 if ((stat & (MDM_STAT_FREADY | MDM_STAT_SYSRES)) == MDM_STAT_FREADY)
533 cnt_ready++;
534 else
535 cnt_ready = 0;
536
537 } while (cnt_ready < 32);
538
539 /*
540 * ... Write the MDM-AP control register to set the Flash Mass
541 * Erase in Progress bit. This will start the mass erase
542 * process...
543 */
544 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, MDM_CTRL_SYS_RES_REQ | MDM_CTRL_FMEIP);
545 if (retval != ERROR_OK) {
546 LOG_ERROR("MDM: failed to start mass erase");
547 goto deassert_reset_and_exit;
548 }
549
550 /*
551 * ... Read the MDM-AP control register until the Flash Mass
552 * Erase in Progress bit clears...
553 * Data sheed defines erase time <3.6 sec/512kB flash block.
554 * The biggest device has 4 pflash blocks => timeout 16 sec.
555 */
556 retval = kinetis_mdm_poll_register(dap, MDM_REG_CTRL, MDM_CTRL_FMEIP, 0, 16000);
557 if (retval != ERROR_OK) {
558 LOG_ERROR("MDM: mass erase timeout");
559 goto deassert_reset_and_exit;
560 }
561
562 target_poll(target);
563 /* enable polling in case kinetis_check_flash_security_status disabled it */
564 jtag_poll_set_enabled(true);
565
566 alive_sleep(100);
567
568 target->reset_halt = true;
569 target->type->assert_reset(target);
570
571 /*
572 * ... Negate the RESET signal or clear the System Reset Request
573 * bit in the MDM-AP control register.
574 */
575 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
576 if (retval != ERROR_OK)
577 LOG_ERROR("MDM: failed to clear MDM_REG_CTRL");
578
579 target->type->deassert_reset(target);
580
581 return retval;
582
583 deassert_reset_and_exit:
584 kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
585 if (has_srst)
586 adapter_deassert_reset();
587 return retval;
588 }
589
590 static const uint32_t kinetis_known_mdm_ids[] = {
591 0x001C0000, /* Kinetis-K Series */
592 0x001C0020, /* Kinetis-L/M/V/E Series */
593 };
594
595 /*
596 * This function implements the procedure to connect to
597 * SWD/JTAG on Kinetis K and L series of devices as it is described in
598 * AN4835 "Production Flash Programming Best Practices for Kinetis K-
599 * and L-series MCUs" Section 4.1.1
600 */
601 COMMAND_HANDLER(kinetis_check_flash_security_status)
602 {
603 struct target *target = get_current_target(CMD_CTX);
604 struct cortex_m_common *cortex_m = target_to_cm(target);
605 struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
606
607 if (!dap) {
608 LOG_WARNING("Cannot check flash security status with a high-level adapter");
609 return ERROR_OK;
610 }
611
612 if (!dap->ops)
613 return ERROR_OK; /* too early to check, in JTAG mode ops may not be initialised */
614
615 uint32_t val;
616 int retval;
617
618 /*
619 * ... The MDM-AP ID register can be read to verify that the
620 * connection is working correctly...
621 */
622 retval = kinetis_mdm_read_register(dap, MDM_REG_ID, &val);
623 if (retval != ERROR_OK) {
624 LOG_ERROR("MDM: failed to read ID register");
625 return ERROR_OK;
626 }
627
628 if (val == 0)
629 return ERROR_OK; /* dap not yet initialised */
630
631 bool found = false;
632 for (size_t i = 0; i < ARRAY_SIZE(kinetis_known_mdm_ids); i++) {
633 if (val == kinetis_known_mdm_ids[i]) {
634 found = true;
635 break;
636 }
637 }
638
639 if (!found)
640 LOG_WARNING("MDM: unknown ID %08" PRIX32, val);
641
642 /*
643 * ... Read the System Security bit to determine if security is enabled.
644 * If System Security = 0, then proceed. If System Security = 1, then
645 * communication with the internals of the processor, including the
646 * flash, will not be possible without issuing a mass erase command or
647 * unsecuring the part through other means (backdoor key unlock)...
648 */
649 retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &val);
650 if (retval != ERROR_OK) {
651 LOG_ERROR("MDM: failed to read MDM_REG_STAT");
652 return ERROR_OK;
653 }
654
655 /*
656 * System Security bit is also active for short time during reset.
657 * If a MCU has blank flash and runs in RESET/WDOG loop,
658 * System Security bit is active most of time!
659 * We should observe Flash Ready bit and read status several times
660 * to avoid false detection of secured MCU
661 */
662 int secured_score = 0, flash_not_ready_score = 0;
663
664 if ((val & (MDM_STAT_SYSSEC | MDM_STAT_FREADY)) != MDM_STAT_FREADY) {
665 uint32_t stats[32];
666 int i;
667
668 for (i = 0; i < 32; i++) {
669 stats[i] = MDM_STAT_FREADY;
670 dap_queue_ap_read(dap_ap(dap, MDM_AP), MDM_REG_STAT, &stats[i]);
671 }
672 retval = dap_run(dap);
673 if (retval != ERROR_OK) {
674 LOG_DEBUG("MDM: dap_run failed when validating secured state");
675 return ERROR_OK;
676 }
677 for (i = 0; i < 32; i++) {
678 if (stats[i] & MDM_STAT_SYSSEC)
679 secured_score++;
680 if (!(stats[i] & MDM_STAT_FREADY))
681 flash_not_ready_score++;
682 }
683 }
684
685 if (flash_not_ready_score <= 8 && secured_score > 24) {
686 jtag_poll_set_enabled(false);
687
688 LOG_WARNING("*********** ATTENTION! ATTENTION! ATTENTION! ATTENTION! **********");
689 LOG_WARNING("**** ****");
690 LOG_WARNING("**** Your Kinetis MCU is in secured state, which means that, ****");
691 LOG_WARNING("**** with exception for very basic communication, JTAG/SWD ****");
692 LOG_WARNING("**** interface will NOT work. In order to restore its ****");
693 LOG_WARNING("**** functionality please issue 'kinetis mdm mass_erase' ****");
694 LOG_WARNING("**** command, power cycle the MCU and restart OpenOCD. ****");
695 LOG_WARNING("**** ****");
696 LOG_WARNING("*********** ATTENTION! ATTENTION! ATTENTION! ATTENTION! **********");
697
698 } else if (flash_not_ready_score > 24) {
699 jtag_poll_set_enabled(false);
700 LOG_WARNING("**** Your Kinetis MCU is probably locked-up in RESET/WDOG loop. ****");
701 LOG_WARNING("**** Common reason is a blank flash (at least a reset vector). ****");
702 LOG_WARNING("**** Issue 'kinetis mdm halt' command or if SRST is connected ****");
703 LOG_WARNING("**** and configured, use 'reset halt' ****");
704 LOG_WARNING("**** If MCU cannot be halted, it is likely secured and running ****");
705 LOG_WARNING("**** in RESET/WDOG loop. Issue 'kinetis mdm mass_erase' ****");
706
707 } else {
708 LOG_INFO("MDM: Chip is unsecured. Continuing.");
709 jtag_poll_set_enabled(true);
710 }
711
712 return ERROR_OK;
713 }
714
715 FLASH_BANK_COMMAND_HANDLER(kinetis_flash_bank_command)
716 {
717 struct kinetis_flash_bank *bank_info;
718
719 if (CMD_ARGC < 6)
720 return ERROR_COMMAND_SYNTAX_ERROR;
721
722 LOG_INFO("add flash_bank kinetis %s", bank->name);
723
724 bank_info = malloc(sizeof(struct kinetis_flash_bank));
725
726 memset(bank_info, 0, sizeof(struct kinetis_flash_bank));
727
728 bank->driver_priv = bank_info;
729
730 return ERROR_OK;
731 }
732
733 /* Disable the watchdog on Kinetis devices */
734 int kinetis_disable_wdog(struct target *target, uint32_t sim_sdid)
735 {
736 struct working_area *wdog_algorithm;
737 struct armv7m_algorithm armv7m_info;
738 uint16_t wdog;
739 int retval;
740
741 static const uint8_t kinetis_unlock_wdog_code[] = {
742 #include "../../../contrib/loaders/watchdog/armv7m_kinetis_wdog.inc"
743 };
744
745 /* Decide whether the connected device needs watchdog disabling.
746 * Disable for all Kx and KVx devices, return if it is a KLx */
747
748 if ((sim_sdid & KINETIS_SDID_SERIESID_MASK) == KINETIS_SDID_SERIESID_KL)
749 return ERROR_OK;
750
751 /* The connected device requires watchdog disabling. */
752 retval = target_read_u16(target, WDOG_STCTRH, &wdog);
753 if (retval != ERROR_OK)
754 return retval;
755
756 if ((wdog & 0x1) == 0) {
757 /* watchdog already disabled */
758 return ERROR_OK;
759 }
760 LOG_INFO("Disabling Kinetis watchdog (initial WDOG_STCTRLH = 0x%x)", wdog);
761
762 if (target->state != TARGET_HALTED) {
763 LOG_ERROR("Target not halted");
764 return ERROR_TARGET_NOT_HALTED;
765 }
766
767 retval = target_alloc_working_area(target, sizeof(kinetis_unlock_wdog_code), &wdog_algorithm);
768 if (retval != ERROR_OK)
769 return retval;
770
771 retval = target_write_buffer(target, wdog_algorithm->address,
772 sizeof(kinetis_unlock_wdog_code), (uint8_t *)kinetis_unlock_wdog_code);
773 if (retval != ERROR_OK) {
774 target_free_working_area(target, wdog_algorithm);
775 return retval;
776 }
777
778 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
779 armv7m_info.core_mode = ARM_MODE_THREAD;
780
781 retval = target_run_algorithm(target, 0, NULL, 0, NULL, wdog_algorithm->address,
782 wdog_algorithm->address + (sizeof(kinetis_unlock_wdog_code) - 2),
783 10000, &armv7m_info);
784
785 if (retval != ERROR_OK)
786 LOG_ERROR("error executing kinetis wdog unlock algorithm");
787
788 retval = target_read_u16(target, WDOG_STCTRH, &wdog);
789 if (retval != ERROR_OK)
790 return retval;
791 LOG_INFO("WDOG_STCTRLH = 0x%x", wdog);
792
793 target_free_working_area(target, wdog_algorithm);
794
795 return retval;
796 }
797
798 COMMAND_HANDLER(kinetis_disable_wdog_handler)
799 {
800 int result;
801 uint32_t sim_sdid;
802 struct target *target = get_current_target(CMD_CTX);
803
804 if (CMD_ARGC > 0)
805 return ERROR_COMMAND_SYNTAX_ERROR;
806
807 result = target_read_u32(target, SIM_SDID, &sim_sdid);
808 if (result != ERROR_OK) {
809 LOG_ERROR("Failed to read SIMSDID");
810 return result;
811 }
812
813 result = kinetis_disable_wdog(target, sim_sdid);
814 return result;
815 }
816
817
818 static int kinetis_ftfx_decode_error(uint8_t fstat)
819 {
820 if (fstat & 0x20) {
821 LOG_ERROR("Flash operation failed, illegal command");
822 return ERROR_FLASH_OPER_UNSUPPORTED;
823
824 } else if (fstat & 0x10)
825 LOG_ERROR("Flash operation failed, protection violated");
826
827 else if (fstat & 0x40)
828 LOG_ERROR("Flash operation failed, read collision");
829
830 else if (fstat & 0x80)
831 return ERROR_OK;
832
833 else
834 LOG_ERROR("Flash operation timed out");
835
836 return ERROR_FLASH_OPERATION_FAILED;
837 }
838
839
840 static int kinetis_ftfx_prepare(struct target *target)
841 {
842 int result, i;
843 uint8_t fstat;
844
845 /* wait until busy */
846 for (i = 0; i < 50; i++) {
847 result = target_read_u8(target, FTFx_FSTAT, &fstat);
848 if (result != ERROR_OK)
849 return result;
850
851 if (fstat & 0x80)
852 break;
853 }
854
855 if ((fstat & 0x80) == 0) {
856 LOG_ERROR("Flash controller is busy");
857 return ERROR_FLASH_OPERATION_FAILED;
858 }
859 if (fstat != 0x80) {
860 /* reset error flags */
861 result = target_write_u8(target, FTFx_FSTAT, 0x70);
862 }
863 return result;
864 }
865
866 /* Kinetis Program-LongWord Microcodes */
867 static const uint8_t kinetis_flash_write_code[] = {
868 #include "../../../contrib/loaders/flash/kinetis/kinetis_flash.inc"
869 };
870
871 /* Program LongWord Block Write */
872 static int kinetis_write_block(struct flash_bank *bank, const uint8_t *buffer,
873 uint32_t offset, uint32_t wcount)
874 {
875 struct target *target = bank->target;
876 uint32_t buffer_size = 2048; /* Default minimum value */
877 struct working_area *write_algorithm;
878 struct working_area *source;
879 struct kinetis_flash_bank *kinfo = bank->driver_priv;
880 uint32_t address = kinfo->prog_base + offset;
881 uint32_t end_address;
882 struct reg_param reg_params[5];
883 struct armv7m_algorithm armv7m_info;
884 int retval;
885 uint8_t fstat;
886
887 /* Increase buffer_size if needed */
888 if (buffer_size < (target->working_area_size/2))
889 buffer_size = (target->working_area_size/2);
890
891 /* allocate working area with flash programming code */
892 if (target_alloc_working_area(target, sizeof(kinetis_flash_write_code),
893 &write_algorithm) != ERROR_OK) {
894 LOG_WARNING("no working area available, can't do block memory writes");
895 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
896 }
897
898 retval = target_write_buffer(target, write_algorithm->address,
899 sizeof(kinetis_flash_write_code), kinetis_flash_write_code);
900 if (retval != ERROR_OK)
901 return retval;
902
903 /* memory buffer */
904 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
905 buffer_size /= 4;
906 if (buffer_size <= 256) {
907 /* free working area, write algorithm already allocated */
908 target_free_working_area(target, write_algorithm);
909
910 LOG_WARNING("No large enough working area available, can't do block memory writes");
911 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
912 }
913 }
914
915 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
916 armv7m_info.core_mode = ARM_MODE_THREAD;
917
918 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* address */
919 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* word count */
920 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
921 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
922 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
923
924 buf_set_u32(reg_params[0].value, 0, 32, address);
925 buf_set_u32(reg_params[1].value, 0, 32, wcount);
926 buf_set_u32(reg_params[2].value, 0, 32, source->address);
927 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
928 buf_set_u32(reg_params[4].value, 0, 32, FTFx_FSTAT);
929
930 retval = target_run_flash_async_algorithm(target, buffer, wcount, 4,
931 0, NULL,
932 5, reg_params,
933 source->address, source->size,
934 write_algorithm->address, 0,
935 &armv7m_info);
936
937 if (retval == ERROR_FLASH_OPERATION_FAILED) {
938 end_address = buf_get_u32(reg_params[0].value, 0, 32);
939
940 LOG_ERROR("Error writing flash at %08" PRIx32, end_address);
941
942 retval = target_read_u8(target, FTFx_FSTAT, &fstat);
943 if (retval == ERROR_OK) {
944 retval = kinetis_ftfx_decode_error(fstat);
945
946 /* reset error flags */
947 target_write_u8(target, FTFx_FSTAT, 0x70);
948 }
949 } else if (retval != ERROR_OK)
950 LOG_ERROR("Error executing kinetis Flash programming algorithm");
951
952 target_free_working_area(target, source);
953 target_free_working_area(target, write_algorithm);
954
955 destroy_reg_param(&reg_params[0]);
956 destroy_reg_param(&reg_params[1]);
957 destroy_reg_param(&reg_params[2]);
958 destroy_reg_param(&reg_params[3]);
959 destroy_reg_param(&reg_params[4]);
960
961 return retval;
962 }
963
964 static int kinetis_protect(struct flash_bank *bank, int set, int first, int last)
965 {
966 int i;
967
968 if (allow_fcf_writes) {
969 LOG_ERROR("Protection setting is possible with 'kinetis fcf_source protection' only!");
970 return ERROR_FAIL;
971 }
972
973 if (!bank->prot_blocks || bank->num_prot_blocks == 0) {
974 LOG_ERROR("No protection possible for current bank!");
975 return ERROR_FLASH_BANK_INVALID;
976 }
977
978 for (i = first; i < bank->num_prot_blocks && i <= last; i++)
979 bank->prot_blocks[i].is_protected = set;
980
981 LOG_INFO("Protection bits will be written at the next FCF sector erase or write.");
982 LOG_INFO("Do not issue 'flash info' command until protection is written,");
983 LOG_INFO("doing so would re-read protection status from MCU.");
984
985 return ERROR_OK;
986 }
987
988 static int kinetis_protect_check(struct flash_bank *bank)
989 {
990 struct kinetis_flash_bank *kinfo = bank->driver_priv;
991 int result;
992 int i, b;
993 uint32_t fprot;
994
995 if (kinfo->flash_class == FC_PFLASH) {
996
997 /* read protection register */
998 result = target_read_u32(bank->target, FTFx_FPROT3, &fprot);
999 if (result != ERROR_OK)
1000 return result;
1001
1002 /* Every bit protects 1/32 of the full flash (not necessarily just this bank) */
1003
1004 } else if (kinfo->flash_class == FC_FLEX_NVM) {
1005 uint8_t fdprot;
1006
1007 /* read protection register */
1008 result = target_read_u8(bank->target, FTFx_FDPROT, &fdprot);
1009 if (result != ERROR_OK)
1010 return result;
1011
1012 fprot = fdprot;
1013
1014 } else {
1015 LOG_ERROR("Protection checks for FlexRAM not supported");
1016 return ERROR_FLASH_BANK_INVALID;
1017 }
1018
1019 b = kinfo->protection_block;
1020 for (i = 0; i < bank->num_prot_blocks; i++) {
1021 if ((fprot >> b) & 1)
1022 bank->prot_blocks[i].is_protected = 0;
1023 else
1024 bank->prot_blocks[i].is_protected = 1;
1025
1026 b++;
1027 }
1028
1029 return ERROR_OK;
1030 }
1031
1032
1033 static int kinetis_fill_fcf(struct flash_bank *bank, uint8_t *fcf)
1034 {
1035 uint32_t fprot = 0xffffffff;
1036 uint8_t fsec = 0xfe; /* set MCU unsecure */
1037 uint8_t fdprot = 0xff;
1038 int i;
1039 uint32_t pflash_bit;
1040 uint8_t dflash_bit;
1041 struct flash_bank *bank_iter;
1042 struct kinetis_flash_bank *kinfo;
1043
1044 memset(fcf, 0xff, FCF_SIZE);
1045
1046 pflash_bit = 1;
1047 dflash_bit = 1;
1048
1049 /* iterate over all kinetis banks */
1050 /* current bank is bank 0, it contains FCF */
1051 for (bank_iter = bank; bank_iter; bank_iter = bank_iter->next) {
1052 if (bank_iter->driver != &kinetis_flash
1053 || bank_iter->target != bank->target)
1054 continue;
1055
1056 kinetis_auto_probe(bank_iter);
1057
1058 kinfo = bank->driver_priv;
1059 if (!kinfo)
1060 continue;
1061
1062 if (kinfo->flash_class == FC_PFLASH) {
1063 for (i = 0; i < bank_iter->num_prot_blocks; i++) {
1064 if (bank_iter->prot_blocks[i].is_protected == 1)
1065 fprot &= ~pflash_bit;
1066
1067 pflash_bit <<= 1;
1068 }
1069
1070 } else if (kinfo->flash_class == FC_FLEX_NVM) {
1071 for (i = 0; i < bank_iter->num_prot_blocks; i++) {
1072 if (bank_iter->prot_blocks[i].is_protected == 1)
1073 fdprot &= ~dflash_bit;
1074
1075 dflash_bit <<= 1;
1076 }
1077
1078 }
1079 }
1080
1081 target_buffer_set_u32(bank->target, fcf + FCF_FPROT, fprot);
1082 fcf[FCF_FSEC] = fsec;
1083 fcf[FCF_FOPT] = fcf_fopt;
1084 fcf[FCF_FDPROT] = fdprot;
1085 return ERROR_OK;
1086 }
1087
1088 static int kinetis_ftfx_command(struct target *target, uint8_t fcmd, uint32_t faddr,
1089 uint8_t fccob4, uint8_t fccob5, uint8_t fccob6, uint8_t fccob7,
1090 uint8_t fccob8, uint8_t fccob9, uint8_t fccoba, uint8_t fccobb,
1091 uint8_t *ftfx_fstat)
1092 {
1093 uint8_t command[12] = {faddr & 0xff, (faddr >> 8) & 0xff, (faddr >> 16) & 0xff, fcmd,
1094 fccob7, fccob6, fccob5, fccob4,
1095 fccobb, fccoba, fccob9, fccob8};
1096 int result;
1097 uint8_t fstat;
1098 int64_t ms_timeout = timeval_ms() + 250;
1099
1100 result = target_write_memory(target, FTFx_FCCOB3, 4, 3, command);
1101 if (result != ERROR_OK)
1102 return result;
1103
1104 /* start command */
1105 result = target_write_u8(target, FTFx_FSTAT, 0x80);
1106 if (result != ERROR_OK)
1107 return result;
1108
1109 /* wait for done */
1110 do {
1111 result = target_read_u8(target, FTFx_FSTAT, &fstat);
1112
1113 if (result != ERROR_OK)
1114 return result;
1115
1116 if (fstat & 0x80)
1117 break;
1118
1119 } while (timeval_ms() < ms_timeout);
1120
1121 if (ftfx_fstat)
1122 *ftfx_fstat = fstat;
1123
1124 if ((fstat & 0xf0) != 0x80) {
1125 LOG_DEBUG("ftfx command failed FSTAT: %02X FCCOB: %02X%02X%02X%02X %02X%02X%02X%02X %02X%02X%02X%02X",
1126 fstat, command[3], command[2], command[1], command[0],
1127 command[7], command[6], command[5], command[4],
1128 command[11], command[10], command[9], command[8]);
1129
1130 return kinetis_ftfx_decode_error(fstat);
1131 }
1132
1133 return ERROR_OK;
1134 }
1135
1136
1137 static int kinetis_check_run_mode(struct target *target)
1138 {
1139 int result, i;
1140 uint8_t pmctrl, pmstat;
1141
1142 if (target->state != TARGET_HALTED) {
1143 LOG_ERROR("Target not halted");
1144 return ERROR_TARGET_NOT_HALTED;
1145 }
1146
1147 result = target_read_u8(target, SMC_PMSTAT, &pmstat);
1148 if (result != ERROR_OK)
1149 return result;
1150
1151 if (pmstat == PM_STAT_RUN)
1152 return ERROR_OK;
1153
1154 if (pmstat == PM_STAT_VLPR) {
1155 /* It is safe to switch from VLPR to RUN mode without changing clock */
1156 LOG_INFO("Switching from VLPR to RUN mode.");
1157 pmctrl = PM_CTRL_RUNM_RUN;
1158 result = target_write_u8(target, SMC_PMCTRL, pmctrl);
1159 if (result != ERROR_OK)
1160 return result;
1161
1162 for (i = 100; i; i--) {
1163 result = target_read_u8(target, SMC_PMSTAT, &pmstat);
1164 if (result != ERROR_OK)
1165 return result;
1166
1167 if (pmstat == PM_STAT_RUN)
1168 return ERROR_OK;
1169 }
1170 }
1171
1172 LOG_ERROR("Flash operation not possible in current run mode: SMC_PMSTAT: 0x%x", pmstat);
1173 LOG_ERROR("Issue a 'reset init' command.");
1174 return ERROR_TARGET_NOT_HALTED;
1175 }
1176
1177
1178 static void kinetis_invalidate_flash_cache(struct flash_bank *bank)
1179 {
1180 struct kinetis_flash_bank *kinfo = bank->driver_priv;
1181 uint8_t pfb01cr_byte2 = 0xf0;
1182
1183 if (!(kinfo->flash_support & FS_INVALIDATE_CACHE))
1184 return;
1185
1186 target_write_memory(bank->target, FMC_PFB01CR + 2, 1, 1, &pfb01cr_byte2);
1187 return;
1188 }
1189
1190
1191 static int kinetis_erase(struct flash_bank *bank, int first, int last)
1192 {
1193 int result, i;
1194 struct kinetis_flash_bank *kinfo = bank->driver_priv;
1195
1196 result = kinetis_check_run_mode(bank->target);
1197 if (result != ERROR_OK)
1198 return result;
1199
1200 /* reset error flags */
1201 result = kinetis_ftfx_prepare(bank->target);
1202 if (result != ERROR_OK)
1203 return result;
1204
1205 if ((first > bank->num_sectors) || (last > bank->num_sectors))
1206 return ERROR_FLASH_OPERATION_FAILED;
1207
1208 /*
1209 * FIXME: TODO: use the 'Erase Flash Block' command if the
1210 * requested erase is PFlash or NVM and encompasses the entire
1211 * block. Should be quicker.
1212 */
1213 for (i = first; i <= last; i++) {
1214 /* set command and sector address */
1215 result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTERASE, kinfo->prog_base + bank->sectors[i].offset,
1216 0, 0, 0, 0, 0, 0, 0, 0, NULL);
1217
1218 if (result != ERROR_OK) {
1219 LOG_WARNING("erase sector %d failed", i);
1220 return ERROR_FLASH_OPERATION_FAILED;
1221 }
1222
1223 bank->sectors[i].is_erased = 1;
1224
1225 if (bank->base == 0
1226 && bank->sectors[i].offset <= FCF_ADDRESS
1227 && bank->sectors[i].offset + bank->sectors[i].size > FCF_ADDRESS + FCF_SIZE) {
1228 if (allow_fcf_writes) {
1229 LOG_WARNING("Flash Configuration Field erased, DO NOT reset or power off the device");
1230 LOG_WARNING("until correct FCF is programmed or MCU gets security lock.");
1231 } else {
1232 uint8_t fcf_buffer[FCF_SIZE];
1233
1234 kinetis_fill_fcf(bank, fcf_buffer);
1235 result = kinetis_write_inner(bank, fcf_buffer, FCF_ADDRESS, FCF_SIZE);
1236 if (result != ERROR_OK)
1237 LOG_WARNING("Flash Configuration Field write failed");
1238 bank->sectors[i].is_erased = 0;
1239 }
1240 }
1241 }
1242
1243 kinetis_invalidate_flash_cache(bank);
1244
1245 return ERROR_OK;
1246 }
1247
1248 static int kinetis_make_ram_ready(struct target *target)
1249 {
1250 int result;
1251 uint8_t ftfx_fcnfg;
1252
1253 /* check if ram ready */
1254 result = target_read_u8(target, FTFx_FCNFG, &ftfx_fcnfg);
1255 if (result != ERROR_OK)
1256 return result;
1257
1258 if (ftfx_fcnfg & (1 << 1))
1259 return ERROR_OK; /* ram ready */
1260
1261 /* make flex ram available */
1262 result = kinetis_ftfx_command(target, FTFx_CMD_SETFLEXRAM, 0x00ff0000,
1263 0, 0, 0, 0, 0, 0, 0, 0, NULL);
1264 if (result != ERROR_OK)
1265 return ERROR_FLASH_OPERATION_FAILED;
1266
1267 /* check again */
1268 result = target_read_u8(target, FTFx_FCNFG, &ftfx_fcnfg);
1269 if (result != ERROR_OK)
1270 return result;
1271
1272 if (ftfx_fcnfg & (1 << 1))
1273 return ERROR_OK; /* ram ready */
1274
1275 return ERROR_FLASH_OPERATION_FAILED;
1276 }
1277
1278
1279 static int kinetis_write_sections(struct flash_bank *bank, const uint8_t *buffer,
1280 uint32_t offset, uint32_t count)
1281 {
1282 int result = ERROR_OK;
1283 struct kinetis_flash_bank *kinfo = bank->driver_priv;
1284 uint8_t *buffer_aligned = NULL;
1285 /*
1286 * Kinetis uses different terms for the granularity of
1287 * sector writes, e.g. "phrase" or "128 bits". We use
1288 * the generic term "chunk". The largest possible
1289 * Kinetis "chunk" is 16 bytes (128 bits).
1290 */
1291 uint32_t prog_section_chunk_bytes = kinfo->sector_size >> 8;
1292 uint32_t prog_size_bytes = kinfo->max_flash_prog_size;
1293
1294 while (count > 0) {
1295 uint32_t size = prog_size_bytes - offset % prog_size_bytes;
1296 uint32_t align_begin = offset % prog_section_chunk_bytes;
1297 uint32_t align_end;
1298 uint32_t size_aligned;
1299 uint16_t chunk_count;
1300 uint8_t ftfx_fstat;
1301
1302 if (size > count)
1303 size = count;
1304
1305 align_end = (align_begin + size) % prog_section_chunk_bytes;
1306 if (align_end)
1307 align_end = prog_section_chunk_bytes - align_end;
1308
1309 size_aligned = align_begin + size + align_end;
1310 chunk_count = size_aligned / prog_section_chunk_bytes;
1311
1312 if (size != size_aligned) {
1313 /* aligned section: the first, the last or the only */
1314 if (!buffer_aligned)
1315 buffer_aligned = malloc(prog_size_bytes);
1316
1317 memset(buffer_aligned, 0xff, size_aligned);
1318 memcpy(buffer_aligned + align_begin, buffer, size);
1319
1320 result = target_write_memory(bank->target, FLEXRAM,
1321 4, size_aligned / 4, buffer_aligned);
1322
1323 LOG_DEBUG("section @ %08" PRIx32 " aligned begin %" PRIu32 ", end %" PRIu32,
1324 bank->base + offset, align_begin, align_end);
1325 } else
1326 result = target_write_memory(bank->target, FLEXRAM,
1327 4, size_aligned / 4, buffer);
1328
1329 LOG_DEBUG("write section @ %08" PRIx32 " with length %" PRIu32 " bytes",
1330 bank->base + offset, size);
1331
1332 if (result != ERROR_OK) {
1333 LOG_ERROR("target_write_memory failed");
1334 break;
1335 }
1336
1337 /* execute section-write command */
1338 result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTWRITE,
1339 kinfo->prog_base + offset - align_begin,
1340 chunk_count>>8, chunk_count, 0, 0,
1341 0, 0, 0, 0, &ftfx_fstat);
1342
1343 if (result != ERROR_OK) {
1344 LOG_ERROR("Error writing section at %08" PRIx32, bank->base + offset);
1345 break;
1346 }
1347
1348 if (ftfx_fstat & 0x01)
1349 LOG_ERROR("Flash write error at %08" PRIx32, bank->base + offset);
1350
1351 buffer += size;
1352 offset += size;
1353 count -= size;
1354 }
1355
1356 free(buffer_aligned);
1357 return result;
1358 }
1359
1360
1361 static int kinetis_write_inner(struct flash_bank *bank, const uint8_t *buffer,
1362 uint32_t offset, uint32_t count)
1363 {
1364 int result, fallback = 0;
1365 struct kinetis_flash_bank *kinfo = bank->driver_priv;
1366
1367 if (!(kinfo->flash_support & FS_PROGRAM_SECTOR)) {
1368 /* fallback to longword write */
1369 fallback = 1;
1370 LOG_WARNING("This device supports Program Longword execution only.");
1371 } else {
1372 result = kinetis_make_ram_ready(bank->target);
1373 if (result != ERROR_OK) {
1374 fallback = 1;
1375 LOG_WARNING("FlexRAM not ready, fallback to slow longword write.");
1376 }
1377 }
1378
1379 LOG_DEBUG("flash write @08%" PRIx32, bank->base + offset);
1380
1381 if (fallback == 0) {
1382 /* program section command */
1383 kinetis_write_sections(bank, buffer, offset, count);
1384 }
1385 else if (kinfo->flash_support & FS_PROGRAM_LONGWORD) {
1386 /* program longword command, not supported in FTFE */
1387 uint8_t *new_buffer = NULL;
1388
1389 /* check word alignment */
1390 if (offset & 0x3) {
1391 LOG_ERROR("offset 0x%" PRIx32 " breaks the required alignment", offset);
1392 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
1393 }
1394
1395 if (count & 0x3) {
1396 uint32_t old_count = count;
1397 count = (old_count | 3) + 1;
1398 new_buffer = malloc(count);
1399 if (new_buffer == NULL) {
1400 LOG_ERROR("odd number of bytes to write and no memory "
1401 "for padding buffer");
1402 return ERROR_FAIL;
1403 }
1404 LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " "
1405 "and padding with 0xff", old_count, count);
1406 memset(new_buffer + old_count, 0xff, count - old_count);
1407 buffer = memcpy(new_buffer, buffer, old_count);
1408 }
1409
1410 uint32_t words_remaining = count / 4;
1411
1412 kinetis_disable_wdog(bank->target, kinfo->sim_sdid);
1413
1414 /* try using a block write */
1415 result = kinetis_write_block(bank, buffer, offset, words_remaining);
1416
1417 if (result == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
1418 /* if block write failed (no sufficient working area),
1419 * we use normal (slow) single word accesses */
1420 LOG_WARNING("couldn't use block writes, falling back to single "
1421 "memory accesses");
1422
1423 while (words_remaining) {
1424 uint8_t ftfx_fstat;
1425
1426 LOG_DEBUG("write longword @ %08" PRIx32, (uint32_t)(bank->base + offset));
1427
1428 result = kinetis_ftfx_command(bank->target, FTFx_CMD_LWORDPROG, kinfo->prog_base + offset,
1429 buffer[3], buffer[2], buffer[1], buffer[0],
1430 0, 0, 0, 0, &ftfx_fstat);
1431
1432 if (result != ERROR_OK) {
1433 LOG_ERROR("Error writing longword at %08" PRIx32, bank->base + offset);
1434 break;
1435 }
1436
1437 if (ftfx_fstat & 0x01)
1438 LOG_ERROR("Flash write error at %08" PRIx32, bank->base + offset);
1439
1440 buffer += 4;
1441 offset += 4;
1442 words_remaining--;
1443 }
1444 }
1445 free(new_buffer);
1446 } else {
1447 LOG_ERROR("Flash write strategy not implemented");
1448 return ERROR_FLASH_OPERATION_FAILED;
1449 }
1450
1451 kinetis_invalidate_flash_cache(bank);
1452 return result;
1453 }
1454
1455
1456 static int kinetis_write(struct flash_bank *bank, const uint8_t *buffer,
1457 uint32_t offset, uint32_t count)
1458 {
1459 int result;
1460 bool set_fcf = false;
1461 int sect = 0;
1462
1463 result = kinetis_check_run_mode(bank->target);
1464 if (result != ERROR_OK)
1465 return result;
1466
1467 /* reset error flags */
1468 result = kinetis_ftfx_prepare(bank->target);
1469 if (result != ERROR_OK)
1470 return result;
1471
1472 if (bank->base == 0 && !allow_fcf_writes) {
1473 if (bank->sectors[1].offset <= FCF_ADDRESS)
1474 sect = 1; /* 1kb sector, FCF in 2nd sector */
1475
1476 if (offset < bank->sectors[sect].offset + bank->sectors[sect].size
1477 && offset + count > bank->sectors[sect].offset)
1478 set_fcf = true; /* write to any part of sector with FCF */
1479 }
1480
1481 if (set_fcf) {
1482 uint8_t fcf_buffer[FCF_SIZE];
1483 uint8_t fcf_current[FCF_SIZE];
1484
1485 kinetis_fill_fcf(bank, fcf_buffer);
1486
1487 if (offset < FCF_ADDRESS) {
1488 /* write part preceding FCF */
1489 result = kinetis_write_inner(bank, buffer, offset, FCF_ADDRESS - offset);
1490 if (result != ERROR_OK)
1491 return result;
1492 }
1493
1494 result = target_read_memory(bank->target, FCF_ADDRESS, 4, FCF_SIZE / 4, fcf_current);
1495 if (result == ERROR_OK && memcmp(fcf_current, fcf_buffer, FCF_SIZE) == 0)
1496 set_fcf = false;
1497
1498 if (set_fcf) {
1499 /* write FCF if differs from flash - eliminate multiple writes */
1500 result = kinetis_write_inner(bank, fcf_buffer, FCF_ADDRESS, FCF_SIZE);
1501 if (result != ERROR_OK)
1502 return result;
1503 }
1504
1505 LOG_WARNING("Flash Configuration Field written.");
1506 LOG_WARNING("Reset or power off the device to make settings effective.");
1507
1508 if (offset + count > FCF_ADDRESS + FCF_SIZE) {
1509 uint32_t delta = FCF_ADDRESS + FCF_SIZE - offset;
1510 /* write part after FCF */
1511 result = kinetis_write_inner(bank, buffer + delta, FCF_ADDRESS + FCF_SIZE, count - delta);
1512 }
1513 return result;
1514
1515 } else
1516 /* no FCF fiddling, normal write */
1517 return kinetis_write_inner(bank, buffer, offset, count);
1518 }
1519
1520
1521 static int kinetis_probe(struct flash_bank *bank)
1522 {
1523 int result, i;
1524 uint8_t fcfg1_nvmsize, fcfg1_pfsize, fcfg1_eesize, fcfg1_depart;
1525 uint8_t fcfg2_maxaddr0, fcfg2_pflsh, fcfg2_maxaddr1;
1526 uint32_t nvm_size = 0, pf_size = 0, df_size = 0, ee_size = 0;
1527 unsigned num_blocks = 0, num_pflash_blocks = 0, num_nvm_blocks = 0, first_nvm_bank = 0,
1528 pflash_sector_size_bytes = 0, nvm_sector_size_bytes = 0;
1529 struct target *target = bank->target;
1530 struct kinetis_flash_bank *kinfo = bank->driver_priv;
1531
1532 kinfo->probed = false;
1533
1534 result = target_read_u32(target, SIM_SDID, &kinfo->sim_sdid);
1535 if (result != ERROR_OK)
1536 return result;
1537
1538 if ((kinfo->sim_sdid & (~KINETIS_SDID_K_SERIES_MASK)) == 0) {
1539 /* older K-series MCU */
1540 uint32_t mcu_type = kinfo->sim_sdid & KINETIS_K_SDID_TYPE_MASK;
1541
1542 switch (mcu_type) {
1543 case KINETIS_K_SDID_K10_M50:
1544 case KINETIS_K_SDID_K20_M50:
1545 /* 1kB sectors */
1546 pflash_sector_size_bytes = 1<<10;
1547 nvm_sector_size_bytes = 1<<10;
1548 num_blocks = 2;
1549 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1550 break;
1551 case KINETIS_K_SDID_K10_M72:
1552 case KINETIS_K_SDID_K20_M72:
1553 case KINETIS_K_SDID_K30_M72:
1554 case KINETIS_K_SDID_K30_M100:
1555 case KINETIS_K_SDID_K40_M72:
1556 case KINETIS_K_SDID_K40_M100:
1557 case KINETIS_K_SDID_K50_M72:
1558 /* 2kB sectors, 1kB FlexNVM sectors */
1559 pflash_sector_size_bytes = 2<<10;
1560 nvm_sector_size_bytes = 1<<10;
1561 num_blocks = 2;
1562 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1563 kinfo->max_flash_prog_size = 1<<10;
1564 break;
1565 case KINETIS_K_SDID_K10_M100:
1566 case KINETIS_K_SDID_K20_M100:
1567 case KINETIS_K_SDID_K11:
1568 case KINETIS_K_SDID_K12:
1569 case KINETIS_K_SDID_K21_M50:
1570 case KINETIS_K_SDID_K22_M50:
1571 case KINETIS_K_SDID_K51_M72:
1572 case KINETIS_K_SDID_K53:
1573 case KINETIS_K_SDID_K60_M100:
1574 /* 2kB sectors */
1575 pflash_sector_size_bytes = 2<<10;
1576 nvm_sector_size_bytes = 2<<10;
1577 num_blocks = 2;
1578 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1579 break;
1580 case KINETIS_K_SDID_K21_M120:
1581 case KINETIS_K_SDID_K22_M120:
1582 /* 4kB sectors (MK21FN1M0, MK21FX512, MK22FN1M0, MK22FX512) */
1583 pflash_sector_size_bytes = 4<<10;
1584 kinfo->max_flash_prog_size = 1<<10;
1585 nvm_sector_size_bytes = 4<<10;
1586 num_blocks = 2;
1587 kinfo->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1588 break;
1589 case KINETIS_K_SDID_K10_M120:
1590 case KINETIS_K_SDID_K20_M120:
1591 case KINETIS_K_SDID_K60_M150:
1592 case KINETIS_K_SDID_K70_M150:
1593 /* 4kB sectors */
1594 pflash_sector_size_bytes = 4<<10;
1595 nvm_sector_size_bytes = 4<<10;
1596 num_blocks = 4;
1597 kinfo->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1598 break;
1599 default:
1600 LOG_ERROR("Unsupported K-family FAMID");
1601 }
1602 } else {
1603 /* Newer K-series or KL series MCU */
1604 switch (kinfo->sim_sdid & KINETIS_SDID_SERIESID_MASK) {
1605 case KINETIS_SDID_SERIESID_K:
1606 switch (kinfo->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
1607 case KINETIS_SDID_FAMILYID_K0X | KINETIS_SDID_SUBFAMID_KX2:
1608 /* K02FN64, K02FN128: FTFA, 2kB sectors */
1609 pflash_sector_size_bytes = 2<<10;
1610 num_blocks = 1;
1611 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_INVALIDATE_CACHE;
1612 break;
1613
1614 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX2: {
1615 /* MK24FN1M reports as K22, this should detect it (according to errata note 1N83J) */
1616 uint32_t sopt1;
1617 result = target_read_u32(target, SIM_SOPT1, &sopt1);
1618 if (result != ERROR_OK)
1619 return result;
1620
1621 if (((kinfo->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K24FN1M) &&
1622 ((sopt1 & KINETIS_SOPT1_RAMSIZE_MASK) == KINETIS_SOPT1_RAMSIZE_K24FN1M)) {
1623 /* MK24FN1M */
1624 pflash_sector_size_bytes = 4<<10;
1625 num_blocks = 2;
1626 kinfo->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1627 kinfo->max_flash_prog_size = 1<<10;
1628 break;
1629 }
1630 if ((kinfo->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN128
1631 || (kinfo->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN256
1632 || (kinfo->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN512) {
1633 /* K22 with new-style SDID - smaller pflash with FTFA, 2kB sectors */
1634 pflash_sector_size_bytes = 2<<10;
1635 /* autodetect 1 or 2 blocks */
1636 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_INVALIDATE_CACHE;
1637 break;
1638 }
1639 LOG_ERROR("Unsupported Kinetis K22 DIEID");
1640 break;
1641 }
1642 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX4:
1643 pflash_sector_size_bytes = 4<<10;
1644 if ((kinfo->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K24FN256) {
1645 /* K24FN256 - smaller pflash with FTFA */
1646 num_blocks = 1;
1647 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_INVALIDATE_CACHE;
1648 break;
1649 }
1650 /* K24FN1M without errata 7534 */
1651 num_blocks = 2;
1652 kinfo->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1653 kinfo->max_flash_prog_size = 1<<10;
1654 break;
1655
1656 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX3:
1657 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX1: /* errata 7534 - should be K63 */
1658 /* K63FN1M0 */
1659 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX4:
1660 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX2: /* errata 7534 - should be K64 */
1661 /* K64FN1M0, K64FX512 */
1662 pflash_sector_size_bytes = 4<<10;
1663 nvm_sector_size_bytes = 4<<10;
1664 kinfo->max_flash_prog_size = 1<<10;
1665 num_blocks = 2;
1666 kinfo->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1667 break;
1668
1669 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX6:
1670 /* K26FN2M0 */
1671 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX6:
1672 /* K66FN2M0, K66FX1M0 */
1673 pflash_sector_size_bytes = 4<<10;
1674 nvm_sector_size_bytes = 4<<10;
1675 kinfo->max_flash_prog_size = 1<<10;
1676 num_blocks = 4;
1677 kinfo->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1678 break;
1679 default:
1680 LOG_ERROR("Unsupported Kinetis FAMILYID SUBFAMID");
1681 }
1682 break;
1683
1684 case KINETIS_SDID_SERIESID_KL:
1685 /* KL-series */
1686 pflash_sector_size_bytes = 1<<10;
1687 nvm_sector_size_bytes = 1<<10;
1688 /* autodetect 1 or 2 blocks */
1689 kinfo->flash_support = FS_PROGRAM_LONGWORD;
1690 break;
1691
1692 case KINETIS_SDID_SERIESID_KV:
1693 /* KV-series */
1694 switch (kinfo->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
1695 case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX0:
1696 /* KV10: FTFA, 1kB sectors */
1697 pflash_sector_size_bytes = 1<<10;
1698 num_blocks = 1;
1699 kinfo->flash_support = FS_PROGRAM_LONGWORD;
1700 break;
1701
1702 case KINETIS_SDID_FAMILYID_K1X | KINETIS_SDID_SUBFAMID_KX1:
1703 /* KV11: FTFA, 2kB sectors */
1704 pflash_sector_size_bytes = 2<<10;
1705 num_blocks = 1;
1706 kinfo->flash_support = FS_PROGRAM_LONGWORD;
1707 break;
1708
1709 case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX0:
1710 /* KV30: FTFA, 2kB sectors, 1 block */
1711 case KINETIS_SDID_FAMILYID_K3X | KINETIS_SDID_SUBFAMID_KX1:
1712 /* KV31: FTFA, 2kB sectors, 2 blocks */
1713 pflash_sector_size_bytes = 2<<10;
1714 /* autodetect 1 or 2 blocks */
1715 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_INVALIDATE_CACHE;
1716 break;
1717
1718 case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX2:
1719 case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX4:
1720 case KINETIS_SDID_FAMILYID_K4X | KINETIS_SDID_SUBFAMID_KX6:
1721 /* KV4x: FTFA, 4kB sectors */
1722 pflash_sector_size_bytes = 4<<10;
1723 num_blocks = 1;
1724 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_INVALIDATE_CACHE;
1725 break;
1726
1727 default:
1728 LOG_ERROR("Unsupported KV FAMILYID SUBFAMID");
1729 }
1730 break;
1731
1732 default:
1733 LOG_ERROR("Unsupported K-series");
1734 }
1735 }
1736
1737 if (pflash_sector_size_bytes == 0) {
1738 LOG_ERROR("MCU is unsupported, SDID 0x%08" PRIx32, kinfo->sim_sdid);
1739 return ERROR_FLASH_OPER_UNSUPPORTED;
1740 }
1741
1742 result = target_read_u32(target, SIM_FCFG1, &kinfo->sim_fcfg1);
1743 if (result != ERROR_OK)
1744 return result;
1745
1746 result = target_read_u32(target, SIM_FCFG2, &kinfo->sim_fcfg2);
1747 if (result != ERROR_OK)
1748 return result;
1749
1750 LOG_DEBUG("SDID: 0x%08" PRIX32 " FCFG1: 0x%08" PRIX32 " FCFG2: 0x%08" PRIX32, kinfo->sim_sdid,
1751 kinfo->sim_fcfg1, kinfo->sim_fcfg2);
1752
1753 fcfg1_nvmsize = (uint8_t)((kinfo->sim_fcfg1 >> 28) & 0x0f);
1754 fcfg1_pfsize = (uint8_t)((kinfo->sim_fcfg1 >> 24) & 0x0f);
1755 fcfg1_eesize = (uint8_t)((kinfo->sim_fcfg1 >> 16) & 0x0f);
1756 fcfg1_depart = (uint8_t)((kinfo->sim_fcfg1 >> 8) & 0x0f);
1757
1758 fcfg2_pflsh = (uint8_t)((kinfo->sim_fcfg2 >> 23) & 0x01);
1759 fcfg2_maxaddr0 = (uint8_t)((kinfo->sim_fcfg2 >> 24) & 0x7f);
1760 fcfg2_maxaddr1 = (uint8_t)((kinfo->sim_fcfg2 >> 16) & 0x7f);
1761
1762 if (num_blocks == 0)
1763 num_blocks = fcfg2_maxaddr1 ? 2 : 1;
1764 else if (fcfg2_maxaddr1 == 0 && num_blocks >= 2) {
1765 num_blocks = 1;
1766 LOG_WARNING("MAXADDR1 is zero, number of flash banks adjusted to 1");
1767 } else if (fcfg2_maxaddr1 != 0 && num_blocks == 1) {
1768 num_blocks = 2;
1769 LOG_WARNING("MAXADDR1 is non zero, number of flash banks adjusted to 2");
1770 }
1771
1772 /* when the PFLSH bit is set, there is no FlexNVM/FlexRAM */
1773 if (!fcfg2_pflsh) {
1774 switch (fcfg1_nvmsize) {
1775 case 0x03:
1776 case 0x05:
1777 case 0x07:
1778 case 0x09:
1779 case 0x0b:
1780 nvm_size = 1 << (14 + (fcfg1_nvmsize >> 1));
1781 break;
1782 case 0x0f:
1783 if (pflash_sector_size_bytes >= 4<<10)
1784 nvm_size = 512<<10;
1785 else
1786 /* K20_100 */
1787 nvm_size = 256<<10;
1788 break;
1789 default:
1790 nvm_size = 0;
1791 break;
1792 }
1793
1794 switch (fcfg1_eesize) {
1795 case 0x00:
1796 case 0x01:
1797 case 0x02:
1798 case 0x03:
1799 case 0x04:
1800 case 0x05:
1801 case 0x06:
1802 case 0x07:
1803 case 0x08:
1804 case 0x09:
1805 ee_size = (16 << (10 - fcfg1_eesize));
1806 break;
1807 default:
1808 ee_size = 0;
1809 break;
1810 }
1811
1812 switch (fcfg1_depart) {
1813 case 0x01:
1814 case 0x02:
1815 case 0x03:
1816 case 0x04:
1817 case 0x05:
1818 case 0x06:
1819 df_size = nvm_size - (4096 << fcfg1_depart);
1820 break;
1821 case 0x08:
1822 df_size = 0;
1823 break;
1824 case 0x09:
1825 case 0x0a:
1826 case 0x0b:
1827 case 0x0c:
1828 case 0x0d:
1829 df_size = 4096 << (fcfg1_depart & 0x7);
1830 break;
1831 default:
1832 df_size = nvm_size;
1833 break;
1834 }
1835 }
1836
1837 switch (fcfg1_pfsize) {
1838 case 0x03:
1839 case 0x05:
1840 case 0x07:
1841 case 0x09:
1842 case 0x0b:
1843 case 0x0d:
1844 pf_size = 1 << (14 + (fcfg1_pfsize >> 1));
1845 break;
1846 case 0x0f:
1847 /* a peculiar case: Freescale states different sizes for 0xf
1848 * K02P64M100SFARM 128 KB ... duplicate of code 0x7
1849 * K22P121M120SF8RM 256 KB ... duplicate of code 0x9
1850 * K22P121M120SF7RM 512 KB ... duplicate of code 0xb
1851 * K22P100M120SF5RM 1024 KB ... duplicate of code 0xd
1852 * K26P169M180SF5RM 2048 KB ... the only unique value
1853 * fcfg2_maxaddr0 seems to be the only clue to pf_size
1854 * Checking fcfg2_maxaddr0 later in this routine is pointless then
1855 */
1856 if (fcfg2_pflsh)
1857 pf_size = ((uint32_t)fcfg2_maxaddr0 << 13) * num_blocks;
1858 else
1859 pf_size = ((uint32_t)fcfg2_maxaddr0 << 13) * num_blocks / 2;
1860 if (pf_size != 2048<<10)
1861 LOG_WARNING("SIM_FCFG1 PFSIZE = 0xf: please check if pflash is %u KB", pf_size>>10);
1862
1863 break;
1864 default:
1865 pf_size = 0;
1866 break;
1867 }
1868
1869 LOG_DEBUG("FlexNVM: %" PRIu32 " PFlash: %" PRIu32 " FlexRAM: %" PRIu32 " PFLSH: %d",
1870 nvm_size, pf_size, ee_size, fcfg2_pflsh);
1871
1872 num_pflash_blocks = num_blocks / (2 - fcfg2_pflsh);
1873 first_nvm_bank = num_pflash_blocks;
1874 num_nvm_blocks = num_blocks - num_pflash_blocks;
1875
1876 LOG_DEBUG("%d blocks total: %d PFlash, %d FlexNVM",
1877 num_blocks, num_pflash_blocks, num_nvm_blocks);
1878
1879 LOG_INFO("Probing flash info for bank %d", bank->bank_number);
1880
1881 if ((unsigned)bank->bank_number < num_pflash_blocks) {
1882 /* pflash, banks start at address zero */
1883 kinfo->flash_class = FC_PFLASH;
1884 bank->size = (pf_size / num_pflash_blocks);
1885 bank->base = 0x00000000 + bank->size * bank->bank_number;
1886 kinfo->prog_base = bank->base;
1887 kinfo->sector_size = pflash_sector_size_bytes;
1888 /* pflash is divided into 32 protection areas for
1889 * parts with more than 32K of PFlash. For parts with
1890 * less the protection unit is set to 1024 bytes */
1891 kinfo->protection_size = MAX(pf_size / 32, 1024);
1892 bank->num_prot_blocks = 32 / num_pflash_blocks;
1893 kinfo->protection_block = bank->num_prot_blocks * bank->bank_number;
1894
1895 } else if ((unsigned)bank->bank_number < num_blocks) {
1896 /* nvm, banks start at address 0x10000000 */
1897 unsigned nvm_ord = bank->bank_number - first_nvm_bank;
1898 uint32_t limit;
1899
1900 kinfo->flash_class = FC_FLEX_NVM;
1901 bank->size = (nvm_size / num_nvm_blocks);
1902 bank->base = 0x10000000 + bank->size * nvm_ord;
1903 kinfo->prog_base = 0x00800000 + bank->size * nvm_ord;
1904 kinfo->sector_size = nvm_sector_size_bytes;
1905 if (df_size == 0) {
1906 kinfo->protection_size = 0;
1907 } else {
1908 for (i = df_size; ~i & 1; i >>= 1)
1909 ;
1910 if (i == 1)
1911 kinfo->protection_size = df_size / 8; /* data flash size = 2^^n */
1912 else
1913 kinfo->protection_size = nvm_size / 8; /* TODO: verify on SF1, not documented in RM */
1914 }
1915 bank->num_prot_blocks = 8 / num_nvm_blocks;
1916 kinfo->protection_block = bank->num_prot_blocks * nvm_ord;
1917
1918 /* EEPROM backup part of FlexNVM is not accessible, use df_size as a limit */
1919 if (df_size > bank->size * nvm_ord)
1920 limit = df_size - bank->size * nvm_ord;
1921 else
1922 limit = 0;
1923
1924 if (bank->size > limit) {
1925 bank->size = limit;
1926 LOG_DEBUG("FlexNVM bank %d limited to 0x%08" PRIx32 " due to active EEPROM backup",
1927 bank->bank_number, limit);
1928 }
1929
1930 } else if ((unsigned)bank->bank_number == num_blocks) {
1931 LOG_ERROR("FlexRAM support not yet implemented");
1932 return ERROR_FLASH_OPER_UNSUPPORTED;
1933 } else {
1934 LOG_ERROR("Cannot determine parameters for bank %d, only %d banks on device",
1935 bank->bank_number, num_blocks);
1936 return ERROR_FLASH_BANK_INVALID;
1937 }
1938
1939 if (bank->bank_number == 0 && ((uint32_t)fcfg2_maxaddr0 << 13) != bank->size)
1940 LOG_WARNING("MAXADDR0 0x%02" PRIx8 " check failed,"
1941 " please report to OpenOCD mailing list", fcfg2_maxaddr0);
1942 if (fcfg2_pflsh) {
1943 if (bank->bank_number == 1 && ((uint32_t)fcfg2_maxaddr1 << 13) != bank->size)
1944 LOG_WARNING("MAXADDR1 0x%02" PRIx8 " check failed,"
1945 " please report to OpenOCD mailing list", fcfg2_maxaddr1);
1946 } else {
1947 if ((unsigned)bank->bank_number == first_nvm_bank
1948 && ((uint32_t)fcfg2_maxaddr1 << 13) != df_size)
1949 LOG_WARNING("FlexNVM MAXADDR1 0x%02" PRIx8 " check failed,"
1950 " please report to OpenOCD mailing list", fcfg2_maxaddr1);
1951 }
1952
1953 if (bank->sectors) {
1954 free(bank->sectors);
1955 bank->sectors = NULL;
1956 }
1957 if (bank->prot_blocks) {
1958 free(bank->prot_blocks);
1959 bank->prot_blocks = NULL;
1960 }
1961
1962 if (kinfo->sector_size == 0) {
1963 LOG_ERROR("Unknown sector size for bank %d", bank->bank_number);
1964 return ERROR_FLASH_BANK_INVALID;
1965 }
1966
1967 if (kinfo->flash_support & FS_PROGRAM_SECTOR
1968 && kinfo->max_flash_prog_size == 0) {
1969 kinfo->max_flash_prog_size = kinfo->sector_size;
1970 /* Program section size is equal to sector size by default */
1971 }
1972
1973 bank->num_sectors = bank->size / kinfo->sector_size;
1974
1975 if (bank->num_sectors > 0) {
1976 /* FlexNVM bank can be used for EEPROM backup therefore zero sized */
1977 bank->sectors = alloc_block_array(0, kinfo->sector_size, bank->num_sectors);
1978 if (!bank->sectors)
1979 return ERROR_FAIL;
1980
1981 bank->prot_blocks = alloc_block_array(0, kinfo->protection_size, bank->num_prot_blocks);
1982 if (!bank->prot_blocks)
1983 return ERROR_FAIL;
1984
1985 } else {
1986 bank->num_prot_blocks = 0;
1987 }
1988
1989 kinfo->probed = true;
1990
1991 return ERROR_OK;
1992 }
1993
1994 static int kinetis_auto_probe(struct flash_bank *bank)
1995 {
1996 struct kinetis_flash_bank *kinfo = bank->driver_priv;
1997
1998 if (kinfo && kinfo->probed)
1999 return ERROR_OK;
2000
2001 return kinetis_probe(bank);
2002 }
2003
2004 static int kinetis_info(struct flash_bank *bank, char *buf, int buf_size)
2005 {
2006 const char *bank_class_names[] = {
2007 "(ANY)", "PFlash", "FlexNVM", "FlexRAM"
2008 };
2009
2010 struct kinetis_flash_bank *kinfo = bank->driver_priv;
2011
2012 (void) snprintf(buf, buf_size,
2013 "%s driver for %s flash bank %s at 0x%8.8" PRIx32 "",
2014 bank->driver->name, bank_class_names[kinfo->flash_class],
2015 bank->name, bank->base);
2016
2017 return ERROR_OK;
2018 }
2019
2020 static int kinetis_blank_check(struct flash_bank *bank)
2021 {
2022 struct kinetis_flash_bank *kinfo = bank->driver_priv;
2023 int result;
2024
2025 /* suprisingly blank check does not work in VLPR and HSRUN modes */
2026 result = kinetis_check_run_mode(bank->target);
2027 if (result != ERROR_OK)
2028 return result;
2029
2030 /* reset error flags */
2031 result = kinetis_ftfx_prepare(bank->target);
2032 if (result != ERROR_OK)
2033 return result;
2034
2035 if (kinfo->flash_class == FC_PFLASH || kinfo->flash_class == FC_FLEX_NVM) {
2036 bool block_dirty = false;
2037 uint8_t ftfx_fstat;
2038
2039 if (kinfo->flash_class == FC_FLEX_NVM) {
2040 uint8_t fcfg1_depart = (uint8_t)((kinfo->sim_fcfg1 >> 8) & 0x0f);
2041 /* block operation cannot be used on FlexNVM when EEPROM backup partition is set */
2042 if (fcfg1_depart != 0xf && fcfg1_depart != 0)
2043 block_dirty = true;
2044 }
2045
2046 if (!block_dirty) {
2047 /* check if whole bank is blank */
2048 result = kinetis_ftfx_command(bank->target, FTFx_CMD_BLOCKSTAT, kinfo->prog_base,
2049 0, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
2050
2051 if (result != ERROR_OK || (ftfx_fstat & 0x01))
2052 block_dirty = true;
2053 }
2054
2055 if (block_dirty) {
2056 /* the whole bank is not erased, check sector-by-sector */
2057 int i;
2058 for (i = 0; i < bank->num_sectors; i++) {
2059 /* normal margin */
2060 result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTSTAT,
2061 kinfo->prog_base + bank->sectors[i].offset,
2062 1, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
2063
2064 if (result == ERROR_OK) {
2065 bank->sectors[i].is_erased = !(ftfx_fstat & 0x01);
2066 } else {
2067 LOG_DEBUG("Ignoring errored PFlash sector blank-check");
2068 bank->sectors[i].is_erased = -1;
2069 }
2070 }
2071 } else {
2072 /* the whole bank is erased, update all sectors */
2073 int i;
2074 for (i = 0; i < bank->num_sectors; i++)
2075 bank->sectors[i].is_erased = 1;
2076 }
2077 } else {
2078 LOG_WARNING("kinetis_blank_check not supported yet for FlexRAM");
2079 return ERROR_FLASH_OPERATION_FAILED;
2080 }
2081
2082 return ERROR_OK;
2083 }
2084
2085
2086 COMMAND_HANDLER(kinetis_nvm_partition)
2087 {
2088 int result, i;
2089 unsigned long par, log2 = 0, ee1 = 0, ee2 = 0;
2090 enum { SHOW_INFO, DF_SIZE, EEBKP_SIZE } sz_type = SHOW_INFO;
2091 bool enable;
2092 uint8_t load_flex_ram = 1;
2093 uint8_t ee_size_code = 0x3f;
2094 uint8_t flex_nvm_partition_code = 0;
2095 uint8_t ee_split = 3;
2096 struct target *target = get_current_target(CMD_CTX);
2097 struct flash_bank *bank;
2098 struct kinetis_flash_bank *kinfo;
2099 uint32_t sim_fcfg1;
2100
2101 if (CMD_ARGC >= 2) {
2102 if (strcmp(CMD_ARGV[0], "dataflash") == 0)
2103 sz_type = DF_SIZE;
2104 else if (strcmp(CMD_ARGV[0], "eebkp") == 0)
2105 sz_type = EEBKP_SIZE;
2106
2107 par = strtoul(CMD_ARGV[1], NULL, 10);
2108 while (par >> (log2 + 3))
2109 log2++;
2110 }
2111 switch (sz_type) {
2112 case SHOW_INFO:
2113 result = target_read_u32(target, SIM_FCFG1, &sim_fcfg1);
2114 if (result != ERROR_OK)
2115 return result;
2116
2117 flex_nvm_partition_code = (uint8_t)((sim_fcfg1 >> 8) & 0x0f);
2118 switch (flex_nvm_partition_code) {
2119 case 0:
2120 command_print(CMD_CTX, "No EEPROM backup, data flash only");
2121 break;
2122 case 1:
2123 case 2:
2124 case 3:
2125 case 4:
2126 case 5:
2127 case 6:
2128 command_print(CMD_CTX, "EEPROM backup %d KB", 4 << flex_nvm_partition_code);
2129 break;
2130 case 8:
2131 command_print(CMD_CTX, "No data flash, EEPROM backup only");
2132 break;
2133 case 0x9:
2134 case 0xA:
2135 case 0xB:
2136 case 0xC:
2137 case 0xD:
2138 case 0xE:
2139 command_print(CMD_CTX, "data flash %d KB", 4 << (flex_nvm_partition_code & 7));
2140 break;
2141 case 0xf:
2142 command_print(CMD_CTX, "No EEPROM backup, data flash only (DEPART not set)");
2143 break;
2144 default:
2145 command_print(CMD_CTX, "Unsupported EEPROM backup size code 0x%02" PRIx8, flex_nvm_partition_code);
2146 }
2147 return ERROR_OK;
2148
2149 case DF_SIZE:
2150 flex_nvm_partition_code = 0x8 | log2;
2151 break;
2152
2153 case EEBKP_SIZE:
2154 flex_nvm_partition_code = log2;
2155 break;
2156 }
2157
2158 if (CMD_ARGC == 3)
2159 ee1 = ee2 = strtoul(CMD_ARGV[2], NULL, 10) / 2;
2160 else if (CMD_ARGC >= 4) {
2161 ee1 = strtoul(CMD_ARGV[2], NULL, 10);
2162 ee2 = strtoul(CMD_ARGV[3], NULL, 10);
2163 }
2164
2165 enable = ee1 + ee2 > 0;
2166 if (enable) {
2167 for (log2 = 2; ; log2++) {
2168 if (ee1 + ee2 == (16u << 10) >> log2)
2169 break;
2170 if (ee1 + ee2 > (16u << 10) >> log2 || log2 >= 9) {
2171 LOG_ERROR("Unsupported EEPROM size");
2172 return ERROR_FLASH_OPERATION_FAILED;
2173 }
2174 }
2175
2176 if (ee1 * 3 == ee2)
2177 ee_split = 1;
2178 else if (ee1 * 7 == ee2)
2179 ee_split = 0;
2180 else if (ee1 != ee2) {
2181 LOG_ERROR("Unsupported EEPROM sizes ratio");
2182 return ERROR_FLASH_OPERATION_FAILED;
2183 }
2184
2185 ee_size_code = log2 | ee_split << 4;
2186 }
2187
2188 if (CMD_ARGC >= 5)
2189 COMMAND_PARSE_ON_OFF(CMD_ARGV[4], enable);
2190 if (enable)
2191 load_flex_ram = 0;
2192
2193 LOG_INFO("DEPART 0x%" PRIx8 ", EEPROM size code 0x%" PRIx8,
2194 flex_nvm_partition_code, ee_size_code);
2195
2196 result = kinetis_check_run_mode(target);
2197 if (result != ERROR_OK)
2198 return result;
2199
2200 /* reset error flags */
2201 result = kinetis_ftfx_prepare(target);
2202 if (result != ERROR_OK)
2203 return result;
2204
2205 result = kinetis_ftfx_command(target, FTFx_CMD_PGMPART, load_flex_ram,
2206 ee_size_code, flex_nvm_partition_code, 0, 0,
2207 0, 0, 0, 0, NULL);
2208 if (result != ERROR_OK)
2209 return result;
2210
2211 command_print(CMD_CTX, "FlexNVM partition set. Please reset MCU.");
2212
2213 for (i = 1; i < 4; i++) {
2214 bank = get_flash_bank_by_num_noprobe(i);
2215 if (bank == NULL)
2216 break;
2217
2218 kinfo = bank->driver_priv;
2219 if (kinfo && kinfo->flash_class == FC_FLEX_NVM)
2220 kinfo->probed = false; /* re-probe before next use */
2221 }
2222
2223 command_print(CMD_CTX, "FlexNVM banks will be re-probed to set new data flash size.");
2224 return ERROR_OK;
2225 }
2226
2227 COMMAND_HANDLER(kinetis_fcf_source_handler)
2228 {
2229 if (CMD_ARGC > 1)
2230 return ERROR_COMMAND_SYNTAX_ERROR;
2231
2232 if (CMD_ARGC == 1) {
2233 if (strcmp(CMD_ARGV[0], "write") == 0)
2234 allow_fcf_writes = true;
2235 else if (strcmp(CMD_ARGV[0], "protection") == 0)
2236 allow_fcf_writes = false;
2237 else
2238 return ERROR_COMMAND_SYNTAX_ERROR;
2239 }
2240
2241 if (allow_fcf_writes) {
2242 command_print(CMD_CTX, "Arbitrary Flash Configuration Field writes enabled.");
2243 command_print(CMD_CTX, "Protection info writes to FCF disabled.");
2244 LOG_WARNING("BEWARE: incorrect flash configuration may permanently lock the device.");
2245 } else {
2246 command_print(CMD_CTX, "Protection info writes to Flash Configuration Field enabled.");
2247 command_print(CMD_CTX, "Arbitrary FCF writes disabled. Mode safe from unwanted locking of the device.");
2248 }
2249
2250 return ERROR_OK;
2251 }
2252
2253 COMMAND_HANDLER(kinetis_fopt_handler)
2254 {
2255 if (CMD_ARGC > 1)
2256 return ERROR_COMMAND_SYNTAX_ERROR;
2257
2258 if (CMD_ARGC == 1)
2259 fcf_fopt = (uint8_t)strtoul(CMD_ARGV[0], NULL, 0);
2260 else
2261 command_print(CMD_CTX, "FCF_FOPT 0x%02" PRIx8, fcf_fopt);
2262
2263 return ERROR_OK;
2264 }
2265
2266
2267 static const struct command_registration kinetis_security_command_handlers[] = {
2268 {
2269 .name = "check_security",
2270 .mode = COMMAND_EXEC,
2271 .help = "Check status of device security lock",
2272 .usage = "",
2273 .handler = kinetis_check_flash_security_status,
2274 },
2275 {
2276 .name = "halt",
2277 .mode = COMMAND_EXEC,
2278 .help = "Issue a halt via the MDM-AP",
2279 .usage = "",
2280 .handler = kinetis_mdm_halt,
2281 },
2282 {
2283 .name = "mass_erase",
2284 .mode = COMMAND_EXEC,
2285 .help = "Issue a complete flash erase via the MDM-AP",
2286 .usage = "",
2287 .handler = kinetis_mdm_mass_erase,
2288 },
2289 { .name = "reset",
2290 .mode = COMMAND_EXEC,
2291 .help = "Issue a reset via the MDM-AP",
2292 .usage = "",
2293 .handler = kinetis_mdm_reset,
2294 },
2295 COMMAND_REGISTRATION_DONE
2296 };
2297
2298 static const struct command_registration kinetis_exec_command_handlers[] = {
2299 {
2300 .name = "mdm",
2301 .mode = COMMAND_ANY,
2302 .help = "MDM-AP command group",
2303 .usage = "",
2304 .chain = kinetis_security_command_handlers,
2305 },
2306 {
2307 .name = "disable_wdog",
2308 .mode = COMMAND_EXEC,
2309 .help = "Disable the watchdog timer",
2310 .usage = "",
2311 .handler = kinetis_disable_wdog_handler,
2312 },
2313 {
2314 .name = "nvm_partition",
2315 .mode = COMMAND_EXEC,
2316 .help = "Show/set data flash or EEPROM backup size in kilobytes,"
2317 " set two EEPROM sizes in bytes and FlexRAM loading during reset",
2318 .usage = "('info'|'dataflash' size|'eebkp' size) [eesize1 eesize2] ['on'|'off']",
2319 .handler = kinetis_nvm_partition,
2320 },
2321 {
2322 .name = "fcf_source",
2323 .mode = COMMAND_EXEC,
2324 .help = "Use protection as a source for Flash Configuration Field or allow writing arbitrary values to the FCF"
2325 " Mode 'protection' is safe from unwanted locking of the device.",
2326 .usage = "['protection'|'write']",
2327 .handler = kinetis_fcf_source_handler,
2328 },
2329 {
2330 .name = "fopt",
2331 .mode = COMMAND_EXEC,
2332 .help = "FCF_FOPT value source in 'kinetis fcf_source protection' mode",
2333 .usage = "[num]",
2334 .handler = kinetis_fopt_handler,
2335 },
2336 COMMAND_REGISTRATION_DONE
2337 };
2338
2339 static const struct command_registration kinetis_command_handler[] = {
2340 {
2341 .name = "kinetis",
2342 .mode = COMMAND_ANY,
2343 .help = "Kinetis flash controller commands",
2344 .usage = "",
2345 .chain = kinetis_exec_command_handlers,
2346 },
2347 COMMAND_REGISTRATION_DONE
2348 };
2349
2350
2351
2352 struct flash_driver kinetis_flash = {
2353 .name = "kinetis",
2354 .commands = kinetis_command_handler,
2355 .flash_bank_command = kinetis_flash_bank_command,
2356 .erase = kinetis_erase,
2357 .protect = kinetis_protect,
2358 .write = kinetis_write,
2359 .read = default_flash_read,
2360 .probe = kinetis_probe,
2361 .auto_probe = kinetis_auto_probe,
2362 .erase_check = kinetis_blank_check,
2363 .protect_check = kinetis_protect_check,
2364 .info = kinetis_info,
2365 };
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