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Kinetis: invalidate flash cache after erase/write
[openocd.git] / src / flash / nor / kinetis.c
1 /***************************************************************************
2 * Copyright (C) 2011 by Mathias Kuester *
3 * kesmtp@freenet.de *
4 * *
5 * Copyright (C) 2011 sleep(5) ltd *
6 * tomas@sleepfive.com *
7 * *
8 * Copyright (C) 2012 by Christopher D. Kilgour *
9 * techie at whiterocker.com *
10 * *
11 * Copyright (C) 2013 Nemui Trinomius *
12 * nemuisan_kawausogasuki@live.jp *
13 * *
14 * Copyright (C) 2015 Tomas Vanek *
15 * vanekt@fbl.cz *
16 * *
17 * This program is free software; you can redistribute it and/or modify *
18 * it under the terms of the GNU General Public License as published by *
19 * the Free Software Foundation; either version 2 of the License, or *
20 * (at your option) any later version. *
21 * *
22 * This program is distributed in the hope that it will be useful, *
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
25 * GNU General Public License for more details. *
26 * *
27 * You should have received a copy of the GNU General Public License *
28 * along with this program; if not, write to the *
29 * Free Software Foundation, Inc., *
30 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
31 ***************************************************************************/
32
33 #ifdef HAVE_CONFIG_H
34 #include "config.h"
35 #endif
36
37 #include "jtag/interface.h"
38 #include "imp.h"
39 #include <helper/binarybuffer.h>
40 #include <target/target_type.h>
41 #include <target/algorithm.h>
42 #include <target/armv7m.h>
43 #include <target/cortex_m.h>
44
45 /*
46 * Implementation Notes
47 *
48 * The persistent memories in the Kinetis chip families K10 through
49 * K70 are all manipulated with the Flash Memory Module. Some
50 * variants call this module the FTFE, others call it the FTFL. To
51 * indicate that both are considered here, we use FTFX.
52 *
53 * Within the module, according to the chip variant, the persistent
54 * memory is divided into what Freescale terms Program Flash, FlexNVM,
55 * and FlexRAM. All chip variants have Program Flash. Some chip
56 * variants also have FlexNVM and FlexRAM, which always appear
57 * together.
58 *
59 * A given Kinetis chip may have 1, 2 or 4 blocks of flash. Here we map
60 * each block to a separate bank. Each block size varies by chip and
61 * may be determined by the read-only SIM_FCFG1 register. The sector
62 * size within each bank/block varies by chip, and may be 1, 2 or 4k.
63 * The sector size may be different for flash and FlexNVM.
64 *
65 * The first half of the flash (1 or 2 blocks) is always Program Flash
66 * and always starts at address 0x00000000. The "PFLSH" flag, bit 23
67 * of the read-only SIM_FCFG2 register, determines whether the second
68 * half of the flash is also Program Flash or FlexNVM+FlexRAM. When
69 * PFLSH is set, the second from the first half. When PFLSH is clear,
70 * the second half of flash is FlexNVM and always starts at address
71 * 0x10000000. FlexRAM, which is also present when PFLSH is clear,
72 * always starts at address 0x14000000.
73 *
74 * The Flash Memory Module provides a register set where flash
75 * commands are loaded to perform flash operations like erase and
76 * program. Different commands are available depending on whether
77 * Program Flash or FlexNVM/FlexRAM is being manipulated. Although
78 * the commands used are quite consistent between flash blocks, the
79 * parameters they accept differ according to the flash sector size.
80 *
81 */
82
83 /* Addressess */
84 #define FLEXRAM 0x14000000
85
86 #define FMC_PFB01CR 0x4001f004
87 #define FTFx_FSTAT 0x40020000
88 #define FTFx_FCNFG 0x40020001
89 #define FTFx_FCCOB3 0x40020004
90 #define FTFx_FPROT3 0x40020010
91 #define FTFx_FDPROT 0x40020017
92 #define SIM_SDID 0x40048024
93 #define SIM_SOPT1 0x40047000
94 #define SIM_FCFG1 0x4004804c
95 #define SIM_FCFG2 0x40048050
96 #define WDOG_STCTRH 0x40052000
97
98 /* Commands */
99 #define FTFx_CMD_BLOCKSTAT 0x00
100 #define FTFx_CMD_SECTSTAT 0x01
101 #define FTFx_CMD_LWORDPROG 0x06
102 #define FTFx_CMD_SECTERASE 0x09
103 #define FTFx_CMD_SECTWRITE 0x0b
104 #define FTFx_CMD_MASSERASE 0x44
105 #define FTFx_CMD_PGMPART 0x80
106 #define FTFx_CMD_SETFLEXRAM 0x81
107
108 /* The older Kinetis K series uses the following SDID layout :
109 * Bit 31-16 : 0
110 * Bit 15-12 : REVID
111 * Bit 11-7 : DIEID
112 * Bit 6-4 : FAMID
113 * Bit 3-0 : PINID
114 *
115 * The newer Kinetis series uses the following SDID layout :
116 * Bit 31-28 : FAMID
117 * Bit 27-24 : SUBFAMID
118 * Bit 23-20 : SERIESID
119 * Bit 19-16 : SRAMSIZE
120 * Bit 15-12 : REVID
121 * Bit 6-4 : Reserved (0)
122 * Bit 3-0 : PINID
123 *
124 * We assume that if bits 31-16 are 0 then it's an older
125 * K-series MCU.
126 */
127
128 #define KINETIS_SOPT1_RAMSIZE_MASK 0x0000F000
129 #define KINETIS_SOPT1_RAMSIZE_K24FN1M 0x0000B000
130
131 #define KINETIS_SDID_K_SERIES_MASK 0x0000FFFF
132
133 #define KINETIS_SDID_DIEID_MASK 0x00000F80
134
135 #define KINETIS_SDID_DIEID_K22FN128 0x00000680 /* smaller pflash with FTFA */
136 #define KINETIS_SDID_DIEID_K22FN256 0x00000A80
137 #define KINETIS_SDID_DIEID_K22FN512 0x00000E80
138 #define KINETIS_SDID_DIEID_K24FN256 0x00000700
139
140 #define KINETIS_SDID_DIEID_K24FN1M 0x00000300 /* Detect Errata 7534 */
141
142 /* We can't rely solely on the FAMID field to determine the MCU
143 * type since some FAMID values identify multiple MCUs with
144 * different flash sector sizes (K20 and K22 for instance).
145 * Therefore we combine it with the DIEID bits which may possibly
146 * break if Freescale bumps the DIEID for a particular MCU. */
147 #define KINETIS_K_SDID_TYPE_MASK 0x00000FF0
148 #define KINETIS_K_SDID_K10_M50 0x00000000
149 #define KINETIS_K_SDID_K10_M72 0x00000080
150 #define KINETIS_K_SDID_K10_M100 0x00000100
151 #define KINETIS_K_SDID_K10_M120 0x00000180
152 #define KINETIS_K_SDID_K11 0x00000220
153 #define KINETIS_K_SDID_K12 0x00000200
154 #define KINETIS_K_SDID_K20_M50 0x00000010
155 #define KINETIS_K_SDID_K20_M72 0x00000090
156 #define KINETIS_K_SDID_K20_M100 0x00000110
157 #define KINETIS_K_SDID_K20_M120 0x00000190
158 #define KINETIS_K_SDID_K21_M50 0x00000230
159 #define KINETIS_K_SDID_K21_M120 0x00000330
160 #define KINETIS_K_SDID_K22_M50 0x00000210
161 #define KINETIS_K_SDID_K22_M120 0x00000310
162 #define KINETIS_K_SDID_K30_M72 0x000000A0
163 #define KINETIS_K_SDID_K30_M100 0x00000120
164 #define KINETIS_K_SDID_K40_M72 0x000000B0
165 #define KINETIS_K_SDID_K40_M100 0x00000130
166 #define KINETIS_K_SDID_K50_M72 0x000000E0
167 #define KINETIS_K_SDID_K51_M72 0x000000F0
168 #define KINETIS_K_SDID_K53 0x00000170
169 #define KINETIS_K_SDID_K60_M100 0x00000140
170 #define KINETIS_K_SDID_K60_M150 0x000001C0
171 #define KINETIS_K_SDID_K70_M150 0x000001D0
172
173 #define KINETIS_SDID_SERIESID_MASK 0x00F00000
174 #define KINETIS_SDID_SERIESID_K 0x00000000
175 #define KINETIS_SDID_SERIESID_KL 0x00100000
176 #define KINETIS_SDID_SERIESID_KW 0x00500000
177 #define KINETIS_SDID_SERIESID_KV 0x00600000
178
179 #define KINETIS_SDID_SUBFAMID_MASK 0x0F000000
180 #define KINETIS_SDID_SUBFAMID_KX0 0x00000000
181 #define KINETIS_SDID_SUBFAMID_KX1 0x01000000
182 #define KINETIS_SDID_SUBFAMID_KX2 0x02000000
183 #define KINETIS_SDID_SUBFAMID_KX3 0x03000000
184 #define KINETIS_SDID_SUBFAMID_KX4 0x04000000
185 #define KINETIS_SDID_SUBFAMID_KX5 0x05000000
186 #define KINETIS_SDID_SUBFAMID_KX6 0x06000000
187
188 #define KINETIS_SDID_FAMILYID_MASK 0xF0000000
189 #define KINETIS_SDID_FAMILYID_K0X 0x00000000
190 #define KINETIS_SDID_FAMILYID_K1X 0x10000000
191 #define KINETIS_SDID_FAMILYID_K2X 0x20000000
192 #define KINETIS_SDID_FAMILYID_K3X 0x30000000
193 #define KINETIS_SDID_FAMILYID_K4X 0x40000000
194 #define KINETIS_SDID_FAMILYID_K6X 0x60000000
195 #define KINETIS_SDID_FAMILYID_K7X 0x70000000
196
197 struct kinetis_flash_bank {
198 bool probed;
199 uint32_t sector_size;
200 uint32_t max_flash_prog_size;
201 uint32_t protection_size;
202 uint32_t prog_base; /* base address for FTFx operations */
203 /* same as bank->base for pflash, differs for FlexNVM */
204 uint32_t protection_block; /* number of first protection block in this bank */
205
206 uint32_t sim_sdid;
207 uint32_t sim_fcfg1;
208 uint32_t sim_fcfg2;
209
210 enum {
211 FC_AUTO = 0,
212 FC_PFLASH,
213 FC_FLEX_NVM,
214 FC_FLEX_RAM,
215 } flash_class;
216
217 enum {
218 FS_PROGRAM_SECTOR = 1,
219 FS_PROGRAM_LONGWORD = 2,
220 FS_PROGRAM_PHRASE = 4, /* Unsupported */
221 FS_INVALIDATE_CACHE = 8,
222 } flash_support;
223 };
224
225 #define MDM_REG_STAT 0x00
226 #define MDM_REG_CTRL 0x04
227 #define MDM_REG_ID 0xfc
228
229 #define MDM_STAT_FMEACK (1<<0)
230 #define MDM_STAT_FREADY (1<<1)
231 #define MDM_STAT_SYSSEC (1<<2)
232 #define MDM_STAT_SYSRES (1<<3)
233 #define MDM_STAT_FMEEN (1<<5)
234 #define MDM_STAT_BACKDOOREN (1<<6)
235 #define MDM_STAT_LPEN (1<<7)
236 #define MDM_STAT_VLPEN (1<<8)
237 #define MDM_STAT_LLSMODEXIT (1<<9)
238 #define MDM_STAT_VLLSXMODEXIT (1<<10)
239 #define MDM_STAT_CORE_HALTED (1<<16)
240 #define MDM_STAT_CORE_SLEEPDEEP (1<<17)
241 #define MDM_STAT_CORESLEEPING (1<<18)
242
243 #define MEM_CTRL_FMEIP (1<<0)
244 #define MEM_CTRL_DBG_DIS (1<<1)
245 #define MEM_CTRL_DBG_REQ (1<<2)
246 #define MEM_CTRL_SYS_RES_REQ (1<<3)
247 #define MEM_CTRL_CORE_HOLD_RES (1<<4)
248 #define MEM_CTRL_VLLSX_DBG_REQ (1<<5)
249 #define MEM_CTRL_VLLSX_DBG_ACK (1<<6)
250 #define MEM_CTRL_VLLSX_STAT_ACK (1<<7)
251
252 #define MDM_ACCESS_TIMEOUT 3000 /* iterations */
253
254 static int kinetis_mdm_write_register(struct adiv5_dap *dap, unsigned reg, uint32_t value)
255 {
256 int retval;
257 LOG_DEBUG("MDM_REG[0x%02x] <- %08" PRIX32, reg, value);
258
259 retval = dap_queue_ap_write(dap_ap(dap, 1), reg, value);
260 if (retval != ERROR_OK) {
261 LOG_DEBUG("MDM: failed to queue a write request");
262 return retval;
263 }
264
265 retval = dap_run(dap);
266 if (retval != ERROR_OK) {
267 LOG_DEBUG("MDM: dap_run failed");
268 return retval;
269 }
270
271
272 return ERROR_OK;
273 }
274
275 static int kinetis_mdm_read_register(struct adiv5_dap *dap, unsigned reg, uint32_t *result)
276 {
277 int retval;
278
279 retval = dap_queue_ap_read(dap_ap(dap, 1), reg, result);
280 if (retval != ERROR_OK) {
281 LOG_DEBUG("MDM: failed to queue a read request");
282 return retval;
283 }
284
285 retval = dap_run(dap);
286 if (retval != ERROR_OK) {
287 LOG_DEBUG("MDM: dap_run failed");
288 return retval;
289 }
290
291 LOG_DEBUG("MDM_REG[0x%02x]: %08" PRIX32, reg, *result);
292 return ERROR_OK;
293 }
294
295 static int kinetis_mdm_poll_register(struct adiv5_dap *dap, unsigned reg, uint32_t mask, uint32_t value)
296 {
297 uint32_t val;
298 int retval;
299 int timeout = MDM_ACCESS_TIMEOUT;
300
301 do {
302 retval = kinetis_mdm_read_register(dap, reg, &val);
303 if (retval != ERROR_OK || (val & mask) == value)
304 return retval;
305
306 alive_sleep(1);
307 } while (timeout--);
308
309 LOG_DEBUG("MDM: polling timed out");
310 return ERROR_FAIL;
311 }
312
313 /*
314 * This function implements the procedure to mass erase the flash via
315 * SWD/JTAG on Kinetis K and L series of devices as it is described in
316 * AN4835 "Production Flash Programming Best Practices for Kinetis K-
317 * and L-series MCUs" Section 4.2.1
318 */
319 COMMAND_HANDLER(kinetis_mdm_mass_erase)
320 {
321 struct target *target = get_current_target(CMD_CTX);
322 struct cortex_m_common *cortex_m = target_to_cm(target);
323 struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
324
325 if (!dap) {
326 LOG_ERROR("Cannot perform mass erase with a high-level adapter");
327 return ERROR_FAIL;
328 }
329
330 int retval;
331
332 /*
333 * ... Power on the processor, or if power has already been
334 * applied, assert the RESET pin to reset the processor. For
335 * devices that do not have a RESET pin, write the System
336 * Reset Request bit in the MDM-AP control register after
337 * establishing communication...
338 */
339
340 /* assert SRST */
341 if (jtag_get_reset_config() & RESET_HAS_SRST)
342 adapter_assert_reset();
343 else
344 LOG_WARNING("Attempting mass erase without hardware reset. This is not reliable; "
345 "it's recommended you connect SRST and use ``reset_config srst_only''.");
346
347 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, MEM_CTRL_SYS_RES_REQ);
348 if (retval != ERROR_OK)
349 return retval;
350
351 /*
352 * ... Read the MDM-AP status register until the Flash Ready bit sets...
353 */
354 retval = kinetis_mdm_poll_register(dap, MDM_REG_STAT,
355 MDM_STAT_FREADY | MDM_STAT_SYSRES,
356 MDM_STAT_FREADY);
357 if (retval != ERROR_OK) {
358 LOG_ERROR("MDM : flash ready timeout");
359 return retval;
360 }
361
362 /*
363 * ... Write the MDM-AP control register to set the Flash Mass
364 * Erase in Progress bit. This will start the mass erase
365 * process...
366 */
367 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL,
368 MEM_CTRL_SYS_RES_REQ | MEM_CTRL_FMEIP);
369 if (retval != ERROR_OK)
370 return retval;
371
372 /* As a sanity check make sure that device started mass erase procedure */
373 retval = kinetis_mdm_poll_register(dap, MDM_REG_STAT,
374 MDM_STAT_FMEACK, MDM_STAT_FMEACK);
375 if (retval != ERROR_OK)
376 return retval;
377
378 /*
379 * ... Read the MDM-AP control register until the Flash Mass
380 * Erase in Progress bit clears...
381 */
382 retval = kinetis_mdm_poll_register(dap, MDM_REG_CTRL,
383 MEM_CTRL_FMEIP,
384 0);
385 if (retval != ERROR_OK)
386 return retval;
387
388 /*
389 * ... Negate the RESET signal or clear the System Reset Request
390 * bit in the MDM-AP control register...
391 */
392 retval = kinetis_mdm_write_register(dap, MDM_REG_CTRL, 0);
393 if (retval != ERROR_OK)
394 return retval;
395
396 if (jtag_get_reset_config() & RESET_HAS_SRST) {
397 /* halt MCU otherwise it loops in hard fault - WDOG reset cycle */
398 target->reset_halt = true;
399 target->type->assert_reset(target);
400 target->type->deassert_reset(target);
401 }
402
403 return ERROR_OK;
404 }
405
406 static const uint32_t kinetis_known_mdm_ids[] = {
407 0x001C0000, /* Kinetis-K Series */
408 0x001C0020, /* Kinetis-L/M/V/E Series */
409 };
410
411 /*
412 * This function implements the procedure to connect to
413 * SWD/JTAG on Kinetis K and L series of devices as it is described in
414 * AN4835 "Production Flash Programming Best Practices for Kinetis K-
415 * and L-series MCUs" Section 4.1.1
416 */
417 COMMAND_HANDLER(kinetis_check_flash_security_status)
418 {
419 struct target *target = get_current_target(CMD_CTX);
420 struct cortex_m_common *cortex_m = target_to_cm(target);
421 struct adiv5_dap *dap = cortex_m->armv7m.arm.dap;
422
423 if (!dap) {
424 LOG_WARNING("Cannot check flash security status with a high-level adapter");
425 return ERROR_OK;
426 }
427
428 uint32_t val;
429 int retval;
430
431 /*
432 * ... The MDM-AP ID register can be read to verify that the
433 * connection is working correctly...
434 */
435 retval = kinetis_mdm_read_register(dap, MDM_REG_ID, &val);
436 if (retval != ERROR_OK) {
437 LOG_ERROR("MDM: failed to read ID register");
438 goto fail;
439 }
440
441 bool found = false;
442 for (size_t i = 0; i < ARRAY_SIZE(kinetis_known_mdm_ids); i++) {
443 if (val == kinetis_known_mdm_ids[i]) {
444 found = true;
445 break;
446 }
447 }
448
449 if (!found)
450 LOG_WARNING("MDM: unknown ID %08" PRIX32, val);
451
452 /*
453 * ... Read the MDM-AP status register until the Flash Ready bit sets...
454 */
455 retval = kinetis_mdm_poll_register(dap, MDM_REG_STAT,
456 MDM_STAT_FREADY,
457 MDM_STAT_FREADY);
458 if (retval != ERROR_OK) {
459 LOG_ERROR("MDM: flash ready timeout");
460 goto fail;
461 }
462
463 /*
464 * ... Read the System Security bit to determine if security is enabled.
465 * If System Security = 0, then proceed. If System Security = 1, then
466 * communication with the internals of the processor, including the
467 * flash, will not be possible without issuing a mass erase command or
468 * unsecuring the part through other means (backdoor key unlock)...
469 */
470 retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &val);
471 if (retval != ERROR_OK) {
472 LOG_ERROR("MDM: failed to read MDM_REG_STAT");
473 goto fail;
474 }
475
476 if ((val & (MDM_STAT_SYSSEC | MDM_STAT_CORE_HALTED)) == MDM_STAT_SYSSEC) {
477 LOG_WARNING("MDM: Secured MCU state detected however it may be a false alarm");
478 LOG_WARNING("MDM: Halting target to detect secured state reliably");
479
480 retval = target_halt(target);
481 if (retval == ERROR_OK)
482 retval = target_wait_state(target, TARGET_HALTED, 100);
483
484 if (retval != ERROR_OK) {
485 LOG_WARNING("MDM: Target not halted, trying reset halt");
486 target->reset_halt = true;
487 target->type->assert_reset(target);
488 target->type->deassert_reset(target);
489 }
490
491 /* re-read status */
492 retval = kinetis_mdm_read_register(dap, MDM_REG_STAT, &val);
493 if (retval != ERROR_OK) {
494 LOG_ERROR("MDM: failed to read MDM_REG_STAT");
495 goto fail;
496 }
497 }
498
499 if (val & MDM_STAT_SYSSEC) {
500 jtag_poll_set_enabled(false);
501
502 LOG_WARNING("*********** ATTENTION! ATTENTION! ATTENTION! ATTENTION! **********");
503 LOG_WARNING("**** ****");
504 LOG_WARNING("**** Your Kinetis MCU is in secured state, which means that, ****");
505 LOG_WARNING("**** with exception for very basic communication, JTAG/SWD ****");
506 LOG_WARNING("**** interface will NOT work. In order to restore its ****");
507 LOG_WARNING("**** functionality please issue 'kinetis mdm mass_erase' ****");
508 LOG_WARNING("**** command, power cycle the MCU and restart OpenOCD. ****");
509 LOG_WARNING("**** ****");
510 LOG_WARNING("*********** ATTENTION! ATTENTION! ATTENTION! ATTENTION! **********");
511 } else {
512 LOG_INFO("MDM: Chip is unsecured. Continuing.");
513 jtag_poll_set_enabled(true);
514 }
515
516 return ERROR_OK;
517
518 fail:
519 LOG_ERROR("MDM: Failed to check security status of the MCU. Cannot proceed further");
520 jtag_poll_set_enabled(false);
521 return retval;
522 }
523
524 FLASH_BANK_COMMAND_HANDLER(kinetis_flash_bank_command)
525 {
526 struct kinetis_flash_bank *bank_info;
527
528 if (CMD_ARGC < 6)
529 return ERROR_COMMAND_SYNTAX_ERROR;
530
531 LOG_INFO("add flash_bank kinetis %s", bank->name);
532
533 bank_info = malloc(sizeof(struct kinetis_flash_bank));
534
535 memset(bank_info, 0, sizeof(struct kinetis_flash_bank));
536
537 bank->driver_priv = bank_info;
538
539 return ERROR_OK;
540 }
541
542 /* Disable the watchdog on Kinetis devices */
543 int kinetis_disable_wdog(struct target *target, uint32_t sim_sdid)
544 {
545 struct working_area *wdog_algorithm;
546 struct armv7m_algorithm armv7m_info;
547 uint16_t wdog;
548 int retval;
549
550 static const uint8_t kinetis_unlock_wdog_code[] = {
551 /* WDOG_UNLOCK = 0xC520 */
552 0x4f, 0xf4, 0x00, 0x53, /* mov.w r3, #8192 ; 0x2000 */
553 0xc4, 0xf2, 0x05, 0x03, /* movt r3, #16389 ; 0x4005 */
554 0x4c, 0xf2, 0x20, 0x52, /* movw r2, #50464 ; 0xc520 */
555 0xda, 0x81, /* strh r2, [r3, #14] */
556
557 /* WDOG_UNLOCK = 0xD928 */
558 0x4f, 0xf4, 0x00, 0x53, /* mov.w r3, #8192 ; 0x2000 */
559 0xc4, 0xf2, 0x05, 0x03, /* movt r3, #16389 ; 0x4005 */
560 0x4d, 0xf6, 0x28, 0x12, /* movw r2, #55592 ; 0xd928 */
561 0xda, 0x81, /* strh r2, [r3, #14] */
562
563 /* WDOG_SCR = 0x1d2 */
564 0x4f, 0xf4, 0x00, 0x53, /* mov.w r3, #8192 ; 0x2000 */
565 0xc4, 0xf2, 0x05, 0x03, /* movt r3, #16389 ; 0x4005 */
566 0x4f, 0xf4, 0xe9, 0x72, /* mov.w r2, #466 ; 0x1d2 */
567 0x1a, 0x80, /* strh r2, [r3, #0] */
568
569 /* END */
570 0x00, 0xBE, /* bkpt #0 */
571 };
572
573 /* Decide whether the connected device needs watchdog disabling.
574 * Disable for all Kx devices, i.e., return if it is a KLx */
575
576 if ((sim_sdid & KINETIS_SDID_SERIESID_MASK) == KINETIS_SDID_SERIESID_KL)
577 return ERROR_OK;
578
579 /* The connected device requires watchdog disabling. */
580 retval = target_read_u16(target, WDOG_STCTRH, &wdog);
581 if (retval != ERROR_OK)
582 return retval;
583
584 if ((wdog & 0x1) == 0) {
585 /* watchdog already disabled */
586 return ERROR_OK;
587 }
588 LOG_INFO("Disabling Kinetis watchdog (initial WDOG_STCTRLH = 0x%x)", wdog);
589
590 if (target->state != TARGET_HALTED) {
591 LOG_ERROR("Target not halted");
592 return ERROR_TARGET_NOT_HALTED;
593 }
594
595 retval = target_alloc_working_area(target, sizeof(kinetis_unlock_wdog_code), &wdog_algorithm);
596 if (retval != ERROR_OK)
597 return retval;
598
599 retval = target_write_buffer(target, wdog_algorithm->address,
600 sizeof(kinetis_unlock_wdog_code), (uint8_t *)kinetis_unlock_wdog_code);
601 if (retval != ERROR_OK) {
602 target_free_working_area(target, wdog_algorithm);
603 return retval;
604 }
605
606 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
607 armv7m_info.core_mode = ARM_MODE_THREAD;
608
609 retval = target_run_algorithm(target, 0, NULL, 0, NULL, wdog_algorithm->address,
610 wdog_algorithm->address + (sizeof(kinetis_unlock_wdog_code) - 2),
611 10000, &armv7m_info);
612
613 if (retval != ERROR_OK)
614 LOG_ERROR("error executing kinetis wdog unlock algorithm");
615
616 retval = target_read_u16(target, WDOG_STCTRH, &wdog);
617 if (retval != ERROR_OK)
618 return retval;
619 LOG_INFO("WDOG_STCTRLH = 0x%x", wdog);
620
621 target_free_working_area(target, wdog_algorithm);
622
623 return retval;
624 }
625
626 COMMAND_HANDLER(kinetis_disable_wdog_handler)
627 {
628 int result;
629 uint32_t sim_sdid;
630 struct target *target = get_current_target(CMD_CTX);
631
632 if (CMD_ARGC > 0)
633 return ERROR_COMMAND_SYNTAX_ERROR;
634
635 result = target_read_u32(target, SIM_SDID, &sim_sdid);
636 if (result != ERROR_OK) {
637 LOG_ERROR("Failed to read SIMSDID");
638 return result;
639 }
640
641 result = kinetis_disable_wdog(target, sim_sdid);
642 return result;
643 }
644
645
646 /* Kinetis Program-LongWord Microcodes */
647 static const uint8_t kinetis_flash_write_code[] = {
648 /* Params:
649 * r0 - workarea buffer
650 * r1 - target address
651 * r2 - wordcount
652 * Clobbered:
653 * r4 - tmp
654 * r5 - tmp
655 * r6 - tmp
656 * r7 - tmp
657 */
658
659 /* .L1: */
660 /* for(register uint32_t i=0;i<wcount;i++){ */
661 0x04, 0x1C, /* mov r4, r0 */
662 0x00, 0x23, /* mov r3, #0 */
663 /* .L2: */
664 0x0E, 0x1A, /* sub r6, r1, r0 */
665 0xA6, 0x19, /* add r6, r4, r6 */
666 0x93, 0x42, /* cmp r3, r2 */
667 0x16, 0xD0, /* beq .L9 */
668 /* .L5: */
669 /* while((FTFx_FSTAT&FTFA_FSTAT_CCIF_MASK) != FTFA_FSTAT_CCIF_MASK){}; */
670 0x0B, 0x4D, /* ldr r5, .L10 */
671 0x2F, 0x78, /* ldrb r7, [r5] */
672 0x7F, 0xB2, /* sxtb r7, r7 */
673 0x00, 0x2F, /* cmp r7, #0 */
674 0xFA, 0xDA, /* bge .L5 */
675 /* FTFx_FSTAT = FTFA_FSTAT_ACCERR_MASK|FTFA_FSTAT_FPVIOL_MASK|FTFA_FSTAT_RDCO */
676 0x70, 0x27, /* mov r7, #112 */
677 0x2F, 0x70, /* strb r7, [r5] */
678 /* FTFx_FCCOB3 = faddr; */
679 0x09, 0x4F, /* ldr r7, .L10+4 */
680 0x3E, 0x60, /* str r6, [r7] */
681 0x06, 0x27, /* mov r7, #6 */
682 /* FTFx_FCCOB0 = 0x06; */
683 0x08, 0x4E, /* ldr r6, .L10+8 */
684 0x37, 0x70, /* strb r7, [r6] */
685 /* FTFx_FCCOB7 = *pLW; */
686 0x80, 0xCC, /* ldmia r4!, {r7} */
687 0x08, 0x4E, /* ldr r6, .L10+12 */
688 0x37, 0x60, /* str r7, [r6] */
689 /* FTFx_FSTAT = FTFA_FSTAT_CCIF_MASK; */
690 0x80, 0x27, /* mov r7, #128 */
691 0x2F, 0x70, /* strb r7, [r5] */
692 /* .L4: */
693 /* while((FTFx_FSTAT&FTFA_FSTAT_CCIF_MASK) != FTFA_FSTAT_CCIF_MASK){}; */
694 0x2E, 0x78, /* ldrb r6, [r5] */
695 0x77, 0xB2, /* sxtb r7, r6 */
696 0x00, 0x2F, /* cmp r7, #0 */
697 0xFB, 0xDA, /* bge .L4 */
698 0x01, 0x33, /* add r3, r3, #1 */
699 0xE4, 0xE7, /* b .L2 */
700 /* .L9: */
701 0x00, 0xBE, /* bkpt #0 */
702 /* .L10: */
703 0x00, 0x00, 0x02, 0x40, /* .word 1073872896 */
704 0x04, 0x00, 0x02, 0x40, /* .word 1073872900 */
705 0x07, 0x00, 0x02, 0x40, /* .word 1073872903 */
706 0x08, 0x00, 0x02, 0x40, /* .word 1073872904 */
707 };
708
709 /* Program LongWord Block Write */
710 static int kinetis_write_block(struct flash_bank *bank, const uint8_t *buffer,
711 uint32_t offset, uint32_t wcount)
712 {
713 struct target *target = bank->target;
714 uint32_t buffer_size = 2048; /* Default minimum value */
715 struct working_area *write_algorithm;
716 struct working_area *source;
717 struct kinetis_flash_bank *kinfo = bank->driver_priv;
718 uint32_t address = kinfo->prog_base + offset;
719 struct reg_param reg_params[3];
720 struct armv7m_algorithm armv7m_info;
721 int retval = ERROR_OK;
722
723 /* Params:
724 * r0 - workarea buffer
725 * r1 - target address
726 * r2 - wordcount
727 * Clobbered:
728 * r4 - tmp
729 * r5 - tmp
730 * r6 - tmp
731 * r7 - tmp
732 */
733
734 /* Increase buffer_size if needed */
735 if (buffer_size < (target->working_area_size/2))
736 buffer_size = (target->working_area_size/2);
737
738 LOG_INFO("Kinetis: FLASH Write ...");
739
740 /* check code alignment */
741 if (offset & 0x1) {
742 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
743 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
744 }
745
746 /* allocate working area with flash programming code */
747 if (target_alloc_working_area(target, sizeof(kinetis_flash_write_code),
748 &write_algorithm) != ERROR_OK) {
749 LOG_WARNING("no working area available, can't do block memory writes");
750 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
751 }
752
753 retval = target_write_buffer(target, write_algorithm->address,
754 sizeof(kinetis_flash_write_code), kinetis_flash_write_code);
755 if (retval != ERROR_OK)
756 return retval;
757
758 /* memory buffer */
759 while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
760 buffer_size /= 4;
761 if (buffer_size <= 256) {
762 /* free working area, write algorithm already allocated */
763 target_free_working_area(target, write_algorithm);
764
765 LOG_WARNING("No large enough working area available, can't do block memory writes");
766 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
767 }
768 }
769
770 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
771 armv7m_info.core_mode = ARM_MODE_THREAD;
772
773 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT); /* *pLW (*buffer) */
774 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* faddr */
775 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* number of words to program */
776
777 /* write code buffer and use Flash programming code within kinetis */
778 /* Set breakpoint to 0 with time-out of 1000 ms */
779 while (wcount > 0) {
780 uint32_t thisrun_count = (wcount > (buffer_size / 4)) ? (buffer_size / 4) : wcount;
781
782 retval = target_write_buffer(target, source->address, thisrun_count * 4, buffer);
783 if (retval != ERROR_OK)
784 break;
785
786 buf_set_u32(reg_params[0].value, 0, 32, source->address);
787 buf_set_u32(reg_params[1].value, 0, 32, address);
788 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
789
790 retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
791 write_algorithm->address, 0, 100000, &armv7m_info);
792 if (retval != ERROR_OK) {
793 LOG_ERROR("Error executing kinetis Flash programming algorithm");
794 retval = ERROR_FLASH_OPERATION_FAILED;
795 break;
796 }
797
798 buffer += thisrun_count * 4;
799 address += thisrun_count * 4;
800 wcount -= thisrun_count;
801 }
802
803 target_free_working_area(target, source);
804 target_free_working_area(target, write_algorithm);
805
806 destroy_reg_param(&reg_params[0]);
807 destroy_reg_param(&reg_params[1]);
808 destroy_reg_param(&reg_params[2]);
809
810 return retval;
811 }
812
813 static int kinetis_protect(struct flash_bank *bank, int set, int first, int last)
814 {
815 LOG_WARNING("kinetis_protect not supported yet");
816 /* FIXME: TODO */
817
818 if (bank->target->state != TARGET_HALTED) {
819 LOG_ERROR("Target not halted");
820 return ERROR_TARGET_NOT_HALTED;
821 }
822
823 return ERROR_FLASH_BANK_INVALID;
824 }
825
826 static int kinetis_protect_check(struct flash_bank *bank)
827 {
828 struct kinetis_flash_bank *kinfo = bank->driver_priv;
829 int result;
830 int i, b;
831 uint32_t fprot, psec;
832
833 if (bank->target->state != TARGET_HALTED) {
834 LOG_ERROR("Target not halted");
835 return ERROR_TARGET_NOT_HALTED;
836 }
837
838 if (kinfo->flash_class == FC_PFLASH) {
839 uint8_t buffer[4];
840
841 /* read protection register */
842 result = target_read_memory(bank->target, FTFx_FPROT3, 1, 4, buffer);
843
844 if (result != ERROR_OK)
845 return result;
846
847 fprot = target_buffer_get_u32(bank->target, buffer);
848 /* Every bit protects 1/32 of the full flash (not necessarily just this bank) */
849
850 } else if (kinfo->flash_class == FC_FLEX_NVM) {
851 uint8_t fdprot;
852
853 /* read protection register */
854 result = target_read_memory(bank->target, FTFx_FDPROT, 1, 1, &fdprot);
855
856 if (result != ERROR_OK)
857 return result;
858
859 fprot = fdprot;
860
861 } else {
862 LOG_ERROR("Protection checks for FlexRAM not supported");
863 return ERROR_FLASH_BANK_INVALID;
864 }
865
866 b = kinfo->protection_block;
867 for (psec = 0, i = 0; i < bank->num_sectors; i++) {
868 if ((fprot >> b) & 1)
869 bank->sectors[i].is_protected = 0;
870 else
871 bank->sectors[i].is_protected = 1;
872
873 psec += bank->sectors[i].size;
874
875 if (psec >= kinfo->protection_size) {
876 psec = 0;
877 b++;
878 }
879 }
880
881 return ERROR_OK;
882 }
883
884 static int kinetis_ftfx_command(struct target *target, uint8_t fcmd, uint32_t faddr,
885 uint8_t fccob4, uint8_t fccob5, uint8_t fccob6, uint8_t fccob7,
886 uint8_t fccob8, uint8_t fccob9, uint8_t fccoba, uint8_t fccobb,
887 uint8_t *ftfx_fstat)
888 {
889 uint8_t command[12] = {faddr & 0xff, (faddr >> 8) & 0xff, (faddr >> 16) & 0xff, fcmd,
890 fccob7, fccob6, fccob5, fccob4,
891 fccobb, fccoba, fccob9, fccob8};
892 int result, i;
893 uint8_t buffer;
894
895 /* wait for done */
896 for (i = 0; i < 50; i++) {
897 result =
898 target_read_memory(target, FTFx_FSTAT, 1, 1, &buffer);
899
900 if (result != ERROR_OK)
901 return result;
902
903 if (buffer & 0x80)
904 break;
905
906 buffer = 0x00;
907 }
908
909 if (buffer != 0x80) {
910 /* reset error flags */
911 buffer = 0x30;
912 result =
913 target_write_memory(target, FTFx_FSTAT, 1, 1, &buffer);
914 if (result != ERROR_OK)
915 return result;
916 }
917
918 result = target_write_memory(target, FTFx_FCCOB3, 4, 3, command);
919
920 if (result != ERROR_OK)
921 return result;
922
923 /* start command */
924 buffer = 0x80;
925 result = target_write_memory(target, FTFx_FSTAT, 1, 1, &buffer);
926 if (result != ERROR_OK)
927 return result;
928
929 /* wait for done */
930 for (i = 0; i < 240; i++) { /* Need longtime for "Mass Erase" Command Nemui Changed */
931 result =
932 target_read_memory(target, FTFx_FSTAT, 1, 1, ftfx_fstat);
933
934 if (result != ERROR_OK)
935 return result;
936
937 if (*ftfx_fstat & 0x80)
938 break;
939 }
940
941 if ((*ftfx_fstat & 0xf0) != 0x80) {
942 LOG_ERROR
943 ("ftfx command failed FSTAT: %02X FCCOB: %02X%02X%02X%02X %02X%02X%02X%02X %02X%02X%02X%02X",
944 *ftfx_fstat, command[3], command[2], command[1], command[0],
945 command[7], command[6], command[5], command[4],
946 command[11], command[10], command[9], command[8]);
947 return ERROR_FLASH_OPERATION_FAILED;
948 }
949
950 return ERROR_OK;
951 }
952
953
954 static void kinetis_invalidate_flash_cache(struct flash_bank *bank)
955 {
956 struct kinetis_flash_bank *kinfo = bank->driver_priv;
957 uint8_t pfb01cr_byte2 = 0xf0;
958
959 if (!(kinfo->flash_support & FS_INVALIDATE_CACHE))
960 return;
961
962 target_write_memory(bank->target, FMC_PFB01CR + 2, 1, 1, &pfb01cr_byte2);
963 return;
964 }
965
966
967 static int kinetis_erase(struct flash_bank *bank, int first, int last)
968 {
969 int result, i;
970 struct kinetis_flash_bank *kinfo = bank->driver_priv;
971
972 if (bank->target->state != TARGET_HALTED) {
973 LOG_ERROR("Target not halted");
974 return ERROR_TARGET_NOT_HALTED;
975 }
976
977 if ((first > bank->num_sectors) || (last > bank->num_sectors))
978 return ERROR_FLASH_OPERATION_FAILED;
979
980 /*
981 * FIXME: TODO: use the 'Erase Flash Block' command if the
982 * requested erase is PFlash or NVM and encompasses the entire
983 * block. Should be quicker.
984 */
985 for (i = first; i <= last; i++) {
986 uint8_t ftfx_fstat;
987 /* set command and sector address */
988 result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTERASE, kinfo->prog_base + bank->sectors[i].offset,
989 0, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
990
991 if (result != ERROR_OK) {
992 LOG_WARNING("erase sector %d failed", i);
993 return ERROR_FLASH_OPERATION_FAILED;
994 }
995
996 bank->sectors[i].is_erased = 1;
997 }
998
999 kinetis_invalidate_flash_cache(bank);
1000
1001 if (first == 0) {
1002 LOG_WARNING
1003 ("flash configuration field erased, please reset the device");
1004 }
1005
1006 return ERROR_OK;
1007 }
1008
1009 static int kinetis_make_ram_ready(struct target *target)
1010 {
1011 int result;
1012 uint8_t ftfx_fstat;
1013 uint8_t ftfx_fcnfg;
1014
1015 /* check if ram ready */
1016 result = target_read_memory(target, FTFx_FCNFG, 1, 1, &ftfx_fcnfg);
1017 if (result != ERROR_OK)
1018 return result;
1019
1020 if (ftfx_fcnfg & (1 << 1))
1021 return ERROR_OK; /* ram ready */
1022
1023 /* make flex ram available */
1024 result = kinetis_ftfx_command(target, FTFx_CMD_SETFLEXRAM, 0x00ff0000,
1025 0, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
1026 if (result != ERROR_OK)
1027 return ERROR_FLASH_OPERATION_FAILED;
1028
1029 /* check again */
1030 result = target_read_memory(target, FTFx_FCNFG, 1, 1, &ftfx_fcnfg);
1031 if (result != ERROR_OK)
1032 return result;
1033
1034 if (ftfx_fcnfg & (1 << 1))
1035 return ERROR_OK; /* ram ready */
1036
1037 return ERROR_FLASH_OPERATION_FAILED;
1038 }
1039
1040 static int kinetis_write(struct flash_bank *bank, const uint8_t *buffer,
1041 uint32_t offset, uint32_t count)
1042 {
1043 unsigned int i, result, fallback = 0;
1044 uint32_t wc;
1045 struct kinetis_flash_bank *kinfo = bank->driver_priv;
1046 uint8_t *new_buffer = NULL;
1047
1048 if (bank->target->state != TARGET_HALTED) {
1049 LOG_ERROR("Target not halted");
1050 return ERROR_TARGET_NOT_HALTED;
1051 }
1052
1053 if (!(kinfo->flash_support & FS_PROGRAM_SECTOR)) {
1054 /* fallback to longword write */
1055 fallback = 1;
1056 LOG_WARNING("This device supports Program Longword execution only.");
1057 } else {
1058 result = kinetis_make_ram_ready(bank->target);
1059 if (result != ERROR_OK) {
1060 fallback = 1;
1061 LOG_WARNING("FlexRAM not ready, fallback to slow longword write.");
1062 }
1063 }
1064
1065 LOG_DEBUG("flash write @08%" PRIX32, offset);
1066
1067
1068 /* program section command */
1069 if (fallback == 0) {
1070 /*
1071 * Kinetis uses different terms for the granularity of
1072 * sector writes, e.g. "phrase" or "128 bits". We use
1073 * the generic term "chunk". The largest possible
1074 * Kinetis "chunk" is 16 bytes (128 bits).
1075 */
1076 unsigned prog_section_chunk_bytes = kinfo->sector_size >> 8;
1077 unsigned prog_size_bytes = kinfo->max_flash_prog_size;
1078 for (i = 0; i < count; i += prog_size_bytes) {
1079 uint8_t residual_buffer[16];
1080 uint8_t ftfx_fstat;
1081 uint32_t section_count = prog_size_bytes / prog_section_chunk_bytes;
1082 uint32_t residual_wc = 0;
1083
1084 /*
1085 * Assume the word count covers an entire
1086 * sector.
1087 */
1088 wc = prog_size_bytes / 4;
1089
1090 /*
1091 * If bytes to be programmed are less than the
1092 * full sector, then determine the number of
1093 * full-words to program, and put together the
1094 * residual buffer so that a full "section"
1095 * may always be programmed.
1096 */
1097 if ((count - i) < prog_size_bytes) {
1098 /* number of bytes to program beyond full section */
1099 unsigned residual_bc = (count-i) % prog_section_chunk_bytes;
1100
1101 /* number of complete words to copy directly from buffer */
1102 wc = (count - i - residual_bc) / 4;
1103
1104 /* number of total sections to write, including residual */
1105 section_count = DIV_ROUND_UP((count-i), prog_section_chunk_bytes);
1106
1107 /* any residual bytes delivers a whole residual section */
1108 residual_wc = (residual_bc ? prog_section_chunk_bytes : 0)/4;
1109
1110 /* clear residual buffer then populate residual bytes */
1111 (void) memset(residual_buffer, 0xff, prog_section_chunk_bytes);
1112 (void) memcpy(residual_buffer, &buffer[i+4*wc], residual_bc);
1113 }
1114
1115 LOG_DEBUG("write section @ %08" PRIX32 " with length %" PRIu32 " bytes",
1116 offset + i, (uint32_t)wc*4);
1117
1118 /* write data to flexram as whole-words */
1119 result = target_write_memory(bank->target, FLEXRAM, 4, wc,
1120 buffer + i);
1121
1122 if (result != ERROR_OK) {
1123 LOG_ERROR("target_write_memory failed");
1124 return result;
1125 }
1126
1127 /* write the residual words to the flexram */
1128 if (residual_wc) {
1129 result = target_write_memory(bank->target,
1130 FLEXRAM+4*wc,
1131 4, residual_wc,
1132 residual_buffer);
1133
1134 if (result != ERROR_OK) {
1135 LOG_ERROR("target_write_memory failed");
1136 return result;
1137 }
1138 }
1139
1140 /* execute section-write command */
1141 result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTWRITE, kinfo->prog_base + offset + i,
1142 section_count>>8, section_count, 0, 0,
1143 0, 0, 0, 0, &ftfx_fstat);
1144
1145 if (result != ERROR_OK)
1146 return ERROR_FLASH_OPERATION_FAILED;
1147 }
1148 }
1149 /* program longword command, not supported in "SF3" devices */
1150 else if (kinfo->flash_support & FS_PROGRAM_LONGWORD) {
1151 if (count & 0x3) {
1152 uint32_t old_count = count;
1153 count = (old_count | 3) + 1;
1154 new_buffer = malloc(count);
1155 if (new_buffer == NULL) {
1156 LOG_ERROR("odd number of bytes to write and no memory "
1157 "for padding buffer");
1158 return ERROR_FAIL;
1159 }
1160 LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " "
1161 "and padding with 0xff", old_count, count);
1162 memset(new_buffer, 0xff, count);
1163 buffer = memcpy(new_buffer, buffer, old_count);
1164 }
1165
1166 uint32_t words_remaining = count / 4;
1167
1168 kinetis_disable_wdog(bank->target, kinfo->sim_sdid);
1169
1170 /* try using a block write */
1171 int retval = kinetis_write_block(bank, buffer, offset, words_remaining);
1172
1173 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
1174 /* if block write failed (no sufficient working area),
1175 * we use normal (slow) single word accesses */
1176 LOG_WARNING("couldn't use block writes, falling back to single "
1177 "memory accesses");
1178
1179 for (i = 0; i < count; i += 4) {
1180 uint8_t ftfx_fstat;
1181
1182 LOG_DEBUG("write longword @ %08" PRIX32, (uint32_t)(offset + i));
1183
1184 uint8_t padding[4] = {0xff, 0xff, 0xff, 0xff};
1185 memcpy(padding, buffer + i, MIN(4, count-i));
1186
1187 result = kinetis_ftfx_command(bank->target, FTFx_CMD_LWORDPROG, kinfo->prog_base + offset + i,
1188 padding[3], padding[2], padding[1], padding[0],
1189 0, 0, 0, 0, &ftfx_fstat);
1190
1191 if (result != ERROR_OK)
1192 return ERROR_FLASH_OPERATION_FAILED;
1193 }
1194 }
1195 } else {
1196 LOG_ERROR("Flash write strategy not implemented");
1197 return ERROR_FLASH_OPERATION_FAILED;
1198 }
1199
1200 kinetis_invalidate_flash_cache(bank);
1201 return ERROR_OK;
1202 }
1203
1204 static int kinetis_read_part_info(struct flash_bank *bank)
1205 {
1206 int result, i;
1207 uint32_t offset = 0;
1208 uint8_t fcfg1_nvmsize, fcfg1_pfsize, fcfg1_eesize, fcfg1_depart;
1209 uint8_t fcfg2_maxaddr0, fcfg2_pflsh, fcfg2_maxaddr1;
1210 uint32_t nvm_size = 0, pf_size = 0, df_size = 0, ee_size = 0;
1211 unsigned num_blocks = 0, num_pflash_blocks = 0, num_nvm_blocks = 0, first_nvm_bank = 0,
1212 pflash_sector_size_bytes = 0, nvm_sector_size_bytes = 0;
1213 struct target *target = bank->target;
1214 struct kinetis_flash_bank *kinfo = bank->driver_priv;
1215
1216 kinfo->probed = false;
1217
1218 result = target_read_u32(target, SIM_SDID, &kinfo->sim_sdid);
1219 if (result != ERROR_OK)
1220 return result;
1221
1222 if ((kinfo->sim_sdid & (~KINETIS_SDID_K_SERIES_MASK)) == 0) {
1223 /* older K-series MCU */
1224 uint32_t mcu_type = kinfo->sim_sdid & KINETIS_K_SDID_TYPE_MASK;
1225
1226 switch (mcu_type) {
1227 case KINETIS_K_SDID_K10_M50:
1228 case KINETIS_K_SDID_K20_M50:
1229 /* 1kB sectors */
1230 pflash_sector_size_bytes = 1<<10;
1231 nvm_sector_size_bytes = 1<<10;
1232 num_blocks = 2;
1233 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1234 break;
1235 case KINETIS_K_SDID_K10_M72:
1236 case KINETIS_K_SDID_K20_M72:
1237 case KINETIS_K_SDID_K30_M72:
1238 case KINETIS_K_SDID_K30_M100:
1239 case KINETIS_K_SDID_K40_M72:
1240 case KINETIS_K_SDID_K40_M100:
1241 case KINETIS_K_SDID_K50_M72:
1242 /* 2kB sectors, 1kB FlexNVM sectors */
1243 pflash_sector_size_bytes = 2<<10;
1244 nvm_sector_size_bytes = 1<<10;
1245 num_blocks = 2;
1246 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1247 kinfo->max_flash_prog_size = 1<<10;
1248 break;
1249 case KINETIS_K_SDID_K10_M100:
1250 case KINETIS_K_SDID_K20_M100:
1251 case KINETIS_K_SDID_K11:
1252 case KINETIS_K_SDID_K12:
1253 case KINETIS_K_SDID_K21_M50:
1254 case KINETIS_K_SDID_K22_M50:
1255 case KINETIS_K_SDID_K51_M72:
1256 case KINETIS_K_SDID_K53:
1257 case KINETIS_K_SDID_K60_M100:
1258 /* 2kB sectors */
1259 pflash_sector_size_bytes = 2<<10;
1260 nvm_sector_size_bytes = 2<<10;
1261 num_blocks = 2;
1262 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1263 break;
1264 case KINETIS_K_SDID_K21_M120:
1265 case KINETIS_K_SDID_K22_M120:
1266 /* 4kB sectors (MK21FN1M0, MK21FX512, MK22FN1M0, MK22FX512) */
1267 pflash_sector_size_bytes = 4<<10;
1268 kinfo->max_flash_prog_size = 1<<10;
1269 nvm_sector_size_bytes = 4<<10;
1270 num_blocks = 2;
1271 kinfo->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1272 break;
1273 case KINETIS_K_SDID_K10_M120:
1274 case KINETIS_K_SDID_K20_M120:
1275 case KINETIS_K_SDID_K60_M150:
1276 case KINETIS_K_SDID_K70_M150:
1277 /* 4kB sectors */
1278 pflash_sector_size_bytes = 4<<10;
1279 nvm_sector_size_bytes = 4<<10;
1280 num_blocks = 4;
1281 kinfo->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1282 break;
1283 default:
1284 LOG_ERROR("Unsupported K-family FAMID");
1285 }
1286 } else {
1287 /* Newer K-series or KL series MCU */
1288 switch (kinfo->sim_sdid & KINETIS_SDID_SERIESID_MASK) {
1289 case KINETIS_SDID_SERIESID_K:
1290 switch (kinfo->sim_sdid & (KINETIS_SDID_FAMILYID_MASK | KINETIS_SDID_SUBFAMID_MASK)) {
1291 case KINETIS_SDID_FAMILYID_K0X | KINETIS_SDID_SUBFAMID_KX2:
1292 /* K02FN64, K02FN128: FTFA, 2kB sectors */
1293 pflash_sector_size_bytes = 2<<10;
1294 num_blocks = 1;
1295 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_INVALIDATE_CACHE;
1296 break;
1297
1298 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX2: {
1299 /* MK24FN1M reports as K22, this should detect it (according to errata note 1N83J) */
1300 uint32_t sopt1;
1301 result = target_read_u32(target, SIM_SOPT1, &sopt1);
1302 if (result != ERROR_OK)
1303 return result;
1304
1305 if (((kinfo->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K24FN1M) &&
1306 ((sopt1 & KINETIS_SOPT1_RAMSIZE_MASK) == KINETIS_SOPT1_RAMSIZE_K24FN1M)) {
1307 /* MK24FN1M */
1308 pflash_sector_size_bytes = 4<<10;
1309 num_blocks = 2;
1310 kinfo->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1311 kinfo->max_flash_prog_size = 1<<10;
1312 break;
1313 }
1314 if ((kinfo->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN128
1315 || (kinfo->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN256
1316 || (kinfo->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K22FN512) {
1317 /* K22 with new-style SDID - smaller pflash with FTFA, 2kB sectors */
1318 pflash_sector_size_bytes = 2<<10;
1319 /* autodetect 1 or 2 blocks */
1320 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_INVALIDATE_CACHE;
1321 break;
1322 }
1323 LOG_ERROR("Unsupported Kinetis K22 DIEID");
1324 break;
1325 }
1326 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX4:
1327 pflash_sector_size_bytes = 4<<10;
1328 if ((kinfo->sim_sdid & (KINETIS_SDID_DIEID_MASK)) == KINETIS_SDID_DIEID_K24FN256) {
1329 /* K24FN256 - smaller pflash with FTFA */
1330 num_blocks = 1;
1331 kinfo->flash_support = FS_PROGRAM_LONGWORD | FS_INVALIDATE_CACHE;
1332 break;
1333 }
1334 /* K24FN1M without errata 7534 */
1335 num_blocks = 2;
1336 kinfo->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1337 kinfo->max_flash_prog_size = 1<<10;
1338 break;
1339
1340 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX3:
1341 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX1: /* errata 7534 - should be K63 */
1342 /* K63FN1M0 */
1343 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX4:
1344 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX2: /* errata 7534 - should be K64 */
1345 /* K64FN1M0, K64FX512 */
1346 pflash_sector_size_bytes = 4<<10;
1347 nvm_sector_size_bytes = 4<<10;
1348 kinfo->max_flash_prog_size = 1<<10;
1349 num_blocks = 2;
1350 kinfo->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1351 break;
1352
1353 case KINETIS_SDID_FAMILYID_K2X | KINETIS_SDID_SUBFAMID_KX6:
1354 /* K26FN2M0 */
1355 case KINETIS_SDID_FAMILYID_K6X | KINETIS_SDID_SUBFAMID_KX6:
1356 /* K66FN2M0, K66FX1M0 */
1357 pflash_sector_size_bytes = 4<<10;
1358 nvm_sector_size_bytes = 4<<10;
1359 kinfo->max_flash_prog_size = 1<<10;
1360 num_blocks = 4;
1361 kinfo->flash_support = FS_PROGRAM_PHRASE | FS_PROGRAM_SECTOR | FS_INVALIDATE_CACHE;
1362 break;
1363 default:
1364 LOG_ERROR("Unsupported Kinetis FAMILYID SUBFAMID");
1365 }
1366 break;
1367 case KINETIS_SDID_SERIESID_KL:
1368 /* KL-series */
1369 pflash_sector_size_bytes = 1<<10;
1370 nvm_sector_size_bytes = 1<<10;
1371 /* autodetect 1 or 2 blocks */
1372 kinfo->flash_support = FS_PROGRAM_LONGWORD;
1373 break;
1374 default:
1375 LOG_ERROR("Unsupported K-series");
1376 }
1377 }
1378
1379 if (pflash_sector_size_bytes == 0) {
1380 LOG_ERROR("MCU is unsupported, SDID 0x%08" PRIx32, kinfo->sim_sdid);
1381 return ERROR_FLASH_OPER_UNSUPPORTED;
1382 }
1383
1384 result = target_read_u32(target, SIM_FCFG1, &kinfo->sim_fcfg1);
1385 if (result != ERROR_OK)
1386 return result;
1387
1388 result = target_read_u32(target, SIM_FCFG2, &kinfo->sim_fcfg2);
1389 if (result != ERROR_OK)
1390 return result;
1391
1392 LOG_DEBUG("SDID: 0x%08" PRIX32 " FCFG1: 0x%08" PRIX32 " FCFG2: 0x%08" PRIX32, kinfo->sim_sdid,
1393 kinfo->sim_fcfg1, kinfo->sim_fcfg2);
1394
1395 fcfg1_nvmsize = (uint8_t)((kinfo->sim_fcfg1 >> 28) & 0x0f);
1396 fcfg1_pfsize = (uint8_t)((kinfo->sim_fcfg1 >> 24) & 0x0f);
1397 fcfg1_eesize = (uint8_t)((kinfo->sim_fcfg1 >> 16) & 0x0f);
1398 fcfg1_depart = (uint8_t)((kinfo->sim_fcfg1 >> 8) & 0x0f);
1399
1400 fcfg2_pflsh = (uint8_t)((kinfo->sim_fcfg2 >> 23) & 0x01);
1401 fcfg2_maxaddr0 = (uint8_t)((kinfo->sim_fcfg2 >> 24) & 0x7f);
1402 fcfg2_maxaddr1 = (uint8_t)((kinfo->sim_fcfg2 >> 16) & 0x7f);
1403
1404 if (num_blocks == 0)
1405 num_blocks = fcfg2_maxaddr1 ? 2 : 1;
1406 else if (fcfg2_maxaddr1 == 0 && num_blocks >= 2) {
1407 num_blocks = 1;
1408 LOG_WARNING("MAXADDR1 is zero, number of flash banks adjusted to 1");
1409 } else if (fcfg2_maxaddr1 != 0 && num_blocks == 1) {
1410 num_blocks = 2;
1411 LOG_WARNING("MAXADDR1 is non zero, number of flash banks adjusted to 2");
1412 }
1413
1414 /* when the PFLSH bit is set, there is no FlexNVM/FlexRAM */
1415 if (!fcfg2_pflsh) {
1416 switch (fcfg1_nvmsize) {
1417 case 0x03:
1418 case 0x05:
1419 case 0x07:
1420 case 0x09:
1421 case 0x0b:
1422 nvm_size = 1 << (14 + (fcfg1_nvmsize >> 1));
1423 break;
1424 case 0x0f:
1425 if (pflash_sector_size_bytes >= 4<<10)
1426 nvm_size = 512<<10;
1427 else
1428 /* K20_100 */
1429 nvm_size = 256<<10;
1430 break;
1431 default:
1432 nvm_size = 0;
1433 break;
1434 }
1435
1436 switch (fcfg1_eesize) {
1437 case 0x00:
1438 case 0x01:
1439 case 0x02:
1440 case 0x03:
1441 case 0x04:
1442 case 0x05:
1443 case 0x06:
1444 case 0x07:
1445 case 0x08:
1446 case 0x09:
1447 ee_size = (16 << (10 - fcfg1_eesize));
1448 break;
1449 default:
1450 ee_size = 0;
1451 break;
1452 }
1453
1454 switch (fcfg1_depart) {
1455 case 0x01:
1456 case 0x02:
1457 case 0x03:
1458 case 0x04:
1459 case 0x05:
1460 case 0x06:
1461 df_size = nvm_size - (4096 << fcfg1_depart);
1462 break;
1463 case 0x08:
1464 df_size = 0;
1465 break;
1466 case 0x09:
1467 case 0x0a:
1468 case 0x0b:
1469 case 0x0c:
1470 case 0x0d:
1471 df_size = 4096 << (fcfg1_depart & 0x7);
1472 break;
1473 default:
1474 df_size = nvm_size;
1475 break;
1476 }
1477 }
1478
1479 switch (fcfg1_pfsize) {
1480 case 0x03:
1481 case 0x05:
1482 case 0x07:
1483 case 0x09:
1484 case 0x0b:
1485 case 0x0d:
1486 pf_size = 1 << (14 + (fcfg1_pfsize >> 1));
1487 break;
1488 case 0x0f:
1489 /* a peculiar case: Freescale states different sizes for 0xf
1490 * K02P64M100SFARM 128 KB ... duplicate of code 0x7
1491 * K22P121M120SF8RM 256 KB ... duplicate of code 0x9
1492 * K22P121M120SF7RM 512 KB ... duplicate of code 0xb
1493 * K22P100M120SF5RM 1024 KB ... duplicate of code 0xd
1494 * K26P169M180SF5RM 2048 KB ... the only unique value
1495 * fcfg2_maxaddr0 seems to be the only clue to pf_size
1496 * Checking fcfg2_maxaddr0 later in this routine is pointless then
1497 */
1498 if (fcfg2_pflsh)
1499 pf_size = ((uint32_t)fcfg2_maxaddr0 << 13) * num_blocks;
1500 else
1501 pf_size = ((uint32_t)fcfg2_maxaddr0 << 13) * num_blocks / 2;
1502 if (pf_size != 2048<<10)
1503 LOG_WARNING("SIM_FCFG1 PFSIZE = 0xf: please check if pflash is %u KB", pf_size>>10);
1504
1505 break;
1506 default:
1507 pf_size = 0;
1508 break;
1509 }
1510
1511 LOG_DEBUG("FlexNVM: %" PRIu32 " PFlash: %" PRIu32 " FlexRAM: %" PRIu32 " PFLSH: %d",
1512 nvm_size, pf_size, ee_size, fcfg2_pflsh);
1513
1514 num_pflash_blocks = num_blocks / (2 - fcfg2_pflsh);
1515 first_nvm_bank = num_pflash_blocks;
1516 num_nvm_blocks = num_blocks - num_pflash_blocks;
1517
1518 LOG_DEBUG("%d blocks total: %d PFlash, %d FlexNVM",
1519 num_blocks, num_pflash_blocks, num_nvm_blocks);
1520
1521 LOG_INFO("Probing flash info for bank %d", bank->bank_number);
1522
1523 if ((unsigned)bank->bank_number < num_pflash_blocks) {
1524 /* pflash, banks start at address zero */
1525 kinfo->flash_class = FC_PFLASH;
1526 bank->size = (pf_size / num_pflash_blocks);
1527 bank->base = 0x00000000 + bank->size * bank->bank_number;
1528 kinfo->prog_base = bank->base;
1529 kinfo->sector_size = pflash_sector_size_bytes;
1530 kinfo->protection_size = pf_size / 32;
1531 kinfo->protection_block = (32 / num_pflash_blocks) * bank->bank_number;
1532
1533 } else if ((unsigned)bank->bank_number < num_blocks) {
1534 /* nvm, banks start at address 0x10000000 */
1535 unsigned nvm_ord = bank->bank_number - first_nvm_bank;
1536 uint32_t limit;
1537
1538 kinfo->flash_class = FC_FLEX_NVM;
1539 bank->size = (nvm_size / num_nvm_blocks);
1540 bank->base = 0x10000000 + bank->size * nvm_ord;
1541 kinfo->prog_base = 0x00800000 + bank->size * nvm_ord;
1542 kinfo->sector_size = nvm_sector_size_bytes;
1543 if (df_size == 0) {
1544 kinfo->protection_size = 0;
1545 } else {
1546 for (i = df_size; ~i & 1; i >>= 1)
1547 ;
1548 if (i == 1)
1549 kinfo->protection_size = df_size / 8; /* data flash size = 2^^n */
1550 else
1551 kinfo->protection_size = nvm_size / 8; /* TODO: verify on SF1, not documented in RM */
1552 }
1553 kinfo->protection_block = (8 / num_nvm_blocks) * nvm_ord;
1554
1555 /* EEPROM backup part of FlexNVM is not accessible, use df_size as a limit */
1556 if (df_size > bank->size * nvm_ord)
1557 limit = df_size - bank->size * nvm_ord;
1558 else
1559 limit = 0;
1560
1561 if (bank->size > limit) {
1562 bank->size = limit;
1563 LOG_DEBUG("FlexNVM bank %d limited to 0x%08" PRIx32 " due to active EEPROM backup",
1564 bank->bank_number, limit);
1565 }
1566
1567 } else if ((unsigned)bank->bank_number == num_blocks) {
1568 LOG_ERROR("FlexRAM support not yet implemented");
1569 return ERROR_FLASH_OPER_UNSUPPORTED;
1570 } else {
1571 LOG_ERROR("Cannot determine parameters for bank %d, only %d banks on device",
1572 bank->bank_number, num_blocks);
1573 return ERROR_FLASH_BANK_INVALID;
1574 }
1575
1576 if (bank->bank_number == 0 && ((uint32_t)fcfg2_maxaddr0 << 13) != bank->size)
1577 LOG_WARNING("MAXADDR0 0x%02" PRIx8 " check failed,"
1578 " please report to OpenOCD mailing list", fcfg2_maxaddr0);
1579 if (fcfg2_pflsh) {
1580 if (bank->bank_number == 1 && ((uint32_t)fcfg2_maxaddr1 << 13) != bank->size)
1581 LOG_WARNING("MAXADDR1 0x%02" PRIx8 " check failed,"
1582 " please report to OpenOCD mailing list", fcfg2_maxaddr1);
1583 } else {
1584 if ((unsigned)bank->bank_number == first_nvm_bank
1585 && ((uint32_t)fcfg2_maxaddr1 << 13) != df_size)
1586 LOG_WARNING("FlexNVM MAXADDR1 0x%02" PRIx8 " check failed,"
1587 " please report to OpenOCD mailing list", fcfg2_maxaddr1);
1588 }
1589
1590 if (bank->sectors) {
1591 free(bank->sectors);
1592 bank->sectors = NULL;
1593 }
1594
1595 if (kinfo->sector_size == 0) {
1596 LOG_ERROR("Unknown sector size for bank %d", bank->bank_number);
1597 return ERROR_FLASH_BANK_INVALID;
1598 }
1599
1600 if (kinfo->flash_support & FS_PROGRAM_SECTOR
1601 && kinfo->max_flash_prog_size == 0) {
1602 kinfo->max_flash_prog_size = kinfo->sector_size;
1603 /* Program section size is equal to sector size by default */
1604 }
1605
1606 bank->num_sectors = bank->size / kinfo->sector_size;
1607
1608 if (bank->num_sectors > 0) {
1609 /* FlexNVM bank can be used for EEPROM backup therefore zero sized */
1610 bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
1611
1612 for (i = 0; i < bank->num_sectors; i++) {
1613 bank->sectors[i].offset = offset;
1614 bank->sectors[i].size = kinfo->sector_size;
1615 offset += kinfo->sector_size;
1616 bank->sectors[i].is_erased = -1;
1617 bank->sectors[i].is_protected = 1;
1618 }
1619 }
1620
1621 kinfo->probed = true;
1622
1623 return ERROR_OK;
1624 }
1625
1626 static int kinetis_probe(struct flash_bank *bank)
1627 {
1628 if (bank->target->state != TARGET_HALTED) {
1629 LOG_WARNING("Cannot communicate... target not halted.");
1630 return ERROR_TARGET_NOT_HALTED;
1631 }
1632
1633 return kinetis_read_part_info(bank);
1634 }
1635
1636 static int kinetis_auto_probe(struct flash_bank *bank)
1637 {
1638 struct kinetis_flash_bank *kinfo = bank->driver_priv;
1639
1640 if (kinfo && kinfo->probed)
1641 return ERROR_OK;
1642
1643 return kinetis_probe(bank);
1644 }
1645
1646 static int kinetis_info(struct flash_bank *bank, char *buf, int buf_size)
1647 {
1648 const char *bank_class_names[] = {
1649 "(ANY)", "PFlash", "FlexNVM", "FlexRAM"
1650 };
1651
1652 struct kinetis_flash_bank *kinfo = bank->driver_priv;
1653
1654 (void) snprintf(buf, buf_size,
1655 "%s driver for %s flash bank %s at 0x%8.8" PRIx32 "",
1656 bank->driver->name, bank_class_names[kinfo->flash_class],
1657 bank->name, bank->base);
1658
1659 return ERROR_OK;
1660 }
1661
1662 static int kinetis_blank_check(struct flash_bank *bank)
1663 {
1664 struct kinetis_flash_bank *kinfo = bank->driver_priv;
1665
1666 if (bank->target->state != TARGET_HALTED) {
1667 LOG_ERROR("Target not halted");
1668 return ERROR_TARGET_NOT_HALTED;
1669 }
1670
1671 if (kinfo->flash_class == FC_PFLASH || kinfo->flash_class == FC_FLEX_NVM) {
1672 int result;
1673 bool block_dirty = false;
1674 uint8_t ftfx_fstat;
1675
1676 if (kinfo->flash_class == FC_FLEX_NVM) {
1677 uint8_t fcfg1_depart = (uint8_t)((kinfo->sim_fcfg1 >> 8) & 0x0f);
1678 /* block operation cannot be used on FlexNVM when EEPROM backup partition is set */
1679 if (fcfg1_depart != 0xf && fcfg1_depart != 0)
1680 block_dirty = true;
1681 }
1682
1683 if (!block_dirty) {
1684 /* check if whole bank is blank */
1685 result = kinetis_ftfx_command(bank->target, FTFx_CMD_BLOCKSTAT, kinfo->prog_base,
1686 0, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
1687
1688 if (result != ERROR_OK || (ftfx_fstat & 0x01))
1689 block_dirty = true;
1690 }
1691
1692 if (block_dirty) {
1693 /* the whole bank is not erased, check sector-by-sector */
1694 int i;
1695 for (i = 0; i < bank->num_sectors; i++) {
1696 /* normal margin */
1697 result = kinetis_ftfx_command(bank->target, FTFx_CMD_SECTSTAT,
1698 kinfo->prog_base + bank->sectors[i].offset,
1699 1, 0, 0, 0, 0, 0, 0, 0, &ftfx_fstat);
1700
1701 if (result == ERROR_OK) {
1702 bank->sectors[i].is_erased = !(ftfx_fstat & 0x01);
1703 } else {
1704 LOG_DEBUG("Ignoring errored PFlash sector blank-check");
1705 bank->sectors[i].is_erased = -1;
1706 }
1707 }
1708 } else {
1709 /* the whole bank is erased, update all sectors */
1710 int i;
1711 for (i = 0; i < bank->num_sectors; i++)
1712 bank->sectors[i].is_erased = 1;
1713 }
1714 } else {
1715 LOG_WARNING("kinetis_blank_check not supported yet for FlexRAM");
1716 return ERROR_FLASH_OPERATION_FAILED;
1717 }
1718
1719 return ERROR_OK;
1720 }
1721
1722
1723 COMMAND_HANDLER(kinetis_nvm_partition)
1724 {
1725 int result, i;
1726 unsigned long par, log2 = 0, ee1 = 0, ee2 = 0;
1727 enum { SHOW_INFO, DF_SIZE, EEBKP_SIZE } sz_type = SHOW_INFO;
1728 bool enable;
1729 uint8_t ftfx_fstat;
1730 uint8_t load_flex_ram = 1;
1731 uint8_t ee_size_code = 0x3f;
1732 uint8_t flex_nvm_partition_code = 0;
1733 uint8_t ee_split = 3;
1734 struct target *target = get_current_target(CMD_CTX);
1735 struct flash_bank *bank;
1736 struct kinetis_flash_bank *kinfo;
1737 uint32_t sim_fcfg1;
1738
1739 if (CMD_ARGC >= 2) {
1740 if (strcmp(CMD_ARGV[0], "dataflash") == 0)
1741 sz_type = DF_SIZE;
1742 else if (strcmp(CMD_ARGV[0], "eebkp") == 0)
1743 sz_type = EEBKP_SIZE;
1744
1745 par = strtoul(CMD_ARGV[1], NULL, 10);
1746 while (par >> (log2 + 3))
1747 log2++;
1748 }
1749 switch (sz_type) {
1750 case SHOW_INFO:
1751 result = target_read_u32(target, SIM_FCFG1, &sim_fcfg1);
1752 if (result != ERROR_OK)
1753 return result;
1754
1755 flex_nvm_partition_code = (uint8_t)((sim_fcfg1 >> 8) & 0x0f);
1756 switch (flex_nvm_partition_code) {
1757 case 0:
1758 command_print(CMD_CTX, "No EEPROM backup, data flash only");
1759 break;
1760 case 1:
1761 case 2:
1762 case 3:
1763 case 4:
1764 case 5:
1765 case 6:
1766 command_print(CMD_CTX, "EEPROM backup %d KB", 4 << flex_nvm_partition_code);
1767 break;
1768 case 8:
1769 command_print(CMD_CTX, "No data flash, EEPROM backup only");
1770 break;
1771 case 0x9:
1772 case 0xA:
1773 case 0xB:
1774 case 0xC:
1775 case 0xD:
1776 case 0xE:
1777 command_print(CMD_CTX, "data flash %d KB", 4 << (flex_nvm_partition_code & 7));
1778 break;
1779 case 0xf:
1780 command_print(CMD_CTX, "No EEPROM backup, data flash only (DEPART not set)");
1781 break;
1782 default:
1783 command_print(CMD_CTX, "Unsupported EEPROM backup size code 0x%02" PRIx8, flex_nvm_partition_code);
1784 }
1785 return ERROR_OK;
1786
1787 case DF_SIZE:
1788 flex_nvm_partition_code = 0x8 | log2;
1789 break;
1790
1791 case EEBKP_SIZE:
1792 flex_nvm_partition_code = log2;
1793 break;
1794 }
1795
1796 if (CMD_ARGC == 3)
1797 ee1 = ee2 = strtoul(CMD_ARGV[2], NULL, 10) / 2;
1798 else if (CMD_ARGC >= 4) {
1799 ee1 = strtoul(CMD_ARGV[2], NULL, 10);
1800 ee2 = strtoul(CMD_ARGV[3], NULL, 10);
1801 }
1802
1803 enable = ee1 + ee2 > 0;
1804 if (enable) {
1805 for (log2 = 2; ; log2++) {
1806 if (ee1 + ee2 == (16u << 10) >> log2)
1807 break;
1808 if (ee1 + ee2 > (16u << 10) >> log2 || log2 >= 9) {
1809 LOG_ERROR("Unsupported EEPROM size");
1810 return ERROR_FLASH_OPERATION_FAILED;
1811 }
1812 }
1813
1814 if (ee1 * 3 == ee2)
1815 ee_split = 1;
1816 else if (ee1 * 7 == ee2)
1817 ee_split = 0;
1818 else if (ee1 != ee2) {
1819 LOG_ERROR("Unsupported EEPROM sizes ratio");
1820 return ERROR_FLASH_OPERATION_FAILED;
1821 }
1822
1823 ee_size_code = log2 | ee_split << 4;
1824 }
1825
1826 if (CMD_ARGC >= 5)
1827 COMMAND_PARSE_ON_OFF(CMD_ARGV[4], enable);
1828 if (enable)
1829 load_flex_ram = 0;
1830
1831 LOG_INFO("DEPART 0x%" PRIx8 ", EEPROM size code 0x%" PRIx8,
1832 flex_nvm_partition_code, ee_size_code);
1833
1834 if (target->state != TARGET_HALTED) {
1835 LOG_ERROR("Target not halted");
1836 return ERROR_TARGET_NOT_HALTED;
1837 }
1838
1839 result = kinetis_ftfx_command(target, FTFx_CMD_PGMPART, load_flex_ram,
1840 ee_size_code, flex_nvm_partition_code, 0, 0,
1841 0, 0, 0, 0, &ftfx_fstat);
1842 if (result != ERROR_OK)
1843 return result;
1844
1845 command_print(CMD_CTX, "FlexNVM partition set. Please reset MCU.");
1846
1847 for (i = 1; i < 4; i++) {
1848 bank = get_flash_bank_by_num_noprobe(i);
1849 if (bank == NULL)
1850 break;
1851
1852 kinfo = bank->driver_priv;
1853 if (kinfo && kinfo->flash_class == FC_FLEX_NVM)
1854 kinfo->probed = false; /* re-probe before next use */
1855 }
1856
1857 command_print(CMD_CTX, "FlexNVM banks will be re-probed to set new data flash size.");
1858 return ERROR_OK;
1859 }
1860
1861
1862 static const struct command_registration kinetis_securtiy_command_handlers[] = {
1863 {
1864 .name = "check_security",
1865 .mode = COMMAND_EXEC,
1866 .help = "",
1867 .usage = "",
1868 .handler = kinetis_check_flash_security_status,
1869 },
1870 {
1871 .name = "mass_erase",
1872 .mode = COMMAND_EXEC,
1873 .help = "",
1874 .usage = "",
1875 .handler = kinetis_mdm_mass_erase,
1876 },
1877 COMMAND_REGISTRATION_DONE
1878 };
1879
1880 static const struct command_registration kinetis_exec_command_handlers[] = {
1881 {
1882 .name = "mdm",
1883 .mode = COMMAND_ANY,
1884 .help = "",
1885 .usage = "",
1886 .chain = kinetis_securtiy_command_handlers,
1887 },
1888 {
1889 .name = "disable_wdog",
1890 .mode = COMMAND_EXEC,
1891 .help = "Disable the watchdog timer",
1892 .usage = "",
1893 .handler = kinetis_disable_wdog_handler,
1894 },
1895 {
1896 .name = "nvm_partition",
1897 .mode = COMMAND_EXEC,
1898 .help = "Show/set data flash or EEPROM backup size in kilobytes,"
1899 " set two EEPROM sizes in bytes and FlexRAM loading during reset",
1900 .usage = "('info'|'dataflash' size|'eebkp' size) [eesize1 eesize2] ['on'|'off']",
1901 .handler = kinetis_nvm_partition,
1902 },
1903 COMMAND_REGISTRATION_DONE
1904 };
1905
1906 static const struct command_registration kinetis_command_handler[] = {
1907 {
1908 .name = "kinetis",
1909 .mode = COMMAND_ANY,
1910 .help = "kinetis flash controller commands",
1911 .usage = "",
1912 .chain = kinetis_exec_command_handlers,
1913 },
1914 COMMAND_REGISTRATION_DONE
1915 };
1916
1917
1918
1919 struct flash_driver kinetis_flash = {
1920 .name = "kinetis",
1921 .commands = kinetis_command_handler,
1922 .flash_bank_command = kinetis_flash_bank_command,
1923 .erase = kinetis_erase,
1924 .protect = kinetis_protect,
1925 .write = kinetis_write,
1926 .read = default_flash_read,
1927 .probe = kinetis_probe,
1928 .auto_probe = kinetis_auto_probe,
1929 .erase_check = kinetis_blank_check,
1930 .protect_check = kinetis_protect_check,
1931 .info = kinetis_info,
1932 };
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