1 /***************************************************************************
2 * Copyright (C) 2008 by *
3 * Karl RobinSod <karl.robinsod@gmail.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
21 /***************************************************************************
22 * There are some things to notice
24 * You need to unprotect flash sectors each time you connect the OpenOCD
25 * Dumping 1MB takes about 60 Seconds
26 * Full erase (sectors 0-22 inclusive) takes 2-4 seconds
27 * Writing 1MB takes 88 seconds
29 ***************************************************************************/
35 #include <helper/binarybuffer.h>
38 #define LOAD_TIMER_ERASE 0
39 #define LOAD_TIMER_WRITE 1
41 #define FLASH_PAGE_SIZE 512
43 /* LPC288X control registers */
44 #define DBGU_CIDR 0x8000507C
45 /* LPC288X flash registers */
46 #define F_CTRL 0x80102000 /* Flash control register R/W 0x5 */
47 #define F_STAT 0x80102004 /* Flash status register RO 0x45 */
48 #define F_PROG_TIME 0x80102008 /* Flash program time register R/W 0 */
49 #define F_WAIT 0x80102010 /* Flash read wait state register R/W 0xC004 */
50 #define F_CLK_TIME 0x8010201C /* Flash clock divider for 66 kHz generation R/W 0 */
51 #define F_INTEN_CLR 0x80102FD8 /* Clear interrupt enable bits WO - */
52 #define F_INTEN_SET 0x80102FDC /* Set interrupt enable bits WO - */
53 #define F_INT_STAT 0x80102FE0 /* Interrupt status bits RO 0 */
54 #define F_INTEN 0x80102FE4 /* Interrupt enable bits RO 0 */
55 #define F_INT_CLR 0x80102FE8 /* Clear interrupt status bits WO */
56 #define F_INT_SET 0x80102FEC /* Set interrupt status bits WO - */
57 #define FLASH_PD 0x80005030 /* Allows turning off the Flash memory for power savings. R/W 1*/
58 #define FLASH_INIT 0x80005034 /* Monitors Flash readiness, such as recovery from Power Down mode. R/W -*/
62 #define FC_FUNC 0x0002
64 #define FC_RD_LATCH 0x0020
65 #define FC_PROTECT 0x0080
66 #define FC_SET_DATA 0x0400
67 #define FC_RSSL 0x0800
68 #define FC_PROG_REQ 0x1000
69 #define FC_CLR_BUF 0x4000
70 #define FC_LOAD_REQ 0x8000
72 #define FS_DONE 0x0001
73 #define FS_PROGGNT 0x0002
77 #define FPT_TIME_MASK 0x7FFF
79 #define FPT_ENABLE 0x8000
81 #define FW_WAIT_STATES_MASK 0x00FF
82 #define FW_SET_MASK 0xC000
85 #define FCT_CLK_DIV_MASK 0x0FFF
87 struct lpc288x_flash_bank
89 uint32_t working_area
;
90 uint32_t working_area_size
;
92 /* chip id register */
94 const char * target_name
;
97 uint32_t sector_size_break
;
100 static uint32_t lpc288x_wait_status_busy(struct flash_bank
*bank
, int timeout
);
101 static void lpc288x_load_timer(int erase
, struct target
*target
);
102 static void lpc288x_set_flash_clk(struct flash_bank
*bank
);
103 static uint32_t lpc288x_system_ready(struct flash_bank
*bank
);
105 static uint32_t lpc288x_wait_status_busy(struct flash_bank
*bank
, int timeout
)
108 struct target
*target
= bank
->target
;
113 target_read_u32(target
, F_STAT
, &status
);
114 } while (((status
& FS_DONE
) == 0) && timeout
);
118 LOG_DEBUG("Timedout!");
119 return ERROR_FLASH_OPERATION_FAILED
;
124 /* Read device id register and fill in driver info structure */
125 static int lpc288x_read_part_info(struct flash_bank
*bank
)
127 struct lpc288x_flash_bank
*lpc288x_info
= bank
->driver_priv
;
128 struct target
*target
= bank
->target
;
134 if (lpc288x_info
->cidr
== 0x0102100A)
135 return ERROR_OK
; /* already probed, multiple probes may cause memory leak, not allowed */
137 /* Read and parse chip identification register */
138 target_read_u32(target
, DBGU_CIDR
, &cidr
);
140 if (cidr
!= 0x0102100A)
142 LOG_WARNING("Cannot identify target as an LPC288X (%08" PRIx32
")",cidr
);
143 return ERROR_FLASH_OPERATION_FAILED
;
146 lpc288x_info
->cidr
= cidr
;
147 lpc288x_info
->sector_size_break
= 0x000F0000;
148 lpc288x_info
->target_name
= "LPC288x";
150 /* setup the sector info... */
152 bank
->num_sectors
= 23;
153 bank
->sectors
= malloc(sizeof(struct flash_sector
) * 23);
155 for (i
= 0; i
< 15; i
++)
157 bank
->sectors
[i
].offset
= offset
;
158 bank
->sectors
[i
].size
= 64 * 1024;
159 offset
+= bank
->sectors
[i
].size
;
160 bank
->sectors
[i
].is_erased
= -1;
161 bank
->sectors
[i
].is_protected
= 1;
163 for (i
= 15; i
< 23; i
++)
165 bank
->sectors
[i
].offset
= offset
;
166 bank
->sectors
[i
].size
= 8 * 1024;
167 offset
+= bank
->sectors
[i
].size
;
168 bank
->sectors
[i
].is_erased
= -1;
169 bank
->sectors
[i
].is_protected
= 1;
175 static int lpc288x_protect_check(struct flash_bank
*bank
)
180 /* flash_bank LPC288x 0 0 0 0 <target#> <cclk> */
181 FLASH_BANK_COMMAND_HANDLER(lpc288x_flash_bank_command
)
183 struct lpc288x_flash_bank
*lpc288x_info
;
187 return ERROR_COMMAND_SYNTAX_ERROR
;
190 lpc288x_info
= malloc(sizeof(struct lpc288x_flash_bank
));
191 bank
->driver_priv
= lpc288x_info
;
193 /* part wasn't probed for info yet */
194 lpc288x_info
->cidr
= 0;
195 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[6], lpc288x_info
->cclk
);
200 /* The frequency is the AHB clock frequency divided by (CLK_DIV ×3) + 1.
201 * This must be programmed such that the Flash Programming clock frequency is 66 kHz ± 20%.
203 * 12000000/66000 = 182
205 static void lpc288x_set_flash_clk(struct flash_bank
*bank
)
208 struct lpc288x_flash_bank
*lpc288x_info
= bank
->driver_priv
;
209 clk_time
= (lpc288x_info
->cclk
/ 66000) / 3;
210 target_write_u32(bank
->target
, F_CTRL
, FC_CS
| FC_WEN
);
211 target_write_u32(bank
->target
, F_CLK_TIME
, clk_time
);
214 /* AHB tcyc (in ns) 83 ns
215 * LOAD_TIMER_ERASE FPT_TIME = ((400,000,000 / AHB tcyc (in ns)) - 2) / 512
216 * = 9412 (9500) (AN10548 9375)
217 * LOAD_TIMER_WRITE FPT_TIME = ((1,000,000 / AHB tcyc (in ns)) - 2) / 512
218 * = 23 (75) (AN10548 72 - is this wrong?)
219 * TODO: Sort out timing calcs ;) */
220 static void lpc288x_load_timer(int erase
, struct target
*target
)
222 if (erase
== LOAD_TIMER_ERASE
)
224 target_write_u32(target
, F_PROG_TIME
, FPT_ENABLE
| 9500);
228 target_write_u32(target
, F_PROG_TIME
, FPT_ENABLE
| 75);
232 static uint32_t lpc288x_system_ready(struct flash_bank
*bank
)
234 struct lpc288x_flash_bank
*lpc288x_info
= bank
->driver_priv
;
235 if (lpc288x_info
->cidr
== 0)
237 return ERROR_FLASH_BANK_NOT_PROBED
;
240 if (bank
->target
->state
!= TARGET_HALTED
)
242 LOG_ERROR("Target not halted");
243 return ERROR_TARGET_NOT_HALTED
;
248 static int lpc288x_erase_check(struct flash_bank
*bank
)
250 uint32_t status
= lpc288x_system_ready(bank
); /* probed? halted? */
251 if (status
!= ERROR_OK
)
253 LOG_INFO("Processor not halted/not probed");
260 static int lpc288x_erase(struct flash_bank
*bank
, int first
, int last
)
264 struct target
*target
= bank
->target
;
266 status
= lpc288x_system_ready(bank
); /* probed? halted? */
267 if (status
!= ERROR_OK
)
272 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
274 LOG_INFO("Bad sector range");
275 return ERROR_FLASH_SECTOR_INVALID
;
278 /* Configure the flash controller timing */
279 lpc288x_set_flash_clk(bank
);
281 for (sector
= first
; sector
<= last
; sector
++)
283 if (lpc288x_wait_status_busy(bank
, 1000) != ERROR_OK
)
285 return ERROR_FLASH_OPERATION_FAILED
;
288 lpc288x_load_timer(LOAD_TIMER_ERASE
,target
);
290 target_write_u32(target
, bank
->sectors
[sector
].offset
, 0x00);
292 target_write_u32(target
, F_CTRL
, FC_PROG_REQ
| FC_PROTECT
| FC_CS
);
294 if (lpc288x_wait_status_busy(bank
, 1000) != ERROR_OK
)
296 return ERROR_FLASH_OPERATION_FAILED
;
301 static int lpc288x_write(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t offset
, uint32_t count
)
303 uint8_t page_buffer
[FLASH_PAGE_SIZE
];
304 uint32_t status
, source_offset
,dest_offset
;
305 struct target
*target
= bank
->target
;
306 uint32_t bytes_remaining
= count
;
307 uint32_t first_sector
, last_sector
, sector
, page
;
310 /* probed? halted? */
311 status
= lpc288x_system_ready(bank
);
312 if (status
!= ERROR_OK
)
317 /* Initialise search indices */
318 first_sector
= last_sector
= 0xffffffff;
320 /* validate the write range... */
321 for (i
= 0; i
< bank
->num_sectors
; i
++)
323 if ((offset
>= bank
->sectors
[i
].offset
) &&
324 (offset
< (bank
->sectors
[i
].offset
+ bank
->sectors
[i
].size
)) &&
325 (first_sector
== 0xffffffff))
328 /* all writes must start on a sector boundary... */
329 if (offset
% bank
->sectors
[i
].size
)
331 LOG_INFO("offset 0x%" PRIx32
" breaks required alignment 0x%" PRIx32
"", offset
, bank
->sectors
[i
].size
);
332 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
335 if (((offset
+ count
) > bank
->sectors
[i
].offset
) &&
336 ((offset
+ count
) <= (bank
->sectors
[i
].offset
+ bank
->sectors
[i
].size
)) &&
337 (last_sector
== 0xffffffff))
344 if (first_sector
== 0xffffffff || last_sector
== 0xffffffff)
346 LOG_INFO("Range check failed %" PRIx32
" %" PRIx32
"", offset
, count
);
347 return ERROR_FLASH_DST_OUT_OF_BANK
;
350 /* Configure the flash controller timing */
351 lpc288x_set_flash_clk(bank
);
353 /* initialise the offsets */
357 for (sector
= first_sector
; sector
<= last_sector
; sector
++)
359 for (page
= 0; page
< bank
->sectors
[sector
].size
/ FLASH_PAGE_SIZE
; page
++)
361 if (bytes_remaining
== 0)
364 memset(page_buffer
, 0xFF, FLASH_PAGE_SIZE
);
366 else if (bytes_remaining
< FLASH_PAGE_SIZE
)
368 count
= bytes_remaining
;
369 memset(page_buffer
, 0xFF, FLASH_PAGE_SIZE
);
370 memcpy(page_buffer
, &buffer
[source_offset
], count
);
374 count
= FLASH_PAGE_SIZE
;
375 memcpy(page_buffer
, &buffer
[source_offset
], count
);
378 /* Wait for flash to become ready */
379 if (lpc288x_wait_status_busy(bank
, 1000) != ERROR_OK
)
381 return ERROR_FLASH_OPERATION_FAILED
;
384 /* fill flash data latches with 1's */
385 target_write_u32(target
, F_CTRL
, FC_CS
| FC_SET_DATA
| FC_WEN
| FC_FUNC
);
387 target_write_u32(target
, F_CTRL
, FC_CS
| FC_WEN
| FC_FUNC
);
388 /*would be better to use the clean target_write_buffer() interface but
389 * it seems not to be a LOT slower....
390 * bulk_write_memory() is no quicker :(*/
392 if (target_write_memory(target
, offset
+ dest_offset
, 4, 128, page_buffer
) != ERROR_OK
)
394 LOG_ERROR("Write failed s %" PRIx32
" p %" PRIx32
"", sector
, page
);
395 return ERROR_FLASH_OPERATION_FAILED
;
398 if (target_write_buffer(target
, offset
+ dest_offset
, FLASH_PAGE_SIZE
, page_buffer
) != ERROR_OK
)
400 LOG_INFO("Write to flash buffer failed");
401 return ERROR_FLASH_OPERATION_FAILED
;
404 dest_offset
+= FLASH_PAGE_SIZE
;
405 source_offset
+= count
;
406 bytes_remaining
-= count
;
408 lpc288x_load_timer(LOAD_TIMER_WRITE
, target
);
410 target_write_u32(target
, F_CTRL
, FC_PROG_REQ
| FC_PROTECT
| FC_FUNC
| FC_CS
);
417 static int lpc288x_probe(struct flash_bank
*bank
)
419 /* we only deal with LPC2888 so flash config is fixed */
420 struct lpc288x_flash_bank
*lpc288x_info
= bank
->driver_priv
;
423 if (lpc288x_info
->cidr
!= 0)
425 return ERROR_OK
; /* already probed */
428 if (bank
->target
->state
!= TARGET_HALTED
)
430 LOG_ERROR("Target not halted");
431 return ERROR_TARGET_NOT_HALTED
;
434 retval
= lpc288x_read_part_info(bank
);
435 if (retval
!= ERROR_OK
)
440 static int lpc288x_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
442 snprintf(buf
, buf_size
, "lpc288x flash driver");
446 static int lpc288x_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
448 int lockregion
, status
;
450 struct target
*target
= bank
->target
;
452 /* probed? halted? */
453 status
= lpc288x_system_ready(bank
);
454 if (status
!= ERROR_OK
)
459 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
461 return ERROR_FLASH_SECTOR_INVALID
;
464 /* Configure the flash controller timing */
465 lpc288x_set_flash_clk(bank
);
467 for (lockregion
= first
; lockregion
<= last
; lockregion
++)
471 /* write an odd value to base addy to protect... */
476 /* write an even value to base addy to unprotect... */
479 target_write_u32(target
, bank
->sectors
[lockregion
].offset
, value
);
480 target_write_u32(target
, F_CTRL
, FC_LOAD_REQ
| FC_PROTECT
| FC_WEN
| FC_FUNC
| FC_CS
);
486 struct flash_driver lpc288x_flash
= {
488 .flash_bank_command
= lpc288x_flash_bank_command
,
489 .erase
= lpc288x_erase
,
490 .protect
= lpc288x_protect
,
491 .write
= lpc288x_write
,
492 .read
= default_flash_read
,
493 .probe
= lpc288x_probe
,
494 .auto_probe
= lpc288x_probe
,
495 .erase_check
= lpc288x_erase_check
,
496 .protect_check
= lpc288x_protect_check
,
497 .info
= lpc288x_info
,
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