1 /***************************************************************************
2 * Copyright (C) 2013 Synapse Product Development *
3 * Andrey Smirnov <andrew.smironv@gmail.com> *
4 * Angus Gratton <gus@projectgus.com> *
5 * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
19 ***************************************************************************/
26 #include <target/algorithm.h>
27 #include <target/armv7m.h>
28 #include <helper/types.h>
29 #include <helper/time_support.h>
32 NRF5_FLASH_BASE
= 0x00000000,
35 enum nrf5_ficr_registers
{
36 NRF5_FICR_BASE
= 0x10000000, /* Factory Information Configuration Registers */
38 #define NRF5_FICR_REG(offset) (NRF5_FICR_BASE + offset)
40 NRF5_FICR_CODEPAGESIZE
= NRF5_FICR_REG(0x010),
41 NRF5_FICR_CODESIZE
= NRF5_FICR_REG(0x014),
42 NRF5_FICR_CLENR0
= NRF5_FICR_REG(0x028),
43 NRF5_FICR_PPFC
= NRF5_FICR_REG(0x02C),
44 NRF5_FICR_NUMRAMBLOCK
= NRF5_FICR_REG(0x034),
45 NRF5_FICR_SIZERAMBLOCK0
= NRF5_FICR_REG(0x038),
46 NRF5_FICR_SIZERAMBLOCK1
= NRF5_FICR_REG(0x03C),
47 NRF5_FICR_SIZERAMBLOCK2
= NRF5_FICR_REG(0x040),
48 NRF5_FICR_SIZERAMBLOCK3
= NRF5_FICR_REG(0x044),
49 NRF5_FICR_CONFIGID
= NRF5_FICR_REG(0x05C),
50 NRF5_FICR_DEVICEID0
= NRF5_FICR_REG(0x060),
51 NRF5_FICR_DEVICEID1
= NRF5_FICR_REG(0x064),
52 NRF5_FICR_ER0
= NRF5_FICR_REG(0x080),
53 NRF5_FICR_ER1
= NRF5_FICR_REG(0x084),
54 NRF5_FICR_ER2
= NRF5_FICR_REG(0x088),
55 NRF5_FICR_ER3
= NRF5_FICR_REG(0x08C),
56 NRF5_FICR_IR0
= NRF5_FICR_REG(0x090),
57 NRF5_FICR_IR1
= NRF5_FICR_REG(0x094),
58 NRF5_FICR_IR2
= NRF5_FICR_REG(0x098),
59 NRF5_FICR_IR3
= NRF5_FICR_REG(0x09C),
60 NRF5_FICR_DEVICEADDRTYPE
= NRF5_FICR_REG(0x0A0),
61 NRF5_FICR_DEVICEADDR0
= NRF5_FICR_REG(0x0A4),
62 NRF5_FICR_DEVICEADDR1
= NRF5_FICR_REG(0x0A8),
63 NRF5_FICR_OVERRIDEN
= NRF5_FICR_REG(0x0AC),
64 NRF5_FICR_NRF_1MBIT0
= NRF5_FICR_REG(0x0B0),
65 NRF5_FICR_NRF_1MBIT1
= NRF5_FICR_REG(0x0B4),
66 NRF5_FICR_NRF_1MBIT2
= NRF5_FICR_REG(0x0B8),
67 NRF5_FICR_NRF_1MBIT3
= NRF5_FICR_REG(0x0BC),
68 NRF5_FICR_NRF_1MBIT4
= NRF5_FICR_REG(0x0C0),
69 NRF5_FICR_BLE_1MBIT0
= NRF5_FICR_REG(0x0EC),
70 NRF5_FICR_BLE_1MBIT1
= NRF5_FICR_REG(0x0F0),
71 NRF5_FICR_BLE_1MBIT2
= NRF5_FICR_REG(0x0F4),
72 NRF5_FICR_BLE_1MBIT3
= NRF5_FICR_REG(0x0F8),
73 NRF5_FICR_BLE_1MBIT4
= NRF5_FICR_REG(0x0FC),
76 enum nrf5_uicr_registers
{
77 NRF5_UICR_BASE
= 0x10001000, /* User Information
78 * Configuration Regsters */
80 NRF5_UICR_SIZE
= 0x100,
82 #define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
84 NRF5_UICR_CLENR0
= NRF5_UICR_REG(0x000),
85 NRF5_UICR_RBPCONF
= NRF5_UICR_REG(0x004),
86 NRF5_UICR_XTALFREQ
= NRF5_UICR_REG(0x008),
87 NRF5_UICR_FWID
= NRF5_UICR_REG(0x010),
90 enum nrf5_nvmc_registers
{
91 NRF5_NVMC_BASE
= 0x4001E000, /* Non-Volatile Memory
92 * Controller Regsters */
94 #define NRF5_NVMC_REG(offset) (NRF5_NVMC_BASE + offset)
96 NRF5_NVMC_READY
= NRF5_NVMC_REG(0x400),
97 NRF5_NVMC_CONFIG
= NRF5_NVMC_REG(0x504),
98 NRF5_NVMC_ERASEPAGE
= NRF5_NVMC_REG(0x508),
99 NRF5_NVMC_ERASEALL
= NRF5_NVMC_REG(0x50C),
100 NRF5_NVMC_ERASEUICR
= NRF5_NVMC_REG(0x514),
103 enum nrf5_nvmc_config_bits
{
104 NRF5_NVMC_CONFIG_REN
= 0x00,
105 NRF5_NVMC_CONFIG_WEN
= 0x01,
106 NRF5_NVMC_CONFIG_EEN
= 0x02,
111 uint32_t code_page_size
;
116 int (*write
) (struct flash_bank
*bank
,
117 struct nrf5_info
*chip
,
118 const uint8_t *buffer
, uint32_t offset
, uint32_t count
);
120 struct target
*target
;
123 struct nrf5_device_spec
{
127 const char *build_code
;
128 unsigned int flash_size_kb
;
131 #define NRF5_DEVICE_DEF(id, pt, var, bcode, fsize) \
136 .build_code = bcode, \
137 .flash_size_kb = (fsize), \
140 /* The known devices table below is derived from the "nRF51 Series
141 * Compatibility Matrix" document, which can be found by searching for
142 * ATTN-51 on the Nordic Semi website:
144 * http://www.nordicsemi.com/eng/content/search?SearchText=ATTN-51
146 * Up to date with Matrix v2.0, plus some additional HWIDs.
148 * The additional HWIDs apply where the build code in the matrix is
149 * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
150 * for x==0, x!=0 means different (unspecified) HWIDs.
152 static const struct nrf5_device_spec nrf5_known_devices_table
[] = {
153 /* nRF51822 Devices (IC rev 1). */
154 NRF5_DEVICE_DEF(0x001D, "51822", "QFAA", "CA/C0", 256),
155 NRF5_DEVICE_DEF(0x0026, "51822", "QFAB", "AA", 128),
156 NRF5_DEVICE_DEF(0x0027, "51822", "QFAB", "A0", 128),
157 NRF5_DEVICE_DEF(0x0020, "51822", "CEAA", "BA", 256),
158 NRF5_DEVICE_DEF(0x002F, "51822", "CEAA", "B0", 256),
160 /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
161 with built-in jlink seem to use engineering samples not listed
162 in the nRF51 Series Compatibility Matrix V1.0. */
163 NRF5_DEVICE_DEF(0x0071, "51822", "QFAC", "AB", 256),
165 /* nRF51822 Devices (IC rev 2). */
166 NRF5_DEVICE_DEF(0x002A, "51822", "QFAA", "FA0", 256),
167 NRF5_DEVICE_DEF(0x0044, "51822", "QFAA", "GC0", 256),
168 NRF5_DEVICE_DEF(0x003C, "51822", "QFAA", "G0", 256),
169 NRF5_DEVICE_DEF(0x0057, "51822", "QFAA", "G2", 256),
170 NRF5_DEVICE_DEF(0x0058, "51822", "QFAA", "G3", 256),
171 NRF5_DEVICE_DEF(0x004C, "51822", "QFAB", "B0", 128),
172 NRF5_DEVICE_DEF(0x0040, "51822", "CEAA", "CA0", 256),
173 NRF5_DEVICE_DEF(0x0047, "51822", "CEAA", "DA0", 256),
174 NRF5_DEVICE_DEF(0x004D, "51822", "CEAA", "D00", 256),
176 /* nRF51822 Devices (IC rev 3). */
177 NRF5_DEVICE_DEF(0x0072, "51822", "QFAA", "H0", 256),
178 NRF5_DEVICE_DEF(0x00D1, "51822", "QFAA", "H2", 256),
179 NRF5_DEVICE_DEF(0x007B, "51822", "QFAB", "C0", 128),
180 NRF5_DEVICE_DEF(0x0083, "51822", "QFAC", "A0", 256),
181 NRF5_DEVICE_DEF(0x0084, "51822", "QFAC", "A1", 256),
182 NRF5_DEVICE_DEF(0x007D, "51822", "CDAB", "A0", 128),
183 NRF5_DEVICE_DEF(0x0079, "51822", "CEAA", "E0", 256),
184 NRF5_DEVICE_DEF(0x0087, "51822", "CFAC", "A0", 256),
185 NRF5_DEVICE_DEF(0x008F, "51822", "QFAA", "H1", 256),
187 /* nRF51422 Devices (IC rev 1). */
188 NRF5_DEVICE_DEF(0x001E, "51422", "QFAA", "CA", 256),
189 NRF5_DEVICE_DEF(0x0024, "51422", "QFAA", "C0", 256),
190 NRF5_DEVICE_DEF(0x0031, "51422", "CEAA", "A0A", 256),
192 /* nRF51422 Devices (IC rev 2). */
193 NRF5_DEVICE_DEF(0x002D, "51422", "QFAA", "DAA", 256),
194 NRF5_DEVICE_DEF(0x002E, "51422", "QFAA", "E0", 256),
195 NRF5_DEVICE_DEF(0x0061, "51422", "QFAB", "A00", 128),
196 NRF5_DEVICE_DEF(0x0050, "51422", "CEAA", "B0", 256),
198 /* nRF51422 Devices (IC rev 3). */
199 NRF5_DEVICE_DEF(0x0073, "51422", "QFAA", "F0", 256),
200 NRF5_DEVICE_DEF(0x007C, "51422", "QFAB", "B0", 128),
201 NRF5_DEVICE_DEF(0x0085, "51422", "QFAC", "A0", 256),
202 NRF5_DEVICE_DEF(0x0086, "51422", "QFAC", "A1", 256),
203 NRF5_DEVICE_DEF(0x007E, "51422", "CDAB", "A0", 128),
204 NRF5_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
205 NRF5_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
207 /* nRF52832 Devices */
208 NRF5_DEVICE_DEF(0x00C7, "52832", "QFAA", "B0", 512),
209 NRF5_DEVICE_DEF(0x0139, "52832", "QFAA", "E0", 512),
212 static int nrf5_bank_is_probed(struct flash_bank
*bank
)
214 struct nrf5_info
*chip
= bank
->driver_priv
;
216 assert(chip
!= NULL
);
218 return chip
->bank
[bank
->bank_number
].probed
;
220 static int nrf5_probe(struct flash_bank
*bank
);
222 static int nrf5_get_probed_chip_if_halted(struct flash_bank
*bank
, struct nrf5_info
**chip
)
224 if (bank
->target
->state
!= TARGET_HALTED
) {
225 LOG_ERROR("Target not halted");
226 return ERROR_TARGET_NOT_HALTED
;
229 *chip
= bank
->driver_priv
;
231 int probed
= nrf5_bank_is_probed(bank
);
235 return nrf5_probe(bank
);
240 static int nrf5_wait_for_nvmc(struct nrf5_info
*chip
)
244 int timeout_ms
= 200;
245 int64_t ts_start
= timeval_ms();
248 res
= target_read_u32(chip
->target
, NRF5_NVMC_READY
, &ready
);
249 if (res
!= ERROR_OK
) {
250 LOG_ERROR("Couldn't read NVMC_READY register");
254 if (ready
== 0x00000001)
259 } while ((timeval_ms()-ts_start
) < timeout_ms
);
261 LOG_DEBUG("Timed out waiting for NVMC_READY");
262 return ERROR_FLASH_BUSY
;
265 static int nrf5_nvmc_erase_enable(struct nrf5_info
*chip
)
268 res
= target_write_u32(chip
->target
,
270 NRF5_NVMC_CONFIG_EEN
);
272 if (res
!= ERROR_OK
) {
273 LOG_ERROR("Failed to enable erase operation");
278 According to NVMC examples in Nordic SDK busy status must be
279 checked after writing to NVMC_CONFIG
281 res
= nrf5_wait_for_nvmc(chip
);
283 LOG_ERROR("Erase enable did not complete");
288 static int nrf5_nvmc_write_enable(struct nrf5_info
*chip
)
291 res
= target_write_u32(chip
->target
,
293 NRF5_NVMC_CONFIG_WEN
);
295 if (res
!= ERROR_OK
) {
296 LOG_ERROR("Failed to enable write operation");
301 According to NVMC examples in Nordic SDK busy status must be
302 checked after writing to NVMC_CONFIG
304 res
= nrf5_wait_for_nvmc(chip
);
306 LOG_ERROR("Write enable did not complete");
311 static int nrf5_nvmc_read_only(struct nrf5_info
*chip
)
314 res
= target_write_u32(chip
->target
,
316 NRF5_NVMC_CONFIG_REN
);
318 if (res
!= ERROR_OK
) {
319 LOG_ERROR("Failed to enable read-only operation");
323 According to NVMC examples in Nordic SDK busy status must be
324 checked after writing to NVMC_CONFIG
326 res
= nrf5_wait_for_nvmc(chip
);
328 LOG_ERROR("Read only enable did not complete");
333 static int nrf5_nvmc_generic_erase(struct nrf5_info
*chip
,
334 uint32_t erase_register
, uint32_t erase_value
)
338 res
= nrf5_nvmc_erase_enable(chip
);
342 res
= target_write_u32(chip
->target
,
348 res
= nrf5_wait_for_nvmc(chip
);
352 return nrf5_nvmc_read_only(chip
);
355 nrf5_nvmc_read_only(chip
);
357 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32
" val: 0x%08"PRIx32
,
358 erase_register
, erase_value
);
362 static int nrf5_protect_check(struct flash_bank
*bank
)
367 /* UICR cannot be write protected so just return early */
368 if (bank
->base
== NRF5_UICR_BASE
)
371 struct nrf5_info
*chip
= bank
->driver_priv
;
373 assert(chip
!= NULL
);
375 res
= target_read_u32(chip
->target
, NRF5_FICR_CLENR0
,
377 if (res
!= ERROR_OK
) {
378 LOG_ERROR("Couldn't read code region 0 size[FICR]");
382 if (clenr0
== 0xFFFFFFFF) {
383 res
= target_read_u32(chip
->target
, NRF5_UICR_CLENR0
,
385 if (res
!= ERROR_OK
) {
386 LOG_ERROR("Couldn't read code region 0 size[UICR]");
391 for (int i
= 0; i
< bank
->num_sectors
; i
++)
392 bank
->sectors
[i
].is_protected
=
393 clenr0
!= 0xFFFFFFFF && bank
->sectors
[i
].offset
< clenr0
;
398 static int nrf5_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
401 uint32_t clenr0
, ppfc
;
402 struct nrf5_info
*chip
;
404 /* UICR cannot be write protected so just bail out early */
405 if (bank
->base
== NRF5_UICR_BASE
)
408 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
413 LOG_ERROR("Code region 0 must start at the begining of the bank");
417 res
= target_read_u32(chip
->target
, NRF5_FICR_PPFC
,
419 if (res
!= ERROR_OK
) {
420 LOG_ERROR("Couldn't read PPFC register");
424 if ((ppfc
& 0xFF) == 0x00) {
425 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
429 res
= target_read_u32(chip
->target
, NRF5_UICR_CLENR0
,
431 if (res
!= ERROR_OK
) {
432 LOG_ERROR("Couldn't read code region 0 size[UICR]");
436 if (clenr0
== 0xFFFFFFFF) {
437 res
= target_write_u32(chip
->target
, NRF5_UICR_CLENR0
,
439 if (res
!= ERROR_OK
) {
440 LOG_ERROR("Couldn't write code region 0 size[UICR]");
445 LOG_ERROR("You need to perform chip erase before changing the protection settings");
448 nrf5_protect_check(bank
);
453 static int nrf5_probe(struct flash_bank
*bank
)
457 struct nrf5_info
*chip
= bank
->driver_priv
;
459 res
= target_read_u32(chip
->target
, NRF5_FICR_CONFIGID
, &hwid
);
460 if (res
!= ERROR_OK
) {
461 LOG_ERROR("Couldn't read CONFIGID register");
465 hwid
&= 0xFFFF; /* HWID is stored in the lower two
466 * bytes of the CONFIGID register */
468 const struct nrf5_device_spec
*spec
= NULL
;
469 for (size_t i
= 0; i
< ARRAY_SIZE(nrf5_known_devices_table
); i
++) {
470 if (hwid
== nrf5_known_devices_table
[i
].hwid
) {
471 spec
= &nrf5_known_devices_table
[i
];
476 if (!chip
->bank
[0].probed
&& !chip
->bank
[1].probed
) {
478 LOG_INFO("nRF%s-%s(build code: %s) %ukB Flash",
479 spec
->part
, spec
->variant
, spec
->build_code
,
480 spec
->flash_size_kb
);
482 LOG_WARNING("Unknown device (HWID 0x%08" PRIx32
")", hwid
);
485 if (bank
->base
== NRF5_FLASH_BASE
) {
486 /* The value stored in NRF5_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
487 res
= target_read_u32(chip
->target
, NRF5_FICR_CODEPAGESIZE
,
488 &chip
->code_page_size
);
489 if (res
!= ERROR_OK
) {
490 LOG_ERROR("Couldn't read code page size");
494 /* Note the register name is misleading,
495 * NRF5_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */
496 uint32_t num_sectors
;
497 res
= target_read_u32(chip
->target
, NRF5_FICR_CODESIZE
, &num_sectors
);
498 if (res
!= ERROR_OK
) {
499 LOG_ERROR("Couldn't read code memory size");
503 bank
->num_sectors
= num_sectors
;
504 bank
->size
= num_sectors
* chip
->code_page_size
;
506 if (spec
&& bank
->size
/ 1024 != spec
->flash_size_kb
)
507 LOG_WARNING("Chip's reported Flash capacity does not match expected one");
509 bank
->sectors
= calloc(bank
->num_sectors
,
510 sizeof((bank
->sectors
)[0]));
512 return ERROR_FLASH_BANK_NOT_PROBED
;
514 /* Fill out the sector information: all NRF5 sectors are the same size and
515 * there is always a fixed number of them. */
516 for (int i
= 0; i
< bank
->num_sectors
; i
++) {
517 bank
->sectors
[i
].size
= chip
->code_page_size
;
518 bank
->sectors
[i
].offset
= i
* chip
->code_page_size
;
520 /* mark as unknown */
521 bank
->sectors
[i
].is_erased
= -1;
522 bank
->sectors
[i
].is_protected
= -1;
525 nrf5_protect_check(bank
);
527 chip
->bank
[0].probed
= true;
529 bank
->size
= NRF5_UICR_SIZE
;
530 bank
->num_sectors
= 1;
531 bank
->sectors
= calloc(bank
->num_sectors
,
532 sizeof((bank
->sectors
)[0]));
534 return ERROR_FLASH_BANK_NOT_PROBED
;
536 bank
->sectors
[0].size
= bank
->size
;
537 bank
->sectors
[0].offset
= 0;
539 bank
->sectors
[0].is_erased
= 0;
540 bank
->sectors
[0].is_protected
= 0;
542 chip
->bank
[1].probed
= true;
548 static int nrf5_auto_probe(struct flash_bank
*bank
)
550 int probed
= nrf5_bank_is_probed(bank
);
557 return nrf5_probe(bank
);
560 static int nrf5_erase_all(struct nrf5_info
*chip
)
562 LOG_DEBUG("Erasing all non-volatile memory");
563 return nrf5_nvmc_generic_erase(chip
,
568 static int nrf5_erase_page(struct flash_bank
*bank
,
569 struct nrf5_info
*chip
,
570 struct flash_sector
*sector
)
574 LOG_DEBUG("Erasing page at 0x%"PRIx32
, sector
->offset
);
575 if (sector
->is_protected
) {
576 LOG_ERROR("Cannot erase protected sector at 0x%" PRIx32
, sector
->offset
);
580 if (bank
->base
== NRF5_UICR_BASE
) {
582 res
= target_read_u32(chip
->target
, NRF5_FICR_PPFC
,
584 if (res
!= ERROR_OK
) {
585 LOG_ERROR("Couldn't read PPFC register");
589 if ((ppfc
& 0xFF) == 0xFF) {
590 /* We can't erase the UICR. Double-check to
591 see if it's already erased before complaining. */
592 default_flash_blank_check(bank
);
593 if (sector
->is_erased
== 1)
596 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
600 res
= nrf5_nvmc_generic_erase(chip
,
606 res
= nrf5_nvmc_generic_erase(chip
,
614 static const uint8_t nrf5_flash_write_code
[] = {
615 /* See contrib/loaders/flash/cortex-m0.S */
617 0x0d, 0x68, /* ldr r5, [r1, #0] */
618 0x00, 0x2d, /* cmp r5, #0 */
619 0x0b, 0xd0, /* beq.n 1e <exit> */
620 0x4c, 0x68, /* ldr r4, [r1, #4] */
621 0xac, 0x42, /* cmp r4, r5 */
622 0xf9, 0xd0, /* beq.n 0 <wait_fifo> */
623 0x20, 0xcc, /* ldmia r4!, {r5} */
624 0x20, 0xc3, /* stmia r3!, {r5} */
625 0x94, 0x42, /* cmp r4, r2 */
626 0x01, 0xd3, /* bcc.n 18 <no_wrap> */
627 0x0c, 0x46, /* mov r4, r1 */
628 0x08, 0x34, /* adds r4, #8 */
630 0x4c, 0x60, /* str r4, [r1, #4] */
631 0x04, 0x38, /* subs r0, #4 */
632 0xf0, 0xd1, /* bne.n 0 <wait_fifo> */
634 0x00, 0xbe /* bkpt 0x0000 */
638 /* Start a low level flash write for the specified region */
639 static int nrf5_ll_flash_write(struct nrf5_info
*chip
, uint32_t offset
, const uint8_t *buffer
, uint32_t bytes
)
641 struct target
*target
= chip
->target
;
642 uint32_t buffer_size
= 8192;
643 struct working_area
*write_algorithm
;
644 struct working_area
*source
;
645 uint32_t address
= NRF5_FLASH_BASE
+ offset
;
646 struct reg_param reg_params
[4];
647 struct armv7m_algorithm armv7m_info
;
648 int retval
= ERROR_OK
;
651 LOG_DEBUG("Writing buffer to flash offset=0x%"PRIx32
" bytes=0x%"PRIx32
, offset
, bytes
);
652 assert(bytes
% 4 == 0);
654 /* allocate working area with flash programming code */
655 if (target_alloc_working_area(target
, sizeof(nrf5_flash_write_code
),
656 &write_algorithm
) != ERROR_OK
) {
657 LOG_WARNING("no working area available, falling back to slow memory writes");
659 for (; bytes
> 0; bytes
-= 4) {
660 retval
= target_write_memory(chip
->target
, offset
, 4, 1, buffer
);
661 if (retval
!= ERROR_OK
)
664 retval
= nrf5_wait_for_nvmc(chip
);
665 if (retval
!= ERROR_OK
)
675 LOG_WARNING("using fast async flash loader. This is currently supported");
676 LOG_WARNING("only with ST-Link and CMSIS-DAP. If you have issues, add");
677 LOG_WARNING("\"set WORKAREASIZE 0\" before sourcing nrf51.cfg/nrf52.cfg to disable it");
679 retval
= target_write_buffer(target
, write_algorithm
->address
,
680 sizeof(nrf5_flash_write_code
),
681 nrf5_flash_write_code
);
682 if (retval
!= ERROR_OK
)
686 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
) {
688 buffer_size
&= ~3UL; /* Make sure it's 4 byte aligned */
689 if (buffer_size
<= 256) {
690 /* free working area, write algorithm already allocated */
691 target_free_working_area(target
, write_algorithm
);
693 LOG_WARNING("No large enough working area available, can't do block memory writes");
694 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
698 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
699 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
701 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* byte count */
702 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer start */
703 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* buffer end */
704 init_reg_param(®_params
[3], "r3", 32, PARAM_IN_OUT
); /* target address */
706 buf_set_u32(reg_params
[0].value
, 0, 32, bytes
);
707 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
);
708 buf_set_u32(reg_params
[2].value
, 0, 32, source
->address
+ source
->size
);
709 buf_set_u32(reg_params
[3].value
, 0, 32, address
);
711 retval
= target_run_flash_async_algorithm(target
, buffer
, bytes
/4, 4,
714 source
->address
, source
->size
,
715 write_algorithm
->address
, 0,
718 target_free_working_area(target
, source
);
719 target_free_working_area(target
, write_algorithm
);
721 destroy_reg_param(®_params
[0]);
722 destroy_reg_param(®_params
[1]);
723 destroy_reg_param(®_params
[2]);
724 destroy_reg_param(®_params
[3]);
729 /* Check and erase flash sectors in specified range then start a low level page write.
730 start/end must be sector aligned.
732 static int nrf5_write_pages(struct flash_bank
*bank
, uint32_t start
, uint32_t end
, const uint8_t *buffer
)
734 int res
= ERROR_FAIL
;
735 struct nrf5_info
*chip
= bank
->driver_priv
;
737 assert(start
% chip
->code_page_size
== 0);
738 assert(end
% chip
->code_page_size
== 0);
740 res
= nrf5_nvmc_write_enable(chip
);
744 res
= nrf5_ll_flash_write(chip
, start
, buffer
, (end
- start
));
748 return nrf5_nvmc_read_only(chip
);
751 nrf5_nvmc_read_only(chip
);
752 LOG_ERROR("Failed to write to nrf5 flash");
756 static int nrf5_erase(struct flash_bank
*bank
, int first
, int last
)
759 struct nrf5_info
*chip
;
761 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
765 /* For each sector to be erased */
766 for (int s
= first
; s
<= last
&& res
== ERROR_OK
; s
++)
767 res
= nrf5_erase_page(bank
, chip
, &bank
->sectors
[s
]);
772 static int nrf5_code_flash_write(struct flash_bank
*bank
,
773 struct nrf5_info
*chip
,
774 const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
778 /* Need to perform reads to fill any gaps we need to preserve in the first page,
779 before the start of buffer, or in the last page, after the end of buffer */
780 uint32_t first_page
= offset
/chip
->code_page_size
;
781 uint32_t last_page
= DIV_ROUND_UP(offset
+count
, chip
->code_page_size
);
783 uint32_t first_page_offset
= first_page
* chip
->code_page_size
;
784 uint32_t last_page_offset
= last_page
* chip
->code_page_size
;
786 LOG_DEBUG("Padding write from 0x%08"PRIx32
"-0x%08"PRIx32
" as 0x%08"PRIx32
"-0x%08"PRIx32
,
787 offset
, offset
+count
, first_page_offset
, last_page_offset
);
789 uint32_t page_cnt
= last_page
- first_page
;
790 uint8_t buffer_to_flash
[page_cnt
*chip
->code_page_size
];
792 /* Fill in any space between start of first page and start of buffer */
793 uint32_t pre
= offset
- first_page_offset
;
795 res
= target_read_memory(bank
->target
,
804 /* Fill in main contents of buffer */
805 memcpy(buffer_to_flash
+pre
, buffer
, count
);
807 /* Fill in any space between end of buffer and end of last page */
808 uint32_t post
= last_page_offset
- (offset
+count
);
810 /* Retrieve the full row contents from Flash */
811 res
= target_read_memory(bank
->target
,
815 buffer_to_flash
+pre
+count
);
820 return nrf5_write_pages(bank
, first_page_offset
, last_page_offset
, buffer_to_flash
);
823 static int nrf5_uicr_flash_write(struct flash_bank
*bank
,
824 struct nrf5_info
*chip
,
825 const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
828 uint8_t uicr
[NRF5_UICR_SIZE
];
829 struct flash_sector
*sector
= &bank
->sectors
[0];
831 if ((offset
+ count
) > NRF5_UICR_SIZE
)
834 res
= target_read_memory(bank
->target
,
843 res
= nrf5_erase_page(bank
, chip
, sector
);
847 res
= nrf5_nvmc_write_enable(chip
);
851 memcpy(&uicr
[offset
], buffer
, count
);
853 res
= nrf5_ll_flash_write(chip
, NRF5_UICR_BASE
, uicr
, NRF5_UICR_SIZE
);
854 if (res
!= ERROR_OK
) {
855 nrf5_nvmc_read_only(chip
);
859 return nrf5_nvmc_read_only(chip
);
863 static int nrf5_write(struct flash_bank
*bank
, const uint8_t *buffer
,
864 uint32_t offset
, uint32_t count
)
867 struct nrf5_info
*chip
;
869 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
873 return chip
->bank
[bank
->bank_number
].write(bank
, chip
, buffer
, offset
, count
);
876 static void nrf5_free_driver_priv(struct flash_bank
*bank
)
878 struct nrf5_info
*chip
= bank
->driver_priv
;
883 if (chip
->refcount
== 0) {
885 bank
->driver_priv
= NULL
;
889 FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command
)
891 static struct nrf5_info
*chip
;
893 switch (bank
->base
) {
894 case NRF5_FLASH_BASE
:
895 bank
->bank_number
= 0;
898 bank
->bank_number
= 1;
901 LOG_ERROR("Invalid bank address 0x%08" PRIx32
, bank
->base
);
906 /* Create a new chip */
907 chip
= calloc(1, sizeof(*chip
));
911 chip
->target
= bank
->target
;
914 switch (bank
->base
) {
915 case NRF5_FLASH_BASE
:
916 chip
->bank
[bank
->bank_number
].write
= nrf5_code_flash_write
;
919 chip
->bank
[bank
->bank_number
].write
= nrf5_uicr_flash_write
;
924 chip
->bank
[bank
->bank_number
].probed
= false;
925 bank
->driver_priv
= chip
;
930 COMMAND_HANDLER(nrf5_handle_mass_erase_command
)
933 struct flash_bank
*bank
= NULL
;
934 struct target
*target
= get_current_target(CMD_CTX
);
936 res
= get_flash_bank_by_addr(target
, NRF5_FLASH_BASE
, true, &bank
);
940 assert(bank
!= NULL
);
942 struct nrf5_info
*chip
;
944 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
950 res
= target_read_u32(target
, NRF5_FICR_PPFC
,
952 if (res
!= ERROR_OK
) {
953 LOG_ERROR("Couldn't read PPFC register");
957 if ((ppfc
& 0xFF) == 0x00) {
958 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
959 "mass erase command won't work.");
963 res
= nrf5_erase_all(chip
);
964 if (res
!= ERROR_OK
) {
965 LOG_ERROR("Failed to erase the chip");
966 nrf5_protect_check(bank
);
970 res
= nrf5_protect_check(bank
);
971 if (res
!= ERROR_OK
) {
972 LOG_ERROR("Failed to check chip's write protection");
976 res
= get_flash_bank_by_addr(target
, NRF5_UICR_BASE
, true, &bank
);
983 static int nrf5_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
987 struct nrf5_info
*chip
;
989 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
994 const uint32_t address
;
997 { .address
= NRF5_FICR_CODEPAGESIZE
},
998 { .address
= NRF5_FICR_CODESIZE
},
999 { .address
= NRF5_FICR_CLENR0
},
1000 { .address
= NRF5_FICR_PPFC
},
1001 { .address
= NRF5_FICR_NUMRAMBLOCK
},
1002 { .address
= NRF5_FICR_SIZERAMBLOCK0
},
1003 { .address
= NRF5_FICR_SIZERAMBLOCK1
},
1004 { .address
= NRF5_FICR_SIZERAMBLOCK2
},
1005 { .address
= NRF5_FICR_SIZERAMBLOCK3
},
1006 { .address
= NRF5_FICR_CONFIGID
},
1007 { .address
= NRF5_FICR_DEVICEID0
},
1008 { .address
= NRF5_FICR_DEVICEID1
},
1009 { .address
= NRF5_FICR_ER0
},
1010 { .address
= NRF5_FICR_ER1
},
1011 { .address
= NRF5_FICR_ER2
},
1012 { .address
= NRF5_FICR_ER3
},
1013 { .address
= NRF5_FICR_IR0
},
1014 { .address
= NRF5_FICR_IR1
},
1015 { .address
= NRF5_FICR_IR2
},
1016 { .address
= NRF5_FICR_IR3
},
1017 { .address
= NRF5_FICR_DEVICEADDRTYPE
},
1018 { .address
= NRF5_FICR_DEVICEADDR0
},
1019 { .address
= NRF5_FICR_DEVICEADDR1
},
1020 { .address
= NRF5_FICR_OVERRIDEN
},
1021 { .address
= NRF5_FICR_NRF_1MBIT0
},
1022 { .address
= NRF5_FICR_NRF_1MBIT1
},
1023 { .address
= NRF5_FICR_NRF_1MBIT2
},
1024 { .address
= NRF5_FICR_NRF_1MBIT3
},
1025 { .address
= NRF5_FICR_NRF_1MBIT4
},
1026 { .address
= NRF5_FICR_BLE_1MBIT0
},
1027 { .address
= NRF5_FICR_BLE_1MBIT1
},
1028 { .address
= NRF5_FICR_BLE_1MBIT2
},
1029 { .address
= NRF5_FICR_BLE_1MBIT3
},
1030 { .address
= NRF5_FICR_BLE_1MBIT4
},
1032 { .address
= NRF5_UICR_CLENR0
, },
1033 { .address
= NRF5_UICR_RBPCONF
},
1034 { .address
= NRF5_UICR_XTALFREQ
},
1035 { .address
= NRF5_UICR_FWID
},
1038 for (size_t i
= 0; i
< ARRAY_SIZE(ficr
); i
++) {
1039 res
= target_read_u32(chip
->target
, ficr
[i
].address
,
1041 if (res
!= ERROR_OK
) {
1042 LOG_ERROR("Couldn't read %" PRIx32
, ficr
[i
].address
);
1047 for (size_t i
= 0; i
< ARRAY_SIZE(uicr
); i
++) {
1048 res
= target_read_u32(chip
->target
, uicr
[i
].address
,
1050 if (res
!= ERROR_OK
) {
1051 LOG_ERROR("Couldn't read %" PRIx32
, uicr
[i
].address
);
1056 snprintf(buf
, buf_size
,
1057 "\n[factory information control block]\n\n"
1058 "code page size: %"PRIu32
"B\n"
1059 "code memory size: %"PRIu32
"kB\n"
1060 "code region 0 size: %"PRIu32
"kB\n"
1061 "pre-programmed code: %s\n"
1062 "number of ram blocks: %"PRIu32
"\n"
1063 "ram block 0 size: %"PRIu32
"B\n"
1064 "ram block 1 size: %"PRIu32
"B\n"
1065 "ram block 2 size: %"PRIu32
"B\n"
1066 "ram block 3 size: %"PRIu32
"B\n"
1067 "config id: %" PRIx32
"\n"
1068 "device id: 0x%"PRIx32
"%08"PRIx32
"\n"
1069 "encryption root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1070 "identity root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1071 "device address type: 0x%"PRIx32
"\n"
1072 "device address: 0x%"PRIx32
"%08"PRIx32
"\n"
1073 "override enable: %"PRIx32
"\n"
1074 "NRF_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1075 "BLE_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1076 "\n[user information control block]\n\n"
1077 "code region 0 size: %"PRIu32
"kB\n"
1078 "read back protection configuration: %"PRIx32
"\n"
1079 "reset value for XTALFREQ: %"PRIx32
"\n"
1080 "firmware id: 0x%04"PRIx32
,
1082 (ficr
[1].value
* ficr
[0].value
) / 1024,
1083 (ficr
[2].value
== 0xFFFFFFFF) ? 0 : ficr
[2].value
/ 1024,
1084 ((ficr
[3].value
& 0xFF) == 0x00) ? "present" : "not present",
1087 (ficr
[6].value
== 0xFFFFFFFF) ? 0 : ficr
[6].value
,
1088 (ficr
[7].value
== 0xFFFFFFFF) ? 0 : ficr
[7].value
,
1089 (ficr
[8].value
== 0xFFFFFFFF) ? 0 : ficr
[8].value
,
1091 ficr
[10].value
, ficr
[11].value
,
1092 ficr
[12].value
, ficr
[13].value
, ficr
[14].value
, ficr
[15].value
,
1093 ficr
[16].value
, ficr
[17].value
, ficr
[18].value
, ficr
[19].value
,
1095 ficr
[21].value
, ficr
[22].value
,
1097 ficr
[24].value
, ficr
[25].value
, ficr
[26].value
, ficr
[27].value
, ficr
[28].value
,
1098 ficr
[29].value
, ficr
[30].value
, ficr
[31].value
, ficr
[32].value
, ficr
[33].value
,
1099 (uicr
[0].value
== 0xFFFFFFFF) ? 0 : uicr
[0].value
/ 1024,
1100 uicr
[1].value
& 0xFFFF,
1101 uicr
[2].value
& 0xFF,
1102 uicr
[3].value
& 0xFFFF);
1107 static const struct command_registration nrf5_exec_command_handlers
[] = {
1109 .name
= "mass_erase",
1110 .handler
= nrf5_handle_mass_erase_command
,
1111 .mode
= COMMAND_EXEC
,
1112 .help
= "Erase all flash contents of the chip.",
1114 COMMAND_REGISTRATION_DONE
1117 static const struct command_registration nrf5_command_handlers
[] = {
1120 .mode
= COMMAND_ANY
,
1121 .help
= "nrf5 flash command group",
1123 .chain
= nrf5_exec_command_handlers
,
1127 .mode
= COMMAND_ANY
,
1128 .help
= "nrf51 flash command group",
1130 .chain
= nrf5_exec_command_handlers
,
1132 COMMAND_REGISTRATION_DONE
1135 struct flash_driver nrf5_flash
= {
1137 .commands
= nrf5_command_handlers
,
1138 .flash_bank_command
= nrf5_flash_bank_command
,
1140 .erase
= nrf5_erase
,
1141 .protect
= nrf5_protect
,
1142 .write
= nrf5_write
,
1143 .read
= default_flash_read
,
1144 .probe
= nrf5_probe
,
1145 .auto_probe
= nrf5_auto_probe
,
1146 .erase_check
= default_flash_blank_check
,
1147 .protect_check
= nrf5_protect_check
,
1148 .free_driver_priv
= nrf5_free_driver_priv
,
1151 /* We need to retain the flash-driver name as well as the commands
1152 * for backwards compatability */
1153 struct flash_driver nrf51_flash
= {
1155 .commands
= nrf5_command_handlers
,
1156 .flash_bank_command
= nrf5_flash_bank_command
,
1158 .erase
= nrf5_erase
,
1159 .protect
= nrf5_protect
,
1160 .write
= nrf5_write
,
1161 .read
= default_flash_read
,
1162 .probe
= nrf5_probe
,
1163 .auto_probe
= nrf5_auto_probe
,
1164 .erase_check
= default_flash_blank_check
,
1165 .protect_check
= nrf5_protect_check
,
1166 .free_driver_priv
= nrf5_free_driver_priv
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)