1 /***************************************************************************
2 * Copyright (C) 2013 Synapse Product Development *
3 * Andrey Smirnov <andrew.smironv@gmail.com> *
4 * Angus Gratton <gus@projectgus.com> *
5 * Erdem U. Altunyurt <spamjunkeater@gmail.com> *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
19 ***************************************************************************/
26 #include <helper/binarybuffer.h>
27 #include <target/algorithm.h>
28 #include <target/armv7m.h>
29 #include <helper/types.h>
30 #include <helper/time_support.h>
32 /* Both those values are constant across the current spectrum ofr nRF5 devices */
33 #define WATCHDOG_REFRESH_REGISTER 0x40010600
34 #define WATCHDOG_REFRESH_VALUE 0x6e524635
37 NRF5_FLASH_BASE
= 0x00000000,
40 enum nrf5_ficr_registers
{
41 NRF5_FICR_BASE
= 0x10000000, /* Factory Information Configuration Registers */
43 #define NRF5_FICR_REG(offset) (NRF5_FICR_BASE + offset)
45 NRF5_FICR_CODEPAGESIZE
= NRF5_FICR_REG(0x010),
46 NRF5_FICR_CODESIZE
= NRF5_FICR_REG(0x014),
48 NRF51_FICR_CLENR0
= NRF5_FICR_REG(0x028),
49 NRF51_FICR_PPFC
= NRF5_FICR_REG(0x02C),
50 NRF51_FICR_NUMRAMBLOCK
= NRF5_FICR_REG(0x034),
51 NRF51_FICR_SIZERAMBLOCK0
= NRF5_FICR_REG(0x038),
52 NRF51_FICR_SIZERAMBLOCK1
= NRF5_FICR_REG(0x03C),
53 NRF51_FICR_SIZERAMBLOCK2
= NRF5_FICR_REG(0x040),
54 NRF51_FICR_SIZERAMBLOCK3
= NRF5_FICR_REG(0x044),
56 NRF5_FICR_CONFIGID
= NRF5_FICR_REG(0x05C),
57 NRF5_FICR_DEVICEID0
= NRF5_FICR_REG(0x060),
58 NRF5_FICR_DEVICEID1
= NRF5_FICR_REG(0x064),
59 NRF5_FICR_ER0
= NRF5_FICR_REG(0x080),
60 NRF5_FICR_ER1
= NRF5_FICR_REG(0x084),
61 NRF5_FICR_ER2
= NRF5_FICR_REG(0x088),
62 NRF5_FICR_ER3
= NRF5_FICR_REG(0x08C),
63 NRF5_FICR_IR0
= NRF5_FICR_REG(0x090),
64 NRF5_FICR_IR1
= NRF5_FICR_REG(0x094),
65 NRF5_FICR_IR2
= NRF5_FICR_REG(0x098),
66 NRF5_FICR_IR3
= NRF5_FICR_REG(0x09C),
67 NRF5_FICR_DEVICEADDRTYPE
= NRF5_FICR_REG(0x0A0),
68 NRF5_FICR_DEVICEADDR0
= NRF5_FICR_REG(0x0A4),
69 NRF5_FICR_DEVICEADDR1
= NRF5_FICR_REG(0x0A8),
71 NRF51_FICR_OVERRIDEN
= NRF5_FICR_REG(0x0AC),
72 NRF51_FICR_NRF_1MBIT0
= NRF5_FICR_REG(0x0B0),
73 NRF51_FICR_NRF_1MBIT1
= NRF5_FICR_REG(0x0B4),
74 NRF51_FICR_NRF_1MBIT2
= NRF5_FICR_REG(0x0B8),
75 NRF51_FICR_NRF_1MBIT3
= NRF5_FICR_REG(0x0BC),
76 NRF51_FICR_NRF_1MBIT4
= NRF5_FICR_REG(0x0C0),
77 NRF51_FICR_BLE_1MBIT0
= NRF5_FICR_REG(0x0EC),
78 NRF51_FICR_BLE_1MBIT1
= NRF5_FICR_REG(0x0F0),
79 NRF51_FICR_BLE_1MBIT2
= NRF5_FICR_REG(0x0F4),
80 NRF51_FICR_BLE_1MBIT3
= NRF5_FICR_REG(0x0F8),
81 NRF51_FICR_BLE_1MBIT4
= NRF5_FICR_REG(0x0FC),
83 /* Following registers are available on nRF52 and on nRF51 since rev 3 */
84 NRF5_FICR_INFO_PART
= NRF5_FICR_REG(0x100),
85 NRF5_FICR_INFO_VARIANT
= NRF5_FICR_REG(0x104),
86 NRF5_FICR_INFO_PACKAGE
= NRF5_FICR_REG(0x108),
87 NRF5_FICR_INFO_RAM
= NRF5_FICR_REG(0x10C),
88 NRF5_FICR_INFO_FLASH
= NRF5_FICR_REG(0x110),
91 enum nrf5_uicr_registers
{
92 NRF5_UICR_BASE
= 0x10001000, /* User Information
93 * Configuration Registers */
95 #define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
97 NRF51_UICR_CLENR0
= NRF5_UICR_REG(0x000),
98 NRF51_UICR_RBPCONF
= NRF5_UICR_REG(0x004),
99 NRF51_UICR_XTALFREQ
= NRF5_UICR_REG(0x008),
100 NRF51_UICR_FWID
= NRF5_UICR_REG(0x010),
103 enum nrf5_nvmc_registers
{
104 NRF5_NVMC_BASE
= 0x4001E000, /* Non-Volatile Memory
105 * Controller Registers */
107 #define NRF5_NVMC_REG(offset) (NRF5_NVMC_BASE + offset)
109 NRF5_NVMC_READY
= NRF5_NVMC_REG(0x400),
110 NRF5_NVMC_CONFIG
= NRF5_NVMC_REG(0x504),
111 NRF5_NVMC_ERASEPAGE
= NRF5_NVMC_REG(0x508),
112 NRF5_NVMC_ERASEALL
= NRF5_NVMC_REG(0x50C),
113 NRF5_NVMC_ERASEUICR
= NRF5_NVMC_REG(0x514),
115 NRF5_BPROT_BASE
= 0x40000000,
118 enum nrf5_nvmc_config_bits
{
119 NRF5_NVMC_CONFIG_REN
= 0x00,
120 NRF5_NVMC_CONFIG_WEN
= 0x01,
121 NRF5_NVMC_CONFIG_EEN
= 0x02,
125 struct nrf52_ficr_info
{
134 NRF5_FEATURE_SERIES_51
= 1 << 0,
135 NRF5_FEATURE_SERIES_52
= 1 << 1,
136 NRF5_FEATURE_BPROT
= 1 << 2,
137 NRF5_FEATURE_ACL_PROT
= 1 << 3,
140 struct nrf5_device_spec
{
144 const char *build_code
;
145 unsigned int flash_size_kb
;
146 enum nrf5_features features
;
153 struct nrf5_info
*chip
;
156 struct target
*target
;
158 /* chip identification stored in nrf5_probe() for use in nrf5_info() */
159 bool ficr_info_valid
;
160 struct nrf52_ficr_info ficr_info
;
161 const struct nrf5_device_spec
*spec
;
163 enum nrf5_features features
;
164 unsigned int flash_size_kb
;
165 unsigned int ram_size_kb
;
168 #define NRF51_DEVICE_DEF(id, pt, var, bcode, fsize) \
173 .build_code = bcode, \
174 .flash_size_kb = (fsize), \
175 .features = NRF5_FEATURE_SERIES_51, \
178 #define NRF5_DEVICE_DEF(id, pt, var, bcode, fsize, features) \
183 .build_code = bcode, \
184 .flash_size_kb = (fsize), \
185 .features = features, \
188 /* The known devices table below is derived from the "nRF5x series
189 * compatibility matrix" documents, which can be found in the "DocLib" of
192 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51422_ic_revision_overview
193 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51822_ic_revision_overview
194 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51824_ic_revision_overview
195 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52810/latest/COMP/nrf52810/nRF52810_ic_revision_overview
196 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52832/latest/COMP/nrf52832/ic_revision_overview
197 * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52840/latest/COMP/nrf52840/nRF52840_ic_revision_overview
199 * Up to date with Matrix v2.0, plus some additional HWIDs.
201 * The additional HWIDs apply where the build code in the matrix is
202 * shown as Gx0, Bx0, etc. In these cases the HWID in the matrix is
203 * for x==0, x!=0 means different (unspecified) HWIDs.
205 static const struct nrf5_device_spec nrf5_known_devices_table
[] = {
206 /* nRF51822 Devices (IC rev 1). */
207 NRF51_DEVICE_DEF(0x001D, "51822", "QFAA", "CA/C0", 256),
208 NRF51_DEVICE_DEF(0x0026, "51822", "QFAB", "AA", 128),
209 NRF51_DEVICE_DEF(0x0027, "51822", "QFAB", "A0", 128),
210 NRF51_DEVICE_DEF(0x0020, "51822", "CEAA", "BA", 256),
211 NRF51_DEVICE_DEF(0x002F, "51822", "CEAA", "B0", 256),
213 /* Some early nRF51-DK (PCA10028) & nRF51-Dongle (PCA10031) boards
214 with built-in jlink seem to use engineering samples not listed
215 in the nRF51 Series Compatibility Matrix V1.0. */
216 NRF51_DEVICE_DEF(0x0071, "51822", "QFAC", "AB", 256),
218 /* nRF51822 Devices (IC rev 2). */
219 NRF51_DEVICE_DEF(0x002A, "51822", "QFAA", "FA0", 256),
220 NRF51_DEVICE_DEF(0x0044, "51822", "QFAA", "GC0", 256),
221 NRF51_DEVICE_DEF(0x003C, "51822", "QFAA", "G0", 256),
222 NRF51_DEVICE_DEF(0x0057, "51822", "QFAA", "G2", 256),
223 NRF51_DEVICE_DEF(0x0058, "51822", "QFAA", "G3", 256),
224 NRF51_DEVICE_DEF(0x004C, "51822", "QFAB", "B0", 128),
225 NRF51_DEVICE_DEF(0x0040, "51822", "CEAA", "CA0", 256),
226 NRF51_DEVICE_DEF(0x0047, "51822", "CEAA", "DA0", 256),
227 NRF51_DEVICE_DEF(0x004D, "51822", "CEAA", "D00", 256),
229 /* nRF51822 Devices (IC rev 3). */
230 NRF51_DEVICE_DEF(0x0072, "51822", "QFAA", "H0", 256),
231 NRF51_DEVICE_DEF(0x00D1, "51822", "QFAA", "H2", 256),
232 NRF51_DEVICE_DEF(0x007B, "51822", "QFAB", "C0", 128),
233 NRF51_DEVICE_DEF(0x0083, "51822", "QFAC", "A0", 256),
234 NRF51_DEVICE_DEF(0x0084, "51822", "QFAC", "A1", 256),
235 NRF51_DEVICE_DEF(0x007D, "51822", "CDAB", "A0", 128),
236 NRF51_DEVICE_DEF(0x0079, "51822", "CEAA", "E0", 256),
237 NRF51_DEVICE_DEF(0x0087, "51822", "CFAC", "A0", 256),
238 NRF51_DEVICE_DEF(0x008F, "51822", "QFAA", "H1", 256),
240 /* nRF51422 Devices (IC rev 1). */
241 NRF51_DEVICE_DEF(0x001E, "51422", "QFAA", "CA", 256),
242 NRF51_DEVICE_DEF(0x0024, "51422", "QFAA", "C0", 256),
243 NRF51_DEVICE_DEF(0x0031, "51422", "CEAA", "A0A", 256),
245 /* nRF51422 Devices (IC rev 2). */
246 NRF51_DEVICE_DEF(0x002D, "51422", "QFAA", "DAA", 256),
247 NRF51_DEVICE_DEF(0x002E, "51422", "QFAA", "E0", 256),
248 NRF51_DEVICE_DEF(0x0061, "51422", "QFAB", "A00", 128),
249 NRF51_DEVICE_DEF(0x0050, "51422", "CEAA", "B0", 256),
251 /* nRF51422 Devices (IC rev 3). */
252 NRF51_DEVICE_DEF(0x0073, "51422", "QFAA", "F0", 256),
253 NRF51_DEVICE_DEF(0x007C, "51422", "QFAB", "B0", 128),
254 NRF51_DEVICE_DEF(0x0085, "51422", "QFAC", "A0", 256),
255 NRF51_DEVICE_DEF(0x0086, "51422", "QFAC", "A1", 256),
256 NRF51_DEVICE_DEF(0x007E, "51422", "CDAB", "A0", 128),
257 NRF51_DEVICE_DEF(0x007A, "51422", "CEAA", "C0", 256),
258 NRF51_DEVICE_DEF(0x0088, "51422", "CFAC", "A0", 256),
260 /* The driver fully autodetects nRF52 series devices by FICR INFO,
261 * no need for nRF52xxx HWIDs in this table */
263 /* nRF52810 Devices */
264 NRF5_DEVICE_DEF(0x0142, "52810", "QFAA", "B0", 192, NRF5_FEATURE_SERIES_52
| NRF5_FEATURE_BPROT
),
265 NRF5_DEVICE_DEF(0x0143, "52810", "QCAA", "C0", 192, NRF5_FEATURE_SERIES_52
| NRF5_FEATURE_BPROT
),
267 /* nRF52832 Devices */
268 NRF5_DEVICE_DEF(0x00C7, "52832", "QFAA", "B0", 512, NRF5_FEATURE_SERIES_52
| NRF5_FEATURE_BPROT
),
269 NRF5_DEVICE_DEF(0x0139, "52832", "QFAA", "E0", 512, NRF5_FEATURE_SERIES_52
| NRF5_FEATURE_BPROT
),
270 NRF5_DEVICE_DEF(0x00E3, "52832", "CIAA", "B0", 512, NRF5_FEATURE_SERIES_52
| NRF5_FEATURE_BPROT
),
272 /* nRF52840 Devices */
273 NRF5_DEVICE_DEF(0x0150, "52840", "QIAA", "C0", 1024, NRF5_FEATURE_SERIES_52
| NRF5_FEATURE_ACL_PROT
),
277 struct nrf5_device_package
{
282 /* Newer devices have FICR INFO.PACKAGE.
283 * This table converts its value to two character code */
284 static const struct nrf5_device_package nrf5_packages_table
[] = {
291 const struct flash_driver nrf5_flash
, nrf51_flash
;
293 static bool nrf5_bank_is_probed(const struct flash_bank
*bank
)
295 struct nrf5_bank
*nbank
= bank
->driver_priv
;
299 return nbank
->probed
;
301 static int nrf5_probe(struct flash_bank
*bank
);
303 static int nrf5_get_probed_chip_if_halted(struct flash_bank
*bank
, struct nrf5_info
**chip
)
305 if (bank
->target
->state
!= TARGET_HALTED
) {
306 LOG_ERROR("Target not halted");
307 return ERROR_TARGET_NOT_HALTED
;
310 struct nrf5_bank
*nbank
= bank
->driver_priv
;
313 if (nrf5_bank_is_probed(bank
))
316 return nrf5_probe(bank
);
319 static int nrf5_wait_for_nvmc(struct nrf5_info
*chip
)
323 int timeout_ms
= 340;
324 int64_t ts_start
= timeval_ms();
327 res
= target_read_u32(chip
->target
, NRF5_NVMC_READY
, &ready
);
328 if (res
!= ERROR_OK
) {
329 LOG_ERROR("Error waiting NVMC_READY: generic flash write/erase error (check protection etc...)");
333 if (ready
== 0x00000001)
338 } while ((timeval_ms()-ts_start
) < timeout_ms
);
340 LOG_DEBUG("Timed out waiting for NVMC_READY");
341 return ERROR_FLASH_BUSY
;
344 static int nrf5_nvmc_erase_enable(struct nrf5_info
*chip
)
347 res
= target_write_u32(chip
->target
,
349 NRF5_NVMC_CONFIG_EEN
);
351 if (res
!= ERROR_OK
) {
352 LOG_ERROR("Failed to enable erase operation");
357 According to NVMC examples in Nordic SDK busy status must be
358 checked after writing to NVMC_CONFIG
360 res
= nrf5_wait_for_nvmc(chip
);
362 LOG_ERROR("Erase enable did not complete");
367 static int nrf5_nvmc_write_enable(struct nrf5_info
*chip
)
370 res
= target_write_u32(chip
->target
,
372 NRF5_NVMC_CONFIG_WEN
);
374 if (res
!= ERROR_OK
) {
375 LOG_ERROR("Failed to enable write operation");
380 According to NVMC examples in Nordic SDK busy status must be
381 checked after writing to NVMC_CONFIG
383 res
= nrf5_wait_for_nvmc(chip
);
385 LOG_ERROR("Write enable did not complete");
390 static int nrf5_nvmc_read_only(struct nrf5_info
*chip
)
393 res
= target_write_u32(chip
->target
,
395 NRF5_NVMC_CONFIG_REN
);
397 if (res
!= ERROR_OK
) {
398 LOG_ERROR("Failed to enable read-only operation");
402 According to NVMC examples in Nordic SDK busy status must be
403 checked after writing to NVMC_CONFIG
405 res
= nrf5_wait_for_nvmc(chip
);
407 LOG_ERROR("Read only enable did not complete");
412 static int nrf5_nvmc_generic_erase(struct nrf5_info
*chip
,
413 uint32_t erase_register
, uint32_t erase_value
)
417 res
= nrf5_nvmc_erase_enable(chip
);
421 res
= target_write_u32(chip
->target
,
427 res
= nrf5_wait_for_nvmc(chip
);
431 return nrf5_nvmc_read_only(chip
);
434 nrf5_nvmc_read_only(chip
);
436 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32
" val: 0x%08"PRIx32
,
437 erase_register
, erase_value
);
441 static int nrf5_protect_check_clenr0(struct flash_bank
*bank
)
445 struct nrf5_bank
*nbank
= bank
->driver_priv
;
446 struct nrf5_info
*chip
= nbank
->chip
;
450 res
= target_read_u32(chip
->target
, NRF51_FICR_CLENR0
,
452 if (res
!= ERROR_OK
) {
453 LOG_ERROR("Couldn't read code region 0 size[FICR]");
457 if (clenr0
== 0xFFFFFFFF) {
458 res
= target_read_u32(chip
->target
, NRF51_UICR_CLENR0
,
460 if (res
!= ERROR_OK
) {
461 LOG_ERROR("Couldn't read code region 0 size[UICR]");
466 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++)
467 bank
->sectors
[i
].is_protected
=
468 clenr0
!= 0xFFFFFFFF && bank
->sectors
[i
].offset
< clenr0
;
473 static int nrf5_protect_check_bprot(struct flash_bank
*bank
)
475 struct nrf5_bank
*nbank
= bank
->driver_priv
;
476 struct nrf5_info
*chip
= nbank
->chip
;
480 static uint32_t nrf5_bprot_offsets
[4] = { 0x600, 0x604, 0x610, 0x614 };
481 uint32_t bprot_reg
= 0;
484 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++) {
485 unsigned int bit
= i
% 32;
487 unsigned int n_reg
= i
/ 32;
488 if (n_reg
>= ARRAY_SIZE(nrf5_bprot_offsets
))
491 res
= target_read_u32(chip
->target
, NRF5_BPROT_BASE
+ nrf5_bprot_offsets
[n_reg
], &bprot_reg
);
495 bank
->sectors
[i
].is_protected
= (bprot_reg
& (1 << bit
)) ? 1 : 0;
500 static int nrf5_protect_check(struct flash_bank
*bank
)
502 /* UICR cannot be write protected so just return early */
503 if (bank
->base
== NRF5_UICR_BASE
)
506 struct nrf5_bank
*nbank
= bank
->driver_priv
;
507 struct nrf5_info
*chip
= nbank
->chip
;
511 if (chip
->features
& NRF5_FEATURE_BPROT
)
512 return nrf5_protect_check_bprot(bank
);
514 if (chip
->features
& NRF5_FEATURE_SERIES_51
)
515 return nrf5_protect_check_clenr0(bank
);
517 LOG_WARNING("Flash protection of this nRF device is not supported");
518 return ERROR_FLASH_OPER_UNSUPPORTED
;
521 static int nrf5_protect_clenr0(struct flash_bank
*bank
, int set
, unsigned int first
,
525 uint32_t clenr0
, ppfc
;
526 struct nrf5_bank
*nbank
= bank
->driver_priv
;
527 struct nrf5_info
*chip
= nbank
->chip
;
530 LOG_ERROR("Code region 0 must start at the beginning of the bank");
534 res
= target_read_u32(chip
->target
, NRF51_FICR_PPFC
,
536 if (res
!= ERROR_OK
) {
537 LOG_ERROR("Couldn't read PPFC register");
541 if ((ppfc
& 0xFF) == 0x00) {
542 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
546 res
= target_read_u32(chip
->target
, NRF51_UICR_CLENR0
,
548 if (res
!= ERROR_OK
) {
549 LOG_ERROR("Couldn't read code region 0 size from UICR");
553 if (!set
|| clenr0
!= 0xFFFFFFFF) {
554 LOG_ERROR("You need to perform chip erase before changing the protection settings");
558 res
= nrf5_nvmc_write_enable(chip
);
562 clenr0
= bank
->sectors
[last
].offset
+ bank
->sectors
[last
].size
;
563 res
= target_write_u32(chip
->target
, NRF51_UICR_CLENR0
, clenr0
);
565 int res2
= nrf5_wait_for_nvmc(chip
);
571 LOG_INFO("A reset or power cycle is required for the new protection settings to take effect.");
573 LOG_ERROR("Couldn't write code region 0 size to UICR");
576 nrf5_nvmc_read_only(chip
);
581 static int nrf5_protect(struct flash_bank
*bank
, int set
, unsigned int first
,
585 struct nrf5_info
*chip
;
587 /* UICR cannot be write protected so just bail out early */
588 if (bank
->base
== NRF5_UICR_BASE
) {
589 LOG_ERROR("UICR page does not support protection");
590 return ERROR_FLASH_OPER_UNSUPPORTED
;
593 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
597 if (chip
->features
& NRF5_FEATURE_SERIES_51
)
598 return nrf5_protect_clenr0(bank
, set
, first
, last
);
600 LOG_ERROR("Flash protection setting is not supported on this nRF5 device");
601 return ERROR_FLASH_OPER_UNSUPPORTED
;
604 static bool nrf5_info_variant_to_str(uint32_t variant
, char *bf
)
608 h_u32_to_be(b
, variant
);
609 if (isalnum(b
[0]) && isalnum(b
[1]) && isalnum(b
[2]) && isalnum(b
[3])) {
619 static const char *nrf5_decode_info_package(uint32_t package
)
621 for (size_t i
= 0; i
< ARRAY_SIZE(nrf5_packages_table
); i
++) {
622 if (nrf5_packages_table
[i
].package
== package
)
623 return nrf5_packages_table
[i
].code
;
628 static int get_nrf5_chip_type_str(const struct nrf5_info
*chip
, char *buf
, unsigned int buf_size
)
632 res
= snprintf(buf
, buf_size
, "nRF%s-%s(build code: %s)",
633 chip
->spec
->part
, chip
->spec
->variant
, chip
->spec
->build_code
);
634 } else if (chip
->ficr_info_valid
) {
636 nrf5_info_variant_to_str(chip
->ficr_info
.variant
, variant
);
637 res
= snprintf(buf
, buf_size
, "nRF%" PRIx32
"-%s%.2s(build code: %s)",
638 chip
->ficr_info
.part
,
639 nrf5_decode_info_package(chip
->ficr_info
.package
),
640 variant
, &variant
[2]);
642 res
= snprintf(buf
, buf_size
, "nRF51xxx (HWID 0x%04" PRIx16
")", chip
->hwid
);
646 if (res
<= 0 || (unsigned int)res
>= buf_size
) {
647 LOG_ERROR("BUG: buffer problem in %s", __func__
);
653 static int nrf5_info(struct flash_bank
*bank
, struct command_invocation
*cmd
)
655 struct nrf5_bank
*nbank
= bank
->driver_priv
;
656 struct nrf5_info
*chip
= nbank
->chip
;
658 char chip_type_str
[256];
659 if (get_nrf5_chip_type_str(chip
, chip_type_str
, sizeof(chip_type_str
)) != ERROR_OK
)
662 command_print_sameline(cmd
, "%s %ukB Flash, %ukB RAM",
663 chip_type_str
, chip
->flash_size_kb
, chip
->ram_size_kb
);
667 static int nrf5_read_ficr_info(struct nrf5_info
*chip
)
670 struct target
*target
= chip
->target
;
672 chip
->ficr_info_valid
= false;
674 res
= target_read_u32(target
, NRF5_FICR_INFO_PART
, &chip
->ficr_info
.part
);
675 if (res
!= ERROR_OK
) {
676 LOG_DEBUG("Couldn't read FICR INFO.PART register");
680 uint32_t series
= chip
->ficr_info
.part
& 0xfffff000;
683 chip
->features
= NRF5_FEATURE_SERIES_51
;
687 chip
->features
= NRF5_FEATURE_SERIES_52
;
689 switch (chip
->ficr_info
.part
) {
692 chip
->features
|= NRF5_FEATURE_BPROT
;
696 chip
->features
|= NRF5_FEATURE_ACL_PROT
;
702 LOG_DEBUG("FICR INFO likely not implemented. Invalid PART value 0x%08"
703 PRIx32
, chip
->ficr_info
.part
);
704 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
707 /* Now we know the device has FICR INFO filled by something relevant:
708 * Although it is not documented, the tested nRF51 rev 3 devices
709 * have FICR INFO.PART, RAM and FLASH of the same format as nRF52.
710 * VARIANT and PACKAGE coding is unknown for a nRF51 device.
711 * nRF52 devices have FICR INFO documented and always filled. */
713 res
= target_read_u32(target
, NRF5_FICR_INFO_VARIANT
, &chip
->ficr_info
.variant
);
717 res
= target_read_u32(target
, NRF5_FICR_INFO_PACKAGE
, &chip
->ficr_info
.package
);
721 res
= target_read_u32(target
, NRF5_FICR_INFO_RAM
, &chip
->ficr_info
.ram
);
725 res
= target_read_u32(target
, NRF5_FICR_INFO_FLASH
, &chip
->ficr_info
.flash
);
729 chip
->ficr_info_valid
= true;
733 static int nrf5_get_ram_size(struct target
*target
, uint32_t *ram_size
)
739 uint32_t numramblock
;
740 res
= target_read_u32(target
, NRF51_FICR_NUMRAMBLOCK
, &numramblock
);
741 if (res
!= ERROR_OK
) {
742 LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
746 if (numramblock
< 1 || numramblock
> 4) {
747 LOG_DEBUG("FICR NUMRAMBLOCK strange value %" PRIx32
, numramblock
);
748 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
751 for (unsigned int i
= 0; i
< numramblock
; i
++) {
752 uint32_t sizeramblock
;
753 res
= target_read_u32(target
, NRF51_FICR_SIZERAMBLOCK0
+ sizeof(uint32_t)*i
, &sizeramblock
);
754 if (res
!= ERROR_OK
) {
755 LOG_DEBUG("Couldn't read FICR NUMRAMBLOCK register");
758 if (sizeramblock
< 1024 || sizeramblock
> 65536)
759 LOG_DEBUG("FICR SIZERAMBLOCK strange value %" PRIx32
, sizeramblock
);
761 *ram_size
+= sizeramblock
;
766 static int nrf5_probe(struct flash_bank
*bank
)
769 struct nrf5_bank
*nbank
= bank
->driver_priv
;
770 struct nrf5_info
*chip
= nbank
->chip
;
771 struct target
*target
= chip
->target
;
774 res
= target_read_u32(target
, NRF5_FICR_CONFIGID
, &configid
);
775 if (res
!= ERROR_OK
) {
776 LOG_ERROR("Couldn't read CONFIGID register");
780 /* HWID is stored in the lower two bytes of the CONFIGID register */
781 chip
->hwid
= configid
& 0xFFFF;
783 /* guess a nRF51 series if the device has no FICR INFO and we don't know HWID */
784 chip
->features
= NRF5_FEATURE_SERIES_51
;
786 /* Don't bail out on error for the case that some old engineering
787 * sample has FICR INFO registers unreadable. We can proceed anyway. */
788 (void)nrf5_read_ficr_info(chip
);
791 for (size_t i
= 0; i
< ARRAY_SIZE(nrf5_known_devices_table
); i
++) {
792 if (chip
->hwid
== nrf5_known_devices_table
[i
].hwid
) {
793 chip
->spec
= &nrf5_known_devices_table
[i
];
794 chip
->features
= chip
->spec
->features
;
799 if (chip
->spec
&& chip
->ficr_info_valid
) {
800 /* check if HWID table gives the same part as FICR INFO */
801 if (chip
->ficr_info
.part
!= strtoul(chip
->spec
->part
, NULL
, 16))
802 LOG_WARNING("HWID 0x%04" PRIx32
" mismatch: FICR INFO.PART %"
803 PRIx32
, chip
->hwid
, chip
->ficr_info
.part
);
806 if (chip
->ficr_info_valid
) {
807 chip
->ram_size_kb
= chip
->ficr_info
.ram
;
810 nrf5_get_ram_size(target
, &ram_size
);
811 chip
->ram_size_kb
= ram_size
/ 1024;
814 /* The value stored in NRF5_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
815 uint32_t flash_page_size
;
816 res
= target_read_u32(chip
->target
, NRF5_FICR_CODEPAGESIZE
,
818 if (res
!= ERROR_OK
) {
819 LOG_ERROR("Couldn't read code page size");
823 /* Note the register name is misleading,
824 * NRF5_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */
825 uint32_t num_sectors
;
826 res
= target_read_u32(chip
->target
, NRF5_FICR_CODESIZE
, &num_sectors
);
827 if (res
!= ERROR_OK
) {
828 LOG_ERROR("Couldn't read code memory size");
832 chip
->flash_size_kb
= num_sectors
* flash_page_size
/ 1024;
834 if (!chip
->bank
[0].probed
&& !chip
->bank
[1].probed
) {
835 char chip_type_str
[256];
836 if (get_nrf5_chip_type_str(chip
, chip_type_str
, sizeof(chip_type_str
)) != ERROR_OK
)
838 const bool device_is_unknown
= (!chip
->spec
&& !chip
->ficr_info_valid
);
839 LOG_INFO("%s%s %ukB Flash, %ukB RAM",
840 device_is_unknown
? "Unknown device: " : "",
848 if (bank
->base
== NRF5_FLASH_BASE
) {
850 if (chip
->spec
&& chip
->flash_size_kb
!= chip
->spec
->flash_size_kb
)
851 LOG_WARNING("Chip's reported Flash capacity does not match expected one");
852 if (chip
->ficr_info_valid
&& chip
->flash_size_kb
!= chip
->ficr_info
.flash
)
853 LOG_WARNING("Chip's reported Flash capacity does not match FICR INFO.FLASH");
855 bank
->num_sectors
= num_sectors
;
856 bank
->size
= num_sectors
* flash_page_size
;
858 bank
->sectors
= alloc_block_array(0, flash_page_size
, num_sectors
);
862 chip
->bank
[0].probed
= true;
865 bank
->num_sectors
= 1;
866 bank
->size
= flash_page_size
;
868 bank
->sectors
= alloc_block_array(0, flash_page_size
, num_sectors
);
872 bank
->sectors
[0].is_protected
= 0;
874 chip
->bank
[1].probed
= true;
880 static int nrf5_auto_probe(struct flash_bank
*bank
)
882 if (nrf5_bank_is_probed(bank
))
885 return nrf5_probe(bank
);
888 static int nrf5_erase_all(struct nrf5_info
*chip
)
890 LOG_DEBUG("Erasing all non-volatile memory");
891 return nrf5_nvmc_generic_erase(chip
,
896 static int nrf5_erase_page(struct flash_bank
*bank
,
897 struct nrf5_info
*chip
,
898 struct flash_sector
*sector
)
902 LOG_DEBUG("Erasing page at 0x%"PRIx32
, sector
->offset
);
904 if (bank
->base
== NRF5_UICR_BASE
) {
905 if (chip
->features
& NRF5_FEATURE_SERIES_51
) {
907 res
= target_read_u32(chip
->target
, NRF51_FICR_PPFC
,
909 if (res
!= ERROR_OK
) {
910 LOG_ERROR("Couldn't read PPFC register");
914 if ((ppfc
& 0xFF) == 0xFF) {
915 /* We can't erase the UICR. Double-check to
916 see if it's already erased before complaining. */
917 default_flash_blank_check(bank
);
918 if (sector
->is_erased
== 1)
921 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
926 res
= nrf5_nvmc_generic_erase(chip
,
932 res
= nrf5_nvmc_generic_erase(chip
,
940 /* Start a low level flash write for the specified region */
941 static int nrf5_ll_flash_write(struct nrf5_info
*chip
, uint32_t address
, const uint8_t *buffer
, uint32_t bytes
)
943 struct target
*target
= chip
->target
;
944 uint32_t buffer_size
= 8192;
945 struct working_area
*write_algorithm
;
946 struct working_area
*source
;
947 struct reg_param reg_params
[6];
948 struct armv7m_algorithm armv7m_info
;
949 int retval
= ERROR_OK
;
951 static const uint8_t nrf5_flash_write_code
[] = {
952 #include "../../../contrib/loaders/flash/nrf5/nrf5.inc"
955 LOG_DEBUG("Writing buffer to flash address=0x%"PRIx32
" bytes=0x%"PRIx32
, address
, bytes
);
956 assert(bytes
% 4 == 0);
958 /* allocate working area with flash programming code */
959 if (target_alloc_working_area(target
, sizeof(nrf5_flash_write_code
),
960 &write_algorithm
) != ERROR_OK
) {
961 LOG_WARNING("no working area available, falling back to slow memory writes");
963 for (; bytes
> 0; bytes
-= 4) {
964 retval
= target_write_memory(target
, address
, 4, 1, buffer
);
965 if (retval
!= ERROR_OK
)
968 retval
= nrf5_wait_for_nvmc(chip
);
969 if (retval
!= ERROR_OK
)
979 retval
= target_write_buffer(target
, write_algorithm
->address
,
980 sizeof(nrf5_flash_write_code
),
981 nrf5_flash_write_code
);
982 if (retval
!= ERROR_OK
)
986 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
) {
988 buffer_size
&= ~3UL; /* Make sure it's 4 byte aligned */
989 if (buffer_size
<= 256) {
990 /* free working area, write algorithm already allocated */
991 target_free_working_area(target
, write_algorithm
);
993 LOG_WARNING("No large enough working area available, can't do block memory writes");
994 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
998 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
999 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
1001 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* byte count */
1002 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer start */
1003 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* buffer end */
1004 init_reg_param(®_params
[3], "r3", 32, PARAM_IN_OUT
); /* target address */
1005 init_reg_param(®_params
[4], "r6", 32, PARAM_OUT
); /* watchdog refresh value */
1006 init_reg_param(®_params
[5], "r7", 32, PARAM_OUT
); /* watchdog refresh register address */
1008 buf_set_u32(reg_params
[0].value
, 0, 32, bytes
);
1009 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
);
1010 buf_set_u32(reg_params
[2].value
, 0, 32, source
->address
+ source
->size
);
1011 buf_set_u32(reg_params
[3].value
, 0, 32, address
);
1012 buf_set_u32(reg_params
[4].value
, 0, 32, WATCHDOG_REFRESH_VALUE
);
1013 buf_set_u32(reg_params
[5].value
, 0, 32, WATCHDOG_REFRESH_REGISTER
);
1015 retval
= target_run_flash_async_algorithm(target
, buffer
, bytes
/4, 4,
1017 ARRAY_SIZE(reg_params
), reg_params
,
1018 source
->address
, source
->size
,
1019 write_algorithm
->address
, write_algorithm
->address
+ sizeof(nrf5_flash_write_code
) - 2,
1022 target_free_working_area(target
, source
);
1023 target_free_working_area(target
, write_algorithm
);
1025 destroy_reg_param(®_params
[0]);
1026 destroy_reg_param(®_params
[1]);
1027 destroy_reg_param(®_params
[2]);
1028 destroy_reg_param(®_params
[3]);
1029 destroy_reg_param(®_params
[4]);
1030 destroy_reg_param(®_params
[5]);
1035 static int nrf5_write(struct flash_bank
*bank
, const uint8_t *buffer
,
1036 uint32_t offset
, uint32_t count
)
1038 struct nrf5_info
*chip
;
1040 int res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
1041 if (res
!= ERROR_OK
)
1044 assert(offset
% 4 == 0);
1045 assert(count
% 4 == 0);
1047 /* UICR CLENR0 based protection used on nRF51 is somewhat clumsy:
1048 * RM reads: Code running from code region 1 will not be able to write
1050 * Unfortunately the flash loader running from RAM can write to both
1051 * code regions without any hint the protection is violated.
1053 * Update protection state and check if any flash sector to be written
1055 if (chip
->features
& NRF5_FEATURE_SERIES_51
) {
1057 res
= nrf5_protect_check_clenr0(bank
);
1058 if (res
!= ERROR_OK
)
1061 for (unsigned int sector
= 0; sector
< bank
->num_sectors
; sector
++) {
1062 struct flash_sector
*bs
= &bank
->sectors
[sector
];
1064 /* Start offset in or before this sector? */
1065 /* End offset in or behind this sector? */
1066 if ((offset
< (bs
->offset
+ bs
->size
))
1067 && ((offset
+ count
- 1) >= bs
->offset
)
1068 && bs
->is_protected
== 1) {
1069 LOG_ERROR("Write refused, sector %d is protected", sector
);
1070 return ERROR_FLASH_PROTECTED
;
1075 res
= nrf5_nvmc_write_enable(chip
);
1076 if (res
!= ERROR_OK
)
1079 res
= nrf5_ll_flash_write(chip
, bank
->base
+ offset
, buffer
, count
);
1080 if (res
!= ERROR_OK
)
1083 return nrf5_nvmc_read_only(chip
);
1086 nrf5_nvmc_read_only(chip
);
1087 LOG_ERROR("Failed to write to nrf5 flash");
1091 static int nrf5_erase(struct flash_bank
*bank
, unsigned int first
,
1095 struct nrf5_info
*chip
;
1097 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
1098 if (res
!= ERROR_OK
)
1101 /* UICR CLENR0 based protection used on nRF51 prevents erase
1102 * absolutely silently. NVMC has no flag to indicate the protection
1105 * Update protection state and check if any flash sector to be erased
1107 if (chip
->features
& NRF5_FEATURE_SERIES_51
) {
1109 res
= nrf5_protect_check_clenr0(bank
);
1110 if (res
!= ERROR_OK
)
1114 /* For each sector to be erased */
1115 for (unsigned int s
= first
; s
<= last
&& res
== ERROR_OK
; s
++) {
1117 if (chip
->features
& NRF5_FEATURE_SERIES_51
1118 && bank
->sectors
[s
].is_protected
== 1) {
1119 LOG_ERROR("Flash sector %d is protected", s
);
1120 return ERROR_FLASH_PROTECTED
;
1123 res
= nrf5_erase_page(bank
, chip
, &bank
->sectors
[s
]);
1124 if (res
!= ERROR_OK
) {
1125 LOG_ERROR("Error erasing sector %d", s
);
1133 static void nrf5_free_driver_priv(struct flash_bank
*bank
)
1135 struct nrf5_bank
*nbank
= bank
->driver_priv
;
1136 struct nrf5_info
*chip
= nbank
->chip
;
1141 if (chip
->refcount
== 0) {
1143 bank
->driver_priv
= NULL
;
1147 static struct nrf5_info
*nrf5_get_chip(struct target
*target
)
1149 struct flash_bank
*bank_iter
;
1151 /* iterate over nrf5 banks of same target */
1152 for (bank_iter
= flash_bank_list(); bank_iter
; bank_iter
= bank_iter
->next
) {
1153 if (bank_iter
->driver
!= &nrf5_flash
&& bank_iter
->driver
!= &nrf51_flash
)
1156 if (bank_iter
->target
!= target
)
1159 struct nrf5_bank
*nbank
= bank_iter
->driver_priv
;
1169 FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command
)
1171 struct nrf5_info
*chip
;
1172 struct nrf5_bank
*nbank
= NULL
;
1174 switch (bank
->base
) {
1175 case NRF5_FLASH_BASE
:
1176 case NRF5_UICR_BASE
:
1179 LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT
, bank
->base
);
1183 chip
= nrf5_get_chip(bank
->target
);
1185 /* Create a new chip */
1186 chip
= calloc(1, sizeof(*chip
));
1190 chip
->target
= bank
->target
;
1193 switch (bank
->base
) {
1194 case NRF5_FLASH_BASE
:
1195 nbank
= &chip
->bank
[0];
1197 case NRF5_UICR_BASE
:
1198 nbank
= &chip
->bank
[1];
1205 nbank
->probed
= false;
1206 bank
->driver_priv
= nbank
;
1207 bank
->write_start_alignment
= bank
->write_end_alignment
= 4;
1212 COMMAND_HANDLER(nrf5_handle_mass_erase_command
)
1215 struct flash_bank
*bank
= NULL
;
1216 struct target
*target
= get_current_target(CMD_CTX
);
1218 res
= get_flash_bank_by_addr(target
, NRF5_FLASH_BASE
, true, &bank
);
1219 if (res
!= ERROR_OK
)
1224 struct nrf5_info
*chip
;
1226 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
1227 if (res
!= ERROR_OK
)
1230 if (chip
->features
& NRF5_FEATURE_SERIES_51
) {
1232 res
= target_read_u32(target
, NRF51_FICR_PPFC
,
1234 if (res
!= ERROR_OK
) {
1235 LOG_ERROR("Couldn't read PPFC register");
1239 if ((ppfc
& 0xFF) == 0x00) {
1240 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
1241 "mass erase command won't work.");
1246 res
= nrf5_erase_all(chip
);
1247 if (res
== ERROR_OK
) {
1248 LOG_INFO("Mass erase completed.");
1249 if (chip
->features
& NRF5_FEATURE_SERIES_51
)
1250 LOG_INFO("A reset or power cycle is required if the flash was protected before.");
1253 LOG_ERROR("Failed to erase the chip");
1259 COMMAND_HANDLER(nrf5_handle_info_command
)
1262 struct flash_bank
*bank
= NULL
;
1263 struct target
*target
= get_current_target(CMD_CTX
);
1265 res
= get_flash_bank_by_addr(target
, NRF5_FLASH_BASE
, true, &bank
);
1266 if (res
!= ERROR_OK
)
1271 struct nrf5_info
*chip
;
1273 res
= nrf5_get_probed_chip_if_halted(bank
, &chip
);
1274 if (res
!= ERROR_OK
)
1278 const uint32_t address
;
1281 { .address
= NRF5_FICR_CODEPAGESIZE
},
1282 { .address
= NRF5_FICR_CODESIZE
},
1283 { .address
= NRF51_FICR_CLENR0
},
1284 { .address
= NRF51_FICR_PPFC
},
1285 { .address
= NRF51_FICR_NUMRAMBLOCK
},
1286 { .address
= NRF51_FICR_SIZERAMBLOCK0
},
1287 { .address
= NRF51_FICR_SIZERAMBLOCK1
},
1288 { .address
= NRF51_FICR_SIZERAMBLOCK2
},
1289 { .address
= NRF51_FICR_SIZERAMBLOCK3
},
1290 { .address
= NRF5_FICR_CONFIGID
},
1291 { .address
= NRF5_FICR_DEVICEID0
},
1292 { .address
= NRF5_FICR_DEVICEID1
},
1293 { .address
= NRF5_FICR_ER0
},
1294 { .address
= NRF5_FICR_ER1
},
1295 { .address
= NRF5_FICR_ER2
},
1296 { .address
= NRF5_FICR_ER3
},
1297 { .address
= NRF5_FICR_IR0
},
1298 { .address
= NRF5_FICR_IR1
},
1299 { .address
= NRF5_FICR_IR2
},
1300 { .address
= NRF5_FICR_IR3
},
1301 { .address
= NRF5_FICR_DEVICEADDRTYPE
},
1302 { .address
= NRF5_FICR_DEVICEADDR0
},
1303 { .address
= NRF5_FICR_DEVICEADDR1
},
1304 { .address
= NRF51_FICR_OVERRIDEN
},
1305 { .address
= NRF51_FICR_NRF_1MBIT0
},
1306 { .address
= NRF51_FICR_NRF_1MBIT1
},
1307 { .address
= NRF51_FICR_NRF_1MBIT2
},
1308 { .address
= NRF51_FICR_NRF_1MBIT3
},
1309 { .address
= NRF51_FICR_NRF_1MBIT4
},
1310 { .address
= NRF51_FICR_BLE_1MBIT0
},
1311 { .address
= NRF51_FICR_BLE_1MBIT1
},
1312 { .address
= NRF51_FICR_BLE_1MBIT2
},
1313 { .address
= NRF51_FICR_BLE_1MBIT3
},
1314 { .address
= NRF51_FICR_BLE_1MBIT4
},
1316 { .address
= NRF51_UICR_CLENR0
, },
1317 { .address
= NRF51_UICR_RBPCONF
},
1318 { .address
= NRF51_UICR_XTALFREQ
},
1319 { .address
= NRF51_UICR_FWID
},
1322 for (size_t i
= 0; i
< ARRAY_SIZE(ficr
); i
++) {
1323 res
= target_read_u32(chip
->target
, ficr
[i
].address
,
1325 if (res
!= ERROR_OK
) {
1326 LOG_ERROR("Couldn't read %" PRIx32
, ficr
[i
].address
);
1331 for (size_t i
= 0; i
< ARRAY_SIZE(uicr
); i
++) {
1332 res
= target_read_u32(chip
->target
, uicr
[i
].address
,
1334 if (res
!= ERROR_OK
) {
1335 LOG_ERROR("Couldn't read %" PRIx32
, uicr
[i
].address
);
1341 "\n[factory information control block]\n\n"
1342 "code page size: %"PRIu32
"B\n"
1343 "code memory size: %"PRIu32
"kB\n"
1344 "code region 0 size: %"PRIu32
"kB\n"
1345 "pre-programmed code: %s\n"
1346 "number of ram blocks: %"PRIu32
"\n"
1347 "ram block 0 size: %"PRIu32
"B\n"
1348 "ram block 1 size: %"PRIu32
"B\n"
1349 "ram block 2 size: %"PRIu32
"B\n"
1350 "ram block 3 size: %"PRIu32
"B\n"
1351 "config id: %" PRIx32
"\n"
1352 "device id: 0x%"PRIx32
"%08"PRIx32
"\n"
1353 "encryption root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1354 "identity root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1355 "device address type: 0x%"PRIx32
"\n"
1356 "device address: 0x%"PRIx32
"%08"PRIx32
"\n"
1357 "override enable: %"PRIx32
"\n"
1358 "NRF_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1359 "BLE_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1360 "\n[user information control block]\n\n"
1361 "code region 0 size: %"PRIu32
"kB\n"
1362 "read back protection configuration: %"PRIx32
"\n"
1363 "reset value for XTALFREQ: %"PRIx32
"\n"
1364 "firmware id: 0x%04"PRIx32
,
1366 (ficr
[1].value
* ficr
[0].value
) / 1024,
1367 (ficr
[2].value
== 0xFFFFFFFF) ? 0 : ficr
[2].value
/ 1024,
1368 ((ficr
[3].value
& 0xFF) == 0x00) ? "present" : "not present",
1371 (ficr
[6].value
== 0xFFFFFFFF) ? 0 : ficr
[6].value
,
1372 (ficr
[7].value
== 0xFFFFFFFF) ? 0 : ficr
[7].value
,
1373 (ficr
[8].value
== 0xFFFFFFFF) ? 0 : ficr
[8].value
,
1375 ficr
[10].value
, ficr
[11].value
,
1376 ficr
[12].value
, ficr
[13].value
, ficr
[14].value
, ficr
[15].value
,
1377 ficr
[16].value
, ficr
[17].value
, ficr
[18].value
, ficr
[19].value
,
1379 ficr
[21].value
, ficr
[22].value
,
1381 ficr
[24].value
, ficr
[25].value
, ficr
[26].value
, ficr
[27].value
, ficr
[28].value
,
1382 ficr
[29].value
, ficr
[30].value
, ficr
[31].value
, ficr
[32].value
, ficr
[33].value
,
1383 (uicr
[0].value
== 0xFFFFFFFF) ? 0 : uicr
[0].value
/ 1024,
1384 uicr
[1].value
& 0xFFFF,
1385 uicr
[2].value
& 0xFF,
1386 uicr
[3].value
& 0xFFFF);
1391 static const struct command_registration nrf5_exec_command_handlers
[] = {
1393 .name
= "mass_erase",
1394 .handler
= nrf5_handle_mass_erase_command
,
1395 .mode
= COMMAND_EXEC
,
1396 .help
= "Erase all flash contents of the chip.",
1401 .handler
= nrf5_handle_info_command
,
1402 .mode
= COMMAND_EXEC
,
1403 .help
= "Show FICR and UICR info.",
1406 COMMAND_REGISTRATION_DONE
1409 static const struct command_registration nrf5_command_handlers
[] = {
1412 .mode
= COMMAND_ANY
,
1413 .help
= "nrf5 flash command group",
1415 .chain
= nrf5_exec_command_handlers
,
1419 .mode
= COMMAND_ANY
,
1420 .help
= "nrf51 flash command group",
1422 .chain
= nrf5_exec_command_handlers
,
1424 COMMAND_REGISTRATION_DONE
1427 const struct flash_driver nrf5_flash
= {
1429 .commands
= nrf5_command_handlers
,
1430 .flash_bank_command
= nrf5_flash_bank_command
,
1432 .erase
= nrf5_erase
,
1433 .protect
= nrf5_protect
,
1434 .write
= nrf5_write
,
1435 .read
= default_flash_read
,
1436 .probe
= nrf5_probe
,
1437 .auto_probe
= nrf5_auto_probe
,
1438 .erase_check
= default_flash_blank_check
,
1439 .protect_check
= nrf5_protect_check
,
1440 .free_driver_priv
= nrf5_free_driver_priv
,
1443 /* We need to retain the flash-driver name as well as the commands
1444 * for backwards compatibility */
1445 const struct flash_driver nrf51_flash
= {
1447 .commands
= nrf5_command_handlers
,
1448 .flash_bank_command
= nrf5_flash_bank_command
,
1450 .erase
= nrf5_erase
,
1451 .protect
= nrf5_protect
,
1452 .write
= nrf5_write
,
1453 .read
= default_flash_read
,
1454 .probe
= nrf5_probe
,
1455 .auto_probe
= nrf5_auto_probe
,
1456 .erase_check
= default_flash_blank_check
,
1457 .protect_check
= nrf5_protect_check
,
1458 .free_driver_priv
= nrf5_free_driver_priv
,
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