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7820baf5581cd728b2395d45d6a0464c93644e11
[openocd.git] / src / flash / nor / nrf51.c
1 /***************************************************************************
2 * Copyright (C) 2013 Synapse Product Development *
3 * Andrey Smirnov <andrew.smironv@gmail.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
20
21 #ifdef HAVE_CONFIG_H
22 #include "config.h"
23 #endif
24
25 #include "imp.h"
26
27 enum {
28 NRF51_FLASH_BASE = 0x00000000,
29 };
30
31 enum nrf51_ficr_registers {
32 NRF51_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
33
34 #define NRF51_FICR_REG(offset) (NRF51_FICR_BASE + offset)
35
36 NRF51_FICR_CODEPAGESIZE = NRF51_FICR_REG(0x010),
37 NRF51_FICR_CODESIZE = NRF51_FICR_REG(0x014),
38 NRF51_FICR_CLENR0 = NRF51_FICR_REG(0x028),
39 NRF51_FICR_PPFC = NRF51_FICR_REG(0x02C),
40 NRF51_FICR_NUMRAMBLOCK = NRF51_FICR_REG(0x034),
41 NRF51_FICR_SIZERAMBLOCK0 = NRF51_FICR_REG(0x038),
42 NRF51_FICR_SIZERAMBLOCK1 = NRF51_FICR_REG(0x03C),
43 NRF51_FICR_SIZERAMBLOCK2 = NRF51_FICR_REG(0x040),
44 NRF51_FICR_SIZERAMBLOCK3 = NRF51_FICR_REG(0x044),
45 NRF51_FICR_CONFIGID = NRF51_FICR_REG(0x05C),
46 NRF51_FICR_DEVICEID0 = NRF51_FICR_REG(0x060),
47 NRF51_FICR_DEVICEID1 = NRF51_FICR_REG(0x064),
48 NRF51_FICR_ER0 = NRF51_FICR_REG(0x080),
49 NRF51_FICR_ER1 = NRF51_FICR_REG(0x084),
50 NRF51_FICR_ER2 = NRF51_FICR_REG(0x088),
51 NRF51_FICR_ER3 = NRF51_FICR_REG(0x08C),
52 NRF51_FICR_IR0 = NRF51_FICR_REG(0x090),
53 NRF51_FICR_IR1 = NRF51_FICR_REG(0x094),
54 NRF51_FICR_IR2 = NRF51_FICR_REG(0x098),
55 NRF51_FICR_IR3 = NRF51_FICR_REG(0x09C),
56 NRF51_FICR_DEVICEADDRTYPE = NRF51_FICR_REG(0x0A0),
57 NRF51_FICR_DEVICEADDR0 = NRF51_FICR_REG(0x0A4),
58 NRF51_FICR_DEVICEADDR1 = NRF51_FICR_REG(0x0A8),
59 NRF51_FICR_OVERRIDEN = NRF51_FICR_REG(0x0AC),
60 NRF51_FICR_NRF_1MBIT0 = NRF51_FICR_REG(0x0B0),
61 NRF51_FICR_NRF_1MBIT1 = NRF51_FICR_REG(0x0B4),
62 NRF51_FICR_NRF_1MBIT2 = NRF51_FICR_REG(0x0B8),
63 NRF51_FICR_NRF_1MBIT3 = NRF51_FICR_REG(0x0BC),
64 NRF51_FICR_NRF_1MBIT4 = NRF51_FICR_REG(0x0C0),
65 NRF51_FICR_BLE_1MBIT0 = NRF51_FICR_REG(0x0EC),
66 NRF51_FICR_BLE_1MBIT1 = NRF51_FICR_REG(0x0F0),
67 NRF51_FICR_BLE_1MBIT2 = NRF51_FICR_REG(0x0F4),
68 NRF51_FICR_BLE_1MBIT3 = NRF51_FICR_REG(0x0F8),
69 NRF51_FICR_BLE_1MBIT4 = NRF51_FICR_REG(0x0FC),
70 };
71
72 enum nrf51_uicr_registers {
73 NRF51_UICR_BASE = 0x10001000, /* User Information
74 * Configuration Regsters */
75
76 #define NRF51_UICR_REG(offset) (NRF51_UICR_BASE + offset)
77
78 NRF51_UICR_CLENR0 = NRF51_UICR_REG(0x000),
79 NRF51_UICR_RBPCONF = NRF51_UICR_REG(0x004),
80 NRF51_UICR_XTALFREQ = NRF51_UICR_REG(0x008),
81 NRF51_UICR_FWID = NRF51_UICR_REG(0x010),
82 };
83
84 enum nrf51_nvmc_registers {
85 NRF51_NVMC_BASE = 0x4001E000, /* Non-Volatile Memory
86 * Controller Regsters */
87
88 #define NRF51_NVMC_REG(offset) (NRF51_NVMC_BASE + offset)
89
90 NRF51_NVMC_READY = NRF51_NVMC_REG(0x400),
91 NRF51_NVMC_CONFIG = NRF51_NVMC_REG(0x504),
92 NRF51_NVMC_ERASEPAGE = NRF51_NVMC_REG(0x508),
93 NRF51_NVMC_ERASEALL = NRF51_NVMC_REG(0x50C),
94 NRF51_NVMC_ERASEUICR = NRF51_NVMC_REG(0x514),
95 };
96
97 enum nrf51_nvmc_config_bits {
98 NRF51_NVMC_CONFIG_REN = 0x00,
99 NRF51_NVMC_CONFIG_WEN = 0x01,
100 NRF51_NVMC_CONFIG_EEN = 0x02,
101
102 };
103
104 struct nrf51_info {
105 uint32_t code_page_size;
106 uint32_t code_memory_size;
107
108 bool probed;
109 struct target *target;
110 };
111
112 struct nrf51_device_spec {
113 uint16_t hwid;
114 const char *variant;
115 const char *build_code;
116 unsigned int flash_size_kb;
117 };
118
119 static const struct nrf51_device_spec nrf51_known_devices_table[] = {
120 {
121 .hwid = 0x001D,
122 .variant = "QFAA",
123 .build_code = "CA/C0",
124 .flash_size_kb = 256,
125 },
126 {
127 .hwid = 0x002A,
128 .variant = "QFAA",
129 .build_code = "FA",
130 .flash_size_kb = 256,
131 },
132 {
133 .hwid = 0x0044,
134 .variant = "QFAA",
135 .build_code = "GC",
136 .flash_size_kb = 256,
137 },
138 {
139 .hwid = 0x003C,
140 .variant = "QFAA",
141 .build_code = "G0",
142 .flash_size_kb = 256,
143 },
144
145 {
146 .hwid = 0x0020,
147 .variant = "CEAA",
148 .build_code = "BA",
149 .flash_size_kb = 256,
150 },
151 {
152 .hwid = 0x002F,
153 .variant = "CEAA",
154 .build_code = "B0",
155 .flash_size_kb = 256,
156 },
157 {
158 .hwid = 0x0040,
159 .variant = "CEAA",
160 .build_code = "CA",
161 .flash_size_kb = 256,
162 },
163 {
164 .hwid = 0x0047,
165 .variant = "CEAA",
166 .build_code = "DA",
167 .flash_size_kb = 256,
168 },
169 {
170 .hwid = 0x004D,
171 .variant = "CEAA",
172 .build_code = "D0",
173 .flash_size_kb = 256,
174 },
175
176 {
177 .hwid = 0x0026,
178 .variant = "QFAB",
179 .build_code = "AA",
180 .flash_size_kb = 128,
181 },
182 {
183 .hwid = 0x0027,
184 .variant = "QFAB",
185 .build_code = "A0",
186 .flash_size_kb = 128,
187 },
188 {
189 .hwid = 0x004C,
190 .variant = "QFAB",
191 .build_code = "B0",
192 .flash_size_kb = 128,
193 },
194
195 };
196
197 static int nrf51_probe(struct flash_bank *bank);
198
199 static int nrf51_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf51_info **chip)
200 {
201 if (bank->target->state != TARGET_HALTED) {
202 LOG_ERROR("Target not halted");
203 return ERROR_TARGET_NOT_HALTED;
204 }
205
206 *chip = (struct nrf51_info *)bank->driver_priv;
207
208 if (!(*chip)->probed)
209 return nrf51_probe(bank);
210
211 return ERROR_OK;
212 }
213
214 static int nrf51_wait_for_nvmc(struct nrf51_info *chip)
215 {
216 uint32_t ready;
217 int res;
218 int timeout = 100;
219
220 do {
221 res = target_read_u32(chip->target, NRF51_NVMC_READY, &ready);
222 if (res != ERROR_OK) {
223 LOG_ERROR("Couldn't read NVMC_READY register");
224 return res;
225 }
226
227 if (ready == 0x00000001)
228 return ERROR_OK;
229
230 alive_sleep(1);
231 } while (timeout--);
232
233 return ERROR_FLASH_BUSY;
234 }
235
236 static int nrf51_nvmc_erase_enable(struct nrf51_info *chip)
237 {
238 int res;
239 res = target_write_u32(chip->target,
240 NRF51_NVMC_CONFIG,
241 NRF51_NVMC_CONFIG_EEN);
242
243 if (res != ERROR_OK) {
244 LOG_ERROR("Failed to enable erase operation");
245 return res;
246 }
247
248 /*
249 According to NVMC examples in Nordic SDK busy status must be
250 checked after writing to NVMC_CONFIG
251 */
252 res = nrf51_wait_for_nvmc(chip);
253 if (res != ERROR_OK)
254 LOG_ERROR("Erase enable did not complete");
255
256 return res;
257 }
258
259 static int nrf51_nvmc_write_enable(struct nrf51_info *chip)
260 {
261 int res;
262 res = target_write_u32(chip->target,
263 NRF51_NVMC_CONFIG,
264 NRF51_NVMC_CONFIG_WEN);
265
266 if (res != ERROR_OK) {
267 LOG_ERROR("Failed to enable write operation");
268 return res;
269 }
270
271 /*
272 According to NVMC examples in Nordic SDK busy status must be
273 checked after writing to NVMC_CONFIG
274 */
275 res = nrf51_wait_for_nvmc(chip);
276 if (res != ERROR_OK)
277 LOG_ERROR("Write enable did not complete");
278
279 return res;
280 }
281
282 static int nrf51_nvmc_read_only(struct nrf51_info *chip)
283 {
284 int res;
285 res = target_write_u32(chip->target,
286 NRF51_NVMC_CONFIG,
287 NRF51_NVMC_CONFIG_REN);
288
289 if (res != ERROR_OK) {
290 LOG_ERROR("Failed to enable read-only operation");
291 return res;
292 }
293 /*
294 According to NVMC examples in Nordic SDK busy status must be
295 checked after writing to NVMC_CONFIG
296 */
297 res = nrf51_wait_for_nvmc(chip);
298 if (res != ERROR_OK)
299 LOG_ERROR("Read only enable did not complete");
300
301 return res;
302 }
303
304 static int nrf51_nvmc_generic_erase(struct nrf51_info *chip,
305 uint32_t erase_register, uint32_t erase_value)
306 {
307 int res;
308
309 res = nrf51_nvmc_erase_enable(chip);
310 if (res != ERROR_OK)
311 goto error;
312
313 res = target_write_u32(chip->target,
314 erase_register,
315 erase_value);
316 if (res != ERROR_OK)
317 goto set_read_only;
318
319 res = nrf51_wait_for_nvmc(chip);
320 if (res != ERROR_OK)
321 goto set_read_only;
322
323 return nrf51_nvmc_read_only(chip);
324
325 set_read_only:
326 nrf51_nvmc_read_only(chip);
327 error:
328 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32" val: 0x%08"PRIx32,
329 erase_register, erase_value);
330 return ERROR_FAIL;
331 }
332
333 static int nrf51_protect_check(struct flash_bank *bank)
334 {
335 int res;
336 uint32_t clenr0;
337
338 struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
339
340 assert(chip != NULL);
341
342 res = target_read_u32(chip->target, NRF51_FICR_CLENR0,
343 &clenr0);
344 if (res != ERROR_OK) {
345 LOG_ERROR("Couldn't read code region 0 size[FICR]");
346 return res;
347 }
348
349 if (clenr0 == 0xFFFFFFFF) {
350 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
351 &clenr0);
352 if (res != ERROR_OK) {
353 LOG_ERROR("Couldn't read code region 0 size[UICR]");
354 return res;
355 }
356 }
357
358 for (int i = 0; i < bank->num_sectors; i++)
359 bank->sectors[i].is_protected =
360 clenr0 != 0xFFFFFFFF && bank->sectors[i].offset < clenr0;
361
362 return ERROR_OK;
363 }
364
365 static int nrf51_protect(struct flash_bank *bank, int set, int first, int last)
366 {
367 int res;
368 uint32_t clenr0, ppfc;
369 struct nrf51_info *chip;
370
371 res = nrf51_get_probed_chip_if_halted(bank, &chip);
372 if (res != ERROR_OK)
373 return res;
374
375 if (first != 0) {
376 LOG_ERROR("Code region 0 must start at the begining of the bank");
377 return ERROR_FAIL;
378 }
379
380 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
381 &ppfc);
382 if (res != ERROR_OK) {
383 LOG_ERROR("Couldn't read PPFC register");
384 return res;
385 }
386
387 if ((ppfc & 0xFF) == 0x00) {
388 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
389 return ERROR_FAIL;
390 };
391
392 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
393 &clenr0);
394 if (res != ERROR_OK) {
395 LOG_ERROR("Couldn't read code region 0 size[UICR]");
396 return res;
397 }
398
399 if (clenr0 == 0xFFFFFFFF) {
400 res = target_write_u32(chip->target, NRF51_UICR_CLENR0,
401 clenr0);
402 if (res != ERROR_OK) {
403 LOG_ERROR("Couldn't write code region 0 size[UICR]");
404 return res;
405 }
406
407 } else {
408 LOG_ERROR("You need to perform chip erase before changing the protection settings");
409 }
410
411 nrf51_protect_check(bank);
412
413 return ERROR_OK;
414 }
415
416 static int nrf51_probe(struct flash_bank *bank)
417 {
418 uint32_t hwid;
419 int res;
420 struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
421
422
423 res = target_read_u32(chip->target, NRF51_FICR_CONFIGID, &hwid);
424 if (res != ERROR_OK) {
425 LOG_ERROR("Couldn't read CONFIGID register");
426 return res;
427 }
428
429 hwid &= 0xFFFF; /* HWID is stored in the lower two
430 * bytes of the CONFIGID register */
431
432 const struct nrf51_device_spec *spec = NULL;
433 for (size_t i = 0; i < ARRAY_SIZE(nrf51_known_devices_table); i++)
434 if (hwid == nrf51_known_devices_table[i].hwid) {
435 spec = &nrf51_known_devices_table[i];
436 break;
437 }
438
439 if (spec) {
440 LOG_INFO("nRF51822-%s(build code: %s) %ukB Flash",
441 spec->variant, spec->build_code, spec->flash_size_kb);
442 } else {
443 LOG_WARNING("Unknown device (HWID 0x%08" PRIx32 ")", hwid);
444 }
445
446 res = target_read_u32(chip->target, NRF51_FICR_CODEPAGESIZE,
447 &chip->code_page_size);
448 if (res != ERROR_OK) {
449 LOG_ERROR("Couldn't read code page size");
450 return res;
451 }
452
453 res = target_read_u32(chip->target, NRF51_FICR_CODESIZE,
454 &chip->code_memory_size);
455 if (res != ERROR_OK) {
456 LOG_ERROR("Couldn't read code memory size");
457 return res;
458 }
459
460 if (spec && chip->code_memory_size != spec->flash_size_kb) {
461 LOG_ERROR("Chip's reported Flash capacity does not match expected one");
462 return ERROR_FAIL;
463 }
464
465 bank->size = chip->code_memory_size * 1024;
466 bank->num_sectors = bank->size / chip->code_page_size;
467 bank->sectors = calloc(bank->num_sectors,
468 sizeof((bank->sectors)[0]));
469 if (!bank->sectors)
470 return ERROR_FLASH_BANK_NOT_PROBED;
471
472 /* Fill out the sector information: all NRF51 sectors are the same size and
473 * there is always a fixed number of them. */
474 for (int i = 0; i < bank->num_sectors; i++) {
475 bank->sectors[i].size = chip->code_page_size;
476 bank->sectors[i].offset = i * chip->code_page_size;
477
478 /* mark as unknown */
479 bank->sectors[i].is_erased = -1;
480 bank->sectors[i].is_protected = -1;
481 }
482
483 nrf51_protect_check(bank);
484
485 chip->probed = true;
486
487 return ERROR_OK;
488 }
489
490 static int nrf51_auto_probe(struct flash_bank *bank)
491 {
492 struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
493
494 if (chip->probed)
495 return ERROR_OK;
496
497 return nrf51_probe(bank);
498 }
499
500 static struct flash_sector *nrf51_find_sector_by_address(struct flash_bank *bank, uint32_t address)
501 {
502 struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
503
504 for (int i = 0; i < bank->num_sectors; i++)
505 if (bank->sectors[i].offset <= address &&
506 address < (bank->sectors[i].offset + chip->code_page_size))
507 return &bank->sectors[i];
508 return NULL;
509 }
510
511 static int nrf51_erase_all(struct nrf51_info *chip)
512 {
513 return nrf51_nvmc_generic_erase(chip,
514 NRF51_NVMC_ERASEALL,
515 0x00000001);
516 }
517
518 static int nrf51_erase_page(struct nrf51_info *chip, struct flash_sector *sector)
519 {
520 int res;
521
522 if (sector->is_protected)
523 return ERROR_FAIL;
524
525 res = nrf51_nvmc_generic_erase(chip,
526 NRF51_NVMC_ERASEPAGE,
527 sector->offset);
528 if (res == ERROR_OK)
529 sector->is_erased = 1;
530
531 return res;
532 }
533
534 static int nrf51_write_page(struct flash_bank *bank, uint32_t offset, const uint8_t *buffer)
535 {
536 assert(offset % 4 == 0);
537
538 int res = ERROR_FAIL;
539 struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
540 struct flash_sector *sector = nrf51_find_sector_by_address(bank, offset);
541
542 if (!sector)
543 goto error;
544
545 if (sector->is_protected)
546 goto error;
547
548 if (!sector->is_erased) {
549 res = nrf51_erase_page(chip, sector);
550 if (res != ERROR_OK)
551 goto error;
552 }
553
554 res = nrf51_nvmc_write_enable(chip);
555 if (res != ERROR_OK)
556 goto error;
557
558 sector->is_erased = 0;
559 res = target_write_memory(bank->target, offset, 4,
560 chip->code_page_size / 4, buffer);
561 if (res != ERROR_OK)
562 goto set_read_only;
563
564 return nrf51_nvmc_read_only(chip);
565
566 set_read_only:
567 nrf51_nvmc_read_only(chip);
568 error:
569 LOG_ERROR("Failed to write sector @ 0x%08"PRIx32, sector->offset);
570 return res;
571 }
572
573 static int nrf51_erase(struct flash_bank *bank, int first, int last)
574 {
575 int res;
576 struct nrf51_info *chip;
577
578 res = nrf51_get_probed_chip_if_halted(bank, &chip);
579 if (res != ERROR_OK)
580 return res;
581
582 /* For each sector to be erased */
583 for (int s = first; s <= last && res == ERROR_OK; s++)
584 res = nrf51_erase_page(chip, &bank->sectors[s]);
585
586 return res;
587 }
588
589 static int nrf51_write(struct flash_bank *bank, const uint8_t *buffer,
590 uint32_t offset, uint32_t count)
591 {
592 int res;
593 struct {
594 uint32_t start, end;
595 } region;
596 struct nrf51_info *chip;
597
598 res = nrf51_get_probed_chip_if_halted(bank, &chip);
599 if (res != ERROR_OK)
600 return res;
601
602 region.start = offset;
603 region.end = offset + count;
604
605 struct {
606 size_t length;
607 const uint8_t *buffer;
608 } start_extra, end_extra;
609
610 start_extra.length = region.start % chip->code_page_size;
611 start_extra.buffer = buffer;
612 end_extra.length = region.end % chip->code_page_size;
613 end_extra.buffer = buffer + count - end_extra.length;
614
615 if (start_extra.length) {
616 uint8_t page[chip->code_page_size];
617
618 res = target_read_memory(bank->target,
619 region.start - start_extra.length,
620 1, start_extra.length, page);
621 if (res != ERROR_OK)
622 return res;
623
624 memcpy(page + start_extra.length,
625 start_extra.buffer,
626 chip->code_page_size - start_extra.length);
627
628 res = nrf51_write_page(bank,
629 region.start - start_extra.length,
630 page);
631 if (res != ERROR_OK)
632 return res;
633 }
634
635 if (end_extra.length) {
636 uint8_t page[chip->code_page_size];
637
638 /* Retrieve the full row contents from Flash */
639 res = target_read_memory(bank->target,
640 region.end,
641 1,
642 (chip->code_page_size - end_extra.length),
643 page + end_extra.length);
644 if (res != ERROR_OK)
645 return res;
646
647 memcpy(page, end_extra.buffer, end_extra.length);
648
649 res = nrf51_write_page(bank,
650 region.end - end_extra.length,
651 page);
652 if (res != ERROR_OK)
653 return res;
654 }
655
656
657 region.start += start_extra.length;
658 region.end -= end_extra.length;
659
660 for (uint32_t address = region.start; address < region.end;
661 address += chip->code_page_size) {
662 res = nrf51_write_page(bank, address, &buffer[address - region.start]);
663
664 if (res != ERROR_OK)
665 return res;
666
667 }
668
669 return ERROR_OK;
670 }
671
672 FLASH_BANK_COMMAND_HANDLER(nrf51_flash_bank_command)
673 {
674 struct nrf51_info *chip;
675
676 /* Create a new chip */
677 chip = calloc(1, sizeof(*chip));
678 if (!chip)
679 return ERROR_FAIL;
680
681 chip->target = bank->target;
682 chip->probed = false;
683
684 bank->driver_priv = chip;
685
686 if (bank->base != NRF51_FLASH_BASE) {
687 LOG_ERROR("Address 0x%08" PRIx32 " invalid bank address (try 0x%08" PRIx32
688 "[nrf51 series] )",
689 bank->base, NRF51_FLASH_BASE);
690 return ERROR_FAIL;
691 }
692
693 return ERROR_OK;
694 }
695
696 COMMAND_HANDLER(nrf51_handle_mass_erase_command)
697 {
698 int res;
699 struct flash_bank *bank;
700
701 res = get_flash_bank_by_num(0, &bank);
702 if (res != ERROR_OK)
703 return res;
704
705 struct nrf51_info *chip;
706
707 res = nrf51_get_probed_chip_if_halted(bank, &chip);
708 if (res != ERROR_OK)
709 return res;
710
711 uint32_t ppfc;
712
713 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
714 &ppfc);
715 if (res != ERROR_OK) {
716 LOG_ERROR("Couldn't read PPFC register");
717 return res;
718 }
719
720 if ((ppfc & 0xFF) == 0x00) {
721 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
722 "mass erase command won't work.");
723 return ERROR_FAIL;
724 };
725
726 res = nrf51_erase_all(chip);
727 if (res != ERROR_OK) {
728 LOG_ERROR("Failed to erase the chip");
729 nrf51_protect_check(bank);
730 return res;
731 }
732
733 for (int i = 0; i < bank->num_sectors; i++)
734 bank->sectors[i].is_erased = 1;
735
736 return nrf51_protect_check(bank);
737 }
738
739 static int nrf51_info(struct flash_bank *bank, char *buf, int buf_size)
740 {
741 int res;
742
743 struct nrf51_info *chip;
744
745 res = nrf51_get_probed_chip_if_halted(bank, &chip);
746 if (res != ERROR_OK)
747 return res;
748
749 struct {
750 uint32_t address, value;
751 } ficr[] = {
752 { .address = NRF51_FICR_CODEPAGESIZE },
753 { .address = NRF51_FICR_CODESIZE },
754 { .address = NRF51_FICR_CLENR0 },
755 { .address = NRF51_FICR_PPFC },
756 { .address = NRF51_FICR_NUMRAMBLOCK },
757 { .address = NRF51_FICR_SIZERAMBLOCK0 },
758 { .address = NRF51_FICR_SIZERAMBLOCK1 },
759 { .address = NRF51_FICR_SIZERAMBLOCK2 },
760 { .address = NRF51_FICR_SIZERAMBLOCK3 },
761 { .address = NRF51_FICR_CONFIGID },
762 { .address = NRF51_FICR_DEVICEID0 },
763 { .address = NRF51_FICR_DEVICEID1 },
764 { .address = NRF51_FICR_ER0 },
765 { .address = NRF51_FICR_ER1 },
766 { .address = NRF51_FICR_ER2 },
767 { .address = NRF51_FICR_ER3 },
768 { .address = NRF51_FICR_IR0 },
769 { .address = NRF51_FICR_IR1 },
770 { .address = NRF51_FICR_IR2 },
771 { .address = NRF51_FICR_IR3 },
772 { .address = NRF51_FICR_DEVICEADDRTYPE },
773 { .address = NRF51_FICR_DEVICEADDR0 },
774 { .address = NRF51_FICR_DEVICEADDR1 },
775 { .address = NRF51_FICR_OVERRIDEN },
776 { .address = NRF51_FICR_NRF_1MBIT0 },
777 { .address = NRF51_FICR_NRF_1MBIT1 },
778 { .address = NRF51_FICR_NRF_1MBIT2 },
779 { .address = NRF51_FICR_NRF_1MBIT3 },
780 { .address = NRF51_FICR_NRF_1MBIT4 },
781 { .address = NRF51_FICR_BLE_1MBIT0 },
782 { .address = NRF51_FICR_BLE_1MBIT1 },
783 { .address = NRF51_FICR_BLE_1MBIT2 },
784 { .address = NRF51_FICR_BLE_1MBIT3 },
785 { .address = NRF51_FICR_BLE_1MBIT4 },
786 }, uicr[] = {
787 { .address = NRF51_UICR_CLENR0, },
788 { .address = NRF51_UICR_RBPCONF },
789 { .address = NRF51_UICR_XTALFREQ },
790 { .address = NRF51_UICR_FWID },
791 };
792
793 for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) {
794 res = target_read_u32(chip->target, ficr[i].address,
795 &ficr[i].value);
796 if (res != ERROR_OK) {
797 LOG_ERROR("Couldn't read %" PRIx32, ficr[i].address);
798 return res;
799 }
800 }
801
802 for (size_t i = 0; i < ARRAY_SIZE(uicr); i++) {
803 res = target_read_u32(chip->target, uicr[i].address,
804 &uicr[i].value);
805 if (res != ERROR_OK) {
806 LOG_ERROR("Couldn't read %" PRIx32, uicr[i].address);
807 return res;
808 }
809 }
810
811 snprintf(buf, buf_size,
812 "\n[factory information control block]\n\n"
813 "code page size: %"PRIu32"B\n"
814 "code memory size: %"PRIu32"kB\n"
815 "code region 0 size: %"PRIu32"kB\n"
816 "pre-programmed code: %s\n"
817 "number of ram blocks: %"PRIu32"\n"
818 "ram block 0 size: %"PRIu32"B\n"
819 "ram block 1 size: %"PRIu32"B\n"
820 "ram block 2 size: %"PRIu32"B\n"
821 "ram block 3 size: %"PRIu32 "B\n"
822 "config id: %" PRIx32 "\n"
823 "device id: 0x%"PRIx32"%08"PRIx32"\n"
824 "encryption root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
825 "identity root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
826 "device address type: 0x%"PRIx32"\n"
827 "device address: 0x%"PRIx32"%08"PRIx32"\n"
828 "override enable: %"PRIx32"\n"
829 "NRF_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
830 "BLE_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
831 "\n[user information control block]\n\n"
832 "code region 0 size: %"PRIu32"kB\n"
833 "read back protection configuration: %"PRIx32"\n"
834 "reset value for XTALFREQ: %"PRIx32"\n"
835 "firmware id: 0x%04"PRIx32,
836 ficr[0].value,
837 ficr[1].value,
838 (ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024,
839 ((ficr[3].value & 0xFF) == 0x00) ? "present" : "not present",
840 ficr[4].value,
841 ficr[5].value,
842 (ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value,
843 (ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value,
844 (ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value,
845 ficr[9].value,
846 ficr[10].value, ficr[11].value,
847 ficr[12].value, ficr[13].value, ficr[14].value, ficr[15].value,
848 ficr[16].value, ficr[17].value, ficr[18].value, ficr[19].value,
849 ficr[20].value,
850 ficr[21].value, ficr[22].value,
851 ficr[23].value,
852 ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, ficr[28].value,
853 ficr[29].value, ficr[30].value, ficr[31].value, ficr[32].value, ficr[33].value,
854 (uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024,
855 uicr[1].value & 0xFFFF,
856 uicr[2].value & 0xFF,
857 uicr[3].value & 0xFFFF);
858
859 return ERROR_OK;
860 }
861
862 static const struct command_registration nrf51_exec_command_handlers[] = {
863 {
864 .name = "mass_erase",
865 .handler = nrf51_handle_mass_erase_command,
866 .mode = COMMAND_EXEC,
867 .help = "Erase all flash contents of the chip.",
868 },
869 COMMAND_REGISTRATION_DONE
870 };
871
872 static const struct command_registration nrf51_command_handlers[] = {
873 {
874 .name = "nrf51",
875 .mode = COMMAND_ANY,
876 .help = "nrf51 flash command group",
877 .usage = "",
878 .chain = nrf51_exec_command_handlers,
879 },
880 COMMAND_REGISTRATION_DONE
881 };
882
883 struct flash_driver nrf51_flash = {
884 .name = "nrf51",
885 .commands = nrf51_command_handlers,
886 .flash_bank_command = nrf51_flash_bank_command,
887 .info = nrf51_info,
888 .erase = nrf51_erase,
889 .protect = nrf51_protect,
890 .write = nrf51_write,
891 .read = default_flash_read,
892 .probe = nrf51_probe,
893 .auto_probe = nrf51_auto_probe,
894 .erase_check = default_flash_blank_check,
895 .protect_check = nrf51_protect_check,
896 };
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