1 /***************************************************************************
2 * Copyright (C) 2013 Synapse Product Development *
3 * Andrey Smirnov <andrew.smironv@gmail.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
28 NRF51_FLASH_BASE
= 0x00000000,
31 enum nrf51_ficr_registers
{
32 NRF51_FICR_BASE
= 0x10000000, /* Factory Information Configuration Registers */
34 #define NRF51_FICR_REG(offset) (NRF51_FICR_BASE + offset)
36 NRF51_FICR_CODEPAGESIZE
= NRF51_FICR_REG(0x010),
37 NRF51_FICR_CODESIZE
= NRF51_FICR_REG(0x014),
38 NRF51_FICR_CLENR0
= NRF51_FICR_REG(0x028),
39 NRF51_FICR_PPFC
= NRF51_FICR_REG(0x02C),
40 NRF51_FICR_NUMRAMBLOCK
= NRF51_FICR_REG(0x034),
41 NRF51_FICR_SIZERAMBLOCK0
= NRF51_FICR_REG(0x038),
42 NRF51_FICR_SIZERAMBLOCK1
= NRF51_FICR_REG(0x03C),
43 NRF51_FICR_SIZERAMBLOCK2
= NRF51_FICR_REG(0x040),
44 NRF51_FICR_SIZERAMBLOCK3
= NRF51_FICR_REG(0x044),
45 NRF51_FICR_CONFIGID
= NRF51_FICR_REG(0x05C),
46 NRF51_FICR_DEVICEID0
= NRF51_FICR_REG(0x060),
47 NRF51_FICR_DEVICEID1
= NRF51_FICR_REG(0x064),
48 NRF51_FICR_ER0
= NRF51_FICR_REG(0x080),
49 NRF51_FICR_ER1
= NRF51_FICR_REG(0x084),
50 NRF51_FICR_ER2
= NRF51_FICR_REG(0x088),
51 NRF51_FICR_ER3
= NRF51_FICR_REG(0x08C),
52 NRF51_FICR_IR0
= NRF51_FICR_REG(0x090),
53 NRF51_FICR_IR1
= NRF51_FICR_REG(0x094),
54 NRF51_FICR_IR2
= NRF51_FICR_REG(0x098),
55 NRF51_FICR_IR3
= NRF51_FICR_REG(0x09C),
56 NRF51_FICR_DEVICEADDRTYPE
= NRF51_FICR_REG(0x0A0),
57 NRF51_FICR_DEVICEADDR0
= NRF51_FICR_REG(0x0A4),
58 NRF51_FICR_DEVICEADDR1
= NRF51_FICR_REG(0x0A8),
59 NRF51_FICR_OVERRIDEN
= NRF51_FICR_REG(0x0AC),
60 NRF51_FICR_NRF_1MBIT0
= NRF51_FICR_REG(0x0B0),
61 NRF51_FICR_NRF_1MBIT1
= NRF51_FICR_REG(0x0B4),
62 NRF51_FICR_NRF_1MBIT2
= NRF51_FICR_REG(0x0B8),
63 NRF51_FICR_NRF_1MBIT3
= NRF51_FICR_REG(0x0BC),
64 NRF51_FICR_NRF_1MBIT4
= NRF51_FICR_REG(0x0C0),
65 NRF51_FICR_BLE_1MBIT0
= NRF51_FICR_REG(0x0EC),
66 NRF51_FICR_BLE_1MBIT1
= NRF51_FICR_REG(0x0F0),
67 NRF51_FICR_BLE_1MBIT2
= NRF51_FICR_REG(0x0F4),
68 NRF51_FICR_BLE_1MBIT3
= NRF51_FICR_REG(0x0F8),
69 NRF51_FICR_BLE_1MBIT4
= NRF51_FICR_REG(0x0FC),
72 enum nrf51_uicr_registers
{
73 NRF51_UICR_BASE
= 0x10001000, /* User Information
74 * Configuration Regsters */
76 #define NRF51_UICR_REG(offset) (NRF51_UICR_BASE + offset)
78 NRF51_UICR_CLENR0
= NRF51_UICR_REG(0x000),
79 NRF51_UICR_RBPCONF
= NRF51_UICR_REG(0x004),
80 NRF51_UICR_XTALFREQ
= NRF51_UICR_REG(0x008),
81 NRF51_UICR_FWID
= NRF51_UICR_REG(0x010),
84 enum nrf51_nvmc_registers
{
85 NRF51_NVMC_BASE
= 0x4001E000, /* Non-Volatile Memory
86 * Controller Regsters */
88 #define NRF51_NVMC_REG(offset) (NRF51_NVMC_BASE + offset)
90 NRF51_NVMC_READY
= NRF51_NVMC_REG(0x400),
91 NRF51_NVMC_CONFIG
= NRF51_NVMC_REG(0x504),
92 NRF51_NVMC_ERASEPAGE
= NRF51_NVMC_REG(0x508),
93 NRF51_NVMC_ERASEALL
= NRF51_NVMC_REG(0x50C),
94 NRF51_NVMC_ERASEUICR
= NRF51_NVMC_REG(0x514),
97 enum nrf51_nvmc_config_bits
{
98 NRF51_NVMC_CONFIG_REN
= 0x00,
99 NRF51_NVMC_CONFIG_WEN
= 0x01,
100 NRF51_NVMC_CONFIG_EEN
= 0x02,
105 uint32_t code_page_size
;
106 uint32_t code_memory_size
;
109 struct target
*target
;
112 struct nrf51_device_spec
{
115 const char *build_code
;
116 unsigned int flash_size_kb
;
119 static const struct nrf51_device_spec nrf51_known_devices_table
[] = {
123 .build_code
= "CA/C0",
124 .flash_size_kb
= 256,
130 .flash_size_kb
= 256,
136 .flash_size_kb
= 256,
142 .flash_size_kb
= 256,
149 .flash_size_kb
= 256,
155 .flash_size_kb
= 256,
161 .flash_size_kb
= 256,
167 .flash_size_kb
= 256,
173 .flash_size_kb
= 256,
180 .flash_size_kb
= 128,
186 .flash_size_kb
= 128,
192 .flash_size_kb
= 128,
197 static int nrf51_probe(struct flash_bank
*bank
);
199 static int nrf51_get_probed_chip_if_halted(struct flash_bank
*bank
, struct nrf51_info
**chip
)
201 if (bank
->target
->state
!= TARGET_HALTED
) {
202 LOG_ERROR("Target not halted");
203 return ERROR_TARGET_NOT_HALTED
;
206 *chip
= (struct nrf51_info
*)bank
->driver_priv
;
208 if (!(*chip
)->probed
)
209 return nrf51_probe(bank
);
214 static int nrf51_wait_for_nvmc(struct nrf51_info
*chip
)
221 res
= target_read_u32(chip
->target
, NRF51_NVMC_READY
, &ready
);
222 if (res
!= ERROR_OK
) {
223 LOG_ERROR("Couldn't read NVMC_READY register");
227 if (ready
== 0x00000001)
233 return ERROR_FLASH_BUSY
;
236 static int nrf51_nvmc_erase_enable(struct nrf51_info
*chip
)
239 res
= target_write_u32(chip
->target
,
241 NRF51_NVMC_CONFIG_EEN
);
243 if (res
!= ERROR_OK
) {
244 LOG_ERROR("Failed to enable erase operation");
249 According to NVMC examples in Nordic SDK busy status must be
250 checked after writing to NVMC_CONFIG
252 res
= nrf51_wait_for_nvmc(chip
);
254 LOG_ERROR("Erase enable did not complete");
259 static int nrf51_nvmc_write_enable(struct nrf51_info
*chip
)
262 res
= target_write_u32(chip
->target
,
264 NRF51_NVMC_CONFIG_WEN
);
266 if (res
!= ERROR_OK
) {
267 LOG_ERROR("Failed to enable write operation");
272 According to NVMC examples in Nordic SDK busy status must be
273 checked after writing to NVMC_CONFIG
275 res
= nrf51_wait_for_nvmc(chip
);
277 LOG_ERROR("Write enable did not complete");
282 static int nrf51_nvmc_read_only(struct nrf51_info
*chip
)
285 res
= target_write_u32(chip
->target
,
287 NRF51_NVMC_CONFIG_REN
);
289 if (res
!= ERROR_OK
) {
290 LOG_ERROR("Failed to enable read-only operation");
294 According to NVMC examples in Nordic SDK busy status must be
295 checked after writing to NVMC_CONFIG
297 res
= nrf51_wait_for_nvmc(chip
);
299 LOG_ERROR("Read only enable did not complete");
304 static int nrf51_nvmc_generic_erase(struct nrf51_info
*chip
,
305 uint32_t erase_register
, uint32_t erase_value
)
309 res
= nrf51_nvmc_erase_enable(chip
);
313 res
= target_write_u32(chip
->target
,
319 res
= nrf51_wait_for_nvmc(chip
);
323 return nrf51_nvmc_read_only(chip
);
326 nrf51_nvmc_read_only(chip
);
328 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32
" val: 0x%08"PRIx32
,
329 erase_register
, erase_value
);
333 static int nrf51_protect_check(struct flash_bank
*bank
)
338 struct nrf51_info
*chip
= (struct nrf51_info
*)bank
->driver_priv
;
340 assert(chip
!= NULL
);
342 res
= target_read_u32(chip
->target
, NRF51_FICR_CLENR0
,
344 if (res
!= ERROR_OK
) {
345 LOG_ERROR("Couldn't read code region 0 size[FICR]");
349 if (clenr0
== 0xFFFFFFFF) {
350 res
= target_read_u32(chip
->target
, NRF51_UICR_CLENR0
,
352 if (res
!= ERROR_OK
) {
353 LOG_ERROR("Couldn't read code region 0 size[UICR]");
358 for (int i
= 0; i
< bank
->num_sectors
; i
++)
359 bank
->sectors
[i
].is_protected
=
360 clenr0
!= 0xFFFFFFFF && bank
->sectors
[i
].offset
< clenr0
;
365 static int nrf51_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
368 uint32_t clenr0
, ppfc
;
369 struct nrf51_info
*chip
;
371 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
376 LOG_ERROR("Code region 0 must start at the begining of the bank");
380 res
= target_read_u32(chip
->target
, NRF51_FICR_PPFC
,
382 if (res
!= ERROR_OK
) {
383 LOG_ERROR("Couldn't read PPFC register");
387 if ((ppfc
& 0xFF) == 0x00) {
388 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
392 res
= target_read_u32(chip
->target
, NRF51_UICR_CLENR0
,
394 if (res
!= ERROR_OK
) {
395 LOG_ERROR("Couldn't read code region 0 size[UICR]");
399 if (clenr0
== 0xFFFFFFFF) {
400 res
= target_write_u32(chip
->target
, NRF51_UICR_CLENR0
,
402 if (res
!= ERROR_OK
) {
403 LOG_ERROR("Couldn't write code region 0 size[UICR]");
408 LOG_ERROR("You need to perform chip erase before changing the protection settings");
411 nrf51_protect_check(bank
);
416 static int nrf51_probe(struct flash_bank
*bank
)
420 struct nrf51_info
*chip
= (struct nrf51_info
*)bank
->driver_priv
;
423 res
= target_read_u32(chip
->target
, NRF51_FICR_CONFIGID
, &hwid
);
424 if (res
!= ERROR_OK
) {
425 LOG_ERROR("Couldn't read CONFIGID register");
429 hwid
&= 0xFFFF; /* HWID is stored in the lower two
430 * bytes of the CONFIGID register */
432 const struct nrf51_device_spec
*spec
= NULL
;
433 for (size_t i
= 0; i
< ARRAY_SIZE(nrf51_known_devices_table
); i
++)
434 if (hwid
== nrf51_known_devices_table
[i
].hwid
) {
435 spec
= &nrf51_known_devices_table
[i
];
440 LOG_INFO("nRF51822-%s(build code: %s) %ukB Flash",
441 spec
->variant
, spec
->build_code
, spec
->flash_size_kb
);
443 LOG_WARNING("Unknown device (HWID 0x%08" PRIx32
")", hwid
);
446 res
= target_read_u32(chip
->target
, NRF51_FICR_CODEPAGESIZE
,
447 &chip
->code_page_size
);
448 if (res
!= ERROR_OK
) {
449 LOG_ERROR("Couldn't read code page size");
453 res
= target_read_u32(chip
->target
, NRF51_FICR_CODESIZE
,
454 &chip
->code_memory_size
);
455 if (res
!= ERROR_OK
) {
456 LOG_ERROR("Couldn't read code memory size");
460 if (spec
&& chip
->code_memory_size
!= spec
->flash_size_kb
) {
461 LOG_ERROR("Chip's reported Flash capacity does not match expected one");
465 bank
->size
= chip
->code_memory_size
* 1024;
466 bank
->num_sectors
= bank
->size
/ chip
->code_page_size
;
467 bank
->sectors
= calloc(bank
->num_sectors
,
468 sizeof((bank
->sectors
)[0]));
470 return ERROR_FLASH_BANK_NOT_PROBED
;
472 /* Fill out the sector information: all NRF51 sectors are the same size and
473 * there is always a fixed number of them. */
474 for (int i
= 0; i
< bank
->num_sectors
; i
++) {
475 bank
->sectors
[i
].size
= chip
->code_page_size
;
476 bank
->sectors
[i
].offset
= i
* chip
->code_page_size
;
478 /* mark as unknown */
479 bank
->sectors
[i
].is_erased
= -1;
480 bank
->sectors
[i
].is_protected
= -1;
483 nrf51_protect_check(bank
);
490 static int nrf51_auto_probe(struct flash_bank
*bank
)
492 struct nrf51_info
*chip
= (struct nrf51_info
*)bank
->driver_priv
;
497 return nrf51_probe(bank
);
500 static struct flash_sector
*nrf51_find_sector_by_address(struct flash_bank
*bank
, uint32_t address
)
502 struct nrf51_info
*chip
= (struct nrf51_info
*)bank
->driver_priv
;
504 for (int i
= 0; i
< bank
->num_sectors
; i
++)
505 if (bank
->sectors
[i
].offset
<= address
&&
506 address
< (bank
->sectors
[i
].offset
+ chip
->code_page_size
))
507 return &bank
->sectors
[i
];
511 static int nrf51_erase_all(struct nrf51_info
*chip
)
513 return nrf51_nvmc_generic_erase(chip
,
518 static int nrf51_erase_page(struct nrf51_info
*chip
, struct flash_sector
*sector
)
522 if (sector
->is_protected
)
525 res
= nrf51_nvmc_generic_erase(chip
,
526 NRF51_NVMC_ERASEPAGE
,
529 sector
->is_erased
= 1;
534 static int nrf51_write_page(struct flash_bank
*bank
, uint32_t offset
, const uint8_t *buffer
)
536 assert(offset
% 4 == 0);
538 int res
= ERROR_FAIL
;
539 struct nrf51_info
*chip
= (struct nrf51_info
*)bank
->driver_priv
;
540 struct flash_sector
*sector
= nrf51_find_sector_by_address(bank
, offset
);
545 if (sector
->is_protected
)
548 if (!sector
->is_erased
) {
549 res
= nrf51_erase_page(chip
, sector
);
554 res
= nrf51_nvmc_write_enable(chip
);
558 sector
->is_erased
= 0;
559 res
= target_write_memory(bank
->target
, offset
, 4,
560 chip
->code_page_size
/ 4, buffer
);
564 return nrf51_nvmc_read_only(chip
);
567 nrf51_nvmc_read_only(chip
);
569 LOG_ERROR("Failed to write sector @ 0x%08"PRIx32
, sector
->offset
);
573 static int nrf51_erase(struct flash_bank
*bank
, int first
, int last
)
576 struct nrf51_info
*chip
;
578 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
582 /* For each sector to be erased */
583 for (int s
= first
; s
<= last
&& res
== ERROR_OK
; s
++)
584 res
= nrf51_erase_page(chip
, &bank
->sectors
[s
]);
589 static int nrf51_write(struct flash_bank
*bank
, const uint8_t *buffer
,
590 uint32_t offset
, uint32_t count
)
596 struct nrf51_info
*chip
;
598 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
602 region
.start
= offset
;
603 region
.end
= offset
+ count
;
607 const uint8_t *buffer
;
608 } start_extra
, end_extra
;
610 start_extra
.length
= region
.start
% chip
->code_page_size
;
611 start_extra
.buffer
= buffer
;
612 end_extra
.length
= region
.end
% chip
->code_page_size
;
613 end_extra
.buffer
= buffer
+ count
- end_extra
.length
;
615 if (start_extra
.length
) {
616 uint8_t page
[chip
->code_page_size
];
618 res
= target_read_memory(bank
->target
,
619 region
.start
- start_extra
.length
,
620 1, start_extra
.length
, page
);
624 memcpy(page
+ start_extra
.length
,
626 chip
->code_page_size
- start_extra
.length
);
628 res
= nrf51_write_page(bank
,
629 region
.start
- start_extra
.length
,
635 if (end_extra
.length
) {
636 uint8_t page
[chip
->code_page_size
];
638 /* Retrieve the full row contents from Flash */
639 res
= target_read_memory(bank
->target
,
642 (chip
->code_page_size
- end_extra
.length
),
643 page
+ end_extra
.length
);
647 memcpy(page
, end_extra
.buffer
, end_extra
.length
);
649 res
= nrf51_write_page(bank
,
650 region
.end
- end_extra
.length
,
657 region
.start
+= start_extra
.length
;
658 region
.end
-= end_extra
.length
;
660 for (uint32_t address
= region
.start
; address
< region
.end
;
661 address
+= chip
->code_page_size
) {
662 res
= nrf51_write_page(bank
, address
, &buffer
[address
- region
.start
]);
672 FLASH_BANK_COMMAND_HANDLER(nrf51_flash_bank_command
)
674 struct nrf51_info
*chip
;
676 /* Create a new chip */
677 chip
= calloc(1, sizeof(*chip
));
681 chip
->target
= bank
->target
;
682 chip
->probed
= false;
684 bank
->driver_priv
= chip
;
686 if (bank
->base
!= NRF51_FLASH_BASE
) {
687 LOG_ERROR("Address 0x%08" PRIx32
" invalid bank address (try 0x%08" PRIx32
689 bank
->base
, NRF51_FLASH_BASE
);
696 COMMAND_HANDLER(nrf51_handle_mass_erase_command
)
699 struct flash_bank
*bank
;
701 res
= get_flash_bank_by_num(0, &bank
);
705 struct nrf51_info
*chip
;
707 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
713 res
= target_read_u32(chip
->target
, NRF51_FICR_PPFC
,
715 if (res
!= ERROR_OK
) {
716 LOG_ERROR("Couldn't read PPFC register");
720 if ((ppfc
& 0xFF) == 0x00) {
721 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
722 "mass erase command won't work.");
726 res
= nrf51_erase_all(chip
);
727 if (res
!= ERROR_OK
) {
728 LOG_ERROR("Failed to erase the chip");
729 nrf51_protect_check(bank
);
733 for (int i
= 0; i
< bank
->num_sectors
; i
++)
734 bank
->sectors
[i
].is_erased
= 1;
736 return nrf51_protect_check(bank
);
739 static int nrf51_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
743 struct nrf51_info
*chip
;
745 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
750 uint32_t address
, value
;
752 { .address
= NRF51_FICR_CODEPAGESIZE
},
753 { .address
= NRF51_FICR_CODESIZE
},
754 { .address
= NRF51_FICR_CLENR0
},
755 { .address
= NRF51_FICR_PPFC
},
756 { .address
= NRF51_FICR_NUMRAMBLOCK
},
757 { .address
= NRF51_FICR_SIZERAMBLOCK0
},
758 { .address
= NRF51_FICR_SIZERAMBLOCK1
},
759 { .address
= NRF51_FICR_SIZERAMBLOCK2
},
760 { .address
= NRF51_FICR_SIZERAMBLOCK3
},
761 { .address
= NRF51_FICR_CONFIGID
},
762 { .address
= NRF51_FICR_DEVICEID0
},
763 { .address
= NRF51_FICR_DEVICEID1
},
764 { .address
= NRF51_FICR_ER0
},
765 { .address
= NRF51_FICR_ER1
},
766 { .address
= NRF51_FICR_ER2
},
767 { .address
= NRF51_FICR_ER3
},
768 { .address
= NRF51_FICR_IR0
},
769 { .address
= NRF51_FICR_IR1
},
770 { .address
= NRF51_FICR_IR2
},
771 { .address
= NRF51_FICR_IR3
},
772 { .address
= NRF51_FICR_DEVICEADDRTYPE
},
773 { .address
= NRF51_FICR_DEVICEADDR0
},
774 { .address
= NRF51_FICR_DEVICEADDR1
},
775 { .address
= NRF51_FICR_OVERRIDEN
},
776 { .address
= NRF51_FICR_NRF_1MBIT0
},
777 { .address
= NRF51_FICR_NRF_1MBIT1
},
778 { .address
= NRF51_FICR_NRF_1MBIT2
},
779 { .address
= NRF51_FICR_NRF_1MBIT3
},
780 { .address
= NRF51_FICR_NRF_1MBIT4
},
781 { .address
= NRF51_FICR_BLE_1MBIT0
},
782 { .address
= NRF51_FICR_BLE_1MBIT1
},
783 { .address
= NRF51_FICR_BLE_1MBIT2
},
784 { .address
= NRF51_FICR_BLE_1MBIT3
},
785 { .address
= NRF51_FICR_BLE_1MBIT4
},
787 { .address
= NRF51_UICR_CLENR0
, },
788 { .address
= NRF51_UICR_RBPCONF
},
789 { .address
= NRF51_UICR_XTALFREQ
},
790 { .address
= NRF51_UICR_FWID
},
793 for (size_t i
= 0; i
< ARRAY_SIZE(ficr
); i
++) {
794 res
= target_read_u32(chip
->target
, ficr
[i
].address
,
796 if (res
!= ERROR_OK
) {
797 LOG_ERROR("Couldn't read %" PRIx32
, ficr
[i
].address
);
802 for (size_t i
= 0; i
< ARRAY_SIZE(uicr
); i
++) {
803 res
= target_read_u32(chip
->target
, uicr
[i
].address
,
805 if (res
!= ERROR_OK
) {
806 LOG_ERROR("Couldn't read %" PRIx32
, uicr
[i
].address
);
811 snprintf(buf
, buf_size
,
812 "\n[factory information control block]\n\n"
813 "code page size: %"PRIu32
"B\n"
814 "code memory size: %"PRIu32
"kB\n"
815 "code region 0 size: %"PRIu32
"kB\n"
816 "pre-programmed code: %s\n"
817 "number of ram blocks: %"PRIu32
"\n"
818 "ram block 0 size: %"PRIu32
"B\n"
819 "ram block 1 size: %"PRIu32
"B\n"
820 "ram block 2 size: %"PRIu32
"B\n"
821 "ram block 3 size: %"PRIu32
"B\n"
822 "config id: %" PRIx32
"\n"
823 "device id: 0x%"PRIx32
"%08"PRIx32
"\n"
824 "encryption root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
825 "identity root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
826 "device address type: 0x%"PRIx32
"\n"
827 "device address: 0x%"PRIx32
"%08"PRIx32
"\n"
828 "override enable: %"PRIx32
"\n"
829 "NRF_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
830 "BLE_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
831 "\n[user information control block]\n\n"
832 "code region 0 size: %"PRIu32
"kB\n"
833 "read back protection configuration: %"PRIx32
"\n"
834 "reset value for XTALFREQ: %"PRIx32
"\n"
835 "firmware id: 0x%04"PRIx32
,
838 (ficr
[2].value
== 0xFFFFFFFF) ? 0 : ficr
[2].value
/ 1024,
839 ((ficr
[3].value
& 0xFF) == 0x00) ? "present" : "not present",
842 (ficr
[6].value
== 0xFFFFFFFF) ? 0 : ficr
[6].value
,
843 (ficr
[7].value
== 0xFFFFFFFF) ? 0 : ficr
[7].value
,
844 (ficr
[8].value
== 0xFFFFFFFF) ? 0 : ficr
[8].value
,
846 ficr
[10].value
, ficr
[11].value
,
847 ficr
[12].value
, ficr
[13].value
, ficr
[14].value
, ficr
[15].value
,
848 ficr
[16].value
, ficr
[17].value
, ficr
[18].value
, ficr
[19].value
,
850 ficr
[21].value
, ficr
[22].value
,
852 ficr
[24].value
, ficr
[25].value
, ficr
[26].value
, ficr
[27].value
, ficr
[28].value
,
853 ficr
[29].value
, ficr
[30].value
, ficr
[31].value
, ficr
[32].value
, ficr
[33].value
,
854 (uicr
[0].value
== 0xFFFFFFFF) ? 0 : uicr
[0].value
/ 1024,
855 uicr
[1].value
& 0xFFFF,
856 uicr
[2].value
& 0xFF,
857 uicr
[3].value
& 0xFFFF);
862 static const struct command_registration nrf51_exec_command_handlers
[] = {
864 .name
= "mass_erase",
865 .handler
= nrf51_handle_mass_erase_command
,
866 .mode
= COMMAND_EXEC
,
867 .help
= "Erase all flash contents of the chip.",
869 COMMAND_REGISTRATION_DONE
872 static const struct command_registration nrf51_command_handlers
[] = {
876 .help
= "nrf51 flash command group",
878 .chain
= nrf51_exec_command_handlers
,
880 COMMAND_REGISTRATION_DONE
883 struct flash_driver nrf51_flash
= {
885 .commands
= nrf51_command_handlers
,
886 .flash_bank_command
= nrf51_flash_bank_command
,
888 .erase
= nrf51_erase
,
889 .protect
= nrf51_protect
,
890 .write
= nrf51_write
,
891 .read
= default_flash_read
,
892 .probe
= nrf51_probe
,
893 .auto_probe
= nrf51_auto_probe
,
894 .erase_check
= default_flash_blank_check
,
895 .protect_check
= nrf51_protect_check
,
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