Code Review / openocd.git / blob
? search:
summary | shortlog | log | commit | commitdiff | review | tree
history | raw | HEAD
nrf51: Add UICR writing support
[openocd.git] / src / flash / nor / nrf51.c
1 /***************************************************************************
2 * Copyright (C) 2013 Synapse Product Development *
3 * Andrey Smirnov <andrew.smironv@gmail.com> *
4 * *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
9 * *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 * *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
20
21 #ifdef HAVE_CONFIG_H
22 #include "config.h"
23 #endif
24
25 #include "imp.h"
26
27 enum {
28 NRF51_FLASH_BASE = 0x00000000,
29 };
30
31 enum nrf51_ficr_registers {
32 NRF51_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
33
34 #define NRF51_FICR_REG(offset) (NRF51_FICR_BASE + offset)
35
36 NRF51_FICR_CODEPAGESIZE = NRF51_FICR_REG(0x010),
37 NRF51_FICR_CODESIZE = NRF51_FICR_REG(0x014),
38 NRF51_FICR_CLENR0 = NRF51_FICR_REG(0x028),
39 NRF51_FICR_PPFC = NRF51_FICR_REG(0x02C),
40 NRF51_FICR_NUMRAMBLOCK = NRF51_FICR_REG(0x034),
41 NRF51_FICR_SIZERAMBLOCK0 = NRF51_FICR_REG(0x038),
42 NRF51_FICR_SIZERAMBLOCK1 = NRF51_FICR_REG(0x03C),
43 NRF51_FICR_SIZERAMBLOCK2 = NRF51_FICR_REG(0x040),
44 NRF51_FICR_SIZERAMBLOCK3 = NRF51_FICR_REG(0x044),
45 NRF51_FICR_CONFIGID = NRF51_FICR_REG(0x05C),
46 NRF51_FICR_DEVICEID0 = NRF51_FICR_REG(0x060),
47 NRF51_FICR_DEVICEID1 = NRF51_FICR_REG(0x064),
48 NRF51_FICR_ER0 = NRF51_FICR_REG(0x080),
49 NRF51_FICR_ER1 = NRF51_FICR_REG(0x084),
50 NRF51_FICR_ER2 = NRF51_FICR_REG(0x088),
51 NRF51_FICR_ER3 = NRF51_FICR_REG(0x08C),
52 NRF51_FICR_IR0 = NRF51_FICR_REG(0x090),
53 NRF51_FICR_IR1 = NRF51_FICR_REG(0x094),
54 NRF51_FICR_IR2 = NRF51_FICR_REG(0x098),
55 NRF51_FICR_IR3 = NRF51_FICR_REG(0x09C),
56 NRF51_FICR_DEVICEADDRTYPE = NRF51_FICR_REG(0x0A0),
57 NRF51_FICR_DEVICEADDR0 = NRF51_FICR_REG(0x0A4),
58 NRF51_FICR_DEVICEADDR1 = NRF51_FICR_REG(0x0A8),
59 NRF51_FICR_OVERRIDEN = NRF51_FICR_REG(0x0AC),
60 NRF51_FICR_NRF_1MBIT0 = NRF51_FICR_REG(0x0B0),
61 NRF51_FICR_NRF_1MBIT1 = NRF51_FICR_REG(0x0B4),
62 NRF51_FICR_NRF_1MBIT2 = NRF51_FICR_REG(0x0B8),
63 NRF51_FICR_NRF_1MBIT3 = NRF51_FICR_REG(0x0BC),
64 NRF51_FICR_NRF_1MBIT4 = NRF51_FICR_REG(0x0C0),
65 NRF51_FICR_BLE_1MBIT0 = NRF51_FICR_REG(0x0EC),
66 NRF51_FICR_BLE_1MBIT1 = NRF51_FICR_REG(0x0F0),
67 NRF51_FICR_BLE_1MBIT2 = NRF51_FICR_REG(0x0F4),
68 NRF51_FICR_BLE_1MBIT3 = NRF51_FICR_REG(0x0F8),
69 NRF51_FICR_BLE_1MBIT4 = NRF51_FICR_REG(0x0FC),
70 };
71
72 enum nrf51_uicr_registers {
73 NRF51_UICR_BASE = 0x10001000, /* User Information
74 * Configuration Regsters */
75
76 NRF51_UICR_SIZE = 252,
77
78 #define NRF51_UICR_REG(offset) (NRF51_UICR_BASE + offset)
79
80 NRF51_UICR_CLENR0 = NRF51_UICR_REG(0x000),
81 NRF51_UICR_RBPCONF = NRF51_UICR_REG(0x004),
82 NRF51_UICR_XTALFREQ = NRF51_UICR_REG(0x008),
83 NRF51_UICR_FWID = NRF51_UICR_REG(0x010),
84 };
85
86 enum nrf51_nvmc_registers {
87 NRF51_NVMC_BASE = 0x4001E000, /* Non-Volatile Memory
88 * Controller Regsters */
89
90 #define NRF51_NVMC_REG(offset) (NRF51_NVMC_BASE + offset)
91
92 NRF51_NVMC_READY = NRF51_NVMC_REG(0x400),
93 NRF51_NVMC_CONFIG = NRF51_NVMC_REG(0x504),
94 NRF51_NVMC_ERASEPAGE = NRF51_NVMC_REG(0x508),
95 NRF51_NVMC_ERASEALL = NRF51_NVMC_REG(0x50C),
96 NRF51_NVMC_ERASEUICR = NRF51_NVMC_REG(0x514),
97 };
98
99 enum nrf51_nvmc_config_bits {
100 NRF51_NVMC_CONFIG_REN = 0x00,
101 NRF51_NVMC_CONFIG_WEN = 0x01,
102 NRF51_NVMC_CONFIG_EEN = 0x02,
103
104 };
105
106 struct nrf51_info {
107 uint32_t code_page_size;
108 uint32_t code_memory_size;
109
110 struct {
111 bool probed;
112 int (*write) (struct flash_bank *bank,
113 struct nrf51_info *chip,
114 const uint8_t *buffer, uint32_t offset, uint32_t count);
115 } bank[2];
116 struct target *target;
117 };
118
119 struct nrf51_device_spec {
120 uint16_t hwid;
121 const char *variant;
122 const char *build_code;
123 unsigned int flash_size_kb;
124 };
125
126 static const struct nrf51_device_spec nrf51_known_devices_table[] = {
127 {
128 .hwid = 0x001D,
129 .variant = "QFAA",
130 .build_code = "CA/C0",
131 .flash_size_kb = 256,
132 },
133 {
134 .hwid = 0x002A,
135 .variant = "QFAA",
136 .build_code = "FA",
137 .flash_size_kb = 256,
138 },
139 {
140 .hwid = 0x0044,
141 .variant = "QFAA",
142 .build_code = "GC",
143 .flash_size_kb = 256,
144 },
145 {
146 .hwid = 0x003C,
147 .variant = "QFAA",
148 .build_code = "G0",
149 .flash_size_kb = 256,
150 },
151
152 {
153 .hwid = 0x0020,
154 .variant = "CEAA",
155 .build_code = "BA",
156 .flash_size_kb = 256,
157 },
158 {
159 .hwid = 0x002F,
160 .variant = "CEAA",
161 .build_code = "B0",
162 .flash_size_kb = 256,
163 },
164 {
165 .hwid = 0x0040,
166 .variant = "CEAA",
167 .build_code = "CA",
168 .flash_size_kb = 256,
169 },
170 {
171 .hwid = 0x0047,
172 .variant = "CEAA",
173 .build_code = "DA",
174 .flash_size_kb = 256,
175 },
176 {
177 .hwid = 0x004D,
178 .variant = "CEAA",
179 .build_code = "D0",
180 .flash_size_kb = 256,
181 },
182
183 {
184 .hwid = 0x0026,
185 .variant = "QFAB",
186 .build_code = "AA",
187 .flash_size_kb = 128,
188 },
189 {
190 .hwid = 0x0027,
191 .variant = "QFAB",
192 .build_code = "A0",
193 .flash_size_kb = 128,
194 },
195 {
196 .hwid = 0x004C,
197 .variant = "QFAB",
198 .build_code = "B0",
199 .flash_size_kb = 128,
200 },
201
202 };
203
204 static int nrf51_bank_is_probed(struct flash_bank *bank)
205 {
206 struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
207
208 assert(chip != NULL);
209
210 return chip->bank[bank->bank_number].probed;
211 }
212 static int nrf51_probe(struct flash_bank *bank);
213
214 static int nrf51_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf51_info **chip)
215 {
216 if (bank->target->state != TARGET_HALTED) {
217 LOG_ERROR("Target not halted");
218 return ERROR_TARGET_NOT_HALTED;
219 }
220
221 *chip = (struct nrf51_info *)bank->driver_priv;
222
223 int probed = nrf51_bank_is_probed(bank);
224 if (probed < 0)
225 return probed;
226 else if (!probed)
227 return nrf51_probe(bank);
228 else
229 return ERROR_OK;
230 }
231
232 static int nrf51_wait_for_nvmc(struct nrf51_info *chip)
233 {
234 uint32_t ready;
235 int res;
236 int timeout = 100;
237
238 do {
239 res = target_read_u32(chip->target, NRF51_NVMC_READY, &ready);
240 if (res != ERROR_OK) {
241 LOG_ERROR("Couldn't read NVMC_READY register");
242 return res;
243 }
244
245 if (ready == 0x00000001)
246 return ERROR_OK;
247
248 alive_sleep(1);
249 } while (timeout--);
250
251 return ERROR_FLASH_BUSY;
252 }
253
254 static int nrf51_nvmc_erase_enable(struct nrf51_info *chip)
255 {
256 int res;
257 res = target_write_u32(chip->target,
258 NRF51_NVMC_CONFIG,
259 NRF51_NVMC_CONFIG_EEN);
260
261 if (res != ERROR_OK) {
262 LOG_ERROR("Failed to enable erase operation");
263 return res;
264 }
265
266 /*
267 According to NVMC examples in Nordic SDK busy status must be
268 checked after writing to NVMC_CONFIG
269 */
270 res = nrf51_wait_for_nvmc(chip);
271 if (res != ERROR_OK)
272 LOG_ERROR("Erase enable did not complete");
273
274 return res;
275 }
276
277 static int nrf51_nvmc_write_enable(struct nrf51_info *chip)
278 {
279 int res;
280 res = target_write_u32(chip->target,
281 NRF51_NVMC_CONFIG,
282 NRF51_NVMC_CONFIG_WEN);
283
284 if (res != ERROR_OK) {
285 LOG_ERROR("Failed to enable write operation");
286 return res;
287 }
288
289 /*
290 According to NVMC examples in Nordic SDK busy status must be
291 checked after writing to NVMC_CONFIG
292 */
293 res = nrf51_wait_for_nvmc(chip);
294 if (res != ERROR_OK)
295 LOG_ERROR("Write enable did not complete");
296
297 return res;
298 }
299
300 static int nrf51_nvmc_read_only(struct nrf51_info *chip)
301 {
302 int res;
303 res = target_write_u32(chip->target,
304 NRF51_NVMC_CONFIG,
305 NRF51_NVMC_CONFIG_REN);
306
307 if (res != ERROR_OK) {
308 LOG_ERROR("Failed to enable read-only operation");
309 return res;
310 }
311 /*
312 According to NVMC examples in Nordic SDK busy status must be
313 checked after writing to NVMC_CONFIG
314 */
315 res = nrf51_wait_for_nvmc(chip);
316 if (res != ERROR_OK)
317 LOG_ERROR("Read only enable did not complete");
318
319 return res;
320 }
321
322 static int nrf51_nvmc_generic_erase(struct nrf51_info *chip,
323 uint32_t erase_register, uint32_t erase_value)
324 {
325 int res;
326
327 res = nrf51_nvmc_erase_enable(chip);
328 if (res != ERROR_OK)
329 goto error;
330
331 res = target_write_u32(chip->target,
332 erase_register,
333 erase_value);
334 if (res != ERROR_OK)
335 goto set_read_only;
336
337 res = nrf51_wait_for_nvmc(chip);
338 if (res != ERROR_OK)
339 goto set_read_only;
340
341 return nrf51_nvmc_read_only(chip);
342
343 set_read_only:
344 nrf51_nvmc_read_only(chip);
345 error:
346 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32" val: 0x%08"PRIx32,
347 erase_register, erase_value);
348 return ERROR_FAIL;
349 }
350
351 static int nrf51_protect_check(struct flash_bank *bank)
352 {
353 int res;
354 uint32_t clenr0;
355
356 /* UICR cannot be write protected so just return early */
357 if (bank->base == NRF51_UICR_BASE)
358 return ERROR_OK;
359
360 struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
361
362 assert(chip != NULL);
363
364 res = target_read_u32(chip->target, NRF51_FICR_CLENR0,
365 &clenr0);
366 if (res != ERROR_OK) {
367 LOG_ERROR("Couldn't read code region 0 size[FICR]");
368 return res;
369 }
370
371 if (clenr0 == 0xFFFFFFFF) {
372 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
373 &clenr0);
374 if (res != ERROR_OK) {
375 LOG_ERROR("Couldn't read code region 0 size[UICR]");
376 return res;
377 }
378 }
379
380 for (int i = 0; i < bank->num_sectors; i++)
381 bank->sectors[i].is_protected =
382 clenr0 != 0xFFFFFFFF && bank->sectors[i].offset < clenr0;
383
384 return ERROR_OK;
385 }
386
387 static int nrf51_protect(struct flash_bank *bank, int set, int first, int last)
388 {
389 int res;
390 uint32_t clenr0, ppfc;
391 struct nrf51_info *chip;
392
393 /* UICR cannot be write protected so just bail out early */
394 if (bank->base == NRF51_UICR_BASE)
395 return ERROR_FAIL;
396
397 res = nrf51_get_probed_chip_if_halted(bank, &chip);
398 if (res != ERROR_OK)
399 return res;
400
401 if (first != 0) {
402 LOG_ERROR("Code region 0 must start at the begining of the bank");
403 return ERROR_FAIL;
404 }
405
406 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
407 &ppfc);
408 if (res != ERROR_OK) {
409 LOG_ERROR("Couldn't read PPFC register");
410 return res;
411 }
412
413 if ((ppfc & 0xFF) == 0x00) {
414 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
415 return ERROR_FAIL;
416 };
417
418 res = target_read_u32(chip->target, NRF51_UICR_CLENR0,
419 &clenr0);
420 if (res != ERROR_OK) {
421 LOG_ERROR("Couldn't read code region 0 size[UICR]");
422 return res;
423 }
424
425 if (clenr0 == 0xFFFFFFFF) {
426 res = target_write_u32(chip->target, NRF51_UICR_CLENR0,
427 clenr0);
428 if (res != ERROR_OK) {
429 LOG_ERROR("Couldn't write code region 0 size[UICR]");
430 return res;
431 }
432
433 } else {
434 LOG_ERROR("You need to perform chip erase before changing the protection settings");
435 }
436
437 nrf51_protect_check(bank);
438
439 return ERROR_OK;
440 }
441
442 static int nrf51_probe(struct flash_bank *bank)
443 {
444 uint32_t hwid;
445 int res;
446 struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
447
448 res = target_read_u32(chip->target, NRF51_FICR_CONFIGID, &hwid);
449 if (res != ERROR_OK) {
450 LOG_ERROR("Couldn't read CONFIGID register");
451 return res;
452 }
453
454 hwid &= 0xFFFF; /* HWID is stored in the lower two
455 * bytes of the CONFIGID register */
456
457 const struct nrf51_device_spec *spec = NULL;
458 for (size_t i = 0; i < ARRAY_SIZE(nrf51_known_devices_table); i++)
459 if (hwid == nrf51_known_devices_table[i].hwid) {
460 spec = &nrf51_known_devices_table[i];
461 break;
462 }
463
464 if (!chip->bank[0].probed && !chip->bank[1].probed) {
465 if (spec)
466 LOG_INFO("nRF51822-%s(build code: %s) %ukB Flash",
467 spec->variant, spec->build_code, spec->flash_size_kb);
468 else
469 LOG_WARNING("Unknown device (HWID 0x%08" PRIx32 ")", hwid);
470 }
471
472
473 if (bank->base == NRF51_FLASH_BASE) {
474 res = target_read_u32(chip->target, NRF51_FICR_CODEPAGESIZE,
475 &chip->code_page_size);
476 if (res != ERROR_OK) {
477 LOG_ERROR("Couldn't read code page size");
478 return res;
479 }
480
481 res = target_read_u32(chip->target, NRF51_FICR_CODESIZE,
482 &chip->code_memory_size);
483 if (res != ERROR_OK) {
484 LOG_ERROR("Couldn't read code memory size");
485 return res;
486 }
487
488 if (spec && chip->code_memory_size != spec->flash_size_kb) {
489 LOG_ERROR("Chip's reported Flash capacity does not match expected one");
490 return ERROR_FAIL;
491 }
492
493 bank->size = chip->code_memory_size * 1024;
494 bank->num_sectors = bank->size / chip->code_page_size;
495 bank->sectors = calloc(bank->num_sectors,
496 sizeof((bank->sectors)[0]));
497 if (!bank->sectors)
498 return ERROR_FLASH_BANK_NOT_PROBED;
499
500 /* Fill out the sector information: all NRF51 sectors are the same size and
501 * there is always a fixed number of them. */
502 for (int i = 0; i < bank->num_sectors; i++) {
503 bank->sectors[i].size = chip->code_page_size;
504 bank->sectors[i].offset = i * chip->code_page_size;
505
506 /* mark as unknown */
507 bank->sectors[i].is_erased = -1;
508 bank->sectors[i].is_protected = -1;
509 }
510
511 nrf51_protect_check(bank);
512
513 chip->bank[0].probed = true;
514 } else {
515 bank->size = NRF51_UICR_SIZE;
516 bank->num_sectors = 1;
517 bank->sectors = calloc(bank->num_sectors,
518 sizeof((bank->sectors)[0]));
519 if (!bank->sectors)
520 return ERROR_FLASH_BANK_NOT_PROBED;
521
522 bank->sectors[0].size = bank->size;
523 bank->sectors[0].offset = 0;
524
525 /* mark as unknown */
526 bank->sectors[0].is_erased = 0;
527 bank->sectors[0].is_protected = 0;
528
529 chip->bank[1].probed = true;
530 }
531
532 return ERROR_OK;
533 }
534
535 static int nrf51_auto_probe(struct flash_bank *bank)
536 {
537 int probed = nrf51_bank_is_probed(bank);
538
539 if (probed < 0)
540 return probed;
541 else if (probed)
542 return ERROR_OK;
543 else
544 return nrf51_probe(bank);
545 }
546
547 static struct flash_sector *nrf51_find_sector_by_address(struct flash_bank *bank, uint32_t address)
548 {
549 struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
550
551 for (int i = 0; i < bank->num_sectors; i++)
552 if (bank->sectors[i].offset <= address &&
553 address < (bank->sectors[i].offset + chip->code_page_size))
554 return &bank->sectors[i];
555 return NULL;
556 }
557
558 static int nrf51_erase_all(struct nrf51_info *chip)
559 {
560 return nrf51_nvmc_generic_erase(chip,
561 NRF51_NVMC_ERASEALL,
562 0x00000001);
563 }
564
565 static int nrf51_erase_page(struct nrf51_info *chip, struct flash_sector *sector)
566 {
567 int res;
568
569 if (sector->is_protected)
570 return ERROR_FAIL;
571
572 if (sector->offset == NRF51_UICR_BASE) {
573 uint32_t ppfc;
574 res = target_read_u32(chip->target, NRF51_FICR_PPFC,
575 &ppfc);
576 if (res != ERROR_OK) {
577 LOG_ERROR("Couldn't read PPFC register");
578 return res;
579 }
580
581 if ((ppfc & 0xFF) == 0xFF) {
582 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
583 return ERROR_FAIL;
584 };
585
586 res = nrf51_nvmc_generic_erase(chip,
587 NRF51_NVMC_ERASEUICR,
588 0x00000001);
589
590
591 } else {
592 res = nrf51_nvmc_generic_erase(chip,
593 NRF51_NVMC_ERASEPAGE,
594 sector->offset);
595 }
596
597 if (res == ERROR_OK)
598 sector->is_erased = 1;
599
600 return res;
601 }
602
603 static int nrf51_write_page(struct flash_bank *bank, uint32_t offset, const uint8_t *buffer)
604 {
605 assert(offset % 4 == 0);
606
607 int res = ERROR_FAIL;
608 struct nrf51_info *chip = (struct nrf51_info *)bank->driver_priv;
609 struct flash_sector *sector = nrf51_find_sector_by_address(bank, offset);
610
611 if (!sector)
612 goto error;
613
614 if (sector->is_protected)
615 goto error;
616
617 if (!sector->is_erased) {
618 res = nrf51_erase_page(chip, sector);
619 if (res != ERROR_OK) {
620 LOG_ERROR("Failed to erase sector @ 0x%08"PRIx32, sector->offset);
621 goto error;
622 }
623 }
624
625 res = nrf51_nvmc_write_enable(chip);
626 if (res != ERROR_OK)
627 goto error;
628
629 sector->is_erased = 0;
630 res = target_write_memory(bank->target, offset, 4,
631 chip->code_page_size / 4, buffer);
632 if (res != ERROR_OK)
633 goto set_read_only;
634
635 return nrf51_nvmc_read_only(chip);
636
637 set_read_only:
638 nrf51_nvmc_read_only(chip);
639 error:
640 LOG_ERROR("Failed to write sector @ 0x%08"PRIx32, sector->offset);
641 return res;
642 }
643
644 static int nrf51_erase(struct flash_bank *bank, int first, int last)
645 {
646 int res;
647 struct nrf51_info *chip;
648
649 res = nrf51_get_probed_chip_if_halted(bank, &chip);
650 if (res != ERROR_OK)
651 return res;
652
653 /* For each sector to be erased */
654 for (int s = first; s <= last && res == ERROR_OK; s++)
655 res = nrf51_erase_page(chip, &bank->sectors[s]);
656
657 return res;
658 }
659
660 static int nrf51_code_flash_write(struct flash_bank *bank,
661 struct nrf51_info *chip,
662 const uint8_t *buffer, uint32_t offset, uint32_t count)
663 {
664 int res;
665 struct {
666 uint32_t start, end;
667 } region;
668
669 region.start = offset;
670 region.end = offset + count;
671
672 struct {
673 size_t length;
674 const uint8_t *buffer;
675 } start_extra, end_extra;
676
677 start_extra.length = region.start % chip->code_page_size;
678 start_extra.buffer = buffer;
679 end_extra.length = region.end % chip->code_page_size;
680 end_extra.buffer = buffer + count - end_extra.length;
681
682 if (start_extra.length) {
683 uint8_t page[chip->code_page_size];
684
685 res = target_read_memory(bank->target,
686 region.start - start_extra.length,
687 1, start_extra.length, page);
688 if (res != ERROR_OK)
689 return res;
690
691 memcpy(page + start_extra.length,
692 start_extra.buffer,
693 chip->code_page_size - start_extra.length);
694
695 res = nrf51_write_page(bank,
696 region.start - start_extra.length,
697 page);
698 if (res != ERROR_OK)
699 return res;
700 }
701
702 if (end_extra.length) {
703 uint8_t page[chip->code_page_size];
704
705 /* Retrieve the full row contents from Flash */
706 res = target_read_memory(bank->target,
707 region.end,
708 1,
709 (chip->code_page_size - end_extra.length),
710 page + end_extra.length);
711 if (res != ERROR_OK)
712 return res;
713
714 memcpy(page, end_extra.buffer, end_extra.length);
715
716 res = nrf51_write_page(bank,
717 region.end - end_extra.length,
718 page);
719 if (res != ERROR_OK)
720 return res;
721 }
722
723
724 region.start += start_extra.length;
725 region.end -= end_extra.length;
726
727 for (uint32_t address = region.start; address < region.end;
728 address += chip->code_page_size) {
729 res = nrf51_write_page(bank, address, &buffer[address - region.start]);
730
731 if (res != ERROR_OK)
732 return res;
733
734 }
735
736 return ERROR_OK;
737 }
738
739 static int nrf51_uicr_flash_write(struct flash_bank *bank,
740 struct nrf51_info *chip,
741 const uint8_t *buffer, uint32_t offset, uint32_t count)
742 {
743 int res;
744 uint8_t uicr[NRF51_UICR_SIZE];
745 struct flash_sector *sector = &bank->sectors[0];
746
747 if ((offset + count) > NRF51_UICR_SIZE)
748 return ERROR_FAIL;
749
750 res = target_read_memory(bank->target,
751 NRF51_UICR_BASE,
752 1,
753 NRF51_UICR_SIZE,
754 uicr);
755
756 if (res != ERROR_OK)
757 return res;
758
759 if (!sector->is_erased) {
760 res = nrf51_erase_page(chip, sector);
761 if (res != ERROR_OK)
762 return res;
763 }
764
765 res = nrf51_nvmc_write_enable(chip);
766 if (res != ERROR_OK)
767 return res;
768
769 memcpy(&uicr[offset], buffer, count);
770
771 res = target_write_memory(bank->target,
772 NRF51_UICR_BASE,
773 4,
774 NRF51_UICR_SIZE / 4,
775 uicr);
776 if (res != ERROR_OK) {
777 nrf51_nvmc_read_only(chip);
778 return res;
779 }
780
781 return nrf51_nvmc_read_only(chip);
782 }
783
784
785 static int nrf51_write(struct flash_bank *bank, const uint8_t *buffer,
786 uint32_t offset, uint32_t count)
787 {
788 int res;
789 struct nrf51_info *chip;
790
791 res = nrf51_get_probed_chip_if_halted(bank, &chip);
792 if (res != ERROR_OK)
793 return res;
794
795 return chip->bank[bank->bank_number].write(bank, chip, buffer, offset, count);
796 }
797
798
799 FLASH_BANK_COMMAND_HANDLER(nrf51_flash_bank_command)
800 {
801 static struct nrf51_info *chip;
802
803 switch (bank->base) {
804 case NRF51_FLASH_BASE:
805 bank->bank_number = 0;
806 break;
807 case NRF51_UICR_BASE:
808 bank->bank_number = 1;
809 break;
810 default:
811 LOG_ERROR("Invalid bank address 0x%08" PRIx32, bank->base);
812 return ERROR_FAIL;
813 }
814
815 if (!chip) {
816 /* Create a new chip */
817 chip = calloc(1, sizeof(*chip));
818 if (!chip)
819 return ERROR_FAIL;
820
821 chip->target = bank->target;
822 }
823
824 switch (bank->base) {
825 case NRF51_FLASH_BASE:
826 chip->bank[bank->bank_number].write = nrf51_code_flash_write;
827 break;
828 case NRF51_UICR_BASE:
829 chip->bank[bank->bank_number].write = nrf51_uicr_flash_write;
830 break;
831 }
832
833 chip->bank[bank->bank_number].probed = false;
834 bank->driver_priv = chip;
835
836 return ERROR_OK;
837 }
838
839 COMMAND_HANDLER(nrf51_handle_mass_erase_command)
840 {
841 int res;
842 struct flash_bank *bank = NULL;
843 struct target *target = get_current_target(CMD_CTX);
844
845 res = get_flash_bank_by_addr(target, NRF51_FLASH_BASE, true, &bank);
846 if (res != ERROR_OK)
847 return res;
848
849 assert(bank != NULL);
850
851 struct nrf51_info *chip;
852
853 res = nrf51_get_probed_chip_if_halted(bank, &chip);
854 if (res != ERROR_OK)
855 return res;
856
857 uint32_t ppfc;
858
859 res = target_read_u32(target, NRF51_FICR_PPFC,
860 &ppfc);
861 if (res != ERROR_OK) {
862 LOG_ERROR("Couldn't read PPFC register");
863 return res;
864 }
865
866 if ((ppfc & 0xFF) == 0x00) {
867 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
868 "mass erase command won't work.");
869 return ERROR_FAIL;
870 };
871
872 res = nrf51_erase_all(chip);
873 if (res != ERROR_OK) {
874 LOG_ERROR("Failed to erase the chip");
875 nrf51_protect_check(bank);
876 return res;
877 }
878
879 for (int i = 0; i < bank->num_sectors; i++)
880 bank->sectors[i].is_erased = 1;
881
882 res = nrf51_protect_check(bank);
883 if (res != ERROR_OK) {
884 LOG_ERROR("Failed to check chip's write protection");
885 return res;
886 }
887
888 res = get_flash_bank_by_addr(target, NRF51_UICR_BASE, true, &bank);
889 if (res != ERROR_OK)
890 return res;
891
892 bank->sectors[0].is_erased = 1;
893
894 return ERROR_OK;
895 }
896
897 static int nrf51_info(struct flash_bank *bank, char *buf, int buf_size)
898 {
899 int res;
900
901 struct nrf51_info *chip;
902
903 res = nrf51_get_probed_chip_if_halted(bank, &chip);
904 if (res != ERROR_OK)
905 return res;
906
907 struct {
908 uint32_t address, value;
909 } ficr[] = {
910 { .address = NRF51_FICR_CODEPAGESIZE },
911 { .address = NRF51_FICR_CODESIZE },
912 { .address = NRF51_FICR_CLENR0 },
913 { .address = NRF51_FICR_PPFC },
914 { .address = NRF51_FICR_NUMRAMBLOCK },
915 { .address = NRF51_FICR_SIZERAMBLOCK0 },
916 { .address = NRF51_FICR_SIZERAMBLOCK1 },
917 { .address = NRF51_FICR_SIZERAMBLOCK2 },
918 { .address = NRF51_FICR_SIZERAMBLOCK3 },
919 { .address = NRF51_FICR_CONFIGID },
920 { .address = NRF51_FICR_DEVICEID0 },
921 { .address = NRF51_FICR_DEVICEID1 },
922 { .address = NRF51_FICR_ER0 },
923 { .address = NRF51_FICR_ER1 },
924 { .address = NRF51_FICR_ER2 },
925 { .address = NRF51_FICR_ER3 },
926 { .address = NRF51_FICR_IR0 },
927 { .address = NRF51_FICR_IR1 },
928 { .address = NRF51_FICR_IR2 },
929 { .address = NRF51_FICR_IR3 },
930 { .address = NRF51_FICR_DEVICEADDRTYPE },
931 { .address = NRF51_FICR_DEVICEADDR0 },
932 { .address = NRF51_FICR_DEVICEADDR1 },
933 { .address = NRF51_FICR_OVERRIDEN },
934 { .address = NRF51_FICR_NRF_1MBIT0 },
935 { .address = NRF51_FICR_NRF_1MBIT1 },
936 { .address = NRF51_FICR_NRF_1MBIT2 },
937 { .address = NRF51_FICR_NRF_1MBIT3 },
938 { .address = NRF51_FICR_NRF_1MBIT4 },
939 { .address = NRF51_FICR_BLE_1MBIT0 },
940 { .address = NRF51_FICR_BLE_1MBIT1 },
941 { .address = NRF51_FICR_BLE_1MBIT2 },
942 { .address = NRF51_FICR_BLE_1MBIT3 },
943 { .address = NRF51_FICR_BLE_1MBIT4 },
944 }, uicr[] = {
945 { .address = NRF51_UICR_CLENR0, },
946 { .address = NRF51_UICR_RBPCONF },
947 { .address = NRF51_UICR_XTALFREQ },
948 { .address = NRF51_UICR_FWID },
949 };
950
951 for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) {
952 res = target_read_u32(chip->target, ficr[i].address,
953 &ficr[i].value);
954 if (res != ERROR_OK) {
955 LOG_ERROR("Couldn't read %" PRIx32, ficr[i].address);
956 return res;
957 }
958 }
959
960 for (size_t i = 0; i < ARRAY_SIZE(uicr); i++) {
961 res = target_read_u32(chip->target, uicr[i].address,
962 &uicr[i].value);
963 if (res != ERROR_OK) {
964 LOG_ERROR("Couldn't read %" PRIx32, uicr[i].address);
965 return res;
966 }
967 }
968
969 snprintf(buf, buf_size,
970 "\n[factory information control block]\n\n"
971 "code page size: %"PRIu32"B\n"
972 "code memory size: %"PRIu32"kB\n"
973 "code region 0 size: %"PRIu32"kB\n"
974 "pre-programmed code: %s\n"
975 "number of ram blocks: %"PRIu32"\n"
976 "ram block 0 size: %"PRIu32"B\n"
977 "ram block 1 size: %"PRIu32"B\n"
978 "ram block 2 size: %"PRIu32"B\n"
979 "ram block 3 size: %"PRIu32 "B\n"
980 "config id: %" PRIx32 "\n"
981 "device id: 0x%"PRIx32"%08"PRIx32"\n"
982 "encryption root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
983 "identity root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
984 "device address type: 0x%"PRIx32"\n"
985 "device address: 0x%"PRIx32"%08"PRIx32"\n"
986 "override enable: %"PRIx32"\n"
987 "NRF_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
988 "BLE_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
989 "\n[user information control block]\n\n"
990 "code region 0 size: %"PRIu32"kB\n"
991 "read back protection configuration: %"PRIx32"\n"
992 "reset value for XTALFREQ: %"PRIx32"\n"
993 "firmware id: 0x%04"PRIx32,
994 ficr[0].value,
995 ficr[1].value,
996 (ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024,
997 ((ficr[3].value & 0xFF) == 0x00) ? "present" : "not present",
998 ficr[4].value,
999 ficr[5].value,
1000 (ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value,
1001 (ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value,
1002 (ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value,
1003 ficr[9].value,
1004 ficr[10].value, ficr[11].value,
1005 ficr[12].value, ficr[13].value, ficr[14].value, ficr[15].value,
1006 ficr[16].value, ficr[17].value, ficr[18].value, ficr[19].value,
1007 ficr[20].value,
1008 ficr[21].value, ficr[22].value,
1009 ficr[23].value,
1010 ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, ficr[28].value,
1011 ficr[29].value, ficr[30].value, ficr[31].value, ficr[32].value, ficr[33].value,
1012 (uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024,
1013 uicr[1].value & 0xFFFF,
1014 uicr[2].value & 0xFF,
1015 uicr[3].value & 0xFFFF);
1016
1017 return ERROR_OK;
1018 }
1019
1020 static const struct command_registration nrf51_exec_command_handlers[] = {
1021 {
1022 .name = "mass_erase",
1023 .handler = nrf51_handle_mass_erase_command,
1024 .mode = COMMAND_EXEC,
1025 .help = "Erase all flash contents of the chip.",
1026 },
1027 COMMAND_REGISTRATION_DONE
1028 };
1029
1030 static const struct command_registration nrf51_command_handlers[] = {
1031 {
1032 .name = "nrf51",
1033 .mode = COMMAND_ANY,
1034 .help = "nrf51 flash command group",
1035 .usage = "",
1036 .chain = nrf51_exec_command_handlers,
1037 },
1038 COMMAND_REGISTRATION_DONE
1039 };
1040
1041 struct flash_driver nrf51_flash = {
1042 .name = "nrf51",
1043 .commands = nrf51_command_handlers,
1044 .flash_bank_command = nrf51_flash_bank_command,
1045 .info = nrf51_info,
1046 .erase = nrf51_erase,
1047 .protect = nrf51_protect,
1048 .write = nrf51_write,
1049 .read = default_flash_read,
1050 .probe = nrf51_probe,
1051 .auto_probe = nrf51_auto_probe,
1052 .erase_check = default_flash_blank_check,
1053 .protect_check = nrf51_protect_check,
1054 };
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)