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jtag: linuxgpiod: drop extra parenthesis
[openocd.git] / src / flash / nor / renesas_rpchf.c
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Renesas RCar Gen3 RPC Hyperflash driver
4 * Based on U-Boot RPC Hyperflash driver
5 *
6 * Copyright (C) 2016 Renesas Electronics Corporation
7 * Copyright (C) 2016 Cogent Embedded, Inc.
8 * Copyright (C) 2017-2019 Marek Vasut <marek.vasut@gmail.com>
9 */
10
11 #ifdef HAVE_CONFIG_H
12 #include "config.h"
13 #endif
14
15 #include "imp.h"
16 #include "cfi.h"
17 #include "non_cfi.h"
18 #include <helper/binarybuffer.h>
19 #include <helper/bits.h>
20 #include <helper/time_support.h>
21
22 #define RPC_CMNCR 0x0000 /* R/W */
23 #define RPC_CMNCR_MD BIT(31)
24 #define RPC_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
25 #define RPC_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
26 #define RPC_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
27 #define RPC_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
28 #define RPC_CMNCR_MOIIO_HIZ (RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_MOIIO1(3) | \
29 RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO3(3))
30 #define RPC_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
31 #define RPC_CMNCR_IO2FV(val) (((val) & 0x3) << 12)
32 #define RPC_CMNCR_IO3FV(val) (((val) & 0x3) << 14)
33 #define RPC_CMNCR_IOFV_HIZ (RPC_CMNCR_IO0FV(3) | RPC_CMNCR_IO2FV(3) | \
34 RPC_CMNCR_IO3FV(3))
35 #define RPC_CMNCR_BSZ(val) (((val) & 0x3) << 0)
36
37 #define RPC_SSLDR 0x0004 /* R/W */
38 #define RPC_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
39 #define RPC_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
40 #define RPC_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
41
42 #define RPC_DRCR 0x000C /* R/W */
43 #define RPC_DRCR_SSLN BIT(24)
44 #define RPC_DRCR_RBURST(v) (((v) & 0x1F) << 16)
45 #define RPC_DRCR_RCF BIT(9)
46 #define RPC_DRCR_RBE BIT(8)
47 #define RPC_DRCR_SSLE BIT(0)
48
49 #define RPC_DRCMR 0x0010 /* R/W */
50 #define RPC_DRCMR_CMD(c) (((c) & 0xFF) << 16)
51 #define RPC_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
52
53 #define RPC_DREAR 0x0014 /* R/W */
54 #define RPC_DREAR_EAV(v) (((v) & 0xFF) << 16)
55 #define RPC_DREAR_EAC(v) (((v) & 0x7) << 0)
56
57 #define RPC_DROPR 0x0018 /* R/W */
58 #define RPC_DROPR_OPD3(o) (((o) & 0xFF) << 24)
59 #define RPC_DROPR_OPD2(o) (((o) & 0xFF) << 16)
60 #define RPC_DROPR_OPD1(o) (((o) & 0xFF) << 8)
61 #define RPC_DROPR_OPD0(o) (((o) & 0xFF) << 0)
62
63 #define RPC_DRENR 0x001C /* R/W */
64 #define RPC_DRENR_CDB(o) (uint32_t)((((o) & 0x3) << 30))
65 #define RPC_DRENR_OCDB(o) (((o) & 0x3) << 28)
66 #define RPC_DRENR_ADB(o) (((o) & 0x3) << 24)
67 #define RPC_DRENR_OPDB(o) (((o) & 0x3) << 20)
68 #define RPC_DRENR_SPIDB(o) (((o) & 0x3) << 16)
69 #define RPC_DRENR_DME BIT(15)
70 #define RPC_DRENR_CDE BIT(14)
71 #define RPC_DRENR_OCDE BIT(12)
72 #define RPC_DRENR_ADE(v) (((v) & 0xF) << 8)
73 #define RPC_DRENR_OPDE(v) (((v) & 0xF) << 4)
74
75 #define RPC_SMCR 0x0020 /* R/W */
76 #define RPC_SMCR_SSLKP BIT(8)
77 #define RPC_SMCR_SPIRE BIT(2)
78 #define RPC_SMCR_SPIWE BIT(1)
79 #define RPC_SMCR_SPIE BIT(0)
80
81 #define RPC_SMCMR 0x0024 /* R/W */
82 #define RPC_SMCMR_CMD(c) (((c) & 0xFF) << 16)
83 #define RPC_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
84
85 #define RPC_SMADR 0x0028 /* R/W */
86 #define RPC_SMOPR 0x002C /* R/W */
87 #define RPC_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
88 #define RPC_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
89 #define RPC_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
90 #define RPC_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
91
92 #define RPC_SMENR 0x0030 /* R/W */
93 #define RPC_SMENR_CDB(o) (((o) & 0x3) << 30)
94 #define RPC_SMENR_OCDB(o) (((o) & 0x3) << 28)
95 #define RPC_SMENR_ADB(o) (((o) & 0x3) << 24)
96 #define RPC_SMENR_OPDB(o) (((o) & 0x3) << 20)
97 #define RPC_SMENR_SPIDB(o) (((o) & 0x3) << 16)
98 #define RPC_SMENR_DME BIT(15)
99 #define RPC_SMENR_CDE BIT(14)
100 #define RPC_SMENR_OCDE BIT(12)
101 #define RPC_SMENR_ADE(v) (((v) & 0xF) << 8)
102 #define RPC_SMENR_OPDE(v) (((v) & 0xF) << 4)
103 #define RPC_SMENR_SPIDE(v) (((v) & 0xF) << 0)
104
105 #define RPC_SMRDR0 0x0038 /* R */
106 #define RPC_SMRDR1 0x003C /* R */
107 #define RPC_SMWDR0 0x0040 /* R/W */
108 #define RPC_SMWDR1 0x0044 /* R/W */
109 #define RPC_CMNSR 0x0048 /* R */
110 #define RPC_CMNSR_SSLF BIT(1)
111 #define RPC_CMNSR_TEND BIT(0)
112
113 #define RPC_DRDMCR 0x0058 /* R/W */
114 #define RPC_DRDMCR_DMCYC(v) (((v) & 0xF) << 0)
115
116 #define RPC_DRDRENR 0x005C /* R/W */
117 #define RPC_DRDRENR_HYPE (0x5 << 12)
118 #define RPC_DRDRENR_ADDRE BIT(8)
119 #define RPC_DRDRENR_OPDRE BIT(4)
120 #define RPC_DRDRENR_DRDRE BIT(0)
121
122 #define RPC_SMDMCR 0x0060 /* R/W */
123 #define RPC_SMDMCR_DMCYC(v) (((v) & 0xF) << 0)
124
125 #define RPC_SMDRENR 0x0064 /* R/W */
126 #define RPC_SMDRENR_HYPE (0x5 << 12)
127 #define RPC_SMDRENR_ADDRE BIT(8)
128 #define RPC_SMDRENR_OPDRE BIT(4)
129 #define RPC_SMDRENR_SPIDRE BIT(0)
130
131 #define RPC_PHYCNT 0x007C /* R/W */
132 #define RPC_PHYCNT_CAL BIT(31)
133 #define PRC_PHYCNT_OCTA_AA BIT(22)
134 #define PRC_PHYCNT_OCTA_SA BIT(23)
135 #define PRC_PHYCNT_EXDS BIT(21)
136 #define RPC_PHYCNT_OCT BIT(20)
137 #define RPC_PHYCNT_WBUF2 BIT(4)
138 #define RPC_PHYCNT_WBUF BIT(2)
139 #define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0)
140
141 #define RPC_PHYINT 0x0088 /* R/W */
142 #define RPC_PHYINT_RSTEN BIT(18)
143 #define RPC_PHYINT_WPEN BIT(17)
144 #define RPC_PHYINT_INTEN BIT(16)
145 #define RPC_PHYINT_RST BIT(2)
146 #define RPC_PHYINT_WP BIT(1)
147 #define RPC_PHYINT_INT BIT(0)
148
149 #define RPC_WBUF 0x8000 /* R/W size=4/8/16/32/64Bytes */
150 #define RPC_WBUF_SIZE 0x100
151
152 static uint32_t rpc_base = 0xee200000;
153 static uint32_t mem_base = 0x08000000;
154
155 enum rpc_hf_size {
156 RPC_HF_SIZE_16BIT = RPC_SMENR_SPIDE(0x8),
157 RPC_HF_SIZE_32BIT = RPC_SMENR_SPIDE(0xC),
158 RPC_HF_SIZE_64BIT = RPC_SMENR_SPIDE(0xF),
159 };
160
161 static int rpc_hf_wait_tend(struct target *target)
162 {
163 uint32_t reg = rpc_base + RPC_CMNSR;
164 uint32_t val;
165 unsigned long timeout = 1000;
166 long long endtime;
167 int ret;
168
169 endtime = timeval_ms() + timeout;
170 do {
171 ret = target_read_u32(target, reg, &val);
172 if (ret != ERROR_OK)
173 return ERROR_FAIL;
174
175 if (val & RPC_CMNSR_TEND)
176 return ERROR_OK;
177
178 alive_sleep(1);
179 } while (timeval_ms() < endtime);
180
181 LOG_ERROR("timeout");
182 return ERROR_TIMEOUT_REACHED;
183 }
184
185 static int clrsetbits_u32(struct target *target, uint32_t reg,
186 uint32_t clr, uint32_t set)
187 {
188 uint32_t val;
189 int ret;
190
191 ret = target_read_u32(target, reg, &val);
192 if (ret != ERROR_OK)
193 return ret;
194
195 val &= ~clr;
196 val |= set;
197
198 return target_write_u32(target, reg, val);
199 }
200
201 static int rpc_hf_mode(struct target *target, bool manual)
202 {
203 uint32_t val;
204 int ret;
205
206 ret = rpc_hf_wait_tend(target);
207 if (ret != ERROR_OK) {
208 LOG_ERROR("Mode TEND timeout");
209 return ret;
210 }
211
212 ret = clrsetbits_u32(target, rpc_base + RPC_PHYCNT,
213 RPC_PHYCNT_WBUF | RPC_PHYCNT_WBUF2 |
214 RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3),
215 RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3));
216 if (ret != ERROR_OK)
217 return ret;
218
219 ret = clrsetbits_u32(target, rpc_base + RPC_CMNCR,
220 RPC_CMNCR_MD | RPC_CMNCR_BSZ(3),
221 RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ |
222 (manual ? RPC_CMNCR_MD : 0) | RPC_CMNCR_BSZ(1));
223 if (ret != ERROR_OK)
224 return ret;
225
226 if (manual)
227 return ERROR_OK;
228
229 ret = target_write_u32(target, rpc_base + RPC_DRCR,
230 RPC_DRCR_RBURST(0x1F) | RPC_DRCR_RCF |
231 RPC_DRCR_RBE);
232 if (ret != ERROR_OK)
233 return ret;
234
235 ret = target_write_u32(target, rpc_base + RPC_DRCMR,
236 RPC_DRCMR_CMD(0xA0));
237 if (ret != ERROR_OK)
238 return ret;
239 ret = target_write_u32(target, rpc_base + RPC_DRENR,
240 RPC_DRENR_CDB(2) | RPC_DRENR_OCDB(2) |
241 RPC_DRENR_ADB(2) | RPC_DRENR_SPIDB(2) |
242 RPC_DRENR_CDE | RPC_DRENR_OCDE |
243 RPC_DRENR_ADE(4));
244 if (ret != ERROR_OK)
245 return ret;
246
247 ret = target_write_u32(target, rpc_base + RPC_DRDMCR,
248 RPC_DRDMCR_DMCYC(0xE));
249 if (ret != ERROR_OK)
250 return ret;
251
252 ret = target_write_u32(target, rpc_base + RPC_DRDRENR,
253 RPC_DRDRENR_HYPE | RPC_DRDRENR_ADDRE |
254 RPC_DRDRENR_DRDRE);
255 if (ret != ERROR_OK)
256 return ret;
257
258 /* Dummy read */
259 return target_read_u32(target, rpc_base + RPC_DRCR, &val);
260 }
261
262 static int rpc_hf_xfer(struct target *target, target_addr_t addr,
263 uint32_t wdata, uint32_t *rdata, enum rpc_hf_size size,
264 bool write, const uint8_t *wbuf, unsigned int wbuf_size)
265 {
266 int ret;
267 uint32_t val;
268
269 if (wbuf_size != 0) {
270 ret = rpc_hf_wait_tend(target);
271 if (ret != ERROR_OK) {
272 LOG_ERROR("Xfer TEND timeout");
273 return ret;
274 }
275
276 /* Write calibration magic */
277 ret = target_write_u32(target, rpc_base + RPC_DRCR, 0x01FF0301);
278 if (ret != ERROR_OK)
279 return ret;
280
281 ret = target_write_u32(target, rpc_base + RPC_PHYCNT, 0x80030277);
282 if (ret != ERROR_OK)
283 return ret;
284
285 ret = target_write_memory(target, rpc_base | RPC_WBUF, 4,
286 wbuf_size / 4, wbuf);
287 if (ret != ERROR_OK)
288 return ret;
289
290 ret = clrsetbits_u32(target, rpc_base + RPC_CMNCR,
291 RPC_CMNCR_MD | RPC_CMNCR_BSZ(3),
292 RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ |
293 RPC_CMNCR_MD | RPC_CMNCR_BSZ(1));
294 if (ret != ERROR_OK)
295 return ret;
296 } else {
297 ret = rpc_hf_mode(target, 1);
298 if (ret != ERROR_OK)
299 return ret;
300 }
301
302 /* Submit HF address, SMCMR CMD[7] ~= CA Bit# 47 (R/nW) */
303 ret = target_write_u32(target, rpc_base + RPC_SMCMR,
304 write ? 0 : RPC_SMCMR_CMD(0x80));
305 if (ret != ERROR_OK)
306 return ret;
307
308 ret = target_write_u32(target, rpc_base + RPC_SMADR,
309 addr >> 1);
310 if (ret != ERROR_OK)
311 return ret;
312
313 ret = target_write_u32(target, rpc_base + RPC_SMOPR, 0x0);
314 if (ret != ERROR_OK)
315 return ret;
316
317 ret = target_write_u32(target, rpc_base + RPC_SMDRENR,
318 RPC_SMDRENR_HYPE | RPC_SMDRENR_ADDRE |
319 RPC_SMDRENR_SPIDRE);
320 if (ret != ERROR_OK)
321 return ret;
322
323 val = RPC_SMENR_CDB(2) | RPC_SMENR_OCDB(2) |
324 RPC_SMENR_ADB(2) | RPC_SMENR_SPIDB(2) |
325 (wbuf_size ? RPC_SMENR_OPDB(2) : 0) |
326 RPC_SMENR_CDE | RPC_SMENR_OCDE | RPC_SMENR_ADE(4) | size;
327
328 if (write) {
329 ret = target_write_u32(target, rpc_base + RPC_SMENR, val);
330 if (ret != ERROR_OK)
331 return ret;
332
333 if (wbuf_size == 0) {
334 buf_bswap32((uint8_t *)&wdata, (uint8_t *)&wdata, 4);
335 ret = target_write_u32(target, rpc_base + RPC_SMWDR0,
336 wdata);
337 if (ret != ERROR_OK)
338 return ret;
339 }
340
341 ret = target_write_u32(target, rpc_base + RPC_SMCR,
342 RPC_SMCR_SPIWE | RPC_SMCR_SPIE);
343 if (ret != ERROR_OK)
344 return ret;
345 } else {
346 val |= RPC_SMENR_DME;
347
348 ret = target_write_u32(target, rpc_base + RPC_SMDMCR,
349 RPC_SMDMCR_DMCYC(0xE));
350 if (ret != ERROR_OK)
351 return ret;
352
353 ret = target_write_u32(target, rpc_base + RPC_SMENR, val);
354 if (ret != ERROR_OK)
355 return ret;
356
357 ret = target_write_u32(target, rpc_base + RPC_SMCR,
358 RPC_SMCR_SPIRE | RPC_SMCR_SPIE);
359 if (ret != ERROR_OK)
360 return ret;
361
362 ret = rpc_hf_wait_tend(target);
363 if (ret != ERROR_OK)
364 return ret;
365
366 uint32_t val32;
367 ret = target_read_u32(target, rpc_base + RPC_SMRDR0, &val32);
368 if (ret != ERROR_OK)
369 return ret;
370 buf_bswap32((uint8_t *)&val32, (uint8_t *)&val32, 4);
371 *rdata = val32;
372 }
373
374 ret = rpc_hf_mode(target, 0);
375 if (ret != ERROR_OK)
376 LOG_ERROR("Xfer done TEND timeout");
377 return ret;
378 }
379
380 static int rpchf_target_write_memory(struct flash_bank *bank, target_addr_t addr,
381 uint32_t count, const uint8_t *buffer)
382 {
383 struct target *target = bank->target;
384 uint32_t wdata;
385
386 if (count != 2)
387 return ERROR_FAIL;
388
389 wdata = buffer[0] | (buffer[1] << 8);
390
391 return rpc_hf_xfer(target, addr, wdata, NULL, RPC_HF_SIZE_16BIT,
392 true, NULL, 0);
393 }
394
395 static int rpchf_target_read_memory(struct flash_bank *bank, target_addr_t addr,
396 uint32_t count, uint8_t *buffer)
397 {
398 struct target *target = bank->target;
399 uint32_t i, rdata;
400 int ret;
401
402 for (i = 0; i < count; i++) {
403 ret = rpc_hf_xfer(target, addr + (2 * i), 0, &rdata,
404 RPC_HF_SIZE_16BIT, false, NULL, 0);
405 if (ret != ERROR_OK)
406 return ret;
407 buffer[(2 * i) + 0] = rdata & 0xff;
408 buffer[(2 * i) + 1] = (rdata >> 8) & 0xff;
409 }
410
411 return ERROR_OK;
412 }
413
414 FLASH_BANK_COMMAND_HANDLER(rpchf_flash_bank_command)
415 {
416 struct cfi_flash_bank *cfi_info;
417 int ret;
418
419 ret = cfi_flash_bank_cmd(bank, CMD_ARGC, CMD_ARGV);
420 if (ret != ERROR_OK)
421 return ret;
422
423 cfi_info = bank->driver_priv;
424 cfi_info->read_mem = rpchf_target_read_memory;
425 cfi_info->write_mem = rpchf_target_write_memory;
426
427 return ERROR_OK;
428 }
429
430 static int rpchf_spansion_write_words(struct flash_bank *bank, const uint8_t *word,
431 uint32_t wordcount, uint32_t address)
432 {
433 int retval;
434 struct cfi_flash_bank *cfi_info = bank->driver_priv;
435 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
436
437 /* Calculate buffer size and boundary mask
438 * buffersize is (buffer size per chip) * (number of chips)
439 * bufferwsize is buffersize in words */
440 uint32_t buffersize = RPC_WBUF_SIZE;
441 uint32_t buffermask = buffersize - 1;
442 uint32_t bufferwsize = buffersize / 2;
443
444 /* Check for valid range */
445 if (address & buffermask) {
446 LOG_ERROR("Write address at base " TARGET_ADDR_FMT
447 ", address 0x%" PRIx32 " not aligned to 2^%d boundary",
448 bank->base, address, cfi_info->max_buf_write_size);
449 return ERROR_FLASH_OPERATION_FAILED;
450 }
451
452 /* Check for valid size */
453 if (wordcount > bufferwsize) {
454 LOG_ERROR("Number of data words %" PRIu32 " exceeds available buffersize %"
455 PRIu32, wordcount, buffersize);
456 return ERROR_FLASH_OPERATION_FAILED;
457 }
458
459 /* Unlock */
460 retval = cfi_spansion_unlock_seq(bank);
461 if (retval != ERROR_OK)
462 return retval;
463
464 retval = cfi_send_command(bank, 0xa0, cfi_flash_address(bank, 0, pri_ext->_unlock1));
465 if (retval != ERROR_OK)
466 return retval;
467
468 retval = rpc_hf_xfer(bank->target, address, 0, NULL, RPC_HF_SIZE_64BIT, true, word, wordcount * 2);
469 if (retval != ERROR_OK)
470 return retval;
471
472 if (cfi_spansion_wait_status_busy(bank, cfi_info->word_write_timeout) != ERROR_OK) {
473 retval = cfi_send_command(bank, 0xf0, cfi_flash_address(bank, 0, 0x0));
474 if (retval != ERROR_OK)
475 return retval;
476
477 LOG_ERROR("couldn't write block at base " TARGET_ADDR_FMT
478 ", address 0x%" PRIx32 ", size 0x%" PRIx32, bank->base, address,
479 bufferwsize);
480 return ERROR_FLASH_OPERATION_FAILED;
481 }
482
483 return ERROR_OK;
484 }
485
486 static int rpchf_write_words(struct flash_bank *bank, const uint8_t *word,
487 uint32_t wordcount, uint32_t address)
488 {
489 return rpchf_spansion_write_words(bank, word, wordcount, address);
490 }
491
492 static int rpchf_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
493 {
494 struct cfi_flash_bank *cfi_info = bank->driver_priv;
495 uint32_t address = bank->base + offset; /* address of first byte to be programmed */
496 uint32_t write_p;
497 int align; /* number of unaligned bytes */
498 uint8_t current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being
499 *programmed */
500 int retval;
501
502 if (bank->target->state != TARGET_HALTED) {
503 LOG_ERROR("Target not halted");
504 return ERROR_TARGET_NOT_HALTED;
505 }
506
507 if (offset + count > bank->size)
508 return ERROR_FLASH_DST_OUT_OF_BANK;
509
510 if (cfi_info->qry[0] != 'Q')
511 return ERROR_FLASH_BANK_NOT_PROBED;
512
513 /* start at the first byte of the first word (bus_width size) */
514 write_p = address & ~(bank->bus_width - 1);
515 align = address - write_p;
516 if (align != 0) {
517 LOG_INFO("Fixup %d unaligned head bytes", align);
518
519 /* read a complete word from flash */
520 retval = cfi_target_read_memory(bank, write_p, 1, current_word);
521 if (retval != ERROR_OK)
522 return retval;
523
524 /* replace only bytes that must be written */
525 for (unsigned int i = align; (i < bank->bus_width) && (count > 0); i++, count--) {
526 if (cfi_info->data_swap)
527 /* data bytes are swapped (reverse endianness) */
528 current_word[bank->bus_width - i] = *buffer++;
529 else
530 current_word[i] = *buffer++;
531 }
532
533 retval = cfi_write_word(bank, current_word, write_p);
534 if (retval != ERROR_OK)
535 return retval;
536 write_p += bank->bus_width;
537 }
538
539 /* Calculate buffer size and boundary mask
540 * buffersize is (buffer size per chip) * (number of chips)
541 * bufferwsize is buffersize in words */
542 uint32_t buffersize = RPC_WBUF_SIZE;
543 uint32_t buffermask = buffersize-1;
544 uint32_t bufferwsize = buffersize / bank->bus_width;
545
546 /* fall back to memory writes */
547 while (count >= (uint32_t)bank->bus_width) {
548 bool fallback;
549 if ((write_p & 0xff) == 0) {
550 LOG_INFO("Programming at 0x%08" PRIx32 ", count 0x%08"
551 PRIx32 " bytes remaining", write_p, count);
552 }
553 fallback = true;
554 if ((bufferwsize > 0) && (count >= buffersize) &&
555 !(write_p & buffermask)) {
556 retval = rpchf_write_words(bank, buffer, bufferwsize, write_p);
557 if (retval == ERROR_OK) {
558 buffer += buffersize;
559 write_p += buffersize;
560 count -= buffersize;
561 fallback = false;
562 } else if (retval != ERROR_FLASH_OPER_UNSUPPORTED)
563 return retval;
564 }
565 /* try the slow way? */
566 if (fallback) {
567 for (unsigned int i = 0; i < bank->bus_width; i++)
568 current_word[i] = *buffer++;
569
570 retval = cfi_write_word(bank, current_word, write_p);
571 if (retval != ERROR_OK)
572 return retval;
573
574 write_p += bank->bus_width;
575 count -= bank->bus_width;
576 }
577 }
578
579 /* return to read array mode, so we can read from flash again for padding */
580 retval = cfi_reset(bank);
581 if (retval != ERROR_OK)
582 return retval;
583
584 /* handle unaligned tail bytes */
585 if (count > 0) {
586 LOG_INFO("Fixup %" PRIu32 " unaligned tail bytes", count);
587
588 /* read a complete word from flash */
589 retval = cfi_target_read_memory(bank, write_p, 1, current_word);
590 if (retval != ERROR_OK)
591 return retval;
592
593 /* replace only bytes that must be written */
594 for (unsigned int i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
595 if (cfi_info->data_swap)
596 /* data bytes are swapped (reverse endianness) */
597 current_word[bank->bus_width - i] = *buffer++;
598 else
599 current_word[i] = *buffer++;
600
601 retval = cfi_write_word(bank, current_word, write_p);
602 if (retval != ERROR_OK)
603 return retval;
604 }
605
606 /* return to read array mode */
607 return cfi_reset(bank);
608 }
609
610 static int rpchf_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
611 {
612 struct cfi_flash_bank *cfi_info = bank->driver_priv;
613 struct target *target = bank->target;
614
615 LOG_DEBUG("reading buffer of %" PRIu32 " byte at 0x%8.8" PRIx32,
616 count, offset);
617
618 if (bank->target->state != TARGET_HALTED) {
619 LOG_ERROR("Target not halted");
620 return ERROR_TARGET_NOT_HALTED;
621 }
622
623 if (offset + count > bank->size)
624 return ERROR_FLASH_DST_OUT_OF_BANK;
625
626 if (cfi_info->qry[0] != 'Q')
627 return ERROR_FLASH_BANK_NOT_PROBED;
628
629 return target_read_memory(target, offset | mem_base,
630 4, count / 4, buffer);
631 }
632
633 const struct flash_driver renesas_rpchf_flash = {
634 .name = "rpchf",
635 .flash_bank_command = rpchf_flash_bank_command,
636 .erase = cfi_erase,
637 .protect = cfi_protect,
638 .write = rpchf_write,
639 .read = rpchf_read,
640 .probe = cfi_probe,
641 .auto_probe = cfi_auto_probe,
642 .erase_check = default_flash_blank_check,
643 .protect_check = cfi_protect_check,
644 .info = cfi_get_info,
645 .free_driver_priv = default_flash_free_driver_priv,
646 };
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