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stm32: update stm32f1x driver for f0x and f3x option bytes
[openocd.git] / src / flash / nor / stm32f1x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "imp.h"
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
35
36 /* stm32x register locations */
37
38 #define FLASH_REG_BASE_B0 0x40022000
39 #define FLASH_REG_BASE_B1 0x40022040
40
41 #define STM32_FLASH_ACR 0x00
42 #define STM32_FLASH_KEYR 0x04
43 #define STM32_FLASH_OPTKEYR 0x08
44 #define STM32_FLASH_SR 0x0C
45 #define STM32_FLASH_CR 0x10
46 #define STM32_FLASH_AR 0x14
47 #define STM32_FLASH_OBR 0x1C
48 #define STM32_FLASH_WRPR 0x20
49
50 /* TODO: Check if code using these really should be hard coded to bank 0.
51 * There are valid cases, on dual flash devices the protection of the
52 * second bank is done on the bank0 reg's. */
53 #define STM32_FLASH_ACR_B0 0x40022000
54 #define STM32_FLASH_KEYR_B0 0x40022004
55 #define STM32_FLASH_OPTKEYR_B0 0x40022008
56 #define STM32_FLASH_SR_B0 0x4002200C
57 #define STM32_FLASH_CR_B0 0x40022010
58 #define STM32_FLASH_AR_B0 0x40022014
59 #define STM32_FLASH_OBR_B0 0x4002201C
60 #define STM32_FLASH_WRPR_B0 0x40022020
61
62 /* option byte location */
63
64 #define STM32_OB_RDP 0x1FFFF800
65 #define STM32_OB_USER 0x1FFFF802
66 #define STM32_OB_DATA0 0x1FFFF804
67 #define STM32_OB_DATA1 0x1FFFF806
68 #define STM32_OB_WRP0 0x1FFFF808
69 #define STM32_OB_WRP1 0x1FFFF80A
70 #define STM32_OB_WRP2 0x1FFFF80C
71 #define STM32_OB_WRP3 0x1FFFF80E
72
73 /* FLASH_CR register bits */
74
75 #define FLASH_PG (1 << 0)
76 #define FLASH_PER (1 << 1)
77 #define FLASH_MER (1 << 2)
78 #define FLASH_OPTPG (1 << 4)
79 #define FLASH_OPTER (1 << 5)
80 #define FLASH_STRT (1 << 6)
81 #define FLASH_LOCK (1 << 7)
82 #define FLASH_OPTWRE (1 << 9)
83
84 /* FLASH_SR register bits */
85
86 #define FLASH_BSY (1 << 0)
87 #define FLASH_PGERR (1 << 2)
88 #define FLASH_WRPRTERR (1 << 4)
89 #define FLASH_EOP (1 << 5)
90
91 /* STM32_FLASH_OBR bit definitions (reading) */
92
93 #define OPT_ERROR 0
94 #define OPT_READOUT 1
95 #define OPT_RDWDGSW 2
96 #define OPT_RDRSTSTOP 3
97 #define OPT_RDRSTSTDBY 4
98 #define OPT_BFB2 5 /* dual flash bank only */
99
100 /* register unlock keys */
101
102 #define KEY1 0x45670123
103 #define KEY2 0xCDEF89AB
104
105 /* timeout values */
106
107 #define FLASH_WRITE_TIMEOUT 10
108 #define FLASH_ERASE_TIMEOUT 100
109
110 struct stm32x_options {
111 uint16_t RDP;
112 uint16_t user_options;
113 uint16_t user_data;
114 uint16_t protection[4];
115 };
116
117 struct stm32x_flash_bank {
118 struct stm32x_options option_bytes;
119 int ppage_size;
120 int probed;
121
122 bool has_dual_banks;
123 /* used to access dual flash bank stm32xl */
124 uint32_t register_base;
125 uint16_t default_rdp;
126 int user_data_offset;
127 int option_offset;
128 };
129
130 static int stm32x_mass_erase(struct flash_bank *bank);
131 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
132 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
133 uint32_t offset, uint32_t count);
134
135 /* flash bank stm32x <base> <size> 0 0 <target#>
136 */
137 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
138 {
139 struct stm32x_flash_bank *stm32x_info;
140
141 if (CMD_ARGC < 6)
142 return ERROR_COMMAND_SYNTAX_ERROR;
143
144 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
145
146 bank->driver_priv = stm32x_info;
147 stm32x_info->probed = 0;
148 stm32x_info->has_dual_banks = false;
149 stm32x_info->register_base = FLASH_REG_BASE_B0;
150
151 return ERROR_OK;
152 }
153
154 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
155 {
156 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
157 return reg + stm32x_info->register_base;
158 }
159
160 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
161 {
162 struct target *target = bank->target;
163 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
164 }
165
166 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
167 {
168 struct target *target = bank->target;
169 uint32_t status;
170 int retval = ERROR_OK;
171
172 /* wait for busy to clear */
173 for (;;) {
174 retval = stm32x_get_flash_status(bank, &status);
175 if (retval != ERROR_OK)
176 return retval;
177 LOG_DEBUG("status: 0x%" PRIx32 "", status);
178 if ((status & FLASH_BSY) == 0)
179 break;
180 if (timeout-- <= 0) {
181 LOG_ERROR("timed out waiting for flash");
182 return ERROR_FAIL;
183 }
184 alive_sleep(1);
185 }
186
187 if (status & FLASH_WRPRTERR) {
188 LOG_ERROR("stm32x device protected");
189 retval = ERROR_FAIL;
190 }
191
192 if (status & FLASH_PGERR) {
193 LOG_ERROR("stm32x device programming failed");
194 retval = ERROR_FAIL;
195 }
196
197 /* Clear but report errors */
198 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
199 /* If this operation fails, we ignore it and report the original
200 * retval
201 */
202 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
203 FLASH_WRPRTERR | FLASH_PGERR);
204 }
205 return retval;
206 }
207
208 static int stm32x_check_operation_supported(struct flash_bank *bank)
209 {
210 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
211
212 /* if we have a dual flash bank device then
213 * we need to perform option byte stuff on bank0 only */
214 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
215 LOG_ERROR("Option Byte Operation's must use bank0");
216 return ERROR_FLASH_OPERATION_FAILED;
217 }
218
219 return ERROR_OK;
220 }
221
222 static int stm32x_read_options(struct flash_bank *bank)
223 {
224 uint32_t optiondata;
225 struct stm32x_flash_bank *stm32x_info = NULL;
226 struct target *target = bank->target;
227
228 stm32x_info = bank->driver_priv;
229
230 /* read current option bytes */
231 int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
232 if (retval != ERROR_OK)
233 return retval;
234
235 stm32x_info->option_bytes.user_options = (optiondata >> stm32x_info->option_offset >> 2) & 0xffff;
236 stm32x_info->option_bytes.user_data = (optiondata >> stm32x_info->user_data_offset) & 0xffff;
237 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
238
239 if (optiondata & (1 << OPT_READOUT))
240 LOG_INFO("Device Security Bit Set");
241
242 /* each bit refers to a 4bank protection */
243 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
244 if (retval != ERROR_OK)
245 return retval;
246
247 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
248 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
249 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
250 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
251
252 return ERROR_OK;
253 }
254
255 static int stm32x_erase_options(struct flash_bank *bank)
256 {
257 struct stm32x_flash_bank *stm32x_info = NULL;
258 struct target *target = bank->target;
259
260 stm32x_info = bank->driver_priv;
261
262 /* read current options */
263 stm32x_read_options(bank);
264
265 /* unlock flash registers */
266 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
267 if (retval != ERROR_OK)
268 return retval;
269
270 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
271 if (retval != ERROR_OK)
272 return retval;
273
274 /* unlock option flash registers */
275 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
276 if (retval != ERROR_OK)
277 return retval;
278 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
279 if (retval != ERROR_OK)
280 return retval;
281
282 /* erase option bytes */
283 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
284 if (retval != ERROR_OK)
285 return retval;
286 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
287 if (retval != ERROR_OK)
288 return retval;
289
290 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
291 if (retval != ERROR_OK)
292 return retval;
293
294 /* clear readout protection and complementary option bytes
295 * this will also force a device unlock if set */
296 stm32x_info->option_bytes.RDP = stm32x_info->default_rdp;
297
298 return ERROR_OK;
299 }
300
301 static int stm32x_write_options(struct flash_bank *bank)
302 {
303 struct stm32x_flash_bank *stm32x_info = NULL;
304 struct target *target = bank->target;
305
306 stm32x_info = bank->driver_priv;
307
308 /* unlock flash registers */
309 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
310 if (retval != ERROR_OK)
311 return retval;
312 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
313 if (retval != ERROR_OK)
314 return retval;
315
316 /* unlock option flash registers */
317 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
318 if (retval != ERROR_OK)
319 return retval;
320 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
321 if (retval != ERROR_OK)
322 return retval;
323
324 /* program option bytes */
325 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
326 if (retval != ERROR_OK)
327 return retval;
328
329 uint8_t opt_bytes[16];
330
331 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.RDP);
332 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user_options);
333 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.user_data & 0xff);
334 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.user_data >> 8) & 0xff);
335 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection[0]);
336 target_buffer_set_u16(target, opt_bytes + 10, stm32x_info->option_bytes.protection[1]);
337 target_buffer_set_u16(target, opt_bytes + 12, stm32x_info->option_bytes.protection[2]);
338 target_buffer_set_u16(target, opt_bytes + 14, stm32x_info->option_bytes.protection[3]);
339
340 uint32_t offset = STM32_OB_RDP - bank->base;
341 retval = stm32x_write_block(bank, opt_bytes, offset, sizeof(opt_bytes) / 2);
342 if (retval != ERROR_OK) {
343 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
344 LOG_ERROR("working area required to erase options bytes");
345 return retval;
346 }
347
348 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
349 if (retval != ERROR_OK)
350 return retval;
351
352 return ERROR_OK;
353 }
354
355 static int stm32x_protect_check(struct flash_bank *bank)
356 {
357 struct target *target = bank->target;
358 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
359
360 uint32_t protection;
361 int i, s;
362 int num_bits;
363 int set;
364
365 if (target->state != TARGET_HALTED) {
366 LOG_ERROR("Target not halted");
367 return ERROR_TARGET_NOT_HALTED;
368 }
369
370 int retval = stm32x_check_operation_supported(bank);
371 if (ERROR_OK != retval)
372 return retval;
373
374 /* medium density - each bit refers to a 4bank protection
375 * high density - each bit refers to a 2bank protection */
376 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
377 if (retval != ERROR_OK)
378 return retval;
379
380 /* medium density - each protection bit is for 4 * 1K pages
381 * high density - each protection bit is for 2 * 2K pages */
382 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
383
384 if (stm32x_info->ppage_size == 2) {
385 /* high density flash/connectivity line protection */
386
387 set = 1;
388
389 if (protection & (1 << 31))
390 set = 0;
391
392 /* bit 31 controls sector 62 - 255 protection for high density
393 * bit 31 controls sector 62 - 127 protection for connectivity line */
394 for (s = 62; s < bank->num_sectors; s++)
395 bank->sectors[s].is_protected = set;
396
397 if (bank->num_sectors > 61)
398 num_bits = 31;
399
400 for (i = 0; i < num_bits; i++) {
401 set = 1;
402
403 if (protection & (1 << i))
404 set = 0;
405
406 for (s = 0; s < stm32x_info->ppage_size; s++)
407 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
408 }
409 } else {
410 /* low/medium density flash protection */
411 for (i = 0; i < num_bits; i++) {
412 set = 1;
413
414 if (protection & (1 << i))
415 set = 0;
416
417 for (s = 0; s < stm32x_info->ppage_size; s++)
418 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
419 }
420 }
421
422 return ERROR_OK;
423 }
424
425 static int stm32x_erase(struct flash_bank *bank, int first, int last)
426 {
427 struct target *target = bank->target;
428 int i;
429
430 if (bank->target->state != TARGET_HALTED) {
431 LOG_ERROR("Target not halted");
432 return ERROR_TARGET_NOT_HALTED;
433 }
434
435 if ((first == 0) && (last == (bank->num_sectors - 1)))
436 return stm32x_mass_erase(bank);
437
438 /* unlock flash registers */
439 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
440 if (retval != ERROR_OK)
441 return retval;
442 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
443 if (retval != ERROR_OK)
444 return retval;
445
446 for (i = first; i <= last; i++) {
447 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
448 if (retval != ERROR_OK)
449 return retval;
450 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
451 bank->base + bank->sectors[i].offset);
452 if (retval != ERROR_OK)
453 return retval;
454 retval = target_write_u32(target,
455 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
456 if (retval != ERROR_OK)
457 return retval;
458
459 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
460 if (retval != ERROR_OK)
461 return retval;
462
463 bank->sectors[i].is_erased = 1;
464 }
465
466 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
467 if (retval != ERROR_OK)
468 return retval;
469
470 return ERROR_OK;
471 }
472
473 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
474 {
475 struct stm32x_flash_bank *stm32x_info = NULL;
476 struct target *target = bank->target;
477 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
478 int i, reg, bit;
479 int status;
480 uint32_t protection;
481
482 stm32x_info = bank->driver_priv;
483
484 if (target->state != TARGET_HALTED) {
485 LOG_ERROR("Target not halted");
486 return ERROR_TARGET_NOT_HALTED;
487 }
488
489 int retval = stm32x_check_operation_supported(bank);
490 if (ERROR_OK != retval)
491 return retval;
492
493 if ((first % stm32x_info->ppage_size) != 0) {
494 LOG_WARNING("aligned start protect sector to a %d sector boundary",
495 stm32x_info->ppage_size);
496 first = first - (first % stm32x_info->ppage_size);
497 }
498 if (((last + 1) % stm32x_info->ppage_size) != 0) {
499 LOG_WARNING("aligned end protect sector to a %d sector boundary",
500 stm32x_info->ppage_size);
501 last++;
502 last = last - (last % stm32x_info->ppage_size);
503 last--;
504 }
505
506 /* medium density - each bit refers to a 4bank protection
507 * high density - each bit refers to a 2bank protection */
508 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
509 if (retval != ERROR_OK)
510 return retval;
511
512 prot_reg[0] = (uint16_t)protection;
513 prot_reg[1] = (uint16_t)(protection >> 8);
514 prot_reg[2] = (uint16_t)(protection >> 16);
515 prot_reg[3] = (uint16_t)(protection >> 24);
516
517 if (stm32x_info->ppage_size == 2) {
518 /* high density flash */
519
520 /* bit 7 controls sector 62 - 255 protection */
521 if (last > 61) {
522 if (set)
523 prot_reg[3] &= ~(1 << 7);
524 else
525 prot_reg[3] |= (1 << 7);
526 }
527
528 if (first > 61)
529 first = 62;
530 if (last > 61)
531 last = 61;
532
533 for (i = first; i <= last; i++) {
534 reg = (i / stm32x_info->ppage_size) / 8;
535 bit = (i / stm32x_info->ppage_size) - (reg * 8);
536
537 if (set)
538 prot_reg[reg] &= ~(1 << bit);
539 else
540 prot_reg[reg] |= (1 << bit);
541 }
542 } else {
543 /* medium density flash */
544 for (i = first; i <= last; i++) {
545 reg = (i / stm32x_info->ppage_size) / 8;
546 bit = (i / stm32x_info->ppage_size) - (reg * 8);
547
548 if (set)
549 prot_reg[reg] &= ~(1 << bit);
550 else
551 prot_reg[reg] |= (1 << bit);
552 }
553 }
554
555 status = stm32x_erase_options(bank);
556 if (status != ERROR_OK)
557 return status;
558
559 stm32x_info->option_bytes.protection[0] = prot_reg[0];
560 stm32x_info->option_bytes.protection[1] = prot_reg[1];
561 stm32x_info->option_bytes.protection[2] = prot_reg[2];
562 stm32x_info->option_bytes.protection[3] = prot_reg[3];
563
564 return stm32x_write_options(bank);
565 }
566
567 static int stm32x_write_block(struct flash_bank *bank, uint8_t *buffer,
568 uint32_t offset, uint32_t count)
569 {
570 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
571 struct target *target = bank->target;
572 uint32_t buffer_size = 16384;
573 struct working_area *write_algorithm;
574 struct working_area *source;
575 uint32_t address = bank->base + offset;
576 struct reg_param reg_params[5];
577 struct armv7m_algorithm armv7m_info;
578 int retval = ERROR_OK;
579
580 /* see contrib/loaders/flash/stm32f1x.S for src */
581
582 static const uint8_t stm32x_flash_write_code[] = {
583 /* #define STM32_FLASH_SR_OFFSET 0x0C */
584 /* wait_fifo: */
585 0x16, 0x68, /* ldr r6, [r2, #0] */
586 0x00, 0x2e, /* cmp r6, #0 */
587 0x18, 0xd0, /* beq exit */
588 0x55, 0x68, /* ldr r5, [r2, #4] */
589 0xb5, 0x42, /* cmp r5, r6 */
590 0xf9, 0xd0, /* beq wait_fifo */
591 0x2e, 0x88, /* ldrh r6, [r5, #0] */
592 0x26, 0x80, /* strh r6, [r4, #0] */
593 0x02, 0x35, /* adds r5, #2 */
594 0x02, 0x34, /* adds r4, #2 */
595 /* busy: */
596 0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
597 0x01, 0x27, /* movs r7, #1 */
598 0x3e, 0x42, /* tst r6, r7 */
599 0xfb, 0xd1, /* bne busy */
600 0x14, 0x27, /* movs r7, #0x14 */
601 0x3e, 0x42, /* tst r6, r7 */
602 0x08, 0xd1, /* bne error */
603 0x9d, 0x42, /* cmp r5, r3 */
604 0x01, 0xd3, /* bcc no_wrap */
605 0x15, 0x46, /* mov r5, r2 */
606 0x08, 0x35, /* adds r5, #8 */
607 /* no_wrap: */
608 0x55, 0x60, /* str r5, [r2, #4] */
609 0x01, 0x39, /* subs r1, r1, #1 */
610 0x00, 0x29, /* cmp r1, #0 */
611 0x02, 0xd0, /* beq exit */
612 0xe5, 0xe7, /* b wait_fifo */
613 /* error: */
614 0x00, 0x20, /* movs r0, #0 */
615 0x50, 0x60, /* str r0, [r2, #4] */
616 /* exit: */
617 0x30, 0x46, /* mov r0, r6 */
618 0x00, 0xbe, /* bkpt #0 */
619 };
620
621 /* flash write code */
622 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
623 &write_algorithm) != ERROR_OK) {
624 LOG_WARNING("no working area available, can't do block memory writes");
625 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
626 };
627
628 retval = target_write_buffer(target, write_algorithm->address,
629 sizeof(stm32x_flash_write_code), (uint8_t *)stm32x_flash_write_code);
630 if (retval != ERROR_OK)
631 return retval;
632
633 /* memory buffer */
634 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
635 buffer_size /= 2;
636 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
637 if (buffer_size <= 256) {
638 /* we already allocated the writing code, but failed to get a
639 * buffer, free the algorithm */
640 target_free_working_area(target, write_algorithm);
641
642 LOG_WARNING("no large enough working area available, can't do block memory writes");
643 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
644 }
645 };
646
647 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
648 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
649 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
650 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
651 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
652
653 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
654 buf_set_u32(reg_params[1].value, 0, 32, count);
655 buf_set_u32(reg_params[2].value, 0, 32, source->address);
656 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
657 buf_set_u32(reg_params[4].value, 0, 32, address);
658
659 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
660 armv7m_info.core_mode = ARM_MODE_THREAD;
661
662 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
663 0, NULL,
664 5, reg_params,
665 source->address, source->size,
666 write_algorithm->address, 0,
667 &armv7m_info);
668
669 if (retval == ERROR_FLASH_OPERATION_FAILED) {
670 LOG_ERROR("flash write failed at address 0x%"PRIx32,
671 buf_get_u32(reg_params[4].value, 0, 32));
672
673 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
674 LOG_ERROR("flash memory not erased before writing");
675 /* Clear but report errors */
676 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
677 }
678
679 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
680 LOG_ERROR("flash memory write protected");
681 /* Clear but report errors */
682 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
683 }
684 }
685
686 target_free_working_area(target, source);
687 target_free_working_area(target, write_algorithm);
688
689 destroy_reg_param(&reg_params[0]);
690 destroy_reg_param(&reg_params[1]);
691 destroy_reg_param(&reg_params[2]);
692 destroy_reg_param(&reg_params[3]);
693 destroy_reg_param(&reg_params[4]);
694
695 return retval;
696 }
697
698 static int stm32x_write(struct flash_bank *bank, uint8_t *buffer,
699 uint32_t offset, uint32_t count)
700 {
701 struct target *target = bank->target;
702 uint8_t *new_buffer = NULL;
703
704 if (bank->target->state != TARGET_HALTED) {
705 LOG_ERROR("Target not halted");
706 return ERROR_TARGET_NOT_HALTED;
707 }
708
709 if (offset & 0x1) {
710 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
711 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
712 }
713
714 /* If there's an odd number of bytes, the data has to be padded. Duplicate
715 * the buffer and use the normal code path with a single block write since
716 * it's probably cheaper than to special case the last odd write using
717 * discrete accesses. */
718 if (count & 1) {
719 new_buffer = malloc(count + 1);
720 if (new_buffer == NULL) {
721 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
722 return ERROR_FAIL;
723 }
724 LOG_INFO("odd number of bytes to write, padding with 0xff");
725 buffer = memcpy(new_buffer, buffer, count);
726 buffer[count++] = 0xff;
727 }
728
729 uint32_t words_remaining = count / 2;
730 int retval, retval2;
731
732 /* unlock flash registers */
733 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
734 if (retval != ERROR_OK)
735 goto cleanup;
736 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
737 if (retval != ERROR_OK)
738 goto cleanup;
739
740 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
741 if (retval != ERROR_OK)
742 goto cleanup;
743
744 /* try using a block write */
745 retval = stm32x_write_block(bank, buffer, offset, words_remaining);
746
747 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
748 /* if block write failed (no sufficient working area),
749 * we use normal (slow) single halfword accesses */
750 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
751
752 while (words_remaining > 0) {
753 uint16_t value;
754 memcpy(&value, buffer, sizeof(uint16_t));
755
756 retval = target_write_u16(target, bank->base + offset, value);
757 if (retval != ERROR_OK)
758 goto reset_pg_and_lock;
759
760 retval = stm32x_wait_status_busy(bank, 5);
761 if (retval != ERROR_OK)
762 goto reset_pg_and_lock;
763
764 words_remaining--;
765 buffer += 2;
766 offset += 2;
767 }
768 }
769
770 reset_pg_and_lock:
771 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
772 if (retval == ERROR_OK)
773 retval = retval2;
774
775 cleanup:
776 if (new_buffer)
777 free(new_buffer);
778
779 return retval;
780 }
781
782 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
783 {
784 /* This check the device CPUID core register to detect
785 * the M0 from the M3 devices. */
786
787 struct target *target = bank->target;
788 uint32_t cpuid, device_id_register = 0;
789
790 /* Get the CPUID from the ARM Core
791 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
792 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
793 if (retval != ERROR_OK)
794 return retval;
795
796 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
797 /* 0xC20 is M0 devices */
798 device_id_register = 0x40015800;
799 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
800 /* 0xC23 is M3 devices */
801 device_id_register = 0xE0042000;
802 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
803 /* 0xC24 is M4 devices */
804 device_id_register = 0xE0042000;
805 } else {
806 LOG_ERROR("Cannot identify target as a stm32x");
807 return ERROR_FAIL;
808 }
809
810 /* read stm32 device id register */
811 retval = target_read_u32(target, device_id_register, device_id);
812 if (retval != ERROR_OK)
813 return retval;
814
815 return retval;
816 }
817
818 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
819 {
820 struct target *target = bank->target;
821 uint32_t cpuid, flash_size_reg;
822
823 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
824 if (retval != ERROR_OK)
825 return retval;
826
827 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
828 /* 0xC20 is M0 devices */
829 flash_size_reg = 0x1FFFF7CC;
830 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
831 /* 0xC23 is M3 devices */
832 flash_size_reg = 0x1FFFF7E0;
833 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
834 /* 0xC24 is M4 devices */
835 flash_size_reg = 0x1FFFF7CC;
836 } else {
837 LOG_ERROR("Cannot identify target as a stm32x");
838 return ERROR_FAIL;
839 }
840
841 retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
842 if (retval != ERROR_OK)
843 return retval;
844
845 return retval;
846 }
847
848 static int stm32x_probe(struct flash_bank *bank)
849 {
850 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
851 int i;
852 uint16_t flash_size_in_kb;
853 uint16_t max_flash_size_in_kb;
854 uint32_t device_id;
855 int page_size;
856 uint32_t base_address = 0x08000000;
857
858 stm32x_info->probed = 0;
859 stm32x_info->register_base = FLASH_REG_BASE_B0;
860 stm32x_info->user_data_offset = 10;
861 stm32x_info->option_offset = 0;
862
863 /* default factory protection level */
864 stm32x_info->default_rdp = 0x5AA5;
865
866 /* read stm32 device id register */
867 int retval = stm32x_get_device_id(bank, &device_id);
868 if (retval != ERROR_OK)
869 return retval;
870
871 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
872
873 /* set page size, protection granularity and max flash size depending on family */
874 switch (device_id & 0xfff) {
875 case 0x410: /* medium density */
876 page_size = 1024;
877 stm32x_info->ppage_size = 4;
878 max_flash_size_in_kb = 128;
879 break;
880 case 0x412: /* low density */
881 page_size = 1024;
882 stm32x_info->ppage_size = 4;
883 max_flash_size_in_kb = 32;
884 break;
885 case 0x414: /* high density */
886 page_size = 2048;
887 stm32x_info->ppage_size = 2;
888 max_flash_size_in_kb = 512;
889 break;
890 case 0x418: /* connectivity line density */
891 page_size = 2048;
892 stm32x_info->ppage_size = 2;
893 max_flash_size_in_kb = 256;
894 break;
895 case 0x420: /* value line density */
896 page_size = 1024;
897 stm32x_info->ppage_size = 4;
898 max_flash_size_in_kb = 128;
899 break;
900 case 0x422: /* stm32f30x */
901 page_size = 2048;
902 stm32x_info->ppage_size = 2;
903 max_flash_size_in_kb = 256;
904 stm32x_info->user_data_offset = 16;
905 stm32x_info->option_offset = 6;
906 stm32x_info->default_rdp = 0x55AA;
907 break;
908 case 0x428: /* value line High density */
909 page_size = 2048;
910 stm32x_info->ppage_size = 4;
911 max_flash_size_in_kb = 128;
912 break;
913 case 0x430: /* xl line density (dual flash banks) */
914 page_size = 2048;
915 stm32x_info->ppage_size = 2;
916 max_flash_size_in_kb = 1024;
917 stm32x_info->has_dual_banks = true;
918 break;
919 case 0x432: /* stm32f37x */
920 page_size = 2048;
921 stm32x_info->ppage_size = 2;
922 max_flash_size_in_kb = 256;
923 stm32x_info->user_data_offset = 16;
924 stm32x_info->option_offset = 6;
925 stm32x_info->default_rdp = 0x55AA;
926 break;
927 case 0x440: /* stm32f0x */
928 page_size = 1024;
929 stm32x_info->ppage_size = 4;
930 max_flash_size_in_kb = 64;
931 stm32x_info->user_data_offset = 16;
932 stm32x_info->option_offset = 6;
933 stm32x_info->default_rdp = 0x55AA;
934 break;
935 default:
936 LOG_WARNING("Cannot identify target as a STM32 family.");
937 return ERROR_FAIL;
938 }
939
940 /* get flash size from target. */
941 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
942
943 /* failed reading flash size or flash size invalid (early silicon),
944 * default to max target family */
945 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
946 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
947 max_flash_size_in_kb);
948 flash_size_in_kb = max_flash_size_in_kb;
949 }
950
951 if (stm32x_info->has_dual_banks) {
952 /* split reported size into matching bank */
953 if (bank->base != 0x08080000) {
954 /* bank 0 will be fixed 512k */
955 flash_size_in_kb = 512;
956 } else {
957 flash_size_in_kb -= 512;
958 /* bank1 also uses a register offset */
959 stm32x_info->register_base = FLASH_REG_BASE_B1;
960 base_address = 0x08080000;
961 }
962 }
963
964 /* if the user sets the size manually then ignore the probed value
965 * this allows us to work around devices that have a invalid flash size register value */
966 if (bank->size) {
967 LOG_INFO("ignoring flash probed value, using configured bank size");
968 flash_size_in_kb = bank->size / 1024;
969 }
970
971 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
972
973 /* did we assign flash size? */
974 assert(flash_size_in_kb != 0xffff);
975
976 /* calculate numbers of pages */
977 int num_pages = flash_size_in_kb * 1024 / page_size;
978
979 /* check that calculation result makes sense */
980 assert(num_pages > 0);
981
982 if (bank->sectors) {
983 free(bank->sectors);
984 bank->sectors = NULL;
985 }
986
987 bank->base = base_address;
988 bank->size = (num_pages * page_size);
989 bank->num_sectors = num_pages;
990 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
991
992 for (i = 0; i < num_pages; i++) {
993 bank->sectors[i].offset = i * page_size;
994 bank->sectors[i].size = page_size;
995 bank->sectors[i].is_erased = -1;
996 bank->sectors[i].is_protected = 1;
997 }
998
999 stm32x_info->probed = 1;
1000
1001 return ERROR_OK;
1002 }
1003
1004 static int stm32x_auto_probe(struct flash_bank *bank)
1005 {
1006 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1007 if (stm32x_info->probed)
1008 return ERROR_OK;
1009 return stm32x_probe(bank);
1010 }
1011
1012 #if 0
1013 COMMAND_HANDLER(stm32x_handle_part_id_command)
1014 {
1015 return ERROR_OK;
1016 }
1017 #endif
1018
1019 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1020 {
1021 uint32_t device_id;
1022 int printed;
1023
1024 /* read stm32 device id register */
1025 int retval = stm32x_get_device_id(bank, &device_id);
1026 if (retval != ERROR_OK)
1027 return retval;
1028
1029 if ((device_id & 0xfff) == 0x410) {
1030 printed = snprintf(buf, buf_size, "stm32x (Medium Density) - Rev: ");
1031 buf += printed;
1032 buf_size -= printed;
1033
1034 switch (device_id >> 16) {
1035 case 0x0000:
1036 snprintf(buf, buf_size, "A");
1037 break;
1038
1039 case 0x2000:
1040 snprintf(buf, buf_size, "B");
1041 break;
1042
1043 case 0x2001:
1044 snprintf(buf, buf_size, "Z");
1045 break;
1046
1047 case 0x2003:
1048 snprintf(buf, buf_size, "Y");
1049 break;
1050
1051 default:
1052 snprintf(buf, buf_size, "unknown");
1053 break;
1054 }
1055 } else if ((device_id & 0xfff) == 0x412) {
1056 printed = snprintf(buf, buf_size, "stm32x (Low Density) - Rev: ");
1057 buf += printed;
1058 buf_size -= printed;
1059
1060 switch (device_id >> 16) {
1061 case 0x1000:
1062 snprintf(buf, buf_size, "A");
1063 break;
1064
1065 default:
1066 snprintf(buf, buf_size, "unknown");
1067 break;
1068 }
1069 } else if ((device_id & 0xfff) == 0x414) {
1070 printed = snprintf(buf, buf_size, "stm32x (High Density) - Rev: ");
1071 buf += printed;
1072 buf_size -= printed;
1073
1074 switch (device_id >> 16) {
1075 case 0x1000:
1076 snprintf(buf, buf_size, "A");
1077 break;
1078
1079 case 0x1001:
1080 snprintf(buf, buf_size, "Z");
1081 break;
1082
1083 default:
1084 snprintf(buf, buf_size, "unknown");
1085 break;
1086 }
1087 } else if ((device_id & 0xfff) == 0x418) {
1088 printed = snprintf(buf, buf_size, "stm32x (Connectivity) - Rev: ");
1089 buf += printed;
1090 buf_size -= printed;
1091
1092 switch (device_id >> 16) {
1093 case 0x1000:
1094 snprintf(buf, buf_size, "A");
1095 break;
1096
1097 case 0x1001:
1098 snprintf(buf, buf_size, "Z");
1099 break;
1100
1101 default:
1102 snprintf(buf, buf_size, "unknown");
1103 break;
1104 }
1105 } else if ((device_id & 0xfff) == 0x420) {
1106 printed = snprintf(buf, buf_size, "stm32x (Value) - Rev: ");
1107 buf += printed;
1108 buf_size -= printed;
1109
1110 switch (device_id >> 16) {
1111 case 0x1000:
1112 snprintf(buf, buf_size, "A");
1113 break;
1114
1115 case 0x1001:
1116 snprintf(buf, buf_size, "Z");
1117 break;
1118
1119 default:
1120 snprintf(buf, buf_size, "unknown");
1121 break;
1122 }
1123 } else if ((device_id & 0xfff) == 0x422) {
1124 printed = snprintf(buf, buf_size, "stm32f30x - Rev: ");
1125 buf += printed;
1126 buf_size -= printed;
1127
1128 switch (device_id >> 16) {
1129 case 0x1000:
1130 snprintf(buf, buf_size, "A");
1131 break;
1132
1133 case 0x1001:
1134 snprintf(buf, buf_size, "Z");
1135 break;
1136
1137 case 0x2000:
1138 snprintf(buf, buf_size, "B");
1139 break;
1140
1141 default:
1142 snprintf(buf, buf_size, "unknown");
1143 break;
1144 }
1145 } else if ((device_id & 0xfff) == 0x428) {
1146 printed = snprintf(buf, buf_size, "stm32x (Value HD) - Rev: ");
1147 buf += printed;
1148 buf_size -= printed;
1149
1150 switch (device_id >> 16) {
1151 case 0x1000:
1152 snprintf(buf, buf_size, "A");
1153 break;
1154
1155 case 0x1001:
1156 snprintf(buf, buf_size, "Z");
1157 break;
1158
1159 default:
1160 snprintf(buf, buf_size, "unknown");
1161 break;
1162 }
1163 } else if ((device_id & 0xfff) == 0x430) {
1164 printed = snprintf(buf, buf_size, "stm32x (XL) - Rev: ");
1165 buf += printed;
1166 buf_size -= printed;
1167
1168 switch (device_id >> 16) {
1169 case 0x1000:
1170 snprintf(buf, buf_size, "A");
1171 break;
1172
1173 default:
1174 snprintf(buf, buf_size, "unknown");
1175 break;
1176 }
1177 } else if ((device_id & 0xfff) == 0x432) {
1178 printed = snprintf(buf, buf_size, "stm32f37x - Rev: ");
1179 buf += printed;
1180 buf_size -= printed;
1181
1182 switch (device_id >> 16) {
1183 case 0x1000:
1184 snprintf(buf, buf_size, "A");
1185 break;
1186
1187 case 0x2000:
1188 snprintf(buf, buf_size, "B");
1189 break;
1190
1191 default:
1192 snprintf(buf, buf_size, "unknown");
1193 break;
1194 }
1195 } else if ((device_id & 0xfff) == 0x440) {
1196 printed = snprintf(buf, buf_size, "stm32f0x - Rev: ");
1197 buf += printed;
1198 buf_size -= printed;
1199
1200 switch (device_id >> 16) {
1201 case 0x1000:
1202 snprintf(buf, buf_size, "1.0");
1203 break;
1204
1205 case 0x2000:
1206 snprintf(buf, buf_size, "2.0");
1207 break;
1208
1209 default:
1210 snprintf(buf, buf_size, "unknown");
1211 break;
1212 }
1213 } else {
1214 snprintf(buf, buf_size, "Cannot identify target as a stm32x\n");
1215 return ERROR_FAIL;
1216 }
1217
1218 return ERROR_OK;
1219 }
1220
1221 COMMAND_HANDLER(stm32x_handle_lock_command)
1222 {
1223 struct target *target = NULL;
1224 struct stm32x_flash_bank *stm32x_info = NULL;
1225
1226 if (CMD_ARGC < 1)
1227 return ERROR_COMMAND_SYNTAX_ERROR;
1228
1229 struct flash_bank *bank;
1230 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1231 if (ERROR_OK != retval)
1232 return retval;
1233
1234 stm32x_info = bank->driver_priv;
1235
1236 target = bank->target;
1237
1238 if (target->state != TARGET_HALTED) {
1239 LOG_ERROR("Target not halted");
1240 return ERROR_TARGET_NOT_HALTED;
1241 }
1242
1243 retval = stm32x_check_operation_supported(bank);
1244 if (ERROR_OK != retval)
1245 return retval;
1246
1247 if (stm32x_erase_options(bank) != ERROR_OK) {
1248 command_print(CMD_CTX, "stm32x failed to erase options");
1249 return ERROR_OK;
1250 }
1251
1252 /* set readout protection */
1253 stm32x_info->option_bytes.RDP = 0;
1254
1255 if (stm32x_write_options(bank) != ERROR_OK) {
1256 command_print(CMD_CTX, "stm32x failed to lock device");
1257 return ERROR_OK;
1258 }
1259
1260 command_print(CMD_CTX, "stm32x locked");
1261
1262 return ERROR_OK;
1263 }
1264
1265 COMMAND_HANDLER(stm32x_handle_unlock_command)
1266 {
1267 struct target *target = NULL;
1268
1269 if (CMD_ARGC < 1)
1270 return ERROR_COMMAND_SYNTAX_ERROR;
1271
1272 struct flash_bank *bank;
1273 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1274 if (ERROR_OK != retval)
1275 return retval;
1276
1277 target = bank->target;
1278
1279 if (target->state != TARGET_HALTED) {
1280 LOG_ERROR("Target not halted");
1281 return ERROR_TARGET_NOT_HALTED;
1282 }
1283
1284 retval = stm32x_check_operation_supported(bank);
1285 if (ERROR_OK != retval)
1286 return retval;
1287
1288 if (stm32x_erase_options(bank) != ERROR_OK) {
1289 command_print(CMD_CTX, "stm32x failed to unlock device");
1290 return ERROR_OK;
1291 }
1292
1293 if (stm32x_write_options(bank) != ERROR_OK) {
1294 command_print(CMD_CTX, "stm32x failed to lock device");
1295 return ERROR_OK;
1296 }
1297
1298 command_print(CMD_CTX, "stm32x unlocked.\n"
1299 "INFO: a reset or power cycle is required "
1300 "for the new settings to take effect.");
1301
1302 return ERROR_OK;
1303 }
1304
1305 COMMAND_HANDLER(stm32x_handle_options_read_command)
1306 {
1307 uint32_t optionbyte;
1308 struct target *target = NULL;
1309 struct stm32x_flash_bank *stm32x_info = NULL;
1310
1311 if (CMD_ARGC < 1)
1312 return ERROR_COMMAND_SYNTAX_ERROR;
1313
1314 struct flash_bank *bank;
1315 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1316 if (ERROR_OK != retval)
1317 return retval;
1318
1319 stm32x_info = bank->driver_priv;
1320
1321 target = bank->target;
1322
1323 if (target->state != TARGET_HALTED) {
1324 LOG_ERROR("Target not halted");
1325 return ERROR_TARGET_NOT_HALTED;
1326 }
1327
1328 retval = stm32x_check_operation_supported(bank);
1329 if (ERROR_OK != retval)
1330 return retval;
1331
1332 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1333 if (retval != ERROR_OK)
1334 return retval;
1335 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1336
1337 int user_data = optionbyte;
1338
1339 if (buf_get_u32((uint8_t *)&optionbyte, OPT_ERROR, 1))
1340 command_print(CMD_CTX, "Option Byte Complement Error");
1341
1342 if (buf_get_u32((uint8_t *)&optionbyte, OPT_READOUT, 1))
1343 command_print(CMD_CTX, "Readout Protection On");
1344 else
1345 command_print(CMD_CTX, "Readout Protection Off");
1346
1347 /* user option bytes are offset depending on variant */
1348 optionbyte >>= stm32x_info->option_offset;
1349
1350 if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDWDGSW, 1))
1351 command_print(CMD_CTX, "Software Watchdog");
1352 else
1353 command_print(CMD_CTX, "Hardware Watchdog");
1354
1355 if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTOP, 1))
1356 command_print(CMD_CTX, "Stop: No reset generated");
1357 else
1358 command_print(CMD_CTX, "Stop: Reset generated");
1359
1360 if (buf_get_u32((uint8_t *)&optionbyte, OPT_RDRSTSTDBY, 1))
1361 command_print(CMD_CTX, "Standby: No reset generated");
1362 else
1363 command_print(CMD_CTX, "Standby: Reset generated");
1364
1365 if (stm32x_info->has_dual_banks) {
1366 if (buf_get_u32((uint8_t *)&optionbyte, OPT_BFB2, 1))
1367 command_print(CMD_CTX, "Boot: Bank 0");
1368 else
1369 command_print(CMD_CTX, "Boot: Bank 1");
1370 }
1371
1372 command_print(CMD_CTX, "User Option0: 0x%02" PRIx8,
1373 (user_data >> stm32x_info->user_data_offset) & 0xff);
1374 command_print(CMD_CTX, "User Option1: 0x%02" PRIx8,
1375 (user_data >> (stm32x_info->user_data_offset + 8)) & 0xff);
1376
1377 return ERROR_OK;
1378 }
1379
1380 COMMAND_HANDLER(stm32x_handle_options_write_command)
1381 {
1382 struct target *target = NULL;
1383 struct stm32x_flash_bank *stm32x_info = NULL;
1384 uint16_t optionbyte;
1385
1386 if (CMD_ARGC < 2)
1387 return ERROR_COMMAND_SYNTAX_ERROR;
1388
1389 struct flash_bank *bank;
1390 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1391 if (ERROR_OK != retval)
1392 return retval;
1393
1394 stm32x_info = bank->driver_priv;
1395
1396 target = bank->target;
1397
1398 if (target->state != TARGET_HALTED) {
1399 LOG_ERROR("Target not halted");
1400 return ERROR_TARGET_NOT_HALTED;
1401 }
1402
1403 retval = stm32x_check_operation_supported(bank);
1404 if (ERROR_OK != retval)
1405 return retval;
1406
1407 retval = stm32x_read_options(bank);
1408 if (ERROR_OK != retval)
1409 return retval;
1410
1411 /* start with current options */
1412 optionbyte = stm32x_info->option_bytes.user_options;
1413
1414 /* skip over flash bank */
1415 CMD_ARGC--;
1416 CMD_ARGV++;
1417
1418 while (CMD_ARGC) {
1419 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1420 optionbyte |= (1 << 0);
1421 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1422 optionbyte &= ~(1 << 0);
1423 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1424 optionbyte &= ~(1 << 1);
1425 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1426 optionbyte &= ~(1 << 1);
1427 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1428 optionbyte &= ~(1 << 2);
1429 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1430 optionbyte &= ~(1 << 2);
1431 else if (stm32x_info->has_dual_banks) {
1432 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1433 optionbyte |= (1 << 3);
1434 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1435 optionbyte &= ~(1 << 3);
1436 else
1437 return ERROR_COMMAND_SYNTAX_ERROR;
1438 } else
1439 return ERROR_COMMAND_SYNTAX_ERROR;
1440 CMD_ARGC--;
1441 CMD_ARGV++;
1442 }
1443
1444 if (stm32x_erase_options(bank) != ERROR_OK) {
1445 command_print(CMD_CTX, "stm32x failed to erase options");
1446 return ERROR_OK;
1447 }
1448
1449 stm32x_info->option_bytes.user_options = optionbyte;
1450
1451 if (stm32x_write_options(bank) != ERROR_OK) {
1452 command_print(CMD_CTX, "stm32x failed to write options");
1453 return ERROR_OK;
1454 }
1455
1456 command_print(CMD_CTX, "stm32x write options complete.\n"
1457 "INFO: a reset or power cycle is required "
1458 "for the new settings to take effect.");
1459
1460 return ERROR_OK;
1461 }
1462
1463 static int stm32x_mass_erase(struct flash_bank *bank)
1464 {
1465 struct target *target = bank->target;
1466
1467 if (target->state != TARGET_HALTED) {
1468 LOG_ERROR("Target not halted");
1469 return ERROR_TARGET_NOT_HALTED;
1470 }
1471
1472 /* unlock option flash registers */
1473 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1474 if (retval != ERROR_OK)
1475 return retval;
1476 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1477 if (retval != ERROR_OK)
1478 return retval;
1479
1480 /* mass erase flash memory */
1481 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1482 if (retval != ERROR_OK)
1483 return retval;
1484 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1485 FLASH_MER | FLASH_STRT);
1486 if (retval != ERROR_OK)
1487 return retval;
1488
1489 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1490 if (retval != ERROR_OK)
1491 return retval;
1492
1493 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1494 if (retval != ERROR_OK)
1495 return retval;
1496
1497 return ERROR_OK;
1498 }
1499
1500 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1501 {
1502 int i;
1503
1504 if (CMD_ARGC < 1)
1505 return ERROR_COMMAND_SYNTAX_ERROR;
1506
1507 struct flash_bank *bank;
1508 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1509 if (ERROR_OK != retval)
1510 return retval;
1511
1512 retval = stm32x_mass_erase(bank);
1513 if (retval == ERROR_OK) {
1514 /* set all sectors as erased */
1515 for (i = 0; i < bank->num_sectors; i++)
1516 bank->sectors[i].is_erased = 1;
1517
1518 command_print(CMD_CTX, "stm32x mass erase complete");
1519 } else
1520 command_print(CMD_CTX, "stm32x mass erase failed");
1521
1522 return retval;
1523 }
1524
1525 static const struct command_registration stm32x_exec_command_handlers[] = {
1526 {
1527 .name = "lock",
1528 .handler = stm32x_handle_lock_command,
1529 .mode = COMMAND_EXEC,
1530 .usage = "bank_id",
1531 .help = "Lock entire flash device.",
1532 },
1533 {
1534 .name = "unlock",
1535 .handler = stm32x_handle_unlock_command,
1536 .mode = COMMAND_EXEC,
1537 .usage = "bank_id",
1538 .help = "Unlock entire protected flash device.",
1539 },
1540 {
1541 .name = "mass_erase",
1542 .handler = stm32x_handle_mass_erase_command,
1543 .mode = COMMAND_EXEC,
1544 .usage = "bank_id",
1545 .help = "Erase entire flash device.",
1546 },
1547 {
1548 .name = "options_read",
1549 .handler = stm32x_handle_options_read_command,
1550 .mode = COMMAND_EXEC,
1551 .usage = "bank_id",
1552 .help = "Read and display device option byte.",
1553 },
1554 {
1555 .name = "options_write",
1556 .handler = stm32x_handle_options_write_command,
1557 .mode = COMMAND_EXEC,
1558 .usage = "bank_id ('SWWDG'|'HWWDG') "
1559 "('RSTSTNDBY'|'NORSTSTNDBY') "
1560 "('RSTSTOP'|'NORSTSTOP')",
1561 .help = "Replace bits in device option byte.",
1562 },
1563 COMMAND_REGISTRATION_DONE
1564 };
1565
1566 static const struct command_registration stm32x_command_handlers[] = {
1567 {
1568 .name = "stm32f1x",
1569 .mode = COMMAND_ANY,
1570 .help = "stm32f1x flash command group",
1571 .usage = "",
1572 .chain = stm32x_exec_command_handlers,
1573 },
1574 COMMAND_REGISTRATION_DONE
1575 };
1576
1577 struct flash_driver stm32f1x_flash = {
1578 .name = "stm32f1x",
1579 .commands = stm32x_command_handlers,
1580 .flash_bank_command = stm32x_flash_bank_command,
1581 .erase = stm32x_erase,
1582 .protect = stm32x_protect,
1583 .write = stm32x_write,
1584 .read = default_flash_read,
1585 .probe = stm32x_probe,
1586 .auto_probe = stm32x_auto_probe,
1587 .erase_check = default_flash_blank_check,
1588 .protect_check = stm32x_protect_check,
1589 .info = get_stm32x_info,
1590 };
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