Code Review / openocd.git / blob
? search:


90cee641206a3c792601096e5bdb8e985dfbe98b
[openocd.git] / src / flash / nor / stm32f1x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/cortex_m.h>
33
34 /* stm32x register locations */
35
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
38
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
47
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
59
60 /* option byte location */
61
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
70
71 /* FLASH_CR register bits */
72
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
81 #define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
82
83 /* FLASH_SR register bits */
84
85 #define FLASH_BSY (1 << 0)
86 #define FLASH_PGERR (1 << 2)
87 #define FLASH_WRPRTERR (1 << 4)
88 #define FLASH_EOP (1 << 5)
89
90 /* STM32_FLASH_OBR bit definitions (reading) */
91
92 #define OPT_ERROR 0
93 #define OPT_READOUT 1
94 #define OPT_RDWDGSW 2
95 #define OPT_RDRSTSTOP 3
96 #define OPT_RDRSTSTDBY 4
97 #define OPT_BFB2 5 /* dual flash bank only */
98
99 /* register unlock keys */
100
101 #define KEY1 0x45670123
102 #define KEY2 0xCDEF89AB
103
104 /* timeout values */
105
106 #define FLASH_WRITE_TIMEOUT 10
107 #define FLASH_ERASE_TIMEOUT 100
108
109 struct stm32x_options {
110 uint8_t rdp;
111 uint8_t user;
112 uint16_t data;
113 uint32_t protection;
114 };
115
116 struct stm32x_flash_bank {
117 struct stm32x_options option_bytes;
118 int ppage_size;
119 bool probed;
120
121 bool has_dual_banks;
122 /* used to access dual flash bank stm32xl */
123 bool can_load_options;
124 uint32_t register_base;
125 uint8_t default_rdp;
126 int user_data_offset;
127 int option_offset;
128 uint32_t user_bank_size;
129 };
130
131 static int stm32x_mass_erase(struct flash_bank *bank);
132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
134 uint32_t address, uint32_t count);
135
136 /* flash bank stm32x <base> <size> 0 0 <target#>
137 */
138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
139 {
140 struct stm32x_flash_bank *stm32x_info;
141
142 if (CMD_ARGC < 6)
143 return ERROR_COMMAND_SYNTAX_ERROR;
144
145 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
146
147 bank->driver_priv = stm32x_info;
148 stm32x_info->probed = false;
149 stm32x_info->has_dual_banks = false;
150 stm32x_info->can_load_options = false;
151 stm32x_info->register_base = FLASH_REG_BASE_B0;
152 stm32x_info->user_bank_size = bank->size;
153
154 return ERROR_OK;
155 }
156
157 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
158 {
159 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
160 return reg + stm32x_info->register_base;
161 }
162
163 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
164 {
165 struct target *target = bank->target;
166 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
167 }
168
169 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
170 {
171 struct target *target = bank->target;
172 uint32_t status;
173 int retval = ERROR_OK;
174
175 /* wait for busy to clear */
176 for (;;) {
177 retval = stm32x_get_flash_status(bank, &status);
178 if (retval != ERROR_OK)
179 return retval;
180 LOG_DEBUG("status: 0x%" PRIx32 "", status);
181 if ((status & FLASH_BSY) == 0)
182 break;
183 if (timeout-- <= 0) {
184 LOG_ERROR("timed out waiting for flash");
185 return ERROR_FAIL;
186 }
187 alive_sleep(1);
188 }
189
190 if (status & FLASH_WRPRTERR) {
191 LOG_ERROR("stm32x device protected");
192 retval = ERROR_FAIL;
193 }
194
195 if (status & FLASH_PGERR) {
196 LOG_ERROR("stm32x device programming failed");
197 retval = ERROR_FAIL;
198 }
199
200 /* Clear but report errors */
201 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
202 /* If this operation fails, we ignore it and report the original
203 * retval
204 */
205 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
206 FLASH_WRPRTERR | FLASH_PGERR);
207 }
208 return retval;
209 }
210
211 static int stm32x_check_operation_supported(struct flash_bank *bank)
212 {
213 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
214
215 /* if we have a dual flash bank device then
216 * we need to perform option byte stuff on bank0 only */
217 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
218 LOG_ERROR("Option byte operations must use bank 0");
219 return ERROR_FLASH_OPERATION_FAILED;
220 }
221
222 return ERROR_OK;
223 }
224
225 static int stm32x_read_options(struct flash_bank *bank)
226 {
227 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
228 struct target *target = bank->target;
229 uint32_t option_bytes;
230 int retval;
231
232 /* read user and read protection option bytes, user data option bytes */
233 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &option_bytes);
234 if (retval != ERROR_OK)
235 return retval;
236
237 stm32x_info->option_bytes.rdp = (option_bytes & (1 << OPT_READOUT)) ? 0 : stm32x_info->default_rdp;
238 stm32x_info->option_bytes.user = (option_bytes >> stm32x_info->option_offset >> 2) & 0xff;
239 stm32x_info->option_bytes.data = (option_bytes >> stm32x_info->user_data_offset) & 0xffff;
240
241 /* read write protection option bytes */
242 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &stm32x_info->option_bytes.protection);
243 if (retval != ERROR_OK)
244 return retval;
245
246 return ERROR_OK;
247 }
248
249 static int stm32x_erase_options(struct flash_bank *bank)
250 {
251 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
252 struct target *target = bank->target;
253
254 /* read current options */
255 stm32x_read_options(bank);
256
257 /* unlock flash registers */
258 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
259 if (retval != ERROR_OK)
260 return retval;
261
262 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
263 if (retval != ERROR_OK)
264 return retval;
265
266 /* unlock option flash registers */
267 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
268 if (retval != ERROR_OK)
269 return retval;
270 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
271 if (retval != ERROR_OK)
272 return retval;
273
274 /* erase option bytes */
275 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
276 if (retval != ERROR_OK)
277 return retval;
278 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
279 if (retval != ERROR_OK)
280 return retval;
281
282 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
283 if (retval != ERROR_OK)
284 return retval;
285
286 /* clear read protection option byte
287 * this will also force a device unlock if set */
288 stm32x_info->option_bytes.rdp = stm32x_info->default_rdp;
289
290 return ERROR_OK;
291 }
292
293 static int stm32x_write_options(struct flash_bank *bank)
294 {
295 struct stm32x_flash_bank *stm32x_info = NULL;
296 struct target *target = bank->target;
297
298 stm32x_info = bank->driver_priv;
299
300 /* unlock flash registers */
301 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
302 if (retval != ERROR_OK)
303 return retval;
304 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
305 if (retval != ERROR_OK)
306 return retval;
307
308 /* unlock option flash registers */
309 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
310 if (retval != ERROR_OK)
311 return retval;
312 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
313 if (retval != ERROR_OK)
314 return retval;
315
316 /* program option bytes */
317 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
318 if (retval != ERROR_OK)
319 return retval;
320
321 uint8_t opt_bytes[16];
322
323 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.rdp);
324 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user);
325 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.data & 0xff);
326 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.data >> 8) & 0xff);
327 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection & 0xff);
328 target_buffer_set_u16(target, opt_bytes + 10, (stm32x_info->option_bytes.protection >> 8) & 0xff);
329 target_buffer_set_u16(target, opt_bytes + 12, (stm32x_info->option_bytes.protection >> 16) & 0xff);
330 target_buffer_set_u16(target, opt_bytes + 14, (stm32x_info->option_bytes.protection >> 24) & 0xff);
331
332 retval = stm32x_write_block(bank, opt_bytes, STM32_OB_RDP, sizeof(opt_bytes) / 2);
333 if (retval != ERROR_OK) {
334 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
335 LOG_ERROR("working area required to erase options bytes");
336 return retval;
337 }
338
339 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
340 if (retval != ERROR_OK)
341 return retval;
342
343 return ERROR_OK;
344 }
345
346 static int stm32x_protect_check(struct flash_bank *bank)
347 {
348 struct target *target = bank->target;
349 uint32_t protection;
350
351 int retval = stm32x_check_operation_supported(bank);
352 if (retval != ERROR_OK)
353 return retval;
354
355 /* medium density - each bit refers to a 4 sector protection block
356 * high density - each bit refers to a 2 sector protection block
357 * bit 31 refers to all remaining sectors in a bank */
358 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
359 if (retval != ERROR_OK)
360 return retval;
361
362 for (unsigned int i = 0; i < bank->num_prot_blocks; i++)
363 bank->prot_blocks[i].is_protected = (protection & (1 << i)) ? 0 : 1;
364
365 return ERROR_OK;
366 }
367
368 static int stm32x_erase(struct flash_bank *bank, unsigned int first,
369 unsigned int last)
370 {
371 struct target *target = bank->target;
372
373 if (bank->target->state != TARGET_HALTED) {
374 LOG_ERROR("Target not halted");
375 return ERROR_TARGET_NOT_HALTED;
376 }
377
378 if ((first == 0) && (last == (bank->num_sectors - 1)))
379 return stm32x_mass_erase(bank);
380
381 /* unlock flash registers */
382 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
383 if (retval != ERROR_OK)
384 return retval;
385 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
386 if (retval != ERROR_OK)
387 return retval;
388
389 for (unsigned int i = first; i <= last; i++) {
390 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
391 if (retval != ERROR_OK)
392 return retval;
393 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
394 bank->base + bank->sectors[i].offset);
395 if (retval != ERROR_OK)
396 return retval;
397 retval = target_write_u32(target,
398 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
399 if (retval != ERROR_OK)
400 return retval;
401
402 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
403 if (retval != ERROR_OK)
404 return retval;
405 }
406
407 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
408 if (retval != ERROR_OK)
409 return retval;
410
411 return ERROR_OK;
412 }
413
414 static int stm32x_protect(struct flash_bank *bank, int set, unsigned int first,
415 unsigned int last)
416 {
417 struct target *target = bank->target;
418 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
419
420 if (target->state != TARGET_HALTED) {
421 LOG_ERROR("Target not halted");
422 return ERROR_TARGET_NOT_HALTED;
423 }
424
425 int retval = stm32x_check_operation_supported(bank);
426 if (retval != ERROR_OK)
427 return retval;
428
429 retval = stm32x_erase_options(bank);
430 if (retval != ERROR_OK) {
431 LOG_ERROR("stm32x failed to erase options");
432 return retval;
433 }
434
435 for (unsigned int i = first; i <= last; i++) {
436 if (set)
437 stm32x_info->option_bytes.protection &= ~(1 << i);
438 else
439 stm32x_info->option_bytes.protection |= (1 << i);
440 }
441
442 return stm32x_write_options(bank);
443 }
444
445 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
446 uint32_t address, uint32_t count)
447 {
448 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
449 struct target *target = bank->target;
450 uint32_t buffer_size = 16384;
451 struct working_area *write_algorithm;
452 struct working_area *source;
453 struct reg_param reg_params[5];
454 struct armv7m_algorithm armv7m_info;
455 int retval = ERROR_OK;
456
457 static const uint8_t stm32x_flash_write_code[] = {
458 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
459 };
460
461 /* flash write code */
462 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
463 &write_algorithm) != ERROR_OK) {
464 LOG_WARNING("no working area available, can't do block memory writes");
465 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
466 }
467
468 retval = target_write_buffer(target, write_algorithm->address,
469 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
470 if (retval != ERROR_OK) {
471 target_free_working_area(target, write_algorithm);
472 return retval;
473 }
474
475 /* memory buffer */
476 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
477 buffer_size /= 2;
478 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
479 if (buffer_size <= 256) {
480 /* we already allocated the writing code, but failed to get a
481 * buffer, free the algorithm */
482 target_free_working_area(target, write_algorithm);
483
484 LOG_WARNING("no large enough working area available, can't do block memory writes");
485 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
486 }
487 }
488
489 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
490 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
491 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
492 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
493 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
494
495 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
496 buf_set_u32(reg_params[1].value, 0, 32, count);
497 buf_set_u32(reg_params[2].value, 0, 32, source->address);
498 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
499 buf_set_u32(reg_params[4].value, 0, 32, address);
500
501 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
502 armv7m_info.core_mode = ARM_MODE_THREAD;
503
504 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
505 0, NULL,
506 5, reg_params,
507 source->address, source->size,
508 write_algorithm->address, 0,
509 &armv7m_info);
510
511 if (retval == ERROR_FLASH_OPERATION_FAILED) {
512 LOG_ERROR("flash write failed at address 0x%"PRIx32,
513 buf_get_u32(reg_params[4].value, 0, 32));
514
515 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
516 LOG_ERROR("flash memory not erased before writing");
517 /* Clear but report errors */
518 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
519 }
520
521 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
522 LOG_ERROR("flash memory write protected");
523 /* Clear but report errors */
524 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
525 }
526 }
527
528 target_free_working_area(target, source);
529 target_free_working_area(target, write_algorithm);
530
531 destroy_reg_param(&reg_params[0]);
532 destroy_reg_param(&reg_params[1]);
533 destroy_reg_param(&reg_params[2]);
534 destroy_reg_param(&reg_params[3]);
535 destroy_reg_param(&reg_params[4]);
536
537 return retval;
538 }
539
540 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
541 uint32_t offset, uint32_t count)
542 {
543 struct target *target = bank->target;
544 uint8_t *new_buffer = NULL;
545
546 if (bank->target->state != TARGET_HALTED) {
547 LOG_ERROR("Target not halted");
548 return ERROR_TARGET_NOT_HALTED;
549 }
550
551 if (offset & 0x1) {
552 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
553 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
554 }
555
556 /* If there's an odd number of bytes, the data has to be padded. Duplicate
557 * the buffer and use the normal code path with a single block write since
558 * it's probably cheaper than to special case the last odd write using
559 * discrete accesses. */
560 if (count & 1) {
561 new_buffer = malloc(count + 1);
562 if (!new_buffer) {
563 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
564 return ERROR_FAIL;
565 }
566 LOG_INFO("odd number of bytes to write, padding with 0xff");
567 buffer = memcpy(new_buffer, buffer, count);
568 new_buffer[count++] = 0xff;
569 }
570
571 uint32_t words_remaining = count / 2;
572 int retval, retval2;
573
574 /* unlock flash registers */
575 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
576 if (retval != ERROR_OK)
577 goto cleanup;
578 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
579 if (retval != ERROR_OK)
580 goto cleanup;
581
582 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
583 if (retval != ERROR_OK)
584 goto cleanup;
585
586 /* try using a block write */
587 retval = stm32x_write_block(bank, buffer, bank->base + offset, words_remaining);
588
589 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
590 /* if block write failed (no sufficient working area),
591 * we use normal (slow) single halfword accesses */
592 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
593
594 while (words_remaining > 0) {
595 uint16_t value;
596 memcpy(&value, buffer, sizeof(uint16_t));
597
598 retval = target_write_u16(target, bank->base + offset, value);
599 if (retval != ERROR_OK)
600 goto reset_pg_and_lock;
601
602 retval = stm32x_wait_status_busy(bank, 5);
603 if (retval != ERROR_OK)
604 goto reset_pg_and_lock;
605
606 words_remaining--;
607 buffer += 2;
608 offset += 2;
609 }
610 }
611
612 reset_pg_and_lock:
613 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
614 if (retval == ERROR_OK)
615 retval = retval2;
616
617 cleanup:
618 free(new_buffer);
619 return retval;
620 }
621
622 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
623 {
624 struct target *target = bank->target;
625 struct cortex_m_common *cortex_m = target_to_cm(target);
626 uint32_t device_id_register = 0;
627
628 if (!target_was_examined(target)) {
629 LOG_ERROR("Target not examined yet");
630 return ERROR_FAIL;
631 }
632
633 switch (cortex_m->core_info->partno) {
634 case CORTEX_M0_PARTNO: /* STM32F0x devices */
635 device_id_register = 0x40015800;
636 break;
637 case CORTEX_M3_PARTNO: /* STM32F1x devices */
638 device_id_register = 0xE0042000;
639 break;
640 case CORTEX_M4_PARTNO: /* STM32F3x devices */
641 device_id_register = 0xE0042000;
642 break;
643 case CORTEX_M23_PARTNO: /* GD32E23x devices */
644 device_id_register = 0x40015800;
645 break;
646 default:
647 LOG_ERROR("Cannot identify target as a stm32x");
648 return ERROR_FAIL;
649 }
650
651 /* read stm32 device id register */
652 int retval = target_read_u32(target, device_id_register, device_id);
653 if (retval != ERROR_OK)
654 return retval;
655
656 return retval;
657 }
658
659 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
660 {
661 struct target *target = bank->target;
662 struct cortex_m_common *cortex_m = target_to_cm(target);
663 uint32_t flash_size_reg;
664
665 if (!target_was_examined(target)) {
666 LOG_ERROR("Target not examined yet");
667 return ERROR_FAIL;
668 }
669
670 switch (cortex_m->core_info->partno) {
671 case CORTEX_M0_PARTNO: /* STM32F0x devices */
672 flash_size_reg = 0x1FFFF7CC;
673 break;
674 case CORTEX_M3_PARTNO: /* STM32F1x devices */
675 flash_size_reg = 0x1FFFF7E0;
676 break;
677 case CORTEX_M4_PARTNO: /* STM32F3x devices */
678 flash_size_reg = 0x1FFFF7CC;
679 break;
680 case CORTEX_M23_PARTNO: /* GD32E23x devices */
681 flash_size_reg = 0x1FFFF7E0;
682 break;
683 default:
684 LOG_ERROR("Cannot identify target as a stm32x");
685 return ERROR_FAIL;
686 }
687
688 int retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
689 if (retval != ERROR_OK)
690 return retval;
691
692 return retval;
693 }
694
695 static int stm32x_probe(struct flash_bank *bank)
696 {
697 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
698 uint16_t flash_size_in_kb;
699 uint16_t max_flash_size_in_kb;
700 uint32_t dbgmcu_idcode;
701 int page_size;
702 uint32_t base_address = 0x08000000;
703
704 stm32x_info->probed = false;
705 stm32x_info->register_base = FLASH_REG_BASE_B0;
706 stm32x_info->user_data_offset = 10;
707 stm32x_info->option_offset = 0;
708
709 /* default factory read protection level 0 */
710 stm32x_info->default_rdp = 0xA5;
711
712 /* read stm32 device id register */
713 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
714 if (retval != ERROR_OK)
715 return retval;
716
717 LOG_INFO("device id = 0x%08" PRIx32 "", dbgmcu_idcode);
718
719 uint16_t device_id = dbgmcu_idcode & 0xfff;
720 uint16_t rev_id = dbgmcu_idcode >> 16;
721
722 /* set page size, protection granularity and max flash size depending on family */
723 switch (device_id) {
724 case 0x440: /* stm32f05x */
725 page_size = 1024;
726 stm32x_info->ppage_size = 4;
727 max_flash_size_in_kb = 64;
728 stm32x_info->user_data_offset = 16;
729 stm32x_info->option_offset = 6;
730 stm32x_info->default_rdp = 0xAA;
731 stm32x_info->can_load_options = true;
732 break;
733 case 0x444: /* stm32f03x */
734 case 0x445: /* stm32f04x */
735 page_size = 1024;
736 stm32x_info->ppage_size = 4;
737 max_flash_size_in_kb = 32;
738 stm32x_info->user_data_offset = 16;
739 stm32x_info->option_offset = 6;
740 stm32x_info->default_rdp = 0xAA;
741 stm32x_info->can_load_options = true;
742 break;
743 case 0x448: /* stm32f07x */
744 page_size = 2048;
745 stm32x_info->ppage_size = 4;
746 max_flash_size_in_kb = 128;
747 stm32x_info->user_data_offset = 16;
748 stm32x_info->option_offset = 6;
749 stm32x_info->default_rdp = 0xAA;
750 stm32x_info->can_load_options = true;
751 break;
752 case 0x442: /* stm32f09x */
753 page_size = 2048;
754 stm32x_info->ppage_size = 4;
755 max_flash_size_in_kb = 256;
756 stm32x_info->user_data_offset = 16;
757 stm32x_info->option_offset = 6;
758 stm32x_info->default_rdp = 0xAA;
759 stm32x_info->can_load_options = true;
760 break;
761 case 0x410: /* stm32f1x medium-density */
762 page_size = 1024;
763 stm32x_info->ppage_size = 4;
764 max_flash_size_in_kb = 128;
765 /* GigaDevice GD32F1x0 & GD32F3x0 & GD32E23x series devices
766 share DEV_ID with STM32F101/2/3 medium-density line,
767 however they use a REV_ID different from any STM32 device.
768 The main difference is another offset of user option bits
769 (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register
770 (FLASH_OBR/FMC_OBSTAT 0x4002201C).
771 This caused problems e.g. during flash block programming
772 because of unexpected active hardware watchog. */
773 switch (rev_id) {
774 case 0x1303: /* gd32f1x0 */
775 stm32x_info->user_data_offset = 16;
776 stm32x_info->option_offset = 6;
777 max_flash_size_in_kb = 64;
778 break;
779 case 0x1704: /* gd32f3x0 */
780 stm32x_info->user_data_offset = 16;
781 stm32x_info->option_offset = 6;
782 break;
783 case 0x1909: /* gd32e23x */
784 stm32x_info->user_data_offset = 16;
785 stm32x_info->option_offset = 6;
786 max_flash_size_in_kb = 64;
787 break;
788 }
789 break;
790 case 0x412: /* stm32f1x low-density */
791 page_size = 1024;
792 stm32x_info->ppage_size = 4;
793 max_flash_size_in_kb = 32;
794 break;
795 case 0x414: /* stm32f1x high-density */
796 page_size = 2048;
797 stm32x_info->ppage_size = 2;
798 max_flash_size_in_kb = 512;
799 break;
800 case 0x418: /* stm32f1x connectivity */
801 page_size = 2048;
802 stm32x_info->ppage_size = 2;
803 max_flash_size_in_kb = 256;
804 break;
805 case 0x430: /* stm32f1 XL-density (dual flash banks) */
806 page_size = 2048;
807 stm32x_info->ppage_size = 2;
808 max_flash_size_in_kb = 1024;
809 stm32x_info->has_dual_banks = true;
810 break;
811 case 0x420: /* stm32f100xx low- and medium-density value line */
812 page_size = 1024;
813 stm32x_info->ppage_size = 4;
814 max_flash_size_in_kb = 128;
815 break;
816 case 0x428: /* stm32f100xx high-density value line */
817 page_size = 2048;
818 stm32x_info->ppage_size = 4;
819 max_flash_size_in_kb = 512;
820 break;
821 case 0x422: /* stm32f302/3xb/c */
822 page_size = 2048;
823 stm32x_info->ppage_size = 2;
824 max_flash_size_in_kb = 256;
825 stm32x_info->user_data_offset = 16;
826 stm32x_info->option_offset = 6;
827 stm32x_info->default_rdp = 0xAA;
828 stm32x_info->can_load_options = true;
829 break;
830 case 0x446: /* stm32f303xD/E */
831 page_size = 2048;
832 stm32x_info->ppage_size = 2;
833 max_flash_size_in_kb = 512;
834 stm32x_info->user_data_offset = 16;
835 stm32x_info->option_offset = 6;
836 stm32x_info->default_rdp = 0xAA;
837 stm32x_info->can_load_options = true;
838 break;
839 case 0x432: /* stm32f37x */
840 page_size = 2048;
841 stm32x_info->ppage_size = 2;
842 max_flash_size_in_kb = 256;
843 stm32x_info->user_data_offset = 16;
844 stm32x_info->option_offset = 6;
845 stm32x_info->default_rdp = 0xAA;
846 stm32x_info->can_load_options = true;
847 break;
848 case 0x438: /* stm32f33x */
849 case 0x439: /* stm32f302x6/8 */
850 page_size = 2048;
851 stm32x_info->ppage_size = 2;
852 max_flash_size_in_kb = 64;
853 stm32x_info->user_data_offset = 16;
854 stm32x_info->option_offset = 6;
855 stm32x_info->default_rdp = 0xAA;
856 stm32x_info->can_load_options = true;
857 break;
858 default:
859 LOG_WARNING("Cannot identify target as a STM32 family.");
860 return ERROR_FAIL;
861 }
862
863 /* get flash size from target. */
864 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
865
866 /* failed reading flash size or flash size invalid (early silicon),
867 * default to max target family */
868 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
869 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
870 max_flash_size_in_kb);
871 flash_size_in_kb = max_flash_size_in_kb;
872 }
873
874 if (stm32x_info->has_dual_banks) {
875 /* split reported size into matching bank */
876 if (bank->base != 0x08080000) {
877 /* bank 0 will be fixed 512k */
878 flash_size_in_kb = 512;
879 } else {
880 flash_size_in_kb -= 512;
881 /* bank1 also uses a register offset */
882 stm32x_info->register_base = FLASH_REG_BASE_B1;
883 base_address = 0x08080000;
884 }
885 }
886
887 /* if the user sets the size manually then ignore the probed value
888 * this allows us to work around devices that have a invalid flash size register value */
889 if (stm32x_info->user_bank_size) {
890 LOG_INFO("ignoring flash probed value, using configured bank size");
891 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
892 }
893
894 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
895
896 /* did we assign flash size? */
897 assert(flash_size_in_kb != 0xffff);
898
899 /* calculate numbers of pages */
900 int num_pages = flash_size_in_kb * 1024 / page_size;
901
902 /* check that calculation result makes sense */
903 assert(num_pages > 0);
904
905 free(bank->sectors);
906 bank->sectors = NULL;
907
908 free(bank->prot_blocks);
909 bank->prot_blocks = NULL;
910
911 bank->base = base_address;
912 bank->size = (num_pages * page_size);
913
914 bank->num_sectors = num_pages;
915 bank->sectors = alloc_block_array(0, page_size, num_pages);
916 if (!bank->sectors)
917 return ERROR_FAIL;
918
919 /* calculate number of write protection blocks */
920 int num_prot_blocks = num_pages / stm32x_info->ppage_size;
921 if (num_prot_blocks > 32)
922 num_prot_blocks = 32;
923
924 bank->num_prot_blocks = num_prot_blocks;
925 bank->prot_blocks = alloc_block_array(0, stm32x_info->ppage_size * page_size, num_prot_blocks);
926 if (!bank->prot_blocks)
927 return ERROR_FAIL;
928
929 if (num_prot_blocks == 32)
930 bank->prot_blocks[31].size = (num_pages - (31 * stm32x_info->ppage_size)) * page_size;
931
932 stm32x_info->probed = true;
933
934 return ERROR_OK;
935 }
936
937 static int stm32x_auto_probe(struct flash_bank *bank)
938 {
939 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
940 if (stm32x_info->probed)
941 return ERROR_OK;
942 return stm32x_probe(bank);
943 }
944
945 #if 0
946 COMMAND_HANDLER(stm32x_handle_part_id_command)
947 {
948 return ERROR_OK;
949 }
950 #endif
951
952 static const char *get_stm32f0_revision(uint16_t rev_id)
953 {
954 const char *rev_str = NULL;
955
956 switch (rev_id) {
957 case 0x1000:
958 rev_str = "1.0";
959 break;
960 case 0x2000:
961 rev_str = "2.0";
962 break;
963 }
964 return rev_str;
965 }
966
967 static int get_stm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
968 {
969 uint32_t dbgmcu_idcode;
970
971 /* read stm32 device id register */
972 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
973 if (retval != ERROR_OK)
974 return retval;
975
976 uint16_t device_id = dbgmcu_idcode & 0xfff;
977 uint16_t rev_id = dbgmcu_idcode >> 16;
978 const char *device_str;
979 const char *rev_str = NULL;
980
981 switch (device_id) {
982 case 0x410:
983 device_str = "STM32F10x (Medium Density)";
984
985 switch (rev_id) {
986 case 0x0000:
987 rev_str = "A";
988 break;
989
990 case 0x1303: /* gd32f1x0 */
991 device_str = "GD32F1x0";
992 break;
993
994 case 0x1704: /* gd32f3x0 */
995 device_str = "GD32F3x0";
996 break;
997
998 case 0x1909: /* gd32e23x */
999 device_str = "GD32E23x";
1000 break;
1001
1002 case 0x2000:
1003 rev_str = "B";
1004 break;
1005
1006 case 0x2001:
1007 rev_str = "Z";
1008 break;
1009
1010 case 0x2003:
1011 rev_str = "Y";
1012 break;
1013 }
1014 break;
1015
1016 case 0x412:
1017 device_str = "STM32F10x (Low Density)";
1018
1019 switch (rev_id) {
1020 case 0x1000:
1021 rev_str = "A";
1022 break;
1023 }
1024 break;
1025
1026 case 0x414:
1027 device_str = "STM32F10x (High Density)";
1028
1029 switch (rev_id) {
1030 case 0x1000:
1031 rev_str = "A";
1032 break;
1033
1034 case 0x1001:
1035 rev_str = "Z";
1036 break;
1037
1038 case 0x1003:
1039 rev_str = "Y";
1040 break;
1041 }
1042 break;
1043
1044 case 0x418:
1045 device_str = "STM32F10x (Connectivity)";
1046
1047 switch (rev_id) {
1048 case 0x1000:
1049 rev_str = "A";
1050 break;
1051
1052 case 0x1001:
1053 rev_str = "Z";
1054 break;
1055 }
1056 break;
1057
1058 case 0x420:
1059 device_str = "STM32F100 (Low/Medium Density)";
1060
1061 switch (rev_id) {
1062 case 0x1000:
1063 rev_str = "A";
1064 break;
1065
1066 case 0x1001:
1067 rev_str = "Z";
1068 break;
1069 }
1070 break;
1071
1072 case 0x422:
1073 device_str = "STM32F302xB/C";
1074
1075 switch (rev_id) {
1076 case 0x1000:
1077 rev_str = "A";
1078 break;
1079
1080 case 0x1001:
1081 rev_str = "Z";
1082 break;
1083
1084 case 0x1003:
1085 rev_str = "Y";
1086 break;
1087
1088 case 0x2000:
1089 rev_str = "B";
1090 break;
1091 }
1092 break;
1093
1094 case 0x428:
1095 device_str = "STM32F100 (High Density)";
1096
1097 switch (rev_id) {
1098 case 0x1000:
1099 rev_str = "A";
1100 break;
1101
1102 case 0x1001:
1103 rev_str = "Z";
1104 break;
1105 }
1106 break;
1107
1108 case 0x430:
1109 device_str = "STM32F10x (XL Density)";
1110
1111 switch (rev_id) {
1112 case 0x1000:
1113 rev_str = "A";
1114 break;
1115 }
1116 break;
1117
1118 case 0x432:
1119 device_str = "STM32F37x";
1120
1121 switch (rev_id) {
1122 case 0x1000:
1123 rev_str = "A";
1124 break;
1125
1126 case 0x2000:
1127 rev_str = "B";
1128 break;
1129 }
1130 break;
1131
1132 case 0x438:
1133 device_str = "STM32F33x";
1134
1135 switch (rev_id) {
1136 case 0x1000:
1137 rev_str = "A";
1138 break;
1139 }
1140 break;
1141
1142 case 0x439:
1143 device_str = "STM32F302x6/8";
1144
1145 switch (rev_id) {
1146 case 0x1000:
1147 rev_str = "A";
1148 break;
1149
1150 case 0x1001:
1151 rev_str = "Z";
1152 break;
1153 }
1154 break;
1155
1156 case 0x444:
1157 device_str = "STM32F03x";
1158 rev_str = get_stm32f0_revision(rev_id);
1159 break;
1160
1161 case 0x440:
1162 device_str = "STM32F05x";
1163 rev_str = get_stm32f0_revision(rev_id);
1164 break;
1165
1166 case 0x445:
1167 device_str = "STM32F04x";
1168 rev_str = get_stm32f0_revision(rev_id);
1169 break;
1170
1171 case 0x446:
1172 device_str = "STM32F303xD/E";
1173 switch (rev_id) {
1174 case 0x1000:
1175 rev_str = "A";
1176 break;
1177 }
1178 break;
1179
1180 case 0x448:
1181 device_str = "STM32F07x";
1182 rev_str = get_stm32f0_revision(rev_id);
1183 break;
1184
1185 case 0x442:
1186 device_str = "STM32F09x";
1187 rev_str = get_stm32f0_revision(rev_id);
1188 break;
1189
1190 default:
1191 command_print_sameline(cmd, "Cannot identify target as a STM32F0/1/3\n");
1192 return ERROR_FAIL;
1193 }
1194
1195 if (rev_str)
1196 command_print_sameline(cmd, "%s - Rev: %s", device_str, rev_str);
1197 else
1198 command_print_sameline(cmd, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1199
1200 return ERROR_OK;
1201 }
1202
1203 COMMAND_HANDLER(stm32x_handle_lock_command)
1204 {
1205 struct target *target = NULL;
1206 struct stm32x_flash_bank *stm32x_info = NULL;
1207
1208 if (CMD_ARGC < 1)
1209 return ERROR_COMMAND_SYNTAX_ERROR;
1210
1211 struct flash_bank *bank;
1212 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1213 if (retval != ERROR_OK)
1214 return retval;
1215
1216 stm32x_info = bank->driver_priv;
1217
1218 target = bank->target;
1219
1220 if (target->state != TARGET_HALTED) {
1221 LOG_ERROR("Target not halted");
1222 return ERROR_TARGET_NOT_HALTED;
1223 }
1224
1225 retval = stm32x_check_operation_supported(bank);
1226 if (retval != ERROR_OK)
1227 return retval;
1228
1229 if (stm32x_erase_options(bank) != ERROR_OK) {
1230 command_print(CMD, "stm32x failed to erase options");
1231 return ERROR_OK;
1232 }
1233
1234 /* set readout protection */
1235 stm32x_info->option_bytes.rdp = 0;
1236
1237 if (stm32x_write_options(bank) != ERROR_OK) {
1238 command_print(CMD, "stm32x failed to lock device");
1239 return ERROR_OK;
1240 }
1241
1242 command_print(CMD, "stm32x locked");
1243
1244 return ERROR_OK;
1245 }
1246
1247 COMMAND_HANDLER(stm32x_handle_unlock_command)
1248 {
1249 struct target *target = NULL;
1250
1251 if (CMD_ARGC < 1)
1252 return ERROR_COMMAND_SYNTAX_ERROR;
1253
1254 struct flash_bank *bank;
1255 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1256 if (retval != ERROR_OK)
1257 return retval;
1258
1259 target = bank->target;
1260
1261 if (target->state != TARGET_HALTED) {
1262 LOG_ERROR("Target not halted");
1263 return ERROR_TARGET_NOT_HALTED;
1264 }
1265
1266 retval = stm32x_check_operation_supported(bank);
1267 if (retval != ERROR_OK)
1268 return retval;
1269
1270 if (stm32x_erase_options(bank) != ERROR_OK) {
1271 command_print(CMD, "stm32x failed to erase options");
1272 return ERROR_OK;
1273 }
1274
1275 if (stm32x_write_options(bank) != ERROR_OK) {
1276 command_print(CMD, "stm32x failed to unlock device");
1277 return ERROR_OK;
1278 }
1279
1280 command_print(CMD, "stm32x unlocked.\n"
1281 "INFO: a reset or power cycle is required "
1282 "for the new settings to take effect.");
1283
1284 return ERROR_OK;
1285 }
1286
1287 COMMAND_HANDLER(stm32x_handle_options_read_command)
1288 {
1289 uint32_t optionbyte, protection;
1290 struct target *target = NULL;
1291 struct stm32x_flash_bank *stm32x_info = NULL;
1292
1293 if (CMD_ARGC < 1)
1294 return ERROR_COMMAND_SYNTAX_ERROR;
1295
1296 struct flash_bank *bank;
1297 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1298 if (retval != ERROR_OK)
1299 return retval;
1300
1301 stm32x_info = bank->driver_priv;
1302
1303 target = bank->target;
1304
1305 if (target->state != TARGET_HALTED) {
1306 LOG_ERROR("Target not halted");
1307 return ERROR_TARGET_NOT_HALTED;
1308 }
1309
1310 retval = stm32x_check_operation_supported(bank);
1311 if (retval != ERROR_OK)
1312 return retval;
1313
1314 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1315 if (retval != ERROR_OK)
1316 return retval;
1317
1318 uint16_t user_data = optionbyte >> stm32x_info->user_data_offset;
1319
1320 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
1321 if (retval != ERROR_OK)
1322 return retval;
1323
1324 if (optionbyte & (1 << OPT_ERROR))
1325 command_print(CMD, "option byte complement error");
1326
1327 command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
1328 command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
1329
1330 command_print(CMD, "read protection: %s",
1331 (optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
1332
1333 /* user option bytes are offset depending on variant */
1334 optionbyte >>= stm32x_info->option_offset;
1335
1336 command_print(CMD, "watchdog: %sware",
1337 (optionbyte & (1 << OPT_RDWDGSW)) ? "soft" : "hard");
1338
1339 command_print(CMD, "stop mode: %sreset generated upon entry",
1340 (optionbyte & (1 << OPT_RDRSTSTOP)) ? "no " : "");
1341
1342 command_print(CMD, "standby mode: %sreset generated upon entry",
1343 (optionbyte & (1 << OPT_RDRSTSTDBY)) ? "no " : "");
1344
1345 if (stm32x_info->has_dual_banks)
1346 command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
1347
1348 command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
1349
1350 return ERROR_OK;
1351 }
1352
1353 COMMAND_HANDLER(stm32x_handle_options_write_command)
1354 {
1355 struct target *target = NULL;
1356 struct stm32x_flash_bank *stm32x_info = NULL;
1357 uint8_t optionbyte;
1358 uint16_t useropt;
1359
1360 if (CMD_ARGC < 2)
1361 return ERROR_COMMAND_SYNTAX_ERROR;
1362
1363 struct flash_bank *bank;
1364 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1365 if (retval != ERROR_OK)
1366 return retval;
1367
1368 stm32x_info = bank->driver_priv;
1369
1370 target = bank->target;
1371
1372 if (target->state != TARGET_HALTED) {
1373 LOG_ERROR("Target not halted");
1374 return ERROR_TARGET_NOT_HALTED;
1375 }
1376
1377 retval = stm32x_check_operation_supported(bank);
1378 if (retval != ERROR_OK)
1379 return retval;
1380
1381 retval = stm32x_read_options(bank);
1382 if (retval != ERROR_OK)
1383 return retval;
1384
1385 /* start with current options */
1386 optionbyte = stm32x_info->option_bytes.user;
1387 useropt = stm32x_info->option_bytes.data;
1388
1389 /* skip over flash bank */
1390 CMD_ARGC--;
1391 CMD_ARGV++;
1392
1393 while (CMD_ARGC) {
1394 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1395 optionbyte |= (1 << 0);
1396 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1397 optionbyte &= ~(1 << 0);
1398 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1399 optionbyte |= (1 << 1);
1400 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1401 optionbyte &= ~(1 << 1);
1402 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1403 optionbyte |= (1 << 2);
1404 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1405 optionbyte &= ~(1 << 2);
1406 else if (strcmp("USEROPT", CMD_ARGV[0]) == 0) {
1407 if (CMD_ARGC < 2)
1408 return ERROR_COMMAND_SYNTAX_ERROR;
1409 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], useropt);
1410 CMD_ARGC--;
1411 CMD_ARGV++;
1412 } else if (stm32x_info->has_dual_banks) {
1413 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1414 optionbyte |= (1 << 3);
1415 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1416 optionbyte &= ~(1 << 3);
1417 else
1418 return ERROR_COMMAND_SYNTAX_ERROR;
1419 } else
1420 return ERROR_COMMAND_SYNTAX_ERROR;
1421 CMD_ARGC--;
1422 CMD_ARGV++;
1423 }
1424
1425 if (stm32x_erase_options(bank) != ERROR_OK) {
1426 command_print(CMD, "stm32x failed to erase options");
1427 return ERROR_OK;
1428 }
1429
1430 stm32x_info->option_bytes.user = optionbyte;
1431 stm32x_info->option_bytes.data = useropt;
1432
1433 if (stm32x_write_options(bank) != ERROR_OK) {
1434 command_print(CMD, "stm32x failed to write options");
1435 return ERROR_OK;
1436 }
1437
1438 command_print(CMD, "stm32x write options complete.\n"
1439 "INFO: %spower cycle is required "
1440 "for the new settings to take effect.",
1441 stm32x_info->can_load_options
1442 ? "'stm32f1x options_load' command or " : "");
1443
1444 return ERROR_OK;
1445 }
1446
1447 COMMAND_HANDLER(stm32x_handle_options_load_command)
1448 {
1449 if (CMD_ARGC < 1)
1450 return ERROR_COMMAND_SYNTAX_ERROR;
1451
1452 struct flash_bank *bank;
1453 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1454 if (retval != ERROR_OK)
1455 return retval;
1456
1457 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1458
1459 if (!stm32x_info->can_load_options) {
1460 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1461 "required instead.");
1462 return ERROR_FAIL;
1463 }
1464
1465 struct target *target = bank->target;
1466
1467 if (target->state != TARGET_HALTED) {
1468 LOG_ERROR("Target not halted");
1469 return ERROR_TARGET_NOT_HALTED;
1470 }
1471
1472 retval = stm32x_check_operation_supported(bank);
1473 if (retval != ERROR_OK)
1474 return retval;
1475
1476 /* unlock option flash registers */
1477 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1478 if (retval != ERROR_OK)
1479 return retval;
1480 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1481 if (retval != ERROR_OK)
1482 return retval;
1483
1484 /* force re-load of option bytes - generates software reset */
1485 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBL_LAUNCH);
1486 if (retval != ERROR_OK)
1487 return retval;
1488
1489 return ERROR_OK;
1490 }
1491
1492 static int stm32x_mass_erase(struct flash_bank *bank)
1493 {
1494 struct target *target = bank->target;
1495
1496 if (target->state != TARGET_HALTED) {
1497 LOG_ERROR("Target not halted");
1498 return ERROR_TARGET_NOT_HALTED;
1499 }
1500
1501 /* unlock option flash registers */
1502 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1503 if (retval != ERROR_OK)
1504 return retval;
1505 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1506 if (retval != ERROR_OK)
1507 return retval;
1508
1509 /* mass erase flash memory */
1510 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1511 if (retval != ERROR_OK)
1512 return retval;
1513 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1514 FLASH_MER | FLASH_STRT);
1515 if (retval != ERROR_OK)
1516 return retval;
1517
1518 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1519 if (retval != ERROR_OK)
1520 return retval;
1521
1522 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1523 if (retval != ERROR_OK)
1524 return retval;
1525
1526 return ERROR_OK;
1527 }
1528
1529 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1530 {
1531 if (CMD_ARGC < 1)
1532 return ERROR_COMMAND_SYNTAX_ERROR;
1533
1534 struct flash_bank *bank;
1535 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1536 if (retval != ERROR_OK)
1537 return retval;
1538
1539 retval = stm32x_mass_erase(bank);
1540 if (retval == ERROR_OK)
1541 command_print(CMD, "stm32x mass erase complete");
1542 else
1543 command_print(CMD, "stm32x mass erase failed");
1544
1545 return retval;
1546 }
1547
1548 static const struct command_registration stm32f1x_exec_command_handlers[] = {
1549 {
1550 .name = "lock",
1551 .handler = stm32x_handle_lock_command,
1552 .mode = COMMAND_EXEC,
1553 .usage = "bank_id",
1554 .help = "Lock entire flash device.",
1555 },
1556 {
1557 .name = "unlock",
1558 .handler = stm32x_handle_unlock_command,
1559 .mode = COMMAND_EXEC,
1560 .usage = "bank_id",
1561 .help = "Unlock entire protected flash device.",
1562 },
1563 {
1564 .name = "mass_erase",
1565 .handler = stm32x_handle_mass_erase_command,
1566 .mode = COMMAND_EXEC,
1567 .usage = "bank_id",
1568 .help = "Erase entire flash device.",
1569 },
1570 {
1571 .name = "options_read",
1572 .handler = stm32x_handle_options_read_command,
1573 .mode = COMMAND_EXEC,
1574 .usage = "bank_id",
1575 .help = "Read and display device option bytes.",
1576 },
1577 {
1578 .name = "options_write",
1579 .handler = stm32x_handle_options_write_command,
1580 .mode = COMMAND_EXEC,
1581 .usage = "bank_id ('SWWDG'|'HWWDG') "
1582 "('RSTSTNDBY'|'NORSTSTNDBY') "
1583 "('RSTSTOP'|'NORSTSTOP') ('USEROPT' user_data)",
1584 .help = "Replace bits in device option bytes.",
1585 },
1586 {
1587 .name = "options_load",
1588 .handler = stm32x_handle_options_load_command,
1589 .mode = COMMAND_EXEC,
1590 .usage = "bank_id",
1591 .help = "Force re-load of device option bytes.",
1592 },
1593 COMMAND_REGISTRATION_DONE
1594 };
1595
1596 static const struct command_registration stm32f1x_command_handlers[] = {
1597 {
1598 .name = "stm32f1x",
1599 .mode = COMMAND_ANY,
1600 .help = "stm32f1x flash command group",
1601 .usage = "",
1602 .chain = stm32f1x_exec_command_handlers,
1603 },
1604 COMMAND_REGISTRATION_DONE
1605 };
1606
1607 const struct flash_driver stm32f1x_flash = {
1608 .name = "stm32f1x",
1609 .commands = stm32f1x_command_handlers,
1610 .flash_bank_command = stm32x_flash_bank_command,
1611 .erase = stm32x_erase,
1612 .protect = stm32x_protect,
1613 .write = stm32x_write,
1614 .read = default_flash_read,
1615 .probe = stm32x_probe,
1616 .auto_probe = stm32x_auto_probe,
1617 .erase_check = default_flash_blank_check,
1618 .protect_check = stm32x_protect_check,
1619 .info = get_stm32x_info,
1620 .free_driver_priv = default_flash_free_driver_priv,
1621 };
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)