1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
25 ***************************************************************************/
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
36 /* stm32x register locations */
38 #define FLASH_REG_BASE_B0 0x40022000
39 #define FLASH_REG_BASE_B1 0x40022040
41 #define STM32_FLASH_ACR 0x00
42 #define STM32_FLASH_KEYR 0x04
43 #define STM32_FLASH_OPTKEYR 0x08
44 #define STM32_FLASH_SR 0x0C
45 #define STM32_FLASH_CR 0x10
46 #define STM32_FLASH_AR 0x14
47 #define STM32_FLASH_OBR 0x1C
48 #define STM32_FLASH_WRPR 0x20
50 /* TODO: Check if code using these really should be hard coded to bank 0.
51 * There are valid cases, on dual flash devices the protection of the
52 * second bank is done on the bank0 reg's. */
53 #define STM32_FLASH_ACR_B0 0x40022000
54 #define STM32_FLASH_KEYR_B0 0x40022004
55 #define STM32_FLASH_OPTKEYR_B0 0x40022008
56 #define STM32_FLASH_SR_B0 0x4002200C
57 #define STM32_FLASH_CR_B0 0x40022010
58 #define STM32_FLASH_AR_B0 0x40022014
59 #define STM32_FLASH_OBR_B0 0x4002201C
60 #define STM32_FLASH_WRPR_B0 0x40022020
62 /* option byte location */
64 #define STM32_OB_RDP 0x1FFFF800
65 #define STM32_OB_USER 0x1FFFF802
66 #define STM32_OB_DATA0 0x1FFFF804
67 #define STM32_OB_DATA1 0x1FFFF806
68 #define STM32_OB_WRP0 0x1FFFF808
69 #define STM32_OB_WRP1 0x1FFFF80A
70 #define STM32_OB_WRP2 0x1FFFF80C
71 #define STM32_OB_WRP3 0x1FFFF80E
73 /* FLASH_CR register bits */
75 #define FLASH_PG (1 << 0)
76 #define FLASH_PER (1 << 1)
77 #define FLASH_MER (1 << 2)
78 #define FLASH_OPTPG (1 << 4)
79 #define FLASH_OPTER (1 << 5)
80 #define FLASH_STRT (1 << 6)
81 #define FLASH_LOCK (1 << 7)
82 #define FLASH_OPTWRE (1 << 9)
84 /* FLASH_SR register bits */
86 #define FLASH_BSY (1 << 0)
87 #define FLASH_PGERR (1 << 2)
88 #define FLASH_WRPRTERR (1 << 4)
89 #define FLASH_EOP (1 << 5)
91 /* STM32_FLASH_OBR bit definitions (reading) */
96 #define OPT_RDRSTSTOP 3
97 #define OPT_RDRSTSTDBY 4
98 #define OPT_BFB2 5 /* dual flash bank only */
100 /* register unlock keys */
102 #define KEY1 0x45670123
103 #define KEY2 0xCDEF89AB
105 struct stm32x_options
{
107 uint16_t user_options
;
108 uint16_t protection
[4];
111 struct stm32x_flash_bank
{
112 struct stm32x_options option_bytes
;
117 /* used to access dual flash bank stm32xl */
118 uint32_t register_base
;
121 static int stm32x_mass_erase(struct flash_bank
*bank
);
122 static int stm32x_get_device_id(struct flash_bank
*bank
, uint32_t *device_id
);
124 /* flash bank stm32x <base> <size> 0 0 <target#>
126 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command
)
128 struct stm32x_flash_bank
*stm32x_info
;
131 return ERROR_COMMAND_SYNTAX_ERROR
;
133 stm32x_info
= malloc(sizeof(struct stm32x_flash_bank
));
135 bank
->driver_priv
= stm32x_info
;
136 stm32x_info
->probed
= 0;
137 stm32x_info
->has_dual_banks
= false;
138 stm32x_info
->register_base
= FLASH_REG_BASE_B0
;
143 static inline int stm32x_get_flash_reg(struct flash_bank
*bank
, uint32_t reg
)
145 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
146 return reg
+ stm32x_info
->register_base
;
149 static inline int stm32x_get_flash_status(struct flash_bank
*bank
, uint32_t *status
)
151 struct target
*target
= bank
->target
;
152 return target_read_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), status
);
155 static int stm32x_wait_status_busy(struct flash_bank
*bank
, int timeout
)
157 struct target
*target
= bank
->target
;
159 int retval
= ERROR_OK
;
161 /* wait for busy to clear */
163 retval
= stm32x_get_flash_status(bank
, &status
);
164 if (retval
!= ERROR_OK
)
166 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
167 if ((status
& FLASH_BSY
) == 0)
169 if (timeout
-- <= 0) {
170 LOG_ERROR("timed out waiting for flash");
176 if (status
& FLASH_WRPRTERR
) {
177 LOG_ERROR("stm32x device protected");
181 if (status
& FLASH_PGERR
) {
182 LOG_ERROR("stm32x device programming failed");
186 /* Clear but report errors */
187 if (status
& (FLASH_WRPRTERR
| FLASH_PGERR
)) {
188 /* If this operation fails, we ignore it and report the original
191 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
),
192 FLASH_WRPRTERR
| FLASH_PGERR
);
197 int stm32x_check_operation_supported(struct flash_bank
*bank
)
199 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
201 /* if we have a dual flash bank device then
202 * we need to perform option byte stuff on bank0 only */
203 if (stm32x_info
->register_base
!= FLASH_REG_BASE_B0
) {
204 LOG_ERROR("Option Byte Operation's must use bank0");
205 return ERROR_FLASH_OPERATION_FAILED
;
211 static int stm32x_read_options(struct flash_bank
*bank
)
214 struct stm32x_flash_bank
*stm32x_info
= NULL
;
215 struct target
*target
= bank
->target
;
217 stm32x_info
= bank
->driver_priv
;
219 /* read current option bytes */
220 int retval
= target_read_u32(target
, STM32_FLASH_OBR_B0
, &optiondata
);
221 if (retval
!= ERROR_OK
)
224 stm32x_info
->option_bytes
.user_options
= (uint16_t)0xFFF8 | ((optiondata
>> 2) & 0x07);
225 stm32x_info
->option_bytes
.RDP
= (optiondata
& (1 << OPT_READOUT
)) ? 0xFFFF : 0x5AA5;
227 if (optiondata
& (1 << OPT_READOUT
))
228 LOG_INFO("Device Security Bit Set");
230 /* each bit refers to a 4bank protection */
231 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &optiondata
);
232 if (retval
!= ERROR_OK
)
235 stm32x_info
->option_bytes
.protection
[0] = (uint16_t)optiondata
;
236 stm32x_info
->option_bytes
.protection
[1] = (uint16_t)(optiondata
>> 8);
237 stm32x_info
->option_bytes
.protection
[2] = (uint16_t)(optiondata
>> 16);
238 stm32x_info
->option_bytes
.protection
[3] = (uint16_t)(optiondata
>> 24);
243 static int stm32x_erase_options(struct flash_bank
*bank
)
245 struct stm32x_flash_bank
*stm32x_info
= NULL
;
246 struct target
*target
= bank
->target
;
248 stm32x_info
= bank
->driver_priv
;
250 /* stlink is currently does not support 16bit
251 * read/writes. so we cannot write option bytes */
252 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
253 if (armv7m
&& armv7m
->stlink
) {
254 LOG_ERROR("Option bytes currently unsupported for stlink");
258 /* read current options */
259 stm32x_read_options(bank
);
261 /* unlock flash registers */
262 int retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY1
);
263 if (retval
!= ERROR_OK
)
266 retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY2
);
267 if (retval
!= ERROR_OK
)
270 /* unlock option flash registers */
271 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY1
);
272 if (retval
!= ERROR_OK
)
274 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY2
);
275 if (retval
!= ERROR_OK
)
278 /* erase option bytes */
279 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTER
| FLASH_OPTWRE
);
280 if (retval
!= ERROR_OK
)
282 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTER
| FLASH_STRT
| FLASH_OPTWRE
);
283 if (retval
!= ERROR_OK
)
286 retval
= stm32x_wait_status_busy(bank
, 10);
287 if (retval
!= ERROR_OK
)
290 /* clear readout protection and complementary option bytes
291 * this will also force a device unlock if set */
292 stm32x_info
->option_bytes
.RDP
= 0x5AA5;
297 static int stm32x_write_options(struct flash_bank
*bank
)
299 struct stm32x_flash_bank
*stm32x_info
= NULL
;
300 struct target
*target
= bank
->target
;
302 stm32x_info
= bank
->driver_priv
;
304 /* unlock flash registers */
305 int retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY1
);
306 if (retval
!= ERROR_OK
)
308 retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY2
);
309 if (retval
!= ERROR_OK
)
312 /* unlock option flash registers */
313 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY1
);
314 if (retval
!= ERROR_OK
)
316 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY2
);
317 if (retval
!= ERROR_OK
)
320 /* program option bytes */
321 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTPG
| FLASH_OPTWRE
);
322 if (retval
!= ERROR_OK
)
325 /* write user option byte */
326 retval
= target_write_u16(target
, STM32_OB_USER
, stm32x_info
->option_bytes
.user_options
);
327 if (retval
!= ERROR_OK
)
330 retval
= stm32x_wait_status_busy(bank
, 10);
331 if (retval
!= ERROR_OK
)
334 /* write protection byte 1 */
335 retval
= target_write_u16(target
, STM32_OB_WRP0
, stm32x_info
->option_bytes
.protection
[0]);
336 if (retval
!= ERROR_OK
)
339 retval
= stm32x_wait_status_busy(bank
, 10);
340 if (retval
!= ERROR_OK
)
343 /* write protection byte 2 */
344 retval
= target_write_u16(target
, STM32_OB_WRP1
, stm32x_info
->option_bytes
.protection
[1]);
345 if (retval
!= ERROR_OK
)
348 retval
= stm32x_wait_status_busy(bank
, 10);
349 if (retval
!= ERROR_OK
)
352 /* write protection byte 3 */
353 retval
= target_write_u16(target
, STM32_OB_WRP2
, stm32x_info
->option_bytes
.protection
[2]);
354 if (retval
!= ERROR_OK
)
357 retval
= stm32x_wait_status_busy(bank
, 10);
358 if (retval
!= ERROR_OK
)
361 /* write protection byte 4 */
362 retval
= target_write_u16(target
, STM32_OB_WRP3
, stm32x_info
->option_bytes
.protection
[3]);
363 if (retval
!= ERROR_OK
)
366 retval
= stm32x_wait_status_busy(bank
, 10);
367 if (retval
!= ERROR_OK
)
370 /* write readout protection bit */
371 retval
= target_write_u16(target
, STM32_OB_RDP
, stm32x_info
->option_bytes
.RDP
);
372 if (retval
!= ERROR_OK
)
375 retval
= stm32x_wait_status_busy(bank
, 10);
376 if (retval
!= ERROR_OK
)
379 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_LOCK
);
380 if (retval
!= ERROR_OK
)
386 static int stm32x_protect_check(struct flash_bank
*bank
)
388 struct target
*target
= bank
->target
;
389 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
396 if (target
->state
!= TARGET_HALTED
) {
397 LOG_ERROR("Target not halted");
398 return ERROR_TARGET_NOT_HALTED
;
401 int retval
= stm32x_check_operation_supported(bank
);
402 if (ERROR_OK
!= retval
)
405 /* medium density - each bit refers to a 4bank protection
406 * high density - each bit refers to a 2bank protection */
407 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &protection
);
408 if (retval
!= ERROR_OK
)
411 /* medium density - each protection bit is for 4 * 1K pages
412 * high density - each protection bit is for 2 * 2K pages */
413 num_bits
= (bank
->num_sectors
/ stm32x_info
->ppage_size
);
415 if (stm32x_info
->ppage_size
== 2) {
416 /* high density flash/connectivity line protection */
420 if (protection
& (1 << 31))
423 /* bit 31 controls sector 62 - 255 protection for high density
424 * bit 31 controls sector 62 - 127 protection for connectivity line */
425 for (s
= 62; s
< bank
->num_sectors
; s
++)
426 bank
->sectors
[s
].is_protected
= set
;
428 if (bank
->num_sectors
> 61)
431 for (i
= 0; i
< num_bits
; i
++) {
434 if (protection
& (1 << i
))
437 for (s
= 0; s
< stm32x_info
->ppage_size
; s
++)
438 bank
->sectors
[(i
* stm32x_info
->ppage_size
) + s
].is_protected
= set
;
441 /* low/medium density flash protection */
442 for (i
= 0; i
< num_bits
; i
++) {
445 if (protection
& (1 << i
))
448 for (s
= 0; s
< stm32x_info
->ppage_size
; s
++)
449 bank
->sectors
[(i
* stm32x_info
->ppage_size
) + s
].is_protected
= set
;
456 static int stm32x_erase(struct flash_bank
*bank
, int first
, int last
)
458 struct target
*target
= bank
->target
;
461 if (bank
->target
->state
!= TARGET_HALTED
) {
462 LOG_ERROR("Target not halted");
463 return ERROR_TARGET_NOT_HALTED
;
466 if ((first
== 0) && (last
== (bank
->num_sectors
- 1)))
467 return stm32x_mass_erase(bank
);
469 /* unlock flash registers */
470 int retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
471 if (retval
!= ERROR_OK
)
473 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
474 if (retval
!= ERROR_OK
)
477 for (i
= first
; i
<= last
; i
++) {
478 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PER
);
479 if (retval
!= ERROR_OK
)
481 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_AR
),
482 bank
->base
+ bank
->sectors
[i
].offset
);
483 if (retval
!= ERROR_OK
)
485 retval
= target_write_u32(target
,
486 stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PER
| FLASH_STRT
);
487 if (retval
!= ERROR_OK
)
490 retval
= stm32x_wait_status_busy(bank
, 100);
491 if (retval
!= ERROR_OK
)
494 bank
->sectors
[i
].is_erased
= 1;
497 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
498 if (retval
!= ERROR_OK
)
504 static int stm32x_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
506 struct stm32x_flash_bank
*stm32x_info
= NULL
;
507 struct target
*target
= bank
->target
;
508 uint16_t prot_reg
[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
513 stm32x_info
= bank
->driver_priv
;
515 if (target
->state
!= TARGET_HALTED
) {
516 LOG_ERROR("Target not halted");
517 return ERROR_TARGET_NOT_HALTED
;
520 int retval
= stm32x_check_operation_supported(bank
);
521 if (ERROR_OK
!= retval
)
524 if ((first
% stm32x_info
->ppage_size
) != 0) {
525 LOG_WARNING("aligned start protect sector to a %d sector boundary",
526 stm32x_info
->ppage_size
);
527 first
= first
- (first
% stm32x_info
->ppage_size
);
529 if (((last
+ 1) % stm32x_info
->ppage_size
) != 0) {
530 LOG_WARNING("aligned end protect sector to a %d sector boundary",
531 stm32x_info
->ppage_size
);
533 last
= last
- (last
% stm32x_info
->ppage_size
);
537 /* medium density - each bit refers to a 4bank protection
538 * high density - each bit refers to a 2bank protection */
539 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &protection
);
540 if (retval
!= ERROR_OK
)
543 prot_reg
[0] = (uint16_t)protection
;
544 prot_reg
[1] = (uint16_t)(protection
>> 8);
545 prot_reg
[2] = (uint16_t)(protection
>> 16);
546 prot_reg
[3] = (uint16_t)(protection
>> 24);
548 if (stm32x_info
->ppage_size
== 2) {
549 /* high density flash */
551 /* bit 7 controls sector 62 - 255 protection */
554 prot_reg
[3] &= ~(1 << 7);
556 prot_reg
[3] |= (1 << 7);
564 for (i
= first
; i
<= last
; i
++) {
565 reg
= (i
/ stm32x_info
->ppage_size
) / 8;
566 bit
= (i
/ stm32x_info
->ppage_size
) - (reg
* 8);
569 prot_reg
[reg
] &= ~(1 << bit
);
571 prot_reg
[reg
] |= (1 << bit
);
574 /* medium density flash */
575 for (i
= first
; i
<= last
; i
++) {
576 reg
= (i
/ stm32x_info
->ppage_size
) / 8;
577 bit
= (i
/ stm32x_info
->ppage_size
) - (reg
* 8);
580 prot_reg
[reg
] &= ~(1 << bit
);
582 prot_reg
[reg
] |= (1 << bit
);
586 status
= stm32x_erase_options(bank
);
587 if (status
!= ERROR_OK
)
590 stm32x_info
->option_bytes
.protection
[0] = prot_reg
[0];
591 stm32x_info
->option_bytes
.protection
[1] = prot_reg
[1];
592 stm32x_info
->option_bytes
.protection
[2] = prot_reg
[2];
593 stm32x_info
->option_bytes
.protection
[3] = prot_reg
[3];
595 return stm32x_write_options(bank
);
598 static int stm32x_write_block(struct flash_bank
*bank
, uint8_t *buffer
,
599 uint32_t offset
, uint32_t count
)
601 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
602 struct target
*target
= bank
->target
;
603 uint32_t buffer_size
= 16384;
604 struct working_area
*write_algorithm
;
605 struct working_area
*source
;
606 uint32_t address
= bank
->base
+ offset
;
607 struct reg_param reg_params
[5];
608 struct armv7m_algorithm armv7m_info
;
609 int retval
= ERROR_OK
;
611 /* see contrib/loaders/flash/stm32f1x.S for src */
613 static const uint8_t stm32x_flash_write_code
[] = {
614 /* #define STM32_FLASH_SR_OFFSET 0x0C */
616 0x16, 0x68, /* ldr r6, [r2, #0] */
617 0x00, 0x2e, /* cmp r6, #0 */
618 0x18, 0xd0, /* beq exit */
619 0x55, 0x68, /* ldr r5, [r2, #4] */
620 0xb5, 0x42, /* cmp r5, r6 */
621 0xf9, 0xd0, /* beq wait_fifo */
622 0x2e, 0x88, /* ldrh r6, [r5, #0] */
623 0x26, 0x80, /* strh r6, [r4, #0] */
624 0x02, 0x35, /* adds r5, #2 */
625 0x02, 0x34, /* adds r4, #2 */
627 0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
628 0x01, 0x27, /* movs r7, #1 */
629 0x3e, 0x42, /* tst r6, r7 */
630 0xfb, 0xd1, /* bne busy */
631 0x14, 0x27, /* movs r7, #0x14 */
632 0x3e, 0x42, /* tst r6, r7 */
633 0x08, 0xd1, /* bne error */
634 0x9d, 0x42, /* cmp r5, r3 */
635 0x01, 0xd3, /* bcc no_wrap */
636 0x15, 0x46, /* mov r5, r2 */
637 0x08, 0x35, /* adds r5, #8 */
639 0x55, 0x60, /* str r5, [r2, #4] */
640 0x01, 0x39, /* subs r1, r1, #1 */
641 0x00, 0x29, /* cmp r1, #0 */
642 0x02, 0xd0, /* beq exit */
643 0xe5, 0xe7, /* b wait_fifo */
645 0x00, 0x20, /* movs r0, #0 */
646 0x50, 0x60, /* str r0, [r2, #4] */
648 0x30, 0x46, /* mov r0, r6 */
649 0x00, 0xbe, /* bkpt #0 */
652 /* flash write code */
653 if (target_alloc_working_area(target
, sizeof(stm32x_flash_write_code
),
654 &write_algorithm
) != ERROR_OK
) {
655 LOG_WARNING("no working area available, can't do block memory writes");
656 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
659 retval
= target_write_buffer(target
, write_algorithm
->address
,
660 sizeof(stm32x_flash_write_code
), (uint8_t *)stm32x_flash_write_code
);
661 if (retval
!= ERROR_OK
)
665 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
667 buffer_size
&= ~3UL; /* Make sure it's 4 byte aligned */
668 if (buffer_size
<= 256) {
669 /* we already allocated the writing code, but failed to get a
670 * buffer, free the algorithm */
671 target_free_working_area(target
, write_algorithm
);
673 LOG_WARNING("no large enough working area available, can't do block memory writes");
674 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
678 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* flash base (in), status (out) */
679 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* count (halfword-16bit) */
680 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* buffer start */
681 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* buffer end */
682 init_reg_param(®_params
[4], "r4", 32, PARAM_IN_OUT
); /* target address */
684 buf_set_u32(reg_params
[0].value
, 0, 32, stm32x_info
->register_base
);
685 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
686 buf_set_u32(reg_params
[2].value
, 0, 32, source
->address
);
687 buf_set_u32(reg_params
[3].value
, 0, 32, source
->address
+ source
->size
);
688 buf_set_u32(reg_params
[4].value
, 0, 32, address
);
690 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
691 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
693 retval
= target_run_flash_async_algorithm(target
, buffer
, count
, 2,
696 source
->address
, source
->size
,
697 write_algorithm
->address
, 0,
700 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
701 LOG_ERROR("flash write failed at address 0x%"PRIx32
,
702 buf_get_u32(reg_params
[4].value
, 0, 32));
704 if (buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_PGERR
) {
705 LOG_ERROR("flash memory not erased before writing");
706 /* Clear but report errors */
707 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), FLASH_PGERR
);
710 if (buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_WRPRTERR
) {
711 LOG_ERROR("flash memory write protected");
712 /* Clear but report errors */
713 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), FLASH_WRPRTERR
);
717 target_free_working_area(target
, source
);
718 target_free_working_area(target
, write_algorithm
);
720 destroy_reg_param(®_params
[0]);
721 destroy_reg_param(®_params
[1]);
722 destroy_reg_param(®_params
[2]);
723 destroy_reg_param(®_params
[3]);
724 destroy_reg_param(®_params
[4]);
729 static int stm32x_write(struct flash_bank
*bank
, uint8_t *buffer
,
730 uint32_t offset
, uint32_t count
)
732 struct target
*target
= bank
->target
;
733 uint8_t *new_buffer
= NULL
;
735 if (bank
->target
->state
!= TARGET_HALTED
) {
736 LOG_ERROR("Target not halted");
737 return ERROR_TARGET_NOT_HALTED
;
741 LOG_ERROR("offset 0x%" PRIx32
" breaks required 2-byte alignment", offset
);
742 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
745 /* If there's an odd number of bytes, the data has to be padded. Duplicate
746 * the buffer and use the normal code path with a single block write since
747 * it's probably cheaper than to special case the last odd write using
748 * discrete accesses. */
750 new_buffer
= malloc(count
+ 1);
751 if (new_buffer
== NULL
) {
752 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
755 LOG_INFO("odd number of bytes to write, padding with 0xff");
756 buffer
= memcpy(new_buffer
, buffer
, count
);
757 buffer
[count
++] = 0xff;
760 uint32_t words_remaining
= count
/ 2;
763 /* unlock flash registers */
764 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
765 if (retval
!= ERROR_OK
)
767 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
768 if (retval
!= ERROR_OK
)
771 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PG
);
772 if (retval
!= ERROR_OK
)
775 /* try using a block write */
776 retval
= stm32x_write_block(bank
, buffer
, offset
, words_remaining
);
778 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
779 /* if block write failed (no sufficient working area),
780 * we use normal (slow) single halfword accesses */
781 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
783 while (words_remaining
> 0) {
785 memcpy(&value
, buffer
, sizeof(uint16_t));
787 retval
= target_write_u16(target
, bank
->base
+ offset
, value
);
788 if (retval
!= ERROR_OK
)
789 goto reset_pg_and_lock
;
791 retval
= stm32x_wait_status_busy(bank
, 5);
792 if (retval
!= ERROR_OK
)
793 goto reset_pg_and_lock
;
802 retval2
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
803 if (retval
== ERROR_OK
)
813 static int stm32x_get_device_id(struct flash_bank
*bank
, uint32_t *device_id
)
815 /* This check the device CPUID core register to detect
816 * the M0 from the M3 devices. */
818 struct target
*target
= bank
->target
;
819 uint32_t cpuid
, device_id_register
= 0;
821 /* Get the CPUID from the ARM Core
822 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
823 int retval
= target_read_u32(target
, 0xE000ED00, &cpuid
);
824 if (retval
!= ERROR_OK
)
827 if (((cpuid
>> 4) & 0xFFF) == 0xC20) {
828 /* 0xC20 is M0 devices */
829 device_id_register
= 0x40015800;
830 } else if (((cpuid
>> 4) & 0xFFF) == 0xC23) {
831 /* 0xC23 is M3 devices */
832 device_id_register
= 0xE0042000;
833 } else if (((cpuid
>> 4) & 0xFFF) == 0xC24) {
834 /* 0xC24 is M4 devices */
835 device_id_register
= 0xE0042000;
837 LOG_ERROR("Cannot identify target as a stm32x");
841 /* read stm32 device id register */
842 retval
= target_read_u32(target
, device_id_register
, device_id
);
843 if (retval
!= ERROR_OK
)
849 static int stm32x_get_flash_size(struct flash_bank
*bank
, uint16_t *flash_size_in_kb
)
851 struct target
*target
= bank
->target
;
852 uint32_t cpuid
, flash_size_reg
;
854 int retval
= target_read_u32(target
, 0xE000ED00, &cpuid
);
855 if (retval
!= ERROR_OK
)
858 if (((cpuid
>> 4) & 0xFFF) == 0xC20) {
859 /* 0xC20 is M0 devices */
860 flash_size_reg
= 0x1FFFF7CC;
861 } else if (((cpuid
>> 4) & 0xFFF) == 0xC23) {
862 /* 0xC23 is M3 devices */
863 flash_size_reg
= 0x1FFFF7E0;
864 } else if (((cpuid
>> 4) & 0xFFF) == 0xC24) {
865 /* 0xC24 is M4 devices */
866 flash_size_reg
= 0x1FFFF7CC;
868 LOG_ERROR("Cannot identify target as a stm32x");
872 retval
= target_read_u16(target
, flash_size_reg
, flash_size_in_kb
);
873 if (retval
!= ERROR_OK
)
879 static int stm32x_probe(struct flash_bank
*bank
)
881 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
883 uint16_t flash_size_in_kb
;
884 uint16_t max_flash_size_in_kb
;
887 uint32_t base_address
= 0x08000000;
889 stm32x_info
->probed
= 0;
890 stm32x_info
->register_base
= FLASH_REG_BASE_B0
;
892 /* read stm32 device id register */
893 int retval
= stm32x_get_device_id(bank
, &device_id
);
894 if (retval
!= ERROR_OK
)
897 LOG_INFO("device id = 0x%08" PRIx32
"", device_id
);
899 /* set page size, protection granularity and max flash size depending on family */
900 switch (device_id
& 0xfff) {
901 case 0x410: /* medium density */
903 stm32x_info
->ppage_size
= 4;
904 max_flash_size_in_kb
= 128;
906 case 0x412: /* low density */
908 stm32x_info
->ppage_size
= 4;
909 max_flash_size_in_kb
= 32;
911 case 0x414: /* high density */
913 stm32x_info
->ppage_size
= 2;
914 max_flash_size_in_kb
= 512;
916 case 0x418: /* connectivity line density */
918 stm32x_info
->ppage_size
= 2;
919 max_flash_size_in_kb
= 256;
921 case 0x420: /* value line density */
923 stm32x_info
->ppage_size
= 4;
924 max_flash_size_in_kb
= 128;
926 case 0x422: /* stm32f30x */
928 stm32x_info
->ppage_size
= 2;
929 max_flash_size_in_kb
= 256;
931 case 0x428: /* value line High density */
933 stm32x_info
->ppage_size
= 4;
934 max_flash_size_in_kb
= 128;
936 case 0x430: /* xl line density (dual flash banks) */
938 stm32x_info
->ppage_size
= 2;
939 max_flash_size_in_kb
= 1024;
940 stm32x_info
->has_dual_banks
= true;
942 case 0x432: /* stm32f37x */
944 stm32x_info
->ppage_size
= 2;
945 max_flash_size_in_kb
= 256;
947 case 0x440: /* stm32f0x */
949 stm32x_info
->ppage_size
= 4;
950 max_flash_size_in_kb
= 64;
953 LOG_WARNING("Cannot identify target as a STM32 family.");
957 /* get flash size from target. */
958 retval
= stm32x_get_flash_size(bank
, &flash_size_in_kb
);
960 /* failed reading flash size or flash size invalid (early silicon),
961 * default to max target family */
962 if (retval
!= ERROR_OK
|| flash_size_in_kb
== 0xffff || flash_size_in_kb
== 0) {
963 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
964 max_flash_size_in_kb
);
965 flash_size_in_kb
= max_flash_size_in_kb
;
968 if (stm32x_info
->has_dual_banks
) {
969 /* split reported size into matching bank */
970 if (bank
->base
!= 0x08080000) {
971 /* bank 0 will be fixed 512k */
972 flash_size_in_kb
= 512;
974 flash_size_in_kb
-= 512;
975 /* bank1 also uses a register offset */
976 stm32x_info
->register_base
= FLASH_REG_BASE_B1
;
977 base_address
= 0x08080000;
981 LOG_INFO("flash size = %dkbytes", flash_size_in_kb
);
983 /* did we assign flash size? */
984 assert(flash_size_in_kb
!= 0xffff);
986 /* calculate numbers of pages */
987 int num_pages
= flash_size_in_kb
* 1024 / page_size
;
989 /* check that calculation result makes sense */
990 assert(num_pages
> 0);
994 bank
->sectors
= NULL
;
997 bank
->base
= base_address
;
998 bank
->size
= (num_pages
* page_size
);
999 bank
->num_sectors
= num_pages
;
1000 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_pages
);
1002 for (i
= 0; i
< num_pages
; i
++) {
1003 bank
->sectors
[i
].offset
= i
* page_size
;
1004 bank
->sectors
[i
].size
= page_size
;
1005 bank
->sectors
[i
].is_erased
= -1;
1006 bank
->sectors
[i
].is_protected
= 1;
1009 stm32x_info
->probed
= 1;
1014 static int stm32x_auto_probe(struct flash_bank
*bank
)
1016 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
1017 if (stm32x_info
->probed
)
1019 return stm32x_probe(bank
);
1023 COMMAND_HANDLER(stm32x_handle_part_id_command
)
1029 static int get_stm32x_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
1034 /* read stm32 device id register */
1035 int retval
= stm32x_get_device_id(bank
, &device_id
);
1036 if (retval
!= ERROR_OK
)
1039 if ((device_id
& 0xfff) == 0x410) {
1040 printed
= snprintf(buf
, buf_size
, "stm32x (Medium Density) - Rev: ");
1042 buf_size
-= printed
;
1044 switch (device_id
>> 16) {
1046 snprintf(buf
, buf_size
, "A");
1050 snprintf(buf
, buf_size
, "B");
1054 snprintf(buf
, buf_size
, "Z");
1058 snprintf(buf
, buf_size
, "Y");
1062 snprintf(buf
, buf_size
, "unknown");
1065 } else if ((device_id
& 0xfff) == 0x412) {
1066 printed
= snprintf(buf
, buf_size
, "stm32x (Low Density) - Rev: ");
1068 buf_size
-= printed
;
1070 switch (device_id
>> 16) {
1072 snprintf(buf
, buf_size
, "A");
1076 snprintf(buf
, buf_size
, "unknown");
1079 } else if ((device_id
& 0xfff) == 0x414) {
1080 printed
= snprintf(buf
, buf_size
, "stm32x (High Density) - Rev: ");
1082 buf_size
-= printed
;
1084 switch (device_id
>> 16) {
1086 snprintf(buf
, buf_size
, "A");
1090 snprintf(buf
, buf_size
, "Z");
1094 snprintf(buf
, buf_size
, "unknown");
1097 } else if ((device_id
& 0xfff) == 0x418) {
1098 printed
= snprintf(buf
, buf_size
, "stm32x (Connectivity) - Rev: ");
1100 buf_size
-= printed
;
1102 switch (device_id
>> 16) {
1104 snprintf(buf
, buf_size
, "A");
1108 snprintf(buf
, buf_size
, "Z");
1112 snprintf(buf
, buf_size
, "unknown");
1115 } else if ((device_id
& 0xfff) == 0x420) {
1116 printed
= snprintf(buf
, buf_size
, "stm32x (Value) - Rev: ");
1118 buf_size
-= printed
;
1120 switch (device_id
>> 16) {
1122 snprintf(buf
, buf_size
, "A");
1126 snprintf(buf
, buf_size
, "Z");
1130 snprintf(buf
, buf_size
, "unknown");
1133 } else if ((device_id
& 0xfff) == 0x422) {
1134 printed
= snprintf(buf
, buf_size
, "stm32f30x - Rev: ");
1136 buf_size
-= printed
;
1138 switch (device_id
>> 16) {
1140 snprintf(buf
, buf_size
, "1.0");
1144 snprintf(buf
, buf_size
, "2.0");
1148 snprintf(buf
, buf_size
, "unknown");
1151 } else if ((device_id
& 0xfff) == 0x428) {
1152 printed
= snprintf(buf
, buf_size
, "stm32x (Value HD) - Rev: ");
1154 buf_size
-= printed
;
1156 switch (device_id
>> 16) {
1158 snprintf(buf
, buf_size
, "A");
1162 snprintf(buf
, buf_size
, "Z");
1166 snprintf(buf
, buf_size
, "unknown");
1169 } else if ((device_id
& 0xfff) == 0x430) {
1170 printed
= snprintf(buf
, buf_size
, "stm32x (XL) - Rev: ");
1172 buf_size
-= printed
;
1174 switch (device_id
>> 16) {
1176 snprintf(buf
, buf_size
, "A");
1180 snprintf(buf
, buf_size
, "unknown");
1183 } else if ((device_id
& 0xfff) == 0x432) {
1184 printed
= snprintf(buf
, buf_size
, "stm32f37x - Rev: ");
1186 buf_size
-= printed
;
1188 switch (device_id
>> 16) {
1190 snprintf(buf
, buf_size
, "1.0");
1194 snprintf(buf
, buf_size
, "2.0");
1198 snprintf(buf
, buf_size
, "unknown");
1201 } else if ((device_id
& 0xfff) == 0x440) {
1202 printed
= snprintf(buf
, buf_size
, "stm32f0x - Rev: ");
1204 buf_size
-= printed
;
1206 switch (device_id
>> 16) {
1208 snprintf(buf
, buf_size
, "1.0");
1212 snprintf(buf
, buf_size
, "2.0");
1216 snprintf(buf
, buf_size
, "unknown");
1220 snprintf(buf
, buf_size
, "Cannot identify target as a stm32x\n");
1227 COMMAND_HANDLER(stm32x_handle_lock_command
)
1229 struct target
*target
= NULL
;
1230 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1233 return ERROR_COMMAND_SYNTAX_ERROR
;
1235 struct flash_bank
*bank
;
1236 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1237 if (ERROR_OK
!= retval
)
1240 stm32x_info
= bank
->driver_priv
;
1242 target
= bank
->target
;
1244 if (target
->state
!= TARGET_HALTED
) {
1245 LOG_ERROR("Target not halted");
1246 return ERROR_TARGET_NOT_HALTED
;
1249 retval
= stm32x_check_operation_supported(bank
);
1250 if (ERROR_OK
!= retval
)
1253 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1254 command_print(CMD_CTX
, "stm32x failed to erase options");
1258 /* set readout protection */
1259 stm32x_info
->option_bytes
.RDP
= 0;
1261 if (stm32x_write_options(bank
) != ERROR_OK
) {
1262 command_print(CMD_CTX
, "stm32x failed to lock device");
1266 command_print(CMD_CTX
, "stm32x locked");
1271 COMMAND_HANDLER(stm32x_handle_unlock_command
)
1273 struct target
*target
= NULL
;
1276 return ERROR_COMMAND_SYNTAX_ERROR
;
1278 struct flash_bank
*bank
;
1279 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1280 if (ERROR_OK
!= retval
)
1283 target
= bank
->target
;
1285 if (target
->state
!= TARGET_HALTED
) {
1286 LOG_ERROR("Target not halted");
1287 return ERROR_TARGET_NOT_HALTED
;
1290 retval
= stm32x_check_operation_supported(bank
);
1291 if (ERROR_OK
!= retval
)
1294 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1295 command_print(CMD_CTX
, "stm32x failed to unlock device");
1299 if (stm32x_write_options(bank
) != ERROR_OK
) {
1300 command_print(CMD_CTX
, "stm32x failed to lock device");
1304 command_print(CMD_CTX
, "stm32x unlocked.\n"
1305 "INFO: a reset or power cycle is required "
1306 "for the new settings to take effect.");
1311 COMMAND_HANDLER(stm32x_handle_options_read_command
)
1313 uint32_t optionbyte
;
1314 struct target
*target
= NULL
;
1315 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1318 return ERROR_COMMAND_SYNTAX_ERROR
;
1320 struct flash_bank
*bank
;
1321 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1322 if (ERROR_OK
!= retval
)
1325 stm32x_info
= bank
->driver_priv
;
1327 target
= bank
->target
;
1329 if (target
->state
!= TARGET_HALTED
) {
1330 LOG_ERROR("Target not halted");
1331 return ERROR_TARGET_NOT_HALTED
;
1334 retval
= stm32x_check_operation_supported(bank
);
1335 if (ERROR_OK
!= retval
)
1338 retval
= target_read_u32(target
, STM32_FLASH_OBR_B0
, &optionbyte
);
1339 if (retval
!= ERROR_OK
)
1341 command_print(CMD_CTX
, "Option Byte: 0x%" PRIx32
"", optionbyte
);
1343 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_ERROR
, 1))
1344 command_print(CMD_CTX
, "Option Byte Complement Error");
1346 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_READOUT
, 1))
1347 command_print(CMD_CTX
, "Readout Protection On");
1349 command_print(CMD_CTX
, "Readout Protection Off");
1351 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_RDWDGSW
, 1))
1352 command_print(CMD_CTX
, "Software Watchdog");
1354 command_print(CMD_CTX
, "Hardware Watchdog");
1356 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_RDRSTSTOP
, 1))
1357 command_print(CMD_CTX
, "Stop: No reset generated");
1359 command_print(CMD_CTX
, "Stop: Reset generated");
1361 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_RDRSTSTDBY
, 1))
1362 command_print(CMD_CTX
, "Standby: No reset generated");
1364 command_print(CMD_CTX
, "Standby: Reset generated");
1366 if (stm32x_info
->has_dual_banks
) {
1367 if (buf_get_u32((uint8_t *)&optionbyte
, OPT_BFB2
, 1))
1368 command_print(CMD_CTX
, "Boot: Bank 0");
1370 command_print(CMD_CTX
, "Boot: Bank 1");
1376 COMMAND_HANDLER(stm32x_handle_options_write_command
)
1378 struct target
*target
= NULL
;
1379 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1380 uint16_t optionbyte
= 0xF8;
1383 return ERROR_COMMAND_SYNTAX_ERROR
;
1385 struct flash_bank
*bank
;
1386 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1387 if (ERROR_OK
!= retval
)
1390 stm32x_info
= bank
->driver_priv
;
1392 target
= bank
->target
;
1394 if (target
->state
!= TARGET_HALTED
) {
1395 LOG_ERROR("Target not halted");
1396 return ERROR_TARGET_NOT_HALTED
;
1399 retval
= stm32x_check_operation_supported(bank
);
1400 if (ERROR_OK
!= retval
)
1403 /* REVISIT: ignores some options which we will display...
1404 * and doesn't insist on the specified syntax.
1408 if (strcmp(CMD_ARGV
[1], "SWWDG") == 0)
1409 optionbyte
|= (1 << 0);
1410 else /* REVISIT must be "HWWDG" then ... */
1411 optionbyte
&= ~(1 << 0);
1414 if (strcmp(CMD_ARGV
[2], "NORSTSTOP") == 0)
1415 optionbyte
|= (1 << 1);
1416 else /* REVISIT must be "RSTSTNDBY" then ... */
1417 optionbyte
&= ~(1 << 1);
1419 /* OPT_RDRSTSTDBY */
1420 if (strcmp(CMD_ARGV
[3], "NORSTSTNDBY") == 0)
1421 optionbyte
|= (1 << 2);
1422 else /* REVISIT must be "RSTSTOP" then ... */
1423 optionbyte
&= ~(1 << 2);
1425 if (CMD_ARGC
> 4 && stm32x_info
->has_dual_banks
) {
1427 if (strcmp(CMD_ARGV
[4], "BOOT0") == 0)
1428 optionbyte
|= (1 << 3);
1430 optionbyte
&= ~(1 << 3);
1433 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1434 command_print(CMD_CTX
, "stm32x failed to erase options");
1438 stm32x_info
->option_bytes
.user_options
= optionbyte
;
1440 if (stm32x_write_options(bank
) != ERROR_OK
) {
1441 command_print(CMD_CTX
, "stm32x failed to write options");
1445 command_print(CMD_CTX
, "stm32x write options complete.\n"
1446 "INFO: a reset or power cycle is required "
1447 "for the new settings to take effect.");
1452 static int stm32x_mass_erase(struct flash_bank
*bank
)
1454 struct target
*target
= bank
->target
;
1456 if (target
->state
!= TARGET_HALTED
) {
1457 LOG_ERROR("Target not halted");
1458 return ERROR_TARGET_NOT_HALTED
;
1461 /* unlock option flash registers */
1462 int retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
1463 if (retval
!= ERROR_OK
)
1465 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
1466 if (retval
!= ERROR_OK
)
1469 /* mass erase flash memory */
1470 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_MER
);
1471 if (retval
!= ERROR_OK
)
1473 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
),
1474 FLASH_MER
| FLASH_STRT
);
1475 if (retval
!= ERROR_OK
)
1478 retval
= stm32x_wait_status_busy(bank
, 100);
1479 if (retval
!= ERROR_OK
)
1482 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
1483 if (retval
!= ERROR_OK
)
1489 COMMAND_HANDLER(stm32x_handle_mass_erase_command
)
1494 return ERROR_COMMAND_SYNTAX_ERROR
;
1496 struct flash_bank
*bank
;
1497 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1498 if (ERROR_OK
!= retval
)
1501 retval
= stm32x_mass_erase(bank
);
1502 if (retval
== ERROR_OK
) {
1503 /* set all sectors as erased */
1504 for (i
= 0; i
< bank
->num_sectors
; i
++)
1505 bank
->sectors
[i
].is_erased
= 1;
1507 command_print(CMD_CTX
, "stm32x mass erase complete");
1509 command_print(CMD_CTX
, "stm32x mass erase failed");
1514 static const struct command_registration stm32x_exec_command_handlers
[] = {
1517 .handler
= stm32x_handle_lock_command
,
1518 .mode
= COMMAND_EXEC
,
1520 .help
= "Lock entire flash device.",
1524 .handler
= stm32x_handle_unlock_command
,
1525 .mode
= COMMAND_EXEC
,
1527 .help
= "Unlock entire protected flash device.",
1530 .name
= "mass_erase",
1531 .handler
= stm32x_handle_mass_erase_command
,
1532 .mode
= COMMAND_EXEC
,
1534 .help
= "Erase entire flash device.",
1537 .name
= "options_read",
1538 .handler
= stm32x_handle_options_read_command
,
1539 .mode
= COMMAND_EXEC
,
1541 .help
= "Read and display device option byte.",
1544 .name
= "options_write",
1545 .handler
= stm32x_handle_options_write_command
,
1546 .mode
= COMMAND_EXEC
,
1547 .usage
= "bank_id ('SWWDG'|'HWWDG') "
1548 "('RSTSTNDBY'|'NORSTSTNDBY') "
1549 "('RSTSTOP'|'NORSTSTOP')",
1550 .help
= "Replace bits in device option byte.",
1552 COMMAND_REGISTRATION_DONE
1555 static const struct command_registration stm32x_command_handlers
[] = {
1558 .mode
= COMMAND_ANY
,
1559 .help
= "stm32f1x flash command group",
1561 .chain
= stm32x_exec_command_handlers
,
1563 COMMAND_REGISTRATION_DONE
1566 struct flash_driver stm32f1x_flash
= {
1568 .commands
= stm32x_command_handlers
,
1569 .flash_bank_command
= stm32x_flash_bank_command
,
1570 .erase
= stm32x_erase
,
1571 .protect
= stm32x_protect
,
1572 .write
= stm32x_write
,
1573 .read
= default_flash_read
,
1574 .probe
= stm32x_probe
,
1575 .auto_probe
= stm32x_auto_probe
,
1576 .erase_check
= default_flash_blank_check
,
1577 .protect_check
= stm32x_protect_check
,
1578 .info
= get_stm32x_info
,
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