1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
34 /* stm32x register locations */
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
60 /* option byte location */
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
71 /* FLASH_CR register bits */
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
81 #define FLASH_OBL_LAUNCH (1 << 13) /* except stm32f1x series */
83 /* FLASH_SR register bits */
85 #define FLASH_BSY (1 << 0)
86 #define FLASH_PGERR (1 << 2)
87 #define FLASH_WRPRTERR (1 << 4)
88 #define FLASH_EOP (1 << 5)
90 /* STM32_FLASH_OBR bit definitions (reading) */
95 #define OPT_RDRSTSTOP 3
96 #define OPT_RDRSTSTDBY 4
97 #define OPT_BFB2 5 /* dual flash bank only */
99 /* register unlock keys */
101 #define KEY1 0x45670123
102 #define KEY2 0xCDEF89AB
106 #define FLASH_WRITE_TIMEOUT 10
107 #define FLASH_ERASE_TIMEOUT 100
109 struct stm32x_options
{
116 struct stm32x_flash_bank
{
117 struct stm32x_options option_bytes
;
122 /* used to access dual flash bank stm32xl */
123 bool can_load_options
;
124 uint32_t register_base
;
126 int user_data_offset
;
128 uint32_t user_bank_size
;
131 static int stm32x_mass_erase(struct flash_bank
*bank
);
132 static int stm32x_get_device_id(struct flash_bank
*bank
, uint32_t *device_id
);
133 static int stm32x_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
134 uint32_t offset
, uint32_t count
);
136 /* flash bank stm32x <base> <size> 0 0 <target#>
138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command
)
140 struct stm32x_flash_bank
*stm32x_info
;
143 return ERROR_COMMAND_SYNTAX_ERROR
;
145 stm32x_info
= malloc(sizeof(struct stm32x_flash_bank
));
147 bank
->driver_priv
= stm32x_info
;
148 stm32x_info
->probed
= 0;
149 stm32x_info
->has_dual_banks
= false;
150 stm32x_info
->can_load_options
= false;
151 stm32x_info
->register_base
= FLASH_REG_BASE_B0
;
152 stm32x_info
->user_bank_size
= bank
->size
;
157 static inline int stm32x_get_flash_reg(struct flash_bank
*bank
, uint32_t reg
)
159 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
160 return reg
+ stm32x_info
->register_base
;
163 static inline int stm32x_get_flash_status(struct flash_bank
*bank
, uint32_t *status
)
165 struct target
*target
= bank
->target
;
166 return target_read_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), status
);
169 static int stm32x_wait_status_busy(struct flash_bank
*bank
, int timeout
)
171 struct target
*target
= bank
->target
;
173 int retval
= ERROR_OK
;
175 /* wait for busy to clear */
177 retval
= stm32x_get_flash_status(bank
, &status
);
178 if (retval
!= ERROR_OK
)
180 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
181 if ((status
& FLASH_BSY
) == 0)
183 if (timeout
-- <= 0) {
184 LOG_ERROR("timed out waiting for flash");
190 if (status
& FLASH_WRPRTERR
) {
191 LOG_ERROR("stm32x device protected");
195 if (status
& FLASH_PGERR
) {
196 LOG_ERROR("stm32x device programming failed");
200 /* Clear but report errors */
201 if (status
& (FLASH_WRPRTERR
| FLASH_PGERR
)) {
202 /* If this operation fails, we ignore it and report the original
205 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
),
206 FLASH_WRPRTERR
| FLASH_PGERR
);
211 static int stm32x_check_operation_supported(struct flash_bank
*bank
)
213 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
215 /* if we have a dual flash bank device then
216 * we need to perform option byte stuff on bank0 only */
217 if (stm32x_info
->register_base
!= FLASH_REG_BASE_B0
) {
218 LOG_ERROR("Option Byte Operation's must use bank0");
219 return ERROR_FLASH_OPERATION_FAILED
;
225 static int stm32x_read_options(struct flash_bank
*bank
)
227 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
228 struct target
*target
= bank
->target
;
229 uint32_t option_bytes
;
232 /* read user and read protection option bytes */
233 retval
= target_read_u32(target
, STM32_OB_RDP
, &option_bytes
);
234 if (retval
!= ERROR_OK
)
237 stm32x_info
->option_bytes
.rdp
= option_bytes
& 0xFF;
238 stm32x_info
->option_bytes
.user
= (option_bytes
>> 16) & 0xFF;
240 /* read user data option bytes */
241 retval
= target_read_u32(target
, STM32_OB_DATA0
, &option_bytes
);
242 if (retval
!= ERROR_OK
)
245 stm32x_info
->option_bytes
.data
= ((option_bytes
>> 8) & 0xFF00) | (option_bytes
& 0xFF);
247 /* read write protection option bytes */
248 retval
= target_read_u32(target
, STM32_OB_WRP0
, &option_bytes
);
249 if (retval
!= ERROR_OK
)
252 stm32x_info
->option_bytes
.protection
= ((option_bytes
>> 8) & 0xFF00) | (option_bytes
& 0xFF);
254 retval
= target_read_u32(target
, STM32_OB_WRP2
, &option_bytes
);
255 if (retval
!= ERROR_OK
)
258 stm32x_info
->option_bytes
.protection
|= (((option_bytes
>> 8) & 0xFF00) | (option_bytes
& 0xFF)) << 16;
263 static int stm32x_erase_options(struct flash_bank
*bank
)
265 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
266 struct target
*target
= bank
->target
;
268 /* read current options */
269 stm32x_read_options(bank
);
271 /* unlock flash registers */
272 int retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY1
);
273 if (retval
!= ERROR_OK
)
276 retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY2
);
277 if (retval
!= ERROR_OK
)
280 /* unlock option flash registers */
281 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY1
);
282 if (retval
!= ERROR_OK
)
284 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY2
);
285 if (retval
!= ERROR_OK
)
288 /* erase option bytes */
289 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTER
| FLASH_OPTWRE
);
290 if (retval
!= ERROR_OK
)
292 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTER
| FLASH_STRT
| FLASH_OPTWRE
);
293 if (retval
!= ERROR_OK
)
296 retval
= stm32x_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
297 if (retval
!= ERROR_OK
)
300 /* clear read protection option byte
301 * this will also force a device unlock if set */
302 stm32x_info
->option_bytes
.rdp
= stm32x_info
->default_rdp
;
307 static int stm32x_write_options(struct flash_bank
*bank
)
309 struct stm32x_flash_bank
*stm32x_info
= NULL
;
310 struct target
*target
= bank
->target
;
312 stm32x_info
= bank
->driver_priv
;
314 /* unlock flash registers */
315 int retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY1
);
316 if (retval
!= ERROR_OK
)
318 retval
= target_write_u32(target
, STM32_FLASH_KEYR_B0
, KEY2
);
319 if (retval
!= ERROR_OK
)
322 /* unlock option flash registers */
323 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY1
);
324 if (retval
!= ERROR_OK
)
326 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR_B0
, KEY2
);
327 if (retval
!= ERROR_OK
)
330 /* program option bytes */
331 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_OPTPG
| FLASH_OPTWRE
);
332 if (retval
!= ERROR_OK
)
335 uint8_t opt_bytes
[16];
337 target_buffer_set_u16(target
, opt_bytes
, stm32x_info
->option_bytes
.rdp
);
338 target_buffer_set_u16(target
, opt_bytes
+ 2, stm32x_info
->option_bytes
.user
);
339 target_buffer_set_u16(target
, opt_bytes
+ 4, stm32x_info
->option_bytes
.data
& 0xff);
340 target_buffer_set_u16(target
, opt_bytes
+ 6, (stm32x_info
->option_bytes
.data
>> 8) & 0xff);
341 target_buffer_set_u16(target
, opt_bytes
+ 8, stm32x_info
->option_bytes
.protection
& 0xff);
342 target_buffer_set_u16(target
, opt_bytes
+ 10, (stm32x_info
->option_bytes
.protection
>> 8) & 0xff);
343 target_buffer_set_u16(target
, opt_bytes
+ 12, (stm32x_info
->option_bytes
.protection
>> 16) & 0xff);
344 target_buffer_set_u16(target
, opt_bytes
+ 14, (stm32x_info
->option_bytes
.protection
>> 24) & 0xff);
346 uint32_t offset
= STM32_OB_RDP
- bank
->base
;
347 retval
= stm32x_write_block(bank
, opt_bytes
, offset
, sizeof(opt_bytes
) / 2);
348 if (retval
!= ERROR_OK
) {
349 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
350 LOG_ERROR("working area required to erase options bytes");
354 retval
= target_write_u32(target
, STM32_FLASH_CR_B0
, FLASH_LOCK
);
355 if (retval
!= ERROR_OK
)
361 static int stm32x_protect_check(struct flash_bank
*bank
)
363 struct target
*target
= bank
->target
;
366 int retval
= stm32x_check_operation_supported(bank
);
367 if (ERROR_OK
!= retval
)
370 /* medium density - each bit refers to a 4 sector protection block
371 * high density - each bit refers to a 2 sector protection block
372 * bit 31 refers to all remaining sectors in a bank */
373 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &protection
);
374 if (retval
!= ERROR_OK
)
377 for (int i
= 0; i
< bank
->num_prot_blocks
; i
++)
378 bank
->prot_blocks
[i
].is_protected
= (protection
& (1 << i
)) ? 0 : 1;
383 static int stm32x_erase(struct flash_bank
*bank
, int first
, int last
)
385 struct target
*target
= bank
->target
;
388 if (bank
->target
->state
!= TARGET_HALTED
) {
389 LOG_ERROR("Target not halted");
390 return ERROR_TARGET_NOT_HALTED
;
393 if ((first
== 0) && (last
== (bank
->num_sectors
- 1)))
394 return stm32x_mass_erase(bank
);
396 /* unlock flash registers */
397 int retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
398 if (retval
!= ERROR_OK
)
400 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
401 if (retval
!= ERROR_OK
)
404 for (i
= first
; i
<= last
; i
++) {
405 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PER
);
406 if (retval
!= ERROR_OK
)
408 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_AR
),
409 bank
->base
+ bank
->sectors
[i
].offset
);
410 if (retval
!= ERROR_OK
)
412 retval
= target_write_u32(target
,
413 stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PER
| FLASH_STRT
);
414 if (retval
!= ERROR_OK
)
417 retval
= stm32x_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
418 if (retval
!= ERROR_OK
)
421 bank
->sectors
[i
].is_erased
= 1;
424 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
425 if (retval
!= ERROR_OK
)
431 static int stm32x_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
433 struct target
*target
= bank
->target
;
434 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
436 if (target
->state
!= TARGET_HALTED
) {
437 LOG_ERROR("Target not halted");
438 return ERROR_TARGET_NOT_HALTED
;
441 int retval
= stm32x_check_operation_supported(bank
);
442 if (retval
!= ERROR_OK
)
445 retval
= stm32x_erase_options(bank
);
446 if (retval
!= ERROR_OK
) {
447 LOG_ERROR("stm32x failed to erase options");
451 for (int i
= first
; i
<= last
; i
++) {
453 stm32x_info
->option_bytes
.protection
&= ~(1 << i
);
455 stm32x_info
->option_bytes
.protection
|= (1 << i
);
458 return stm32x_write_options(bank
);
461 static int stm32x_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
462 uint32_t offset
, uint32_t count
)
464 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
465 struct target
*target
= bank
->target
;
466 uint32_t buffer_size
= 16384;
467 struct working_area
*write_algorithm
;
468 struct working_area
*source
;
469 uint32_t address
= bank
->base
+ offset
;
470 struct reg_param reg_params
[5];
471 struct armv7m_algorithm armv7m_info
;
472 int retval
= ERROR_OK
;
474 static const uint8_t stm32x_flash_write_code
[] = {
475 #include "../../../contrib/loaders/flash/stm32/stm32f1x.inc"
478 /* flash write code */
479 if (target_alloc_working_area(target
, sizeof(stm32x_flash_write_code
),
480 &write_algorithm
) != ERROR_OK
) {
481 LOG_WARNING("no working area available, can't do block memory writes");
482 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
485 retval
= target_write_buffer(target
, write_algorithm
->address
,
486 sizeof(stm32x_flash_write_code
), stm32x_flash_write_code
);
487 if (retval
!= ERROR_OK
) {
488 target_free_working_area(target
, write_algorithm
);
493 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
495 buffer_size
&= ~3UL; /* Make sure it's 4 byte aligned */
496 if (buffer_size
<= 256) {
497 /* we already allocated the writing code, but failed to get a
498 * buffer, free the algorithm */
499 target_free_working_area(target
, write_algorithm
);
501 LOG_WARNING("no large enough working area available, can't do block memory writes");
502 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
506 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* flash base (in), status (out) */
507 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* count (halfword-16bit) */
508 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* buffer start */
509 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* buffer end */
510 init_reg_param(®_params
[4], "r4", 32, PARAM_IN_OUT
); /* target address */
512 buf_set_u32(reg_params
[0].value
, 0, 32, stm32x_info
->register_base
);
513 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
514 buf_set_u32(reg_params
[2].value
, 0, 32, source
->address
);
515 buf_set_u32(reg_params
[3].value
, 0, 32, source
->address
+ source
->size
);
516 buf_set_u32(reg_params
[4].value
, 0, 32, address
);
518 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
519 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
521 retval
= target_run_flash_async_algorithm(target
, buffer
, count
, 2,
524 source
->address
, source
->size
,
525 write_algorithm
->address
, 0,
528 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
529 LOG_ERROR("flash write failed at address 0x%"PRIx32
,
530 buf_get_u32(reg_params
[4].value
, 0, 32));
532 if (buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_PGERR
) {
533 LOG_ERROR("flash memory not erased before writing");
534 /* Clear but report errors */
535 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), FLASH_PGERR
);
538 if (buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_WRPRTERR
) {
539 LOG_ERROR("flash memory write protected");
540 /* Clear but report errors */
541 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), FLASH_WRPRTERR
);
545 target_free_working_area(target
, source
);
546 target_free_working_area(target
, write_algorithm
);
548 destroy_reg_param(®_params
[0]);
549 destroy_reg_param(®_params
[1]);
550 destroy_reg_param(®_params
[2]);
551 destroy_reg_param(®_params
[3]);
552 destroy_reg_param(®_params
[4]);
557 static int stm32x_write(struct flash_bank
*bank
, const uint8_t *buffer
,
558 uint32_t offset
, uint32_t count
)
560 struct target
*target
= bank
->target
;
561 uint8_t *new_buffer
= NULL
;
563 if (bank
->target
->state
!= TARGET_HALTED
) {
564 LOG_ERROR("Target not halted");
565 return ERROR_TARGET_NOT_HALTED
;
569 LOG_ERROR("offset 0x%" PRIx32
" breaks required 2-byte alignment", offset
);
570 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
573 /* If there's an odd number of bytes, the data has to be padded. Duplicate
574 * the buffer and use the normal code path with a single block write since
575 * it's probably cheaper than to special case the last odd write using
576 * discrete accesses. */
578 new_buffer
= malloc(count
+ 1);
579 if (new_buffer
== NULL
) {
580 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
583 LOG_INFO("odd number of bytes to write, padding with 0xff");
584 buffer
= memcpy(new_buffer
, buffer
, count
);
585 new_buffer
[count
++] = 0xff;
588 uint32_t words_remaining
= count
/ 2;
591 /* unlock flash registers */
592 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
593 if (retval
!= ERROR_OK
)
595 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
596 if (retval
!= ERROR_OK
)
599 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_PG
);
600 if (retval
!= ERROR_OK
)
603 /* try using a block write */
604 retval
= stm32x_write_block(bank
, buffer
, offset
, words_remaining
);
606 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
607 /* if block write failed (no sufficient working area),
608 * we use normal (slow) single halfword accesses */
609 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
611 while (words_remaining
> 0) {
613 memcpy(&value
, buffer
, sizeof(uint16_t));
615 retval
= target_write_u16(target
, bank
->base
+ offset
, value
);
616 if (retval
!= ERROR_OK
)
617 goto reset_pg_and_lock
;
619 retval
= stm32x_wait_status_busy(bank
, 5);
620 if (retval
!= ERROR_OK
)
621 goto reset_pg_and_lock
;
630 retval2
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
631 if (retval
== ERROR_OK
)
641 static int stm32x_get_device_id(struct flash_bank
*bank
, uint32_t *device_id
)
643 /* This check the device CPUID core register to detect
644 * the M0 from the M3 devices. */
646 struct target
*target
= bank
->target
;
647 uint32_t cpuid
, device_id_register
= 0;
649 /* Get the CPUID from the ARM Core
650 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
651 int retval
= target_read_u32(target
, 0xE000ED00, &cpuid
);
652 if (retval
!= ERROR_OK
)
655 if (((cpuid
>> 4) & 0xFFF) == 0xC20) {
656 /* 0xC20 is M0 devices */
657 device_id_register
= 0x40015800;
658 } else if (((cpuid
>> 4) & 0xFFF) == 0xC23) {
659 /* 0xC23 is M3 devices */
660 device_id_register
= 0xE0042000;
661 } else if (((cpuid
>> 4) & 0xFFF) == 0xC24) {
662 /* 0xC24 is M4 devices */
663 device_id_register
= 0xE0042000;
665 LOG_ERROR("Cannot identify target as a stm32x");
669 /* read stm32 device id register */
670 retval
= target_read_u32(target
, device_id_register
, device_id
);
671 if (retval
!= ERROR_OK
)
677 static int stm32x_get_flash_size(struct flash_bank
*bank
, uint16_t *flash_size_in_kb
)
679 struct target
*target
= bank
->target
;
680 uint32_t cpuid
, flash_size_reg
;
682 int retval
= target_read_u32(target
, 0xE000ED00, &cpuid
);
683 if (retval
!= ERROR_OK
)
686 if (((cpuid
>> 4) & 0xFFF) == 0xC20) {
687 /* 0xC20 is M0 devices */
688 flash_size_reg
= 0x1FFFF7CC;
689 } else if (((cpuid
>> 4) & 0xFFF) == 0xC23) {
690 /* 0xC23 is M3 devices */
691 flash_size_reg
= 0x1FFFF7E0;
692 } else if (((cpuid
>> 4) & 0xFFF) == 0xC24) {
693 /* 0xC24 is M4 devices */
694 flash_size_reg
= 0x1FFFF7CC;
696 LOG_ERROR("Cannot identify target as a stm32x");
700 retval
= target_read_u16(target
, flash_size_reg
, flash_size_in_kb
);
701 if (retval
!= ERROR_OK
)
707 static int stm32x_probe(struct flash_bank
*bank
)
709 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
710 uint16_t flash_size_in_kb
;
711 uint16_t max_flash_size_in_kb
;
714 uint32_t base_address
= 0x08000000;
716 stm32x_info
->probed
= 0;
717 stm32x_info
->register_base
= FLASH_REG_BASE_B0
;
718 stm32x_info
->user_data_offset
= 10;
719 stm32x_info
->option_offset
= 0;
721 /* default factory read protection level 0 */
722 stm32x_info
->default_rdp
= 0xA5;
724 /* read stm32 device id register */
725 int retval
= stm32x_get_device_id(bank
, &device_id
);
726 if (retval
!= ERROR_OK
)
729 LOG_INFO("device id = 0x%08" PRIx32
"", device_id
);
731 /* set page size, protection granularity and max flash size depending on family */
732 switch (device_id
& 0xfff) {
733 case 0x410: /* medium density */
735 stm32x_info
->ppage_size
= 4;
736 max_flash_size_in_kb
= 128;
738 case 0x412: /* low density */
740 stm32x_info
->ppage_size
= 4;
741 max_flash_size_in_kb
= 32;
743 case 0x414: /* high density */
745 stm32x_info
->ppage_size
= 2;
746 max_flash_size_in_kb
= 512;
748 case 0x418: /* connectivity line density */
750 stm32x_info
->ppage_size
= 2;
751 max_flash_size_in_kb
= 256;
753 case 0x420: /* value line density */
755 stm32x_info
->ppage_size
= 4;
756 max_flash_size_in_kb
= 128;
758 case 0x422: /* stm32f302/3xb/c */
760 stm32x_info
->ppage_size
= 2;
761 max_flash_size_in_kb
= 256;
762 stm32x_info
->user_data_offset
= 16;
763 stm32x_info
->option_offset
= 6;
764 stm32x_info
->default_rdp
= 0xAA;
765 stm32x_info
->can_load_options
= true;
767 case 0x446: /* stm32f303xD/E */
769 stm32x_info
->ppage_size
= 2;
770 max_flash_size_in_kb
= 512;
771 stm32x_info
->user_data_offset
= 16;
772 stm32x_info
->option_offset
= 6;
773 stm32x_info
->default_rdp
= 0xAA;
774 stm32x_info
->can_load_options
= true;
776 case 0x428: /* value line High density */
778 stm32x_info
->ppage_size
= 4;
779 max_flash_size_in_kb
= 128;
781 case 0x430: /* xl line density (dual flash banks) */
783 stm32x_info
->ppage_size
= 2;
784 max_flash_size_in_kb
= 1024;
785 stm32x_info
->has_dual_banks
= true;
787 case 0x432: /* stm32f37x */
789 stm32x_info
->ppage_size
= 2;
790 max_flash_size_in_kb
= 256;
791 stm32x_info
->user_data_offset
= 16;
792 stm32x_info
->option_offset
= 6;
793 stm32x_info
->default_rdp
= 0xAA;
794 stm32x_info
->can_load_options
= true;
796 case 0x438: /* stm32f33x */
797 case 0x439: /* stm32f302x6/8 */
799 stm32x_info
->ppage_size
= 2;
800 max_flash_size_in_kb
= 64;
801 stm32x_info
->user_data_offset
= 16;
802 stm32x_info
->option_offset
= 6;
803 stm32x_info
->default_rdp
= 0xAA;
804 stm32x_info
->can_load_options
= true;
806 case 0x440: /* stm32f05x */
807 case 0x444: /* stm32f03x */
808 case 0x445: /* stm32f04x */
810 stm32x_info
->ppage_size
= 4;
811 max_flash_size_in_kb
= 64;
812 stm32x_info
->user_data_offset
= 16;
813 stm32x_info
->option_offset
= 6;
814 stm32x_info
->default_rdp
= 0xAA;
815 stm32x_info
->can_load_options
= true;
817 case 0x448: /* stm32f07x */
818 case 0x442: /* stm32f09x */
820 stm32x_info
->ppage_size
= 4;
821 max_flash_size_in_kb
= 256;
822 stm32x_info
->user_data_offset
= 16;
823 stm32x_info
->option_offset
= 6;
824 stm32x_info
->default_rdp
= 0xAA;
825 stm32x_info
->can_load_options
= true;
828 LOG_WARNING("Cannot identify target as a STM32 family.");
832 /* get flash size from target. */
833 retval
= stm32x_get_flash_size(bank
, &flash_size_in_kb
);
835 /* failed reading flash size or flash size invalid (early silicon),
836 * default to max target family */
837 if (retval
!= ERROR_OK
|| flash_size_in_kb
== 0xffff || flash_size_in_kb
== 0) {
838 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
839 max_flash_size_in_kb
);
840 flash_size_in_kb
= max_flash_size_in_kb
;
843 if (stm32x_info
->has_dual_banks
) {
844 /* split reported size into matching bank */
845 if (bank
->base
!= 0x08080000) {
846 /* bank 0 will be fixed 512k */
847 flash_size_in_kb
= 512;
849 flash_size_in_kb
-= 512;
850 /* bank1 also uses a register offset */
851 stm32x_info
->register_base
= FLASH_REG_BASE_B1
;
852 base_address
= 0x08080000;
856 /* if the user sets the size manually then ignore the probed value
857 * this allows us to work around devices that have a invalid flash size register value */
858 if (stm32x_info
->user_bank_size
) {
859 LOG_INFO("ignoring flash probed value, using configured bank size");
860 flash_size_in_kb
= stm32x_info
->user_bank_size
/ 1024;
863 LOG_INFO("flash size = %dkbytes", flash_size_in_kb
);
865 /* did we assign flash size? */
866 assert(flash_size_in_kb
!= 0xffff);
868 /* calculate numbers of pages */
869 int num_pages
= flash_size_in_kb
* 1024 / page_size
;
871 /* check that calculation result makes sense */
872 assert(num_pages
> 0);
876 bank
->sectors
= NULL
;
879 if (bank
->prot_blocks
) {
880 free(bank
->prot_blocks
);
881 bank
->prot_blocks
= NULL
;
884 bank
->base
= base_address
;
885 bank
->size
= (num_pages
* page_size
);
887 bank
->num_sectors
= num_pages
;
888 bank
->sectors
= alloc_block_array(0, page_size
, num_pages
);
892 /* calculate number of write protection blocks */
893 int num_prot_blocks
= num_pages
/ stm32x_info
->ppage_size
;
894 if (num_prot_blocks
> 32)
895 num_prot_blocks
= 32;
897 bank
->num_prot_blocks
= num_prot_blocks
;
898 bank
->prot_blocks
= alloc_block_array(0, stm32x_info
->ppage_size
* page_size
, num_prot_blocks
);
899 if (!bank
->prot_blocks
)
902 if (num_prot_blocks
== 32)
903 bank
->prot_blocks
[31].size
= (num_pages
- (31 * stm32x_info
->ppage_size
)) * page_size
;
905 stm32x_info
->probed
= 1;
910 static int stm32x_auto_probe(struct flash_bank
*bank
)
912 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
913 if (stm32x_info
->probed
)
915 return stm32x_probe(bank
);
919 COMMAND_HANDLER(stm32x_handle_part_id_command
)
925 static const char *get_stm32f0_revision(uint16_t rev_id
)
927 const char *rev_str
= NULL
;
940 static int get_stm32x_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
942 uint32_t dbgmcu_idcode
;
944 /* read stm32 device id register */
945 int retval
= stm32x_get_device_id(bank
, &dbgmcu_idcode
);
946 if (retval
!= ERROR_OK
)
949 uint16_t device_id
= dbgmcu_idcode
& 0xfff;
950 uint16_t rev_id
= dbgmcu_idcode
>> 16;
951 const char *device_str
;
952 const char *rev_str
= NULL
;
956 device_str
= "STM32F10x (Medium Density)";
978 device_str
= "STM32F10x (Low Density)";
988 device_str
= "STM32F10x (High Density)";
1006 device_str
= "STM32F10x (Connectivity)";
1020 device_str
= "STM32F100 (Low/Medium Density)";
1034 device_str
= "STM32F302xB/C";
1056 device_str
= "STM32F100 (High Density)";
1070 device_str
= "STM32F10x (XL Density)";
1080 device_str
= "STM32F37x";
1094 device_str
= "STM32F33x";
1104 device_str
= "STM32F302x6/8";
1118 device_str
= "STM32F03x";
1119 rev_str
= get_stm32f0_revision(rev_id
);
1123 device_str
= "STM32F05x";
1124 rev_str
= get_stm32f0_revision(rev_id
);
1128 device_str
= "STM32F04x";
1129 rev_str
= get_stm32f0_revision(rev_id
);
1133 device_str
= "STM32F303xD/E";
1142 device_str
= "STM32F07x";
1143 rev_str
= get_stm32f0_revision(rev_id
);
1147 device_str
= "STM32F09x";
1148 rev_str
= get_stm32f0_revision(rev_id
);
1152 snprintf(buf
, buf_size
, "Cannot identify target as a STM32F0/1/3\n");
1156 if (rev_str
!= NULL
)
1157 snprintf(buf
, buf_size
, "%s - Rev: %s", device_str
, rev_str
);
1159 snprintf(buf
, buf_size
, "%s - Rev: unknown (0x%04x)", device_str
, rev_id
);
1164 COMMAND_HANDLER(stm32x_handle_lock_command
)
1166 struct target
*target
= NULL
;
1167 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1170 return ERROR_COMMAND_SYNTAX_ERROR
;
1172 struct flash_bank
*bank
;
1173 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1174 if (ERROR_OK
!= retval
)
1177 stm32x_info
= bank
->driver_priv
;
1179 target
= bank
->target
;
1181 if (target
->state
!= TARGET_HALTED
) {
1182 LOG_ERROR("Target not halted");
1183 return ERROR_TARGET_NOT_HALTED
;
1186 retval
= stm32x_check_operation_supported(bank
);
1187 if (ERROR_OK
!= retval
)
1190 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1191 command_print(CMD_CTX
, "stm32x failed to erase options");
1195 /* set readout protection */
1196 stm32x_info
->option_bytes
.rdp
= 0;
1198 if (stm32x_write_options(bank
) != ERROR_OK
) {
1199 command_print(CMD_CTX
, "stm32x failed to lock device");
1203 command_print(CMD_CTX
, "stm32x locked");
1208 COMMAND_HANDLER(stm32x_handle_unlock_command
)
1210 struct target
*target
= NULL
;
1213 return ERROR_COMMAND_SYNTAX_ERROR
;
1215 struct flash_bank
*bank
;
1216 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1217 if (ERROR_OK
!= retval
)
1220 target
= bank
->target
;
1222 if (target
->state
!= TARGET_HALTED
) {
1223 LOG_ERROR("Target not halted");
1224 return ERROR_TARGET_NOT_HALTED
;
1227 retval
= stm32x_check_operation_supported(bank
);
1228 if (ERROR_OK
!= retval
)
1231 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1232 command_print(CMD_CTX
, "stm32x failed to erase options");
1236 if (stm32x_write_options(bank
) != ERROR_OK
) {
1237 command_print(CMD_CTX
, "stm32x failed to unlock device");
1241 command_print(CMD_CTX
, "stm32x unlocked.\n"
1242 "INFO: a reset or power cycle is required "
1243 "for the new settings to take effect.");
1248 COMMAND_HANDLER(stm32x_handle_options_read_command
)
1250 uint32_t optionbyte
, protection
;
1251 struct target
*target
= NULL
;
1252 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1255 return ERROR_COMMAND_SYNTAX_ERROR
;
1257 struct flash_bank
*bank
;
1258 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1259 if (ERROR_OK
!= retval
)
1262 stm32x_info
= bank
->driver_priv
;
1264 target
= bank
->target
;
1266 if (target
->state
!= TARGET_HALTED
) {
1267 LOG_ERROR("Target not halted");
1268 return ERROR_TARGET_NOT_HALTED
;
1271 retval
= stm32x_check_operation_supported(bank
);
1272 if (ERROR_OK
!= retval
)
1275 retval
= target_read_u32(target
, STM32_FLASH_OBR_B0
, &optionbyte
);
1276 if (retval
!= ERROR_OK
)
1279 uint16_t user_data
= optionbyte
>> stm32x_info
->user_data_offset
;
1281 retval
= target_read_u32(target
, STM32_FLASH_WRPR_B0
, &protection
);
1282 if (retval
!= ERROR_OK
)
1285 if (optionbyte
& (1 << OPT_ERROR
))
1286 command_print(CMD_CTX
, "option byte complement error");
1288 command_print(CMD_CTX
, "option byte register = 0x%" PRIx32
"", optionbyte
);
1289 command_print(CMD_CTX
, "write protection register = 0x%" PRIx32
"", protection
);
1291 command_print(CMD_CTX
, "read protection: %s",
1292 (optionbyte
& (1 << OPT_READOUT
)) ? "on" : "off");
1294 /* user option bytes are offset depending on variant */
1295 optionbyte
>>= stm32x_info
->option_offset
;
1297 command_print(CMD_CTX
, "watchdog: %sware",
1298 (optionbyte
& (1 << OPT_RDWDGSW
)) ? "soft" : "hard");
1300 command_print(CMD_CTX
, "stop mode: %sreset generated upon entry",
1301 (optionbyte
& (1 << OPT_RDRSTSTOP
)) ? "no " : "");
1303 command_print(CMD_CTX
, "standby mode: %sreset generated upon entry",
1304 (optionbyte
& (1 << OPT_RDRSTSTDBY
)) ? "no " : "");
1306 if (stm32x_info
->has_dual_banks
)
1307 command_print(CMD_CTX
, "boot: bank %d", (optionbyte
& (1 << OPT_BFB2
)) ? 0 : 1);
1309 command_print(CMD_CTX
, "user data = 0x%02" PRIx16
"", user_data
);
1314 COMMAND_HANDLER(stm32x_handle_options_write_command
)
1316 struct target
*target
= NULL
;
1317 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1318 uint16_t optionbyte
;
1321 return ERROR_COMMAND_SYNTAX_ERROR
;
1323 struct flash_bank
*bank
;
1324 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1325 if (ERROR_OK
!= retval
)
1328 stm32x_info
= bank
->driver_priv
;
1330 target
= bank
->target
;
1332 if (target
->state
!= TARGET_HALTED
) {
1333 LOG_ERROR("Target not halted");
1334 return ERROR_TARGET_NOT_HALTED
;
1337 retval
= stm32x_check_operation_supported(bank
);
1338 if (ERROR_OK
!= retval
)
1341 retval
= stm32x_read_options(bank
);
1342 if (ERROR_OK
!= retval
)
1345 /* start with current options */
1346 optionbyte
= stm32x_info
->option_bytes
.user
;
1348 /* skip over flash bank */
1353 if (strcmp("SWWDG", CMD_ARGV
[0]) == 0)
1354 optionbyte
|= (1 << 0);
1355 else if (strcmp("HWWDG", CMD_ARGV
[0]) == 0)
1356 optionbyte
&= ~(1 << 0);
1357 else if (strcmp("NORSTSTOP", CMD_ARGV
[0]) == 0)
1358 optionbyte
|= (1 << 1);
1359 else if (strcmp("RSTSTOP", CMD_ARGV
[0]) == 0)
1360 optionbyte
&= ~(1 << 1);
1361 else if (strcmp("NORSTSTNDBY", CMD_ARGV
[0]) == 0)
1362 optionbyte
|= (1 << 2);
1363 else if (strcmp("RSTSTNDBY", CMD_ARGV
[0]) == 0)
1364 optionbyte
&= ~(1 << 2);
1365 else if (stm32x_info
->has_dual_banks
) {
1366 if (strcmp("BOOT0", CMD_ARGV
[0]) == 0)
1367 optionbyte
|= (1 << 3);
1368 else if (strcmp("BOOT1", CMD_ARGV
[0]) == 0)
1369 optionbyte
&= ~(1 << 3);
1371 return ERROR_COMMAND_SYNTAX_ERROR
;
1373 return ERROR_COMMAND_SYNTAX_ERROR
;
1378 if (stm32x_erase_options(bank
) != ERROR_OK
) {
1379 command_print(CMD_CTX
, "stm32x failed to erase options");
1383 stm32x_info
->option_bytes
.user
= optionbyte
;
1385 if (stm32x_write_options(bank
) != ERROR_OK
) {
1386 command_print(CMD_CTX
, "stm32x failed to write options");
1390 command_print(CMD_CTX
, "stm32x write options complete.\n"
1391 "INFO: %spower cycle is required "
1392 "for the new settings to take effect.",
1393 stm32x_info
->can_load_options
1394 ? "'stm32f1x options_load' command or " : "");
1399 COMMAND_HANDLER(stm32x_handle_options_load_command
)
1402 return ERROR_COMMAND_SYNTAX_ERROR
;
1404 struct flash_bank
*bank
;
1405 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1406 if (ERROR_OK
!= retval
)
1409 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
1411 if (!stm32x_info
->can_load_options
) {
1412 LOG_ERROR("Command not applicable to stm32f1x devices - power cycle is "
1413 "required instead.");
1417 struct target
*target
= bank
->target
;
1419 if (target
->state
!= TARGET_HALTED
) {
1420 LOG_ERROR("Target not halted");
1421 return ERROR_TARGET_NOT_HALTED
;
1424 retval
= stm32x_check_operation_supported(bank
);
1425 if (ERROR_OK
!= retval
)
1428 /* unlock option flash registers */
1429 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
1430 if (retval
!= ERROR_OK
)
1432 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
1433 if (retval
!= ERROR_OK
)
1436 /* force re-load of option bytes - generates software reset */
1437 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_OBL_LAUNCH
);
1438 if (retval
!= ERROR_OK
)
1444 static int stm32x_mass_erase(struct flash_bank
*bank
)
1446 struct target
*target
= bank
->target
;
1448 if (target
->state
!= TARGET_HALTED
) {
1449 LOG_ERROR("Target not halted");
1450 return ERROR_TARGET_NOT_HALTED
;
1453 /* unlock option flash registers */
1454 int retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY1
);
1455 if (retval
!= ERROR_OK
)
1457 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_KEYR
), KEY2
);
1458 if (retval
!= ERROR_OK
)
1461 /* mass erase flash memory */
1462 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_MER
);
1463 if (retval
!= ERROR_OK
)
1465 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
),
1466 FLASH_MER
| FLASH_STRT
);
1467 if (retval
!= ERROR_OK
)
1470 retval
= stm32x_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
1471 if (retval
!= ERROR_OK
)
1474 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
1475 if (retval
!= ERROR_OK
)
1481 COMMAND_HANDLER(stm32x_handle_mass_erase_command
)
1486 return ERROR_COMMAND_SYNTAX_ERROR
;
1488 struct flash_bank
*bank
;
1489 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1490 if (ERROR_OK
!= retval
)
1493 retval
= stm32x_mass_erase(bank
);
1494 if (retval
== ERROR_OK
) {
1495 /* set all sectors as erased */
1496 for (i
= 0; i
< bank
->num_sectors
; i
++)
1497 bank
->sectors
[i
].is_erased
= 1;
1499 command_print(CMD_CTX
, "stm32x mass erase complete");
1501 command_print(CMD_CTX
, "stm32x mass erase failed");
1506 static const struct command_registration stm32x_exec_command_handlers
[] = {
1509 .handler
= stm32x_handle_lock_command
,
1510 .mode
= COMMAND_EXEC
,
1512 .help
= "Lock entire flash device.",
1516 .handler
= stm32x_handle_unlock_command
,
1517 .mode
= COMMAND_EXEC
,
1519 .help
= "Unlock entire protected flash device.",
1522 .name
= "mass_erase",
1523 .handler
= stm32x_handle_mass_erase_command
,
1524 .mode
= COMMAND_EXEC
,
1526 .help
= "Erase entire flash device.",
1529 .name
= "options_read",
1530 .handler
= stm32x_handle_options_read_command
,
1531 .mode
= COMMAND_EXEC
,
1533 .help
= "Read and display device option bytes.",
1536 .name
= "options_write",
1537 .handler
= stm32x_handle_options_write_command
,
1538 .mode
= COMMAND_EXEC
,
1539 .usage
= "bank_id ('SWWDG'|'HWWDG') "
1540 "('RSTSTNDBY'|'NORSTSTNDBY') "
1541 "('RSTSTOP'|'NORSTSTOP')",
1542 .help
= "Replace bits in device option bytes.",
1545 .name
= "options_load",
1546 .handler
= stm32x_handle_options_load_command
,
1547 .mode
= COMMAND_EXEC
,
1549 .help
= "Force re-load of device option bytes.",
1551 COMMAND_REGISTRATION_DONE
1554 static const struct command_registration stm32x_command_handlers
[] = {
1557 .mode
= COMMAND_ANY
,
1558 .help
= "stm32f1x flash command group",
1560 .chain
= stm32x_exec_command_handlers
,
1562 COMMAND_REGISTRATION_DONE
1565 struct flash_driver stm32f1x_flash
= {
1567 .commands
= stm32x_command_handlers
,
1568 .flash_bank_command
= stm32x_flash_bank_command
,
1569 .erase
= stm32x_erase
,
1570 .protect
= stm32x_protect
,
1571 .write
= stm32x_write
,
1572 .read
= default_flash_read
,
1573 .probe
= stm32x_probe
,
1574 .auto_probe
= stm32x_auto_probe
,
1575 .erase_check
= default_flash_blank_check
,
1576 .protect_check
= stm32x_protect_check
,
1577 .info
= get_stm32x_info
,
1578 .free_driver_priv
= default_flash_free_driver_priv
,
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