Code Review / openocd.git / blob
? search:


a2bd2a2b08624cefb507d9965a990c40c9f78f6e
[openocd.git] / src / flash / nor / stm32f1x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
10 *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program; if not, write to the *
23 * Free Software Foundation, Inc., *
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
25 ***************************************************************************/
26
27 #ifdef HAVE_CONFIG_H
28 #include "config.h"
29 #endif
30
31 #include "imp.h"
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
34 #include <target/armv7m.h>
35
36 /* stm32x register locations */
37
38 #define FLASH_REG_BASE_B0 0x40022000
39 #define FLASH_REG_BASE_B1 0x40022040
40
41 #define STM32_FLASH_ACR 0x00
42 #define STM32_FLASH_KEYR 0x04
43 #define STM32_FLASH_OPTKEYR 0x08
44 #define STM32_FLASH_SR 0x0C
45 #define STM32_FLASH_CR 0x10
46 #define STM32_FLASH_AR 0x14
47 #define STM32_FLASH_OBR 0x1C
48 #define STM32_FLASH_WRPR 0x20
49
50 /* TODO: Check if code using these really should be hard coded to bank 0.
51 * There are valid cases, on dual flash devices the protection of the
52 * second bank is done on the bank0 reg's. */
53 #define STM32_FLASH_ACR_B0 0x40022000
54 #define STM32_FLASH_KEYR_B0 0x40022004
55 #define STM32_FLASH_OPTKEYR_B0 0x40022008
56 #define STM32_FLASH_SR_B0 0x4002200C
57 #define STM32_FLASH_CR_B0 0x40022010
58 #define STM32_FLASH_AR_B0 0x40022014
59 #define STM32_FLASH_OBR_B0 0x4002201C
60 #define STM32_FLASH_WRPR_B0 0x40022020
61
62 /* option byte location */
63
64 #define STM32_OB_RDP 0x1FFFF800
65 #define STM32_OB_USER 0x1FFFF802
66 #define STM32_OB_DATA0 0x1FFFF804
67 #define STM32_OB_DATA1 0x1FFFF806
68 #define STM32_OB_WRP0 0x1FFFF808
69 #define STM32_OB_WRP1 0x1FFFF80A
70 #define STM32_OB_WRP2 0x1FFFF80C
71 #define STM32_OB_WRP3 0x1FFFF80E
72
73 /* FLASH_CR register bits */
74
75 #define FLASH_PG (1 << 0)
76 #define FLASH_PER (1 << 1)
77 #define FLASH_MER (1 << 2)
78 #define FLASH_OPTPG (1 << 4)
79 #define FLASH_OPTER (1 << 5)
80 #define FLASH_STRT (1 << 6)
81 #define FLASH_LOCK (1 << 7)
82 #define FLASH_OPTWRE (1 << 9)
83
84 /* FLASH_SR register bits */
85
86 #define FLASH_BSY (1 << 0)
87 #define FLASH_PGERR (1 << 2)
88 #define FLASH_WRPRTERR (1 << 4)
89 #define FLASH_EOP (1 << 5)
90
91 /* STM32_FLASH_OBR bit definitions (reading) */
92
93 #define OPT_ERROR 0
94 #define OPT_READOUT 1
95 #define OPT_RDWDGSW 2
96 #define OPT_RDRSTSTOP 3
97 #define OPT_RDRSTSTDBY 4
98 #define OPT_BFB2 5 /* dual flash bank only */
99
100 /* register unlock keys */
101
102 #define KEY1 0x45670123
103 #define KEY2 0xCDEF89AB
104
105 /* timeout values */
106
107 #define FLASH_WRITE_TIMEOUT 10
108 #define FLASH_ERASE_TIMEOUT 100
109
110 struct stm32x_options {
111 uint16_t RDP;
112 uint16_t user_options;
113 uint16_t user_data;
114 uint16_t protection[4];
115 };
116
117 struct stm32x_flash_bank {
118 struct stm32x_options option_bytes;
119 int ppage_size;
120 int probed;
121
122 bool has_dual_banks;
123 /* used to access dual flash bank stm32xl */
124 uint32_t register_base;
125 uint16_t default_rdp;
126 int user_data_offset;
127 int option_offset;
128 uint32_t user_bank_size;
129 };
130
131 static int stm32x_mass_erase(struct flash_bank *bank);
132 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
133 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
134 uint32_t offset, uint32_t count);
135
136 /* flash bank stm32x <base> <size> 0 0 <target#>
137 */
138 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
139 {
140 struct stm32x_flash_bank *stm32x_info;
141
142 if (CMD_ARGC < 6)
143 return ERROR_COMMAND_SYNTAX_ERROR;
144
145 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
146
147 bank->driver_priv = stm32x_info;
148 stm32x_info->probed = 0;
149 stm32x_info->has_dual_banks = false;
150 stm32x_info->register_base = FLASH_REG_BASE_B0;
151 stm32x_info->user_bank_size = bank->size;
152
153 return ERROR_OK;
154 }
155
156 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
157 {
158 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
159 return reg + stm32x_info->register_base;
160 }
161
162 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
163 {
164 struct target *target = bank->target;
165 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
166 }
167
168 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
169 {
170 struct target *target = bank->target;
171 uint32_t status;
172 int retval = ERROR_OK;
173
174 /* wait for busy to clear */
175 for (;;) {
176 retval = stm32x_get_flash_status(bank, &status);
177 if (retval != ERROR_OK)
178 return retval;
179 LOG_DEBUG("status: 0x%" PRIx32 "", status);
180 if ((status & FLASH_BSY) == 0)
181 break;
182 if (timeout-- <= 0) {
183 LOG_ERROR("timed out waiting for flash");
184 return ERROR_FAIL;
185 }
186 alive_sleep(1);
187 }
188
189 if (status & FLASH_WRPRTERR) {
190 LOG_ERROR("stm32x device protected");
191 retval = ERROR_FAIL;
192 }
193
194 if (status & FLASH_PGERR) {
195 LOG_ERROR("stm32x device programming failed");
196 retval = ERROR_FAIL;
197 }
198
199 /* Clear but report errors */
200 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
201 /* If this operation fails, we ignore it and report the original
202 * retval
203 */
204 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
205 FLASH_WRPRTERR | FLASH_PGERR);
206 }
207 return retval;
208 }
209
210 static int stm32x_check_operation_supported(struct flash_bank *bank)
211 {
212 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
213
214 /* if we have a dual flash bank device then
215 * we need to perform option byte stuff on bank0 only */
216 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
217 LOG_ERROR("Option Byte Operation's must use bank0");
218 return ERROR_FLASH_OPERATION_FAILED;
219 }
220
221 return ERROR_OK;
222 }
223
224 static int stm32x_read_options(struct flash_bank *bank)
225 {
226 uint32_t optiondata;
227 struct stm32x_flash_bank *stm32x_info = NULL;
228 struct target *target = bank->target;
229
230 stm32x_info = bank->driver_priv;
231
232 /* read current option bytes */
233 int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
234 if (retval != ERROR_OK)
235 return retval;
236
237 stm32x_info->option_bytes.user_options = (optiondata >> stm32x_info->option_offset >> 2) & 0xffff;
238 stm32x_info->option_bytes.user_data = (optiondata >> stm32x_info->user_data_offset) & 0xffff;
239 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
240
241 if (optiondata & (1 << OPT_READOUT))
242 LOG_INFO("Device Security Bit Set");
243
244 /* each bit refers to a 4bank protection */
245 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
246 if (retval != ERROR_OK)
247 return retval;
248
249 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
250 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
251 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
252 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
253
254 return ERROR_OK;
255 }
256
257 static int stm32x_erase_options(struct flash_bank *bank)
258 {
259 struct stm32x_flash_bank *stm32x_info = NULL;
260 struct target *target = bank->target;
261
262 stm32x_info = bank->driver_priv;
263
264 /* read current options */
265 stm32x_read_options(bank);
266
267 /* unlock flash registers */
268 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
269 if (retval != ERROR_OK)
270 return retval;
271
272 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
273 if (retval != ERROR_OK)
274 return retval;
275
276 /* unlock option flash registers */
277 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
278 if (retval != ERROR_OK)
279 return retval;
280 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
281 if (retval != ERROR_OK)
282 return retval;
283
284 /* erase option bytes */
285 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
286 if (retval != ERROR_OK)
287 return retval;
288 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
289 if (retval != ERROR_OK)
290 return retval;
291
292 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
293 if (retval != ERROR_OK)
294 return retval;
295
296 /* clear readout protection and complementary option bytes
297 * this will also force a device unlock if set */
298 stm32x_info->option_bytes.RDP = stm32x_info->default_rdp;
299
300 return ERROR_OK;
301 }
302
303 static int stm32x_write_options(struct flash_bank *bank)
304 {
305 struct stm32x_flash_bank *stm32x_info = NULL;
306 struct target *target = bank->target;
307
308 stm32x_info = bank->driver_priv;
309
310 /* unlock flash registers */
311 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
312 if (retval != ERROR_OK)
313 return retval;
314 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
315 if (retval != ERROR_OK)
316 return retval;
317
318 /* unlock option flash registers */
319 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
320 if (retval != ERROR_OK)
321 return retval;
322 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
323 if (retval != ERROR_OK)
324 return retval;
325
326 /* program option bytes */
327 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
328 if (retval != ERROR_OK)
329 return retval;
330
331 uint8_t opt_bytes[16];
332
333 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.RDP);
334 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user_options);
335 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.user_data & 0xff);
336 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.user_data >> 8) & 0xff);
337 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection[0]);
338 target_buffer_set_u16(target, opt_bytes + 10, stm32x_info->option_bytes.protection[1]);
339 target_buffer_set_u16(target, opt_bytes + 12, stm32x_info->option_bytes.protection[2]);
340 target_buffer_set_u16(target, opt_bytes + 14, stm32x_info->option_bytes.protection[3]);
341
342 uint32_t offset = STM32_OB_RDP - bank->base;
343 retval = stm32x_write_block(bank, opt_bytes, offset, sizeof(opt_bytes) / 2);
344 if (retval != ERROR_OK) {
345 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
346 LOG_ERROR("working area required to erase options bytes");
347 return retval;
348 }
349
350 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
351 if (retval != ERROR_OK)
352 return retval;
353
354 return ERROR_OK;
355 }
356
357 static int stm32x_protect_check(struct flash_bank *bank)
358 {
359 struct target *target = bank->target;
360 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
361
362 uint32_t protection;
363 int i, s;
364 int num_bits;
365 int set;
366
367 int retval = stm32x_check_operation_supported(bank);
368 if (ERROR_OK != retval)
369 return retval;
370
371 /* medium density - each bit refers to a 4bank protection
372 * high density - each bit refers to a 2bank protection */
373 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
374 if (retval != ERROR_OK)
375 return retval;
376
377 /* medium density - each protection bit is for 4 * 1K pages
378 * high density - each protection bit is for 2 * 2K pages */
379 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
380
381 if (stm32x_info->ppage_size == 2) {
382 /* high density flash/connectivity line protection */
383
384 set = 1;
385
386 if (protection & (1 << 31))
387 set = 0;
388
389 /* bit 31 controls sector 62 - 255 protection for high density
390 * bit 31 controls sector 62 - 127 protection for connectivity line */
391 for (s = 62; s < bank->num_sectors; s++)
392 bank->sectors[s].is_protected = set;
393
394 if (bank->num_sectors > 61)
395 num_bits = 31;
396
397 for (i = 0; i < num_bits; i++) {
398 set = 1;
399
400 if (protection & (1 << i))
401 set = 0;
402
403 for (s = 0; s < stm32x_info->ppage_size; s++)
404 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
405 }
406 } else {
407 /* low/medium density flash protection */
408 for (i = 0; i < num_bits; i++) {
409 set = 1;
410
411 if (protection & (1 << i))
412 set = 0;
413
414 for (s = 0; s < stm32x_info->ppage_size; s++)
415 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
416 }
417 }
418
419 return ERROR_OK;
420 }
421
422 static int stm32x_erase(struct flash_bank *bank, int first, int last)
423 {
424 struct target *target = bank->target;
425 int i;
426
427 if (bank->target->state != TARGET_HALTED) {
428 LOG_ERROR("Target not halted");
429 return ERROR_TARGET_NOT_HALTED;
430 }
431
432 if ((first == 0) && (last == (bank->num_sectors - 1)))
433 return stm32x_mass_erase(bank);
434
435 /* unlock flash registers */
436 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
437 if (retval != ERROR_OK)
438 return retval;
439 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
440 if (retval != ERROR_OK)
441 return retval;
442
443 for (i = first; i <= last; i++) {
444 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
445 if (retval != ERROR_OK)
446 return retval;
447 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
448 bank->base + bank->sectors[i].offset);
449 if (retval != ERROR_OK)
450 return retval;
451 retval = target_write_u32(target,
452 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
453 if (retval != ERROR_OK)
454 return retval;
455
456 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
457 if (retval != ERROR_OK)
458 return retval;
459
460 bank->sectors[i].is_erased = 1;
461 }
462
463 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
464 if (retval != ERROR_OK)
465 return retval;
466
467 return ERROR_OK;
468 }
469
470 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
471 {
472 struct stm32x_flash_bank *stm32x_info = NULL;
473 struct target *target = bank->target;
474 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
475 int i, reg, bit;
476 int status;
477 uint32_t protection;
478
479 stm32x_info = bank->driver_priv;
480
481 if (target->state != TARGET_HALTED) {
482 LOG_ERROR("Target not halted");
483 return ERROR_TARGET_NOT_HALTED;
484 }
485
486 int retval = stm32x_check_operation_supported(bank);
487 if (ERROR_OK != retval)
488 return retval;
489
490 if ((first % stm32x_info->ppage_size) != 0) {
491 LOG_WARNING("aligned start protect sector to a %d sector boundary",
492 stm32x_info->ppage_size);
493 first = first - (first % stm32x_info->ppage_size);
494 }
495 if (((last + 1) % stm32x_info->ppage_size) != 0) {
496 LOG_WARNING("aligned end protect sector to a %d sector boundary",
497 stm32x_info->ppage_size);
498 last++;
499 last = last - (last % stm32x_info->ppage_size);
500 last--;
501 }
502
503 /* medium density - each bit refers to a 4bank protection
504 * high density - each bit refers to a 2bank protection */
505 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
506 if (retval != ERROR_OK)
507 return retval;
508
509 prot_reg[0] = (uint16_t)protection;
510 prot_reg[1] = (uint16_t)(protection >> 8);
511 prot_reg[2] = (uint16_t)(protection >> 16);
512 prot_reg[3] = (uint16_t)(protection >> 24);
513
514 if (stm32x_info->ppage_size == 2) {
515 /* high density flash */
516
517 /* bit 7 controls sector 62 - 255 protection */
518 if (last > 61) {
519 if (set)
520 prot_reg[3] &= ~(1 << 7);
521 else
522 prot_reg[3] |= (1 << 7);
523 }
524
525 if (first > 61)
526 first = 62;
527 if (last > 61)
528 last = 61;
529
530 for (i = first; i <= last; i++) {
531 reg = (i / stm32x_info->ppage_size) / 8;
532 bit = (i / stm32x_info->ppage_size) - (reg * 8);
533
534 if (set)
535 prot_reg[reg] &= ~(1 << bit);
536 else
537 prot_reg[reg] |= (1 << bit);
538 }
539 } else {
540 /* medium density flash */
541 for (i = first; i <= last; i++) {
542 reg = (i / stm32x_info->ppage_size) / 8;
543 bit = (i / stm32x_info->ppage_size) - (reg * 8);
544
545 if (set)
546 prot_reg[reg] &= ~(1 << bit);
547 else
548 prot_reg[reg] |= (1 << bit);
549 }
550 }
551
552 status = stm32x_erase_options(bank);
553 if (status != ERROR_OK)
554 return status;
555
556 stm32x_info->option_bytes.protection[0] = prot_reg[0];
557 stm32x_info->option_bytes.protection[1] = prot_reg[1];
558 stm32x_info->option_bytes.protection[2] = prot_reg[2];
559 stm32x_info->option_bytes.protection[3] = prot_reg[3];
560
561 return stm32x_write_options(bank);
562 }
563
564 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
565 uint32_t offset, uint32_t count)
566 {
567 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
568 struct target *target = bank->target;
569 uint32_t buffer_size = 16384;
570 struct working_area *write_algorithm;
571 struct working_area *source;
572 uint32_t address = bank->base + offset;
573 struct reg_param reg_params[5];
574 struct armv7m_algorithm armv7m_info;
575 int retval = ERROR_OK;
576
577 /* see contrib/loaders/flash/stm32f1x.S for src */
578
579 static const uint8_t stm32x_flash_write_code[] = {
580 /* #define STM32_FLASH_SR_OFFSET 0x0C */
581 /* wait_fifo: */
582 0x16, 0x68, /* ldr r6, [r2, #0] */
583 0x00, 0x2e, /* cmp r6, #0 */
584 0x18, 0xd0, /* beq exit */
585 0x55, 0x68, /* ldr r5, [r2, #4] */
586 0xb5, 0x42, /* cmp r5, r6 */
587 0xf9, 0xd0, /* beq wait_fifo */
588 0x2e, 0x88, /* ldrh r6, [r5, #0] */
589 0x26, 0x80, /* strh r6, [r4, #0] */
590 0x02, 0x35, /* adds r5, #2 */
591 0x02, 0x34, /* adds r4, #2 */
592 /* busy: */
593 0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
594 0x01, 0x27, /* movs r7, #1 */
595 0x3e, 0x42, /* tst r6, r7 */
596 0xfb, 0xd1, /* bne busy */
597 0x14, 0x27, /* movs r7, #0x14 */
598 0x3e, 0x42, /* tst r6, r7 */
599 0x08, 0xd1, /* bne error */
600 0x9d, 0x42, /* cmp r5, r3 */
601 0x01, 0xd3, /* bcc no_wrap */
602 0x15, 0x46, /* mov r5, r2 */
603 0x08, 0x35, /* adds r5, #8 */
604 /* no_wrap: */
605 0x55, 0x60, /* str r5, [r2, #4] */
606 0x01, 0x39, /* subs r1, r1, #1 */
607 0x00, 0x29, /* cmp r1, #0 */
608 0x02, 0xd0, /* beq exit */
609 0xe5, 0xe7, /* b wait_fifo */
610 /* error: */
611 0x00, 0x20, /* movs r0, #0 */
612 0x50, 0x60, /* str r0, [r2, #4] */
613 /* exit: */
614 0x30, 0x46, /* mov r0, r6 */
615 0x00, 0xbe, /* bkpt #0 */
616 };
617
618 /* flash write code */
619 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
620 &write_algorithm) != ERROR_OK) {
621 LOG_WARNING("no working area available, can't do block memory writes");
622 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
623 };
624
625 retval = target_write_buffer(target, write_algorithm->address,
626 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
627 if (retval != ERROR_OK)
628 return retval;
629
630 /* memory buffer */
631 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
632 buffer_size /= 2;
633 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
634 if (buffer_size <= 256) {
635 /* we already allocated the writing code, but failed to get a
636 * buffer, free the algorithm */
637 target_free_working_area(target, write_algorithm);
638
639 LOG_WARNING("no large enough working area available, can't do block memory writes");
640 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
641 }
642 };
643
644 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
645 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
646 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* buffer start */
647 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* buffer end */
648 init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
649
650 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
651 buf_set_u32(reg_params[1].value, 0, 32, count);
652 buf_set_u32(reg_params[2].value, 0, 32, source->address);
653 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
654 buf_set_u32(reg_params[4].value, 0, 32, address);
655
656 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
657 armv7m_info.core_mode = ARM_MODE_THREAD;
658
659 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
660 0, NULL,
661 5, reg_params,
662 source->address, source->size,
663 write_algorithm->address, 0,
664 &armv7m_info);
665
666 if (retval == ERROR_FLASH_OPERATION_FAILED) {
667 LOG_ERROR("flash write failed at address 0x%"PRIx32,
668 buf_get_u32(reg_params[4].value, 0, 32));
669
670 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
671 LOG_ERROR("flash memory not erased before writing");
672 /* Clear but report errors */
673 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
674 }
675
676 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
677 LOG_ERROR("flash memory write protected");
678 /* Clear but report errors */
679 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
680 }
681 }
682
683 target_free_working_area(target, source);
684 target_free_working_area(target, write_algorithm);
685
686 destroy_reg_param(&reg_params[0]);
687 destroy_reg_param(&reg_params[1]);
688 destroy_reg_param(&reg_params[2]);
689 destroy_reg_param(&reg_params[3]);
690 destroy_reg_param(&reg_params[4]);
691
692 return retval;
693 }
694
695 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
696 uint32_t offset, uint32_t count)
697 {
698 struct target *target = bank->target;
699 uint8_t *new_buffer = NULL;
700
701 if (bank->target->state != TARGET_HALTED) {
702 LOG_ERROR("Target not halted");
703 return ERROR_TARGET_NOT_HALTED;
704 }
705
706 if (offset & 0x1) {
707 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
708 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
709 }
710
711 /* If there's an odd number of bytes, the data has to be padded. Duplicate
712 * the buffer and use the normal code path with a single block write since
713 * it's probably cheaper than to special case the last odd write using
714 * discrete accesses. */
715 if (count & 1) {
716 new_buffer = malloc(count + 1);
717 if (new_buffer == NULL) {
718 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
719 return ERROR_FAIL;
720 }
721 LOG_INFO("odd number of bytes to write, padding with 0xff");
722 buffer = memcpy(new_buffer, buffer, count);
723 new_buffer[count++] = 0xff;
724 }
725
726 uint32_t words_remaining = count / 2;
727 int retval, retval2;
728
729 /* unlock flash registers */
730 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
731 if (retval != ERROR_OK)
732 goto cleanup;
733 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
734 if (retval != ERROR_OK)
735 goto cleanup;
736
737 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
738 if (retval != ERROR_OK)
739 goto cleanup;
740
741 /* try using a block write */
742 retval = stm32x_write_block(bank, buffer, offset, words_remaining);
743
744 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
745 /* if block write failed (no sufficient working area),
746 * we use normal (slow) single halfword accesses */
747 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
748
749 while (words_remaining > 0) {
750 uint16_t value;
751 memcpy(&value, buffer, sizeof(uint16_t));
752
753 retval = target_write_u16(target, bank->base + offset, value);
754 if (retval != ERROR_OK)
755 goto reset_pg_and_lock;
756
757 retval = stm32x_wait_status_busy(bank, 5);
758 if (retval != ERROR_OK)
759 goto reset_pg_and_lock;
760
761 words_remaining--;
762 buffer += 2;
763 offset += 2;
764 }
765 }
766
767 reset_pg_and_lock:
768 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
769 if (retval == ERROR_OK)
770 retval = retval2;
771
772 cleanup:
773 if (new_buffer)
774 free(new_buffer);
775
776 return retval;
777 }
778
779 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
780 {
781 /* This check the device CPUID core register to detect
782 * the M0 from the M3 devices. */
783
784 struct target *target = bank->target;
785 uint32_t cpuid, device_id_register = 0;
786
787 /* Get the CPUID from the ARM Core
788 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
789 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
790 if (retval != ERROR_OK)
791 return retval;
792
793 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
794 /* 0xC20 is M0 devices */
795 device_id_register = 0x40015800;
796 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
797 /* 0xC23 is M3 devices */
798 device_id_register = 0xE0042000;
799 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
800 /* 0xC24 is M4 devices */
801 device_id_register = 0xE0042000;
802 } else {
803 LOG_ERROR("Cannot identify target as a stm32x");
804 return ERROR_FAIL;
805 }
806
807 /* read stm32 device id register */
808 retval = target_read_u32(target, device_id_register, device_id);
809 if (retval != ERROR_OK)
810 return retval;
811
812 return retval;
813 }
814
815 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
816 {
817 struct target *target = bank->target;
818 uint32_t cpuid, flash_size_reg;
819
820 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
821 if (retval != ERROR_OK)
822 return retval;
823
824 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
825 /* 0xC20 is M0 devices */
826 flash_size_reg = 0x1FFFF7CC;
827 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
828 /* 0xC23 is M3 devices */
829 flash_size_reg = 0x1FFFF7E0;
830 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
831 /* 0xC24 is M4 devices */
832 flash_size_reg = 0x1FFFF7CC;
833 } else {
834 LOG_ERROR("Cannot identify target as a stm32x");
835 return ERROR_FAIL;
836 }
837
838 retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
839 if (retval != ERROR_OK)
840 return retval;
841
842 return retval;
843 }
844
845 static int stm32x_probe(struct flash_bank *bank)
846 {
847 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
848 int i;
849 uint16_t flash_size_in_kb;
850 uint16_t max_flash_size_in_kb;
851 uint32_t device_id;
852 int page_size;
853 uint32_t base_address = 0x08000000;
854
855 stm32x_info->probed = 0;
856 stm32x_info->register_base = FLASH_REG_BASE_B0;
857 stm32x_info->user_data_offset = 10;
858 stm32x_info->option_offset = 0;
859
860 /* default factory protection level */
861 stm32x_info->default_rdp = 0x5AA5;
862
863 /* read stm32 device id register */
864 int retval = stm32x_get_device_id(bank, &device_id);
865 if (retval != ERROR_OK)
866 return retval;
867
868 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
869
870 /* set page size, protection granularity and max flash size depending on family */
871 switch (device_id & 0xfff) {
872 case 0x410: /* medium density */
873 page_size = 1024;
874 stm32x_info->ppage_size = 4;
875 max_flash_size_in_kb = 128;
876 break;
877 case 0x412: /* low density */
878 page_size = 1024;
879 stm32x_info->ppage_size = 4;
880 max_flash_size_in_kb = 32;
881 break;
882 case 0x414: /* high density */
883 page_size = 2048;
884 stm32x_info->ppage_size = 2;
885 max_flash_size_in_kb = 512;
886 break;
887 case 0x418: /* connectivity line density */
888 page_size = 2048;
889 stm32x_info->ppage_size = 2;
890 max_flash_size_in_kb = 256;
891 break;
892 case 0x420: /* value line density */
893 page_size = 1024;
894 stm32x_info->ppage_size = 4;
895 max_flash_size_in_kb = 128;
896 break;
897 case 0x422: /* stm32f302xb/c */
898 page_size = 2048;
899 stm32x_info->ppage_size = 2;
900 max_flash_size_in_kb = 256;
901 stm32x_info->user_data_offset = 16;
902 stm32x_info->option_offset = 6;
903 stm32x_info->default_rdp = 0x55AA;
904 break;
905 case 0x428: /* value line High density */
906 page_size = 2048;
907 stm32x_info->ppage_size = 4;
908 max_flash_size_in_kb = 128;
909 break;
910 case 0x430: /* xl line density (dual flash banks) */
911 page_size = 2048;
912 stm32x_info->ppage_size = 2;
913 max_flash_size_in_kb = 1024;
914 stm32x_info->has_dual_banks = true;
915 break;
916 case 0x432: /* stm32f37x */
917 page_size = 2048;
918 stm32x_info->ppage_size = 2;
919 max_flash_size_in_kb = 256;
920 stm32x_info->user_data_offset = 16;
921 stm32x_info->option_offset = 6;
922 stm32x_info->default_rdp = 0x55AA;
923 break;
924 case 0x438: /* stm32f33x */
925 case 0x439: /* stm32f302x6/8 */
926 page_size = 2048;
927 stm32x_info->ppage_size = 2;
928 max_flash_size_in_kb = 64;
929 stm32x_info->user_data_offset = 16;
930 stm32x_info->option_offset = 6;
931 stm32x_info->default_rdp = 0x55AA;
932 break;
933 case 0x440: /* stm32f05x */
934 case 0x444: /* stm32f03x */
935 case 0x445: /* stm32f04x */
936 page_size = 1024;
937 stm32x_info->ppage_size = 4;
938 max_flash_size_in_kb = 64;
939 stm32x_info->user_data_offset = 16;
940 stm32x_info->option_offset = 6;
941 stm32x_info->default_rdp = 0x55AA;
942 break;
943 case 0x448: /* stm32f07x */
944 page_size = 2048;
945 stm32x_info->ppage_size = 4;
946 max_flash_size_in_kb = 128;
947 stm32x_info->user_data_offset = 16;
948 stm32x_info->option_offset = 6;
949 stm32x_info->default_rdp = 0x55AA;
950 break;
951 case 0x442: /* stm32f09x */
952 page_size = 2048;
953 stm32x_info->ppage_size = 4;
954 max_flash_size_in_kb = 256;
955 stm32x_info->user_data_offset = 16;
956 stm32x_info->option_offset = 6;
957 stm32x_info->default_rdp = 0x55AA;
958 break;
959 default:
960 LOG_WARNING("Cannot identify target as a STM32 family.");
961 return ERROR_FAIL;
962 }
963
964 /* get flash size from target. */
965 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
966
967 /* failed reading flash size or flash size invalid (early silicon),
968 * default to max target family */
969 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
970 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
971 max_flash_size_in_kb);
972 flash_size_in_kb = max_flash_size_in_kb;
973 }
974
975 if (stm32x_info->has_dual_banks) {
976 /* split reported size into matching bank */
977 if (bank->base != 0x08080000) {
978 /* bank 0 will be fixed 512k */
979 flash_size_in_kb = 512;
980 } else {
981 flash_size_in_kb -= 512;
982 /* bank1 also uses a register offset */
983 stm32x_info->register_base = FLASH_REG_BASE_B1;
984 base_address = 0x08080000;
985 }
986 }
987
988 /* if the user sets the size manually then ignore the probed value
989 * this allows us to work around devices that have a invalid flash size register value */
990 if (stm32x_info->user_bank_size) {
991 LOG_INFO("ignoring flash probed value, using configured bank size");
992 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
993 }
994
995 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
996
997 /* did we assign flash size? */
998 assert(flash_size_in_kb != 0xffff);
999
1000 /* calculate numbers of pages */
1001 int num_pages = flash_size_in_kb * 1024 / page_size;
1002
1003 /* check that calculation result makes sense */
1004 assert(num_pages > 0);
1005
1006 if (bank->sectors) {
1007 free(bank->sectors);
1008 bank->sectors = NULL;
1009 }
1010
1011 bank->base = base_address;
1012 bank->size = (num_pages * page_size);
1013 bank->num_sectors = num_pages;
1014 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
1015
1016 for (i = 0; i < num_pages; i++) {
1017 bank->sectors[i].offset = i * page_size;
1018 bank->sectors[i].size = page_size;
1019 bank->sectors[i].is_erased = -1;
1020 bank->sectors[i].is_protected = 1;
1021 }
1022
1023 stm32x_info->probed = 1;
1024
1025 return ERROR_OK;
1026 }
1027
1028 static int stm32x_auto_probe(struct flash_bank *bank)
1029 {
1030 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1031 if (stm32x_info->probed)
1032 return ERROR_OK;
1033 return stm32x_probe(bank);
1034 }
1035
1036 #if 0
1037 COMMAND_HANDLER(stm32x_handle_part_id_command)
1038 {
1039 return ERROR_OK;
1040 }
1041 #endif
1042
1043 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1044 {
1045 uint32_t dbgmcu_idcode;
1046
1047 /* read stm32 device id register */
1048 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
1049 if (retval != ERROR_OK)
1050 return retval;
1051
1052 uint16_t device_id = dbgmcu_idcode & 0xfff;
1053 uint16_t rev_id = dbgmcu_idcode >> 16;
1054 const char *device_str;
1055 const char *rev_str = NULL;
1056
1057 switch (device_id) {
1058 case 0x410:
1059 device_str = "STM32F10x (Medium Density)";
1060
1061 switch (rev_id) {
1062 case 0x0000:
1063 rev_str = "A";
1064 break;
1065
1066 case 0x2000:
1067 rev_str = "B";
1068 break;
1069
1070 case 0x2001:
1071 rev_str = "Z";
1072 break;
1073
1074 case 0x2003:
1075 rev_str = "Y";
1076 break;
1077 }
1078 break;
1079
1080 case 0x412:
1081 device_str = "STM32F10x (Low Density)";
1082
1083 switch (rev_id) {
1084 case 0x1000:
1085 rev_str = "A";
1086 break;
1087 }
1088 break;
1089
1090 case 0x414:
1091 device_str = "STM32F10x (High Density)";
1092
1093 switch (rev_id) {
1094 case 0x1000:
1095 rev_str = "A";
1096 break;
1097
1098 case 0x1001:
1099 rev_str = "Z";
1100 break;
1101
1102 case 0x1003:
1103 rev_str = "Y";
1104 break;
1105 }
1106 break;
1107
1108 case 0x418:
1109 device_str = "STM32F10x (Connectivity)";
1110
1111 switch (rev_id) {
1112 case 0x1000:
1113 rev_str = "A";
1114 break;
1115
1116 case 0x1001:
1117 rev_str = "Z";
1118 break;
1119 }
1120 break;
1121
1122 case 0x420:
1123 device_str = "STM32F100 (Low/Medium Density)";
1124
1125 switch (rev_id) {
1126 case 0x1000:
1127 rev_str = "A";
1128 break;
1129
1130 case 0x1001:
1131 rev_str = "Z";
1132 break;
1133 }
1134 break;
1135
1136 case 0x422:
1137 device_str = "STM32F302xB/C";
1138
1139 switch (rev_id) {
1140 case 0x1000:
1141 rev_str = "A";
1142 break;
1143
1144 case 0x1001:
1145 rev_str = "Z";
1146 break;
1147
1148 case 0x1003:
1149 rev_str = "Y";
1150 break;
1151
1152 case 0x2000:
1153 rev_str = "B";
1154 break;
1155 }
1156 break;
1157
1158 case 0x428:
1159 device_str = "STM32F100 (High Density)";
1160
1161 switch (rev_id) {
1162 case 0x1000:
1163 rev_str = "A";
1164 break;
1165
1166 case 0x1001:
1167 rev_str = "Z";
1168 break;
1169 }
1170 break;
1171
1172 case 0x430:
1173 device_str = "STM32F10x (XL Density)";
1174
1175 switch (rev_id) {
1176 case 0x1000:
1177 rev_str = "A";
1178 break;
1179 }
1180 break;
1181
1182 case 0x432:
1183 device_str = "STM32F37x";
1184
1185 switch (rev_id) {
1186 case 0x1000:
1187 rev_str = "A";
1188 break;
1189
1190 case 0x2000:
1191 rev_str = "B";
1192 break;
1193 }
1194 break;
1195
1196 case 0x438:
1197 device_str = "STM32F33x";
1198
1199 switch (rev_id) {
1200 case 0x1000:
1201 rev_str = "A";
1202 break;
1203 }
1204 break;
1205
1206 case 0x439:
1207 device_str = "STM32F302x6/8";
1208
1209 switch (rev_id) {
1210 case 0x1000:
1211 rev_str = "A";
1212 break;
1213
1214 case 0x1001:
1215 rev_str = "Z";
1216 break;
1217 }
1218 break;
1219
1220 case 0x444:
1221 device_str = "STM32F03x";
1222
1223 switch (rev_id) {
1224 case 0x1000:
1225 rev_str = "1.0";
1226 break;
1227
1228 case 0x2000:
1229 rev_str = "2.0";
1230 break;
1231 }
1232 break;
1233
1234 case 0x440:
1235 device_str = "STM32F05x";
1236
1237 switch (rev_id) {
1238 case 0x1000:
1239 rev_str = "1.0";
1240 break;
1241
1242 case 0x2000:
1243 rev_str = "2.0";
1244 break;
1245 }
1246 break;
1247
1248 case 0x445:
1249 device_str = "STM32F04x";
1250
1251 switch (rev_id) {
1252 case 0x1000:
1253 rev_str = "1.0";
1254 break;
1255
1256 case 0x2000:
1257 rev_str = "2.0";
1258 break;
1259 }
1260 break;
1261
1262 case 0x448:
1263 device_str = "STM32F07x";
1264
1265 switch (rev_id) {
1266 case 0x1000:
1267 rev_str = "1.0";
1268 break;
1269
1270 case 0x2000:
1271 rev_str = "2.0";
1272 break;
1273 }
1274 break;
1275
1276 default:
1277 snprintf(buf, buf_size, "Cannot identify target as a STM32F0/1/3\n");
1278 return ERROR_FAIL;
1279 }
1280
1281 if (rev_str != NULL)
1282 snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
1283 else
1284 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1285
1286 return ERROR_OK;
1287 }
1288
1289 COMMAND_HANDLER(stm32x_handle_lock_command)
1290 {
1291 struct target *target = NULL;
1292 struct stm32x_flash_bank *stm32x_info = NULL;
1293
1294 if (CMD_ARGC < 1)
1295 return ERROR_COMMAND_SYNTAX_ERROR;
1296
1297 struct flash_bank *bank;
1298 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1299 if (ERROR_OK != retval)
1300 return retval;
1301
1302 stm32x_info = bank->driver_priv;
1303
1304 target = bank->target;
1305
1306 if (target->state != TARGET_HALTED) {
1307 LOG_ERROR("Target not halted");
1308 return ERROR_TARGET_NOT_HALTED;
1309 }
1310
1311 retval = stm32x_check_operation_supported(bank);
1312 if (ERROR_OK != retval)
1313 return retval;
1314
1315 if (stm32x_erase_options(bank) != ERROR_OK) {
1316 command_print(CMD_CTX, "stm32x failed to erase options");
1317 return ERROR_OK;
1318 }
1319
1320 /* set readout protection */
1321 stm32x_info->option_bytes.RDP = 0;
1322
1323 if (stm32x_write_options(bank) != ERROR_OK) {
1324 command_print(CMD_CTX, "stm32x failed to lock device");
1325 return ERROR_OK;
1326 }
1327
1328 command_print(CMD_CTX, "stm32x locked");
1329
1330 return ERROR_OK;
1331 }
1332
1333 COMMAND_HANDLER(stm32x_handle_unlock_command)
1334 {
1335 struct target *target = NULL;
1336
1337 if (CMD_ARGC < 1)
1338 return ERROR_COMMAND_SYNTAX_ERROR;
1339
1340 struct flash_bank *bank;
1341 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1342 if (ERROR_OK != retval)
1343 return retval;
1344
1345 target = bank->target;
1346
1347 if (target->state != TARGET_HALTED) {
1348 LOG_ERROR("Target not halted");
1349 return ERROR_TARGET_NOT_HALTED;
1350 }
1351
1352 retval = stm32x_check_operation_supported(bank);
1353 if (ERROR_OK != retval)
1354 return retval;
1355
1356 if (stm32x_erase_options(bank) != ERROR_OK) {
1357 command_print(CMD_CTX, "stm32x failed to unlock device");
1358 return ERROR_OK;
1359 }
1360
1361 if (stm32x_write_options(bank) != ERROR_OK) {
1362 command_print(CMD_CTX, "stm32x failed to lock device");
1363 return ERROR_OK;
1364 }
1365
1366 command_print(CMD_CTX, "stm32x unlocked.\n"
1367 "INFO: a reset or power cycle is required "
1368 "for the new settings to take effect.");
1369
1370 return ERROR_OK;
1371 }
1372
1373 COMMAND_HANDLER(stm32x_handle_options_read_command)
1374 {
1375 uint32_t optionbyte;
1376 struct target *target = NULL;
1377 struct stm32x_flash_bank *stm32x_info = NULL;
1378
1379 if (CMD_ARGC < 1)
1380 return ERROR_COMMAND_SYNTAX_ERROR;
1381
1382 struct flash_bank *bank;
1383 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1384 if (ERROR_OK != retval)
1385 return retval;
1386
1387 stm32x_info = bank->driver_priv;
1388
1389 target = bank->target;
1390
1391 if (target->state != TARGET_HALTED) {
1392 LOG_ERROR("Target not halted");
1393 return ERROR_TARGET_NOT_HALTED;
1394 }
1395
1396 retval = stm32x_check_operation_supported(bank);
1397 if (ERROR_OK != retval)
1398 return retval;
1399
1400 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1401 if (retval != ERROR_OK)
1402 return retval;
1403 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1404
1405 int user_data = optionbyte;
1406
1407 if (optionbyte >> OPT_ERROR & 1)
1408 command_print(CMD_CTX, "Option Byte Complement Error");
1409
1410 if (optionbyte >> OPT_READOUT & 1)
1411 command_print(CMD_CTX, "Readout Protection On");
1412 else
1413 command_print(CMD_CTX, "Readout Protection Off");
1414
1415 /* user option bytes are offset depending on variant */
1416 optionbyte >>= stm32x_info->option_offset;
1417
1418 if (optionbyte >> OPT_RDWDGSW & 1)
1419 command_print(CMD_CTX, "Software Watchdog");
1420 else
1421 command_print(CMD_CTX, "Hardware Watchdog");
1422
1423 if (optionbyte >> OPT_RDRSTSTOP & 1)
1424 command_print(CMD_CTX, "Stop: No reset generated");
1425 else
1426 command_print(CMD_CTX, "Stop: Reset generated");
1427
1428 if (optionbyte >> OPT_RDRSTSTDBY & 1)
1429 command_print(CMD_CTX, "Standby: No reset generated");
1430 else
1431 command_print(CMD_CTX, "Standby: Reset generated");
1432
1433 if (stm32x_info->has_dual_banks) {
1434 if (optionbyte >> OPT_BFB2 & 1)
1435 command_print(CMD_CTX, "Boot: Bank 0");
1436 else
1437 command_print(CMD_CTX, "Boot: Bank 1");
1438 }
1439
1440 command_print(CMD_CTX, "User Option0: 0x%02" PRIx8,
1441 (uint8_t)((user_data >> stm32x_info->user_data_offset) & 0xff));
1442 command_print(CMD_CTX, "User Option1: 0x%02" PRIx8,
1443 (uint8_t)((user_data >> (stm32x_info->user_data_offset + 8)) & 0xff));
1444
1445 return ERROR_OK;
1446 }
1447
1448 COMMAND_HANDLER(stm32x_handle_options_write_command)
1449 {
1450 struct target *target = NULL;
1451 struct stm32x_flash_bank *stm32x_info = NULL;
1452 uint16_t optionbyte;
1453
1454 if (CMD_ARGC < 2)
1455 return ERROR_COMMAND_SYNTAX_ERROR;
1456
1457 struct flash_bank *bank;
1458 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1459 if (ERROR_OK != retval)
1460 return retval;
1461
1462 stm32x_info = bank->driver_priv;
1463
1464 target = bank->target;
1465
1466 if (target->state != TARGET_HALTED) {
1467 LOG_ERROR("Target not halted");
1468 return ERROR_TARGET_NOT_HALTED;
1469 }
1470
1471 retval = stm32x_check_operation_supported(bank);
1472 if (ERROR_OK != retval)
1473 return retval;
1474
1475 retval = stm32x_read_options(bank);
1476 if (ERROR_OK != retval)
1477 return retval;
1478
1479 /* start with current options */
1480 optionbyte = stm32x_info->option_bytes.user_options;
1481
1482 /* skip over flash bank */
1483 CMD_ARGC--;
1484 CMD_ARGV++;
1485
1486 while (CMD_ARGC) {
1487 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1488 optionbyte |= (1 << 0);
1489 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1490 optionbyte &= ~(1 << 0);
1491 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1492 optionbyte |= (1 << 1);
1493 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1494 optionbyte &= ~(1 << 1);
1495 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1496 optionbyte |= (1 << 2);
1497 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1498 optionbyte &= ~(1 << 2);
1499 else if (stm32x_info->has_dual_banks) {
1500 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1501 optionbyte |= (1 << 3);
1502 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1503 optionbyte &= ~(1 << 3);
1504 else
1505 return ERROR_COMMAND_SYNTAX_ERROR;
1506 } else
1507 return ERROR_COMMAND_SYNTAX_ERROR;
1508 CMD_ARGC--;
1509 CMD_ARGV++;
1510 }
1511
1512 if (stm32x_erase_options(bank) != ERROR_OK) {
1513 command_print(CMD_CTX, "stm32x failed to erase options");
1514 return ERROR_OK;
1515 }
1516
1517 stm32x_info->option_bytes.user_options = optionbyte;
1518
1519 if (stm32x_write_options(bank) != ERROR_OK) {
1520 command_print(CMD_CTX, "stm32x failed to write options");
1521 return ERROR_OK;
1522 }
1523
1524 command_print(CMD_CTX, "stm32x write options complete.\n"
1525 "INFO: a reset or power cycle is required "
1526 "for the new settings to take effect.");
1527
1528 return ERROR_OK;
1529 }
1530
1531 static int stm32x_mass_erase(struct flash_bank *bank)
1532 {
1533 struct target *target = bank->target;
1534
1535 if (target->state != TARGET_HALTED) {
1536 LOG_ERROR("Target not halted");
1537 return ERROR_TARGET_NOT_HALTED;
1538 }
1539
1540 /* unlock option flash registers */
1541 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1542 if (retval != ERROR_OK)
1543 return retval;
1544 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1545 if (retval != ERROR_OK)
1546 return retval;
1547
1548 /* mass erase flash memory */
1549 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1550 if (retval != ERROR_OK)
1551 return retval;
1552 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1553 FLASH_MER | FLASH_STRT);
1554 if (retval != ERROR_OK)
1555 return retval;
1556
1557 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1558 if (retval != ERROR_OK)
1559 return retval;
1560
1561 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1562 if (retval != ERROR_OK)
1563 return retval;
1564
1565 return ERROR_OK;
1566 }
1567
1568 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1569 {
1570 int i;
1571
1572 if (CMD_ARGC < 1)
1573 return ERROR_COMMAND_SYNTAX_ERROR;
1574
1575 struct flash_bank *bank;
1576 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1577 if (ERROR_OK != retval)
1578 return retval;
1579
1580 retval = stm32x_mass_erase(bank);
1581 if (retval == ERROR_OK) {
1582 /* set all sectors as erased */
1583 for (i = 0; i < bank->num_sectors; i++)
1584 bank->sectors[i].is_erased = 1;
1585
1586 command_print(CMD_CTX, "stm32x mass erase complete");
1587 } else
1588 command_print(CMD_CTX, "stm32x mass erase failed");
1589
1590 return retval;
1591 }
1592
1593 static const struct command_registration stm32x_exec_command_handlers[] = {
1594 {
1595 .name = "lock",
1596 .handler = stm32x_handle_lock_command,
1597 .mode = COMMAND_EXEC,
1598 .usage = "bank_id",
1599 .help = "Lock entire flash device.",
1600 },
1601 {
1602 .name = "unlock",
1603 .handler = stm32x_handle_unlock_command,
1604 .mode = COMMAND_EXEC,
1605 .usage = "bank_id",
1606 .help = "Unlock entire protected flash device.",
1607 },
1608 {
1609 .name = "mass_erase",
1610 .handler = stm32x_handle_mass_erase_command,
1611 .mode = COMMAND_EXEC,
1612 .usage = "bank_id",
1613 .help = "Erase entire flash device.",
1614 },
1615 {
1616 .name = "options_read",
1617 .handler = stm32x_handle_options_read_command,
1618 .mode = COMMAND_EXEC,
1619 .usage = "bank_id",
1620 .help = "Read and display device option byte.",
1621 },
1622 {
1623 .name = "options_write",
1624 .handler = stm32x_handle_options_write_command,
1625 .mode = COMMAND_EXEC,
1626 .usage = "bank_id ('SWWDG'|'HWWDG') "
1627 "('RSTSTNDBY'|'NORSTSTNDBY') "
1628 "('RSTSTOP'|'NORSTSTOP')",
1629 .help = "Replace bits in device option byte.",
1630 },
1631 COMMAND_REGISTRATION_DONE
1632 };
1633
1634 static const struct command_registration stm32x_command_handlers[] = {
1635 {
1636 .name = "stm32f1x",
1637 .mode = COMMAND_ANY,
1638 .help = "stm32f1x flash command group",
1639 .usage = "",
1640 .chain = stm32x_exec_command_handlers,
1641 },
1642 COMMAND_REGISTRATION_DONE
1643 };
1644
1645 struct flash_driver stm32f1x_flash = {
1646 .name = "stm32f1x",
1647 .commands = stm32x_command_handlers,
1648 .flash_bank_command = stm32x_flash_bank_command,
1649 .erase = stm32x_erase,
1650 .protect = stm32x_protect,
1651 .write = stm32x_write,
1652 .read = default_flash_read,
1653 .probe = stm32x_probe,
1654 .auto_probe = stm32x_auto_probe,
1655 .erase_check = default_flash_blank_check,
1656 .protect_check = stm32x_protect_check,
1657 .info = get_stm32x_info,
1658 };
Open On-Chip Debugger

Linking to existing account procedure

If you already have an account and want to add another login method you MUST first sign in with your existing account and then change URL to read https://review.openocd.org/login/?link to get to this page again but this time it'll work for linking. Thank you.

SSH host keys fingerprints

1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=..              |
|+o..   .         |
|*.o   . .        |
|+B . . .         |
|Bo. = o S        |
|Oo.+ + =         |
|oB=.* = . o      |
| =+=.+   + E     |
|. .=o   . o      |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)