1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
34 /* Regarding performance:
36 * Short story - it might be best to leave the performance at
39 * You may see a jump in speed if you change to using
40 * 32bit words for the block programming.
42 * Its a shame you cannot use the double word as its
43 * even faster - but you require external VPP for that mode.
45 * Having said all that 16bit writes give us the widest vdd
46 * operating range, so may be worth adding a note to that effect.
50 /* Danger!!!! The STM32F1x and STM32F2x series actually have
51 * quite different flash controllers.
53 * What's more scary is that the names of the registers and their
54 * addresses are the same, but the actual bits and what they do are
55 * can be very different.
57 * To reduce testing complexity and dangers of regressions,
58 * a seperate file is used for stm32fx2x.
60 * Sector sizes in kiBytes:
61 * 1 MiByte part with 4 x 16, 1 x 64, 7 x 128.
62 * 1.5 MiByte part with 4 x 16, 1 x 64, 11 x 128.
63 * 2 MiByte part with 4 x 16, 1 x 64, 7 x 128, 4 x 16, 1 x 64, 7 x 128.
64 * 1 MiByte STM32F42x/43x part with DB1M Option set:
65 * 4 x 16, 1 x 64, 3 x 128, 4 x 16, 1 x 64, 3 x 128.
68 * 512 kiByte part with 4 x 16, 1 x 64, 3 x 128.
71 * 1 MiByte part with 4 x 32, 1 x 128, 3 x 256.
74 * 1 MiByte part in single bank mode with 4 x 32, 1 x 128, 3 x 256.
75 * 1 MiByte part in dual-bank mode two banks with 4 x 16, 1 x 64, 3 x 128 each.
76 * 2 MiByte part in single-bank mode with 4 x 32, 1 x 128, 7 x 256.
77 * 2 MiByte part in dual-bank mode two banks with 4 x 16, 1 x 64, 7 x 128 each.
79 * Protection size is sector size.
81 * Tested with STM3220F-EVAL board.
83 * STM32F4xx series for reference.
86 * http://www.st.com/web/en/resource/technical/document/reference_manual/DM00031020.pdf
89 * www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/
90 * PROGRAMMING_MANUAL/CD00233952.pdf
92 * STM32F7xx series for reference.
95 * http://www.st.com/web/en/resource/technical/document/reference_manual/DM00124865.pdf
98 * http://www.st.com/resource/en/reference_manual/dm00224583.pdf
101 * http://www.st.com/resource/en/reference_manual/dm00305666.pdf
104 * http://www.st.com/resource/en/reference_manual/dm00305990.pdf
106 * STM32F1x series - notice that this code was copy, pasted and knocked
107 * into a stm32f2x driver, so in case something has been converted or
108 * bugs haven't been fixed, here are the original manuals:
110 * RM0008 - Reference manual
112 * RM0042, the Flash programming manual for low-, medium- high-density and
113 * connectivity line STM32F10x devices
115 * PM0068, the Flash programming manual for XL-density STM32F10x devices.
119 /* Erase time can be as high as 1000ms, 10x this and it's toast... */
120 #define FLASH_ERASE_TIMEOUT 10000
121 #define FLASH_WRITE_TIMEOUT 5
123 /* Mass erase time can be as high as 32 s in x8 mode. */
124 #define FLASH_MASS_ERASE_TIMEOUT 33000
126 #define FLASH_BANK_BASE 0x80000000
128 #define STM32F2_OTP_SIZE 512
129 #define STM32F2_OTP_SECTOR_SIZE 32
130 #define STM32F2_OTP_BANK_BASE 0x1fff7800
131 #define STM32F2_OTP_LOCK_BASE ((STM32F2_OTP_BANK_BASE) + (STM32F2_OTP_SIZE))
133 /* see RM0410 section 3.6 "One-time programmable bytes" */
134 #define STM32F7_OTP_SECTOR_SIZE 64
135 #define STM32F7_OTP_SIZE 1024
136 #define STM32F7_OTP_BANK_BASE 0x1ff0f000
137 #define STM32F7_OTP_LOCK_BASE ((STM32F7_OTP_BANK_BASE) + (STM32F7_OTP_SIZE))
139 #define STM32_FLASH_BASE 0x40023c00
140 #define STM32_FLASH_ACR 0x40023c00
141 #define STM32_FLASH_KEYR 0x40023c04
142 #define STM32_FLASH_OPTKEYR 0x40023c08
143 #define STM32_FLASH_SR 0x40023c0C
144 #define STM32_FLASH_CR 0x40023c10
145 #define STM32_FLASH_OPTCR 0x40023c14
146 #define STM32_FLASH_OPTCR1 0x40023c18
147 #define STM32_FLASH_OPTCR2 0x40023c1c
149 /* FLASH_CR register bits */
150 #define FLASH_PG (1 << 0)
151 #define FLASH_SER (1 << 1)
152 #define FLASH_MER (1 << 2) /* MER/MER1 for f76x/77x */
153 #define FLASH_MER1 (1 << 15) /* MER2 for f76x/77x, confusing ... */
154 #define FLASH_STRT (1 << 16)
155 #define FLASH_PSIZE_8 (0 << 8)
156 #define FLASH_PSIZE_16 (1 << 8)
157 #define FLASH_PSIZE_32 (2 << 8)
158 #define FLASH_PSIZE_64 (3 << 8)
159 /* The sector number encoding is not straight binary for dual bank flash. */
160 #define FLASH_SNB(a) ((a) << 3)
161 #define FLASH_LOCK (1 << 31)
163 /* FLASH_SR register bits */
164 #define FLASH_BSY (1 << 16)
165 #define FLASH_PGSERR (1 << 7) /* Programming sequence error */
166 #define FLASH_PGPERR (1 << 6) /* Programming parallelism error */
167 #define FLASH_PGAERR (1 << 5) /* Programming alignment error */
168 #define FLASH_WRPERR (1 << 4) /* Write protection error */
169 #define FLASH_OPERR (1 << 1) /* Operation error */
171 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGPERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
173 /* STM32_FLASH_OPTCR register bits */
174 #define OPTCR_LOCK (1 << 0)
175 #define OPTCR_START (1 << 1)
176 #define OPTCR_NDBANK (1 << 29) /* not dual bank mode */
177 #define OPTCR_DB1M (1 << 30) /* 1 MiB devices dual flash bank option */
178 #define OPTCR_SPRMOD (1 << 31) /* switches PCROPi/nWPRi interpretation */
180 /* STM32_FLASH_OPTCR2 register bits */
181 #define OPTCR2_PCROP_RDP (1 << 31) /* erase PCROP zone when decreasing RDP */
183 /* register unlock keys */
184 #define KEY1 0x45670123
185 #define KEY2 0xCDEF89AB
187 /* option register unlock key */
188 #define OPTKEY1 0x08192A3B
189 #define OPTKEY2 0x4C5D6E7F
191 struct stm32x_options
{
193 uint16_t user_options
; /* bit 0-7 usual options, bit 8-11 extra options */
196 uint32_t optcr2_pcrop
;
199 struct stm32x_flash_bank
{
200 struct stm32x_options option_bytes
;
203 bool has_large_mem
; /* F42x/43x/469/479/7xx in dual bank mode */
204 bool has_extra_options
; /* F42x/43x/469/479/7xx */
205 bool has_boot_addr
; /* F7xx */
206 bool has_optcr2_pcrop
; /* F72x/73x */
207 int protection_bits
; /* F413/423 */
208 uint32_t user_bank_size
;
211 static bool stm32x_is_otp(struct flash_bank
*bank
)
213 return bank
->base
== STM32F2_OTP_BANK_BASE
||
214 bank
->base
== STM32F7_OTP_BANK_BASE
;
217 static bool stm32x_otp_is_f7(struct flash_bank
*bank
)
219 return bank
->base
== STM32F7_OTP_BANK_BASE
;
222 static int stm32x_is_otp_unlocked(struct flash_bank
*bank
)
224 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
226 return stm32x_info
->otp_unlocked
;
229 static int stm32x_otp_disable(struct flash_bank
*bank
)
231 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
233 LOG_INFO("OTP memory bank #%d is disabled for write commands.",
235 stm32x_info
->otp_unlocked
= false;
239 static int stm32x_otp_enable(struct flash_bank
*bank
)
241 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
243 if (!stm32x_info
->otp_unlocked
) {
244 LOG_INFO("OTP memory bank #%d is is enabled for write commands.",
246 stm32x_info
->otp_unlocked
= true;
248 LOG_WARNING("OTP memory bank #%d is is already enabled for write commands.",
254 /* flash bank stm32x <base> <size> 0 0 <target#>
256 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command
)
258 struct stm32x_flash_bank
*stm32x_info
;
261 return ERROR_COMMAND_SYNTAX_ERROR
;
263 stm32x_info
= malloc(sizeof(struct stm32x_flash_bank
));
264 bank
->driver_priv
= stm32x_info
;
266 stm32x_info
->probed
= false;
267 stm32x_info
->otp_unlocked
= false;
268 stm32x_info
->user_bank_size
= bank
->size
;
273 static inline int stm32x_get_flash_reg(struct flash_bank
*bank
, uint32_t reg
)
278 static inline int stm32x_get_flash_status(struct flash_bank
*bank
, uint32_t *status
)
280 struct target
*target
= bank
->target
;
281 return target_read_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
), status
);
284 static int stm32x_wait_status_busy(struct flash_bank
*bank
, int timeout
)
286 struct target
*target
= bank
->target
;
288 int retval
= ERROR_OK
;
290 /* wait for busy to clear */
292 retval
= stm32x_get_flash_status(bank
, &status
);
293 if (retval
!= ERROR_OK
)
295 LOG_DEBUG("status: 0x%" PRIx32
"", status
);
296 if ((status
& FLASH_BSY
) == 0)
298 if (timeout
-- <= 0) {
299 LOG_ERROR("timed out waiting for flash");
306 if (status
& FLASH_WRPERR
) {
307 LOG_ERROR("stm32x device protected");
311 /* Clear but report errors */
312 if (status
& FLASH_ERROR
) {
313 if (retval
== ERROR_OK
)
315 /* If this operation fails, we ignore it and report the original
318 target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_SR
),
319 status
& FLASH_ERROR
);
324 static int stm32x_unlock_reg(struct target
*target
)
328 /* first check if not already unlocked
329 * otherwise writing on STM32_FLASH_KEYR will fail
331 int retval
= target_read_u32(target
, STM32_FLASH_CR
, &ctrl
);
332 if (retval
!= ERROR_OK
)
335 if ((ctrl
& FLASH_LOCK
) == 0)
338 /* unlock flash registers */
339 retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY1
);
340 if (retval
!= ERROR_OK
)
343 retval
= target_write_u32(target
, STM32_FLASH_KEYR
, KEY2
);
344 if (retval
!= ERROR_OK
)
347 retval
= target_read_u32(target
, STM32_FLASH_CR
, &ctrl
);
348 if (retval
!= ERROR_OK
)
351 if (ctrl
& FLASH_LOCK
) {
352 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32
, ctrl
);
353 return ERROR_TARGET_FAILURE
;
359 static int stm32x_unlock_option_reg(struct target
*target
)
363 int retval
= target_read_u32(target
, STM32_FLASH_OPTCR
, &ctrl
);
364 if (retval
!= ERROR_OK
)
367 if ((ctrl
& OPTCR_LOCK
) == 0)
370 /* unlock option registers */
371 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR
, OPTKEY1
);
372 if (retval
!= ERROR_OK
)
375 retval
= target_write_u32(target
, STM32_FLASH_OPTKEYR
, OPTKEY2
);
376 if (retval
!= ERROR_OK
)
379 retval
= target_read_u32(target
, STM32_FLASH_OPTCR
, &ctrl
);
380 if (retval
!= ERROR_OK
)
383 if (ctrl
& OPTCR_LOCK
) {
384 LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %" PRIx32
, ctrl
);
385 return ERROR_TARGET_FAILURE
;
391 static int stm32x_read_options(struct flash_bank
*bank
)
394 struct stm32x_flash_bank
*stm32x_info
= NULL
;
395 struct target
*target
= bank
->target
;
397 stm32x_info
= bank
->driver_priv
;
399 /* read current option bytes */
400 int retval
= target_read_u32(target
, STM32_FLASH_OPTCR
, &optiondata
);
401 if (retval
!= ERROR_OK
)
404 /* caution: F2 implements 5 bits (WDG_SW only)
405 * whereas F7 6 bits (IWDG_SW and WWDG_SW) in user_options */
406 stm32x_info
->option_bytes
.user_options
= optiondata
& 0xfc;
407 stm32x_info
->option_bytes
.RDP
= (optiondata
>> 8) & 0xff;
408 stm32x_info
->option_bytes
.protection
=
409 (optiondata
>> 16) & (~(0xffff << stm32x_info
->protection_bits
) & 0xffff);
411 if (stm32x_info
->has_extra_options
) {
412 /* F42x/43x/469/479 and 7xx have up to 4 bits of extra options */
413 stm32x_info
->option_bytes
.user_options
|= (optiondata
>> 20) &
414 ((0xf00 << (stm32x_info
->protection_bits
- 12)) & 0xf00);
417 if (stm32x_info
->has_large_mem
|| stm32x_info
->has_boot_addr
) {
418 retval
= target_read_u32(target
, STM32_FLASH_OPTCR1
, &optiondata
);
419 if (retval
!= ERROR_OK
)
422 /* FLASH_OPTCR1 has quite diffent meanings ... */
423 if (stm32x_info
->has_boot_addr
) {
424 /* for F7xx it contains boot0 and boot1 */
425 stm32x_info
->option_bytes
.boot_addr
= optiondata
;
427 /* for F42x/43x/469/479 it contains 12 additional protection bits */
428 stm32x_info
->option_bytes
.protection
|= (optiondata
>> 4) & 0x00fff000;
432 if (stm32x_info
->has_optcr2_pcrop
) {
433 retval
= target_read_u32(target
, STM32_FLASH_OPTCR2
, &optiondata
);
434 if (retval
!= ERROR_OK
)
437 stm32x_info
->option_bytes
.optcr2_pcrop
= optiondata
;
438 if (stm32x_info
->has_optcr2_pcrop
&&
439 (stm32x_info
->option_bytes
.optcr2_pcrop
& ~OPTCR2_PCROP_RDP
)) {
440 LOG_INFO("PCROP Engaged");
443 stm32x_info
->option_bytes
.optcr2_pcrop
= 0x0;
446 if (stm32x_info
->option_bytes
.RDP
!= 0xAA)
447 LOG_INFO("Device Security Bit Set");
452 static int stm32x_write_options(struct flash_bank
*bank
)
454 struct stm32x_flash_bank
*stm32x_info
= NULL
;
455 struct target
*target
= bank
->target
;
456 uint32_t optiondata
, optiondata2
;
458 stm32x_info
= bank
->driver_priv
;
460 int retval
= stm32x_unlock_option_reg(target
);
461 if (retval
!= ERROR_OK
)
464 /* rebuild option data */
465 optiondata
= stm32x_info
->option_bytes
.user_options
& 0xfc;
466 optiondata
|= stm32x_info
->option_bytes
.RDP
<< 8;
467 optiondata
|= (stm32x_info
->option_bytes
.protection
&
468 (~(0xffff << stm32x_info
->protection_bits
))) << 16;
470 if (stm32x_info
->has_extra_options
) {
471 /* F42x/43x/469/479 and 7xx have up to 4 bits of extra options */
472 optiondata
|= (stm32x_info
->option_bytes
.user_options
&
473 ((0xf00 << (stm32x_info
->protection_bits
- 12)) & 0xf00)) << 20;
476 if (stm32x_info
->has_large_mem
|| stm32x_info
->has_boot_addr
) {
477 if (stm32x_info
->has_boot_addr
) {
478 /* F7xx uses FLASH_OPTCR1 for boot0 and boot1 ... */
479 optiondata2
= stm32x_info
->option_bytes
.boot_addr
;
481 /* F42x/43x/469/479 uses FLASH_OPTCR1 for additional protection bits */
482 optiondata2
= (stm32x_info
->option_bytes
.protection
& 0x00fff000) << 4;
485 retval
= target_write_u32(target
, STM32_FLASH_OPTCR1
, optiondata2
);
486 if (retval
!= ERROR_OK
)
490 /* program extra pcrop register */
491 if (stm32x_info
->has_optcr2_pcrop
) {
492 retval
= target_write_u32(target
, STM32_FLASH_OPTCR2
,
493 stm32x_info
->option_bytes
.optcr2_pcrop
);
494 if (retval
!= ERROR_OK
)
498 /* program options */
499 retval
= target_write_u32(target
, STM32_FLASH_OPTCR
, optiondata
);
500 if (retval
!= ERROR_OK
)
503 /* start programming cycle */
504 retval
= target_write_u32(target
, STM32_FLASH_OPTCR
, optiondata
| OPTCR_START
);
505 if (retval
!= ERROR_OK
)
508 /* wait for completion, this might trigger a security erase and take a while */
509 retval
= stm32x_wait_status_busy(bank
, FLASH_MASS_ERASE_TIMEOUT
);
510 if (retval
!= ERROR_OK
)
513 /* relock registers */
514 retval
= target_write_u32(target
, STM32_FLASH_OPTCR
, optiondata
| OPTCR_LOCK
);
515 if (retval
!= ERROR_OK
)
521 static int stm32x_otp_read_protect(struct flash_bank
*bank
)
523 struct target
*target
= bank
->target
;
528 lock_base
= stm32x_otp_is_f7(bank
) ? STM32F7_OTP_LOCK_BASE
529 : STM32F2_OTP_LOCK_BASE
;
531 for (i
= 0; i
< bank
->num_sectors
; i
++) {
532 retval
= target_read_u8(target
, lock_base
+ i
, &lock
);
533 if (retval
!= ERROR_OK
)
535 bank
->sectors
[i
].is_protected
= !lock
;
541 static int stm32x_otp_protect(struct flash_bank
*bank
, int first
, int last
)
543 struct target
*target
= bank
->target
;
548 assert((0 <= first
) && (first
<= last
) && (last
< bank
->num_sectors
));
550 lock_base
= stm32x_otp_is_f7(bank
) ? STM32F7_OTP_LOCK_BASE
551 : STM32F2_OTP_LOCK_BASE
;
553 for (i
= first
; first
<= last
; i
++) {
554 retval
= target_read_u8(target
, lock_base
+ i
, &lock
);
555 if (retval
!= ERROR_OK
)
561 retval
= target_write_u8(target
, lock_base
+ i
, lock
);
562 if (retval
!= ERROR_OK
)
569 static int stm32x_protect_check(struct flash_bank
*bank
)
571 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
572 struct flash_sector
*prot_blocks
;
576 /* if it's the OTP bank, look at the lock bits there */
577 if (stm32x_is_otp(bank
))
578 return stm32x_otp_read_protect(bank
);
580 /* read write protection settings */
581 retval
= stm32x_read_options(bank
);
582 if (retval
!= ERROR_OK
) {
583 LOG_DEBUG("unable to read option bytes");
587 if (bank
->prot_blocks
) {
588 num_prot_blocks
= bank
->num_prot_blocks
;
589 prot_blocks
= bank
->prot_blocks
;
591 num_prot_blocks
= bank
->num_sectors
;
592 prot_blocks
= bank
->sectors
;
595 for (int i
= 0; i
< num_prot_blocks
; i
++)
596 prot_blocks
[i
].is_protected
=
597 ~(stm32x_info
->option_bytes
.protection
>> i
) & 1;
602 static int stm32x_erase(struct flash_bank
*bank
, int first
, int last
)
604 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
605 struct target
*target
= bank
->target
;
608 if (stm32x_is_otp(bank
)) {
609 LOG_ERROR("Cannot erase OTP memory");
613 assert((0 <= first
) && (first
<= last
) && (last
< bank
->num_sectors
));
615 if (bank
->target
->state
!= TARGET_HALTED
) {
616 LOG_ERROR("Target not halted");
617 return ERROR_TARGET_NOT_HALTED
;
621 retval
= stm32x_unlock_reg(target
);
622 if (retval
!= ERROR_OK
)
627 To erase a sector, follow the procedure below:
628 1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
630 2. Set the SER bit and select the sector
631 you wish to erase (SNB) in the FLASH_CR register
632 3. Set the STRT bit in the FLASH_CR register
633 4. Wait for the BSY bit to be cleared
636 for (i
= first
; i
<= last
; i
++) {
638 if (stm32x_info
->has_large_mem
&& i
>= 12)
639 snb
= (i
- 12) | 0x10;
643 retval
= target_write_u32(target
,
644 stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_SER
| FLASH_SNB(snb
) | FLASH_STRT
);
645 if (retval
!= ERROR_OK
)
648 retval
= stm32x_wait_status_busy(bank
, FLASH_ERASE_TIMEOUT
);
649 if (retval
!= ERROR_OK
)
652 bank
->sectors
[i
].is_erased
= 1;
655 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
656 if (retval
!= ERROR_OK
)
662 static int stm32x_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
664 struct target
*target
= bank
->target
;
665 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
667 if (target
->state
!= TARGET_HALTED
) {
668 LOG_ERROR("Target not halted");
669 return ERROR_TARGET_NOT_HALTED
;
672 if (stm32x_is_otp(bank
)) {
674 return ERROR_COMMAND_ARGUMENT_INVALID
;
676 return stm32x_otp_protect(bank
, first
, last
);
679 /* read protection settings */
680 int retval
= stm32x_read_options(bank
);
681 if (retval
!= ERROR_OK
) {
682 LOG_DEBUG("unable to read option bytes");
686 for (int i
= first
; i
<= last
; i
++) {
688 stm32x_info
->option_bytes
.protection
&= ~(1 << i
);
690 stm32x_info
->option_bytes
.protection
|= (1 << i
);
693 retval
= stm32x_write_options(bank
);
694 if (retval
!= ERROR_OK
)
700 static int stm32x_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
701 uint32_t offset
, uint32_t count
)
703 struct target
*target
= bank
->target
;
704 uint32_t buffer_size
= 16384;
705 struct working_area
*write_algorithm
;
706 struct working_area
*source
;
707 uint32_t address
= bank
->base
+ offset
;
708 struct reg_param reg_params
[5];
709 struct armv7m_algorithm armv7m_info
;
710 int retval
= ERROR_OK
;
712 static const uint8_t stm32x_flash_write_code
[] = {
713 #include "../../../contrib/loaders/flash/stm32/stm32f2x.inc"
716 if (stm32x_is_otp(bank
) && !stm32x_is_otp_unlocked(bank
)) {
717 LOG_ERROR("OTP memory bank is disabled for write commands.");
721 if (target_alloc_working_area(target
, sizeof(stm32x_flash_write_code
),
722 &write_algorithm
) != ERROR_OK
) {
723 LOG_WARNING("no working area available, can't do block memory writes");
724 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
727 retval
= target_write_buffer(target
, write_algorithm
->address
,
728 sizeof(stm32x_flash_write_code
),
729 stm32x_flash_write_code
);
730 if (retval
!= ERROR_OK
) {
731 target_free_working_area(target
, write_algorithm
);
736 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
738 if (buffer_size
<= 256) {
739 /* we already allocated the writing code, but failed to get a
740 * buffer, free the algorithm */
741 target_free_working_area(target
, write_algorithm
);
743 LOG_WARNING("no large enough working area available, can't do block memory writes");
744 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
748 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
749 armv7m_info
.core_mode
= ARM_MODE_THREAD
;
751 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
); /* buffer start, status (out) */
752 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
); /* buffer end */
753 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
); /* target address */
754 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
); /* count (halfword-16bit) */
755 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
); /* flash base */
757 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
758 buf_set_u32(reg_params
[1].value
, 0, 32, source
->address
+ source
->size
);
759 buf_set_u32(reg_params
[2].value
, 0, 32, address
);
760 buf_set_u32(reg_params
[3].value
, 0, 32, count
);
761 buf_set_u32(reg_params
[4].value
, 0, 32, STM32_FLASH_BASE
);
763 retval
= target_run_flash_async_algorithm(target
, buffer
, count
, 2,
766 source
->address
, source
->size
,
767 write_algorithm
->address
, 0,
770 if (retval
== ERROR_FLASH_OPERATION_FAILED
) {
771 LOG_ERROR("error executing stm32x flash write algorithm");
773 uint32_t error
= buf_get_u32(reg_params
[0].value
, 0, 32) & FLASH_ERROR
;
775 if (error
& FLASH_WRPERR
)
776 LOG_ERROR("flash memory write protected");
779 LOG_ERROR("flash write failed = %08" PRIx32
, error
);
780 /* Clear but report errors */
781 target_write_u32(target
, STM32_FLASH_SR
, error
);
786 target_free_working_area(target
, source
);
787 target_free_working_area(target
, write_algorithm
);
789 destroy_reg_param(®_params
[0]);
790 destroy_reg_param(®_params
[1]);
791 destroy_reg_param(®_params
[2]);
792 destroy_reg_param(®_params
[3]);
793 destroy_reg_param(®_params
[4]);
798 static int stm32x_write(struct flash_bank
*bank
, const uint8_t *buffer
,
799 uint32_t offset
, uint32_t count
)
801 struct target
*target
= bank
->target
;
802 uint32_t words_remaining
= (count
/ 2);
803 uint32_t bytes_remaining
= (count
& 0x00000001);
804 uint32_t address
= bank
->base
+ offset
;
805 uint32_t bytes_written
= 0;
808 if (bank
->target
->state
!= TARGET_HALTED
) {
809 LOG_ERROR("Target not halted");
810 return ERROR_TARGET_NOT_HALTED
;
814 LOG_WARNING("offset 0x%" PRIx32
" breaks required 2-byte alignment", offset
);
815 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
818 retval
= stm32x_unlock_reg(target
);
819 if (retval
!= ERROR_OK
)
822 /* multiple half words (2-byte) to be programmed? */
823 if (words_remaining
> 0) {
824 /* try using a block write */
825 retval
= stm32x_write_block(bank
, buffer
, offset
, words_remaining
);
826 if (retval
!= ERROR_OK
) {
827 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
828 /* if block write failed (no sufficient working area),
829 * we use normal (slow) single dword accesses */
830 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
833 buffer
+= words_remaining
* 2;
834 address
+= words_remaining
* 2;
839 if ((retval
!= ERROR_OK
) && (retval
!= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
))
844 The Flash memory programming sequence is as follows:
845 1. Check that no main Flash memory operation is ongoing by checking the BSY bit in the
847 2. Set the PG bit in the FLASH_CR register
848 3. Perform the data write operation(s) to the desired memory address (inside main
849 memory block or OTP area):
850 – – Half-word access in case of x16 parallelism
851 – Word access in case of x32 parallelism
854 Byte access in case of x8 parallelism
855 Double word access in case of x64 parallelism
856 Wait for the BSY bit to be cleared
858 while (words_remaining
> 0) {
860 memcpy(&value
, buffer
+ bytes_written
, sizeof(uint16_t));
862 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
),
863 FLASH_PG
| FLASH_PSIZE_16
);
864 if (retval
!= ERROR_OK
)
867 retval
= target_write_u16(target
, address
, value
);
868 if (retval
!= ERROR_OK
)
871 retval
= stm32x_wait_status_busy(bank
, FLASH_WRITE_TIMEOUT
);
872 if (retval
!= ERROR_OK
)
880 if (bytes_remaining
) {
881 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
),
882 FLASH_PG
| FLASH_PSIZE_8
);
883 if (retval
!= ERROR_OK
)
885 retval
= target_write_u8(target
, address
, buffer
[bytes_written
]);
886 if (retval
!= ERROR_OK
)
889 retval
= stm32x_wait_status_busy(bank
, FLASH_WRITE_TIMEOUT
);
890 if (retval
!= ERROR_OK
)
894 return target_write_u32(target
, STM32_FLASH_CR
, FLASH_LOCK
);
897 static int setup_sector(struct flash_bank
*bank
, int start
, int num
, int size
)
900 for (int i
= start
; i
< (start
+ num
) ; i
++) {
901 assert(i
< bank
->num_sectors
);
902 bank
->sectors
[i
].offset
= bank
->size
;
903 bank
->sectors
[i
].size
= size
;
904 bank
->size
+= bank
->sectors
[i
].size
;
905 LOG_DEBUG("sector %d: %d kBytes", i
, size
>> 10);
911 static void setup_bank(struct flash_bank
*bank
, int start
,
912 uint16_t flash_size_in_kb
, uint16_t max_sector_size_in_kb
)
916 start
= setup_sector(bank
, start
, 4, (max_sector_size_in_kb
/ 8) * 1024);
917 start
= setup_sector(bank
, start
, 1, (max_sector_size_in_kb
/ 2) * 1024);
919 /* remaining sectors all of size max_sector_size_in_kb */
920 remain
= (flash_size_in_kb
/ max_sector_size_in_kb
) - 1;
921 start
= setup_sector(bank
, start
, remain
, max_sector_size_in_kb
* 1024);
924 static int stm32x_get_device_id(struct flash_bank
*bank
, uint32_t *device_id
)
926 /* this checks for a stm32f4x errata issue where a
927 * stm32f2x DBGMCU_IDCODE is incorrectly returned.
928 * If the issue is detected target is forced to stm32f4x Rev A.
929 * Only effects Rev A silicon */
931 struct target
*target
= bank
->target
;
934 /* read stm32 device id register */
935 int retval
= target_read_u32(target
, 0xE0042000, device_id
);
936 if (retval
!= ERROR_OK
)
939 if ((*device_id
& 0xfff) == 0x411) {
940 /* read CPUID reg to check core type */
941 retval
= target_read_u32(target
, 0xE000ED00, &cpuid
);
942 if (retval
!= ERROR_OK
)
945 /* check for cortex_m4 */
946 if (((cpuid
>> 4) & 0xFFF) == 0xC24) {
947 *device_id
&= ~((0xFFFF << 16) | 0xfff);
948 *device_id
|= (0x1000 << 16) | 0x413;
949 LOG_INFO("stm32f4x errata detected - fixing incorrect MCU_IDCODE");
955 static int stm32x_probe(struct flash_bank
*bank
)
957 struct target
*target
= bank
->target
;
958 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
959 int i
, num_prot_blocks
, num_sectors
;
960 uint16_t flash_size_in_kb
;
961 uint16_t otp_size_in_b
;
962 uint16_t otp_sector_size
;
963 uint32_t flash_size_reg
= 0x1FFF7A22;
964 uint16_t max_sector_size_in_kb
= 128;
965 uint16_t max_flash_size_in_kb
;
967 uint32_t base_address
= 0x08000000;
969 stm32x_info
->probed
= false;
970 stm32x_info
->has_large_mem
= false;
971 stm32x_info
->has_boot_addr
= false;
972 stm32x_info
->has_extra_options
= false;
973 stm32x_info
->has_optcr2_pcrop
= false;
974 stm32x_info
->protection_bits
= 12; /* max. number of nWRPi bits (in FLASH_OPTCR !!!) */
979 bank
->num_sectors
= 0;
980 bank
->sectors
= NULL
;
983 if (bank
->prot_blocks
) {
984 free(bank
->prot_blocks
);
985 bank
->num_prot_blocks
= 0;
986 bank
->prot_blocks
= NULL
;
989 /* if explicitely called out as OTP bank, short circuit probe */
990 if (stm32x_is_otp(bank
)) {
991 if (stm32x_otp_is_f7(bank
)) {
992 otp_size_in_b
= STM32F7_OTP_SIZE
;
993 otp_sector_size
= STM32F7_OTP_SECTOR_SIZE
;
995 otp_size_in_b
= STM32F2_OTP_SIZE
;
996 otp_sector_size
= STM32F2_OTP_SECTOR_SIZE
;
999 num_sectors
= otp_size_in_b
/ otp_sector_size
;
1000 LOG_INFO("flash size = %d bytes", otp_size_in_b
);
1002 assert(num_sectors
> 0);
1004 bank
->num_sectors
= num_sectors
;
1005 bank
->sectors
= calloc(sizeof(struct flash_sector
), num_sectors
);
1007 if (stm32x_otp_is_f7(bank
))
1008 bank
->size
= STM32F7_OTP_SIZE
;
1010 bank
->size
= STM32F2_OTP_SIZE
;
1012 for (i
= 0; i
< num_sectors
; i
++) {
1013 bank
->sectors
[i
].offset
= i
* otp_sector_size
;
1014 bank
->sectors
[i
].size
= otp_sector_size
;
1015 bank
->sectors
[i
].is_erased
= 1;
1016 bank
->sectors
[i
].is_protected
= 0;
1019 stm32x_info
->probed
= true;
1023 /* read stm32 device id register */
1024 int retval
= stm32x_get_device_id(bank
, &device_id
);
1025 if (retval
!= ERROR_OK
)
1027 LOG_INFO("device id = 0x%08" PRIx32
"", device_id
);
1028 device_id
&= 0xfff; /* only bits 0-11 are used further on */
1030 /* set max flash size depending on family, id taken from AN2606 */
1031 switch (device_id
) {
1032 case 0x411: /* F20x/21x */
1033 case 0x413: /* F40x/41x */
1034 max_flash_size_in_kb
= 1024;
1037 case 0x419: /* F42x/43x */
1038 case 0x434: /* F469/479 */
1039 stm32x_info
->has_extra_options
= true;
1040 max_flash_size_in_kb
= 2048;
1043 case 0x423: /* F401xB/C */
1044 max_flash_size_in_kb
= 256;
1047 case 0x421: /* F446 */
1048 case 0x431: /* F411 */
1049 case 0x433: /* F401xD/E */
1050 case 0x441: /* F412 */
1051 max_flash_size_in_kb
= 512;
1054 case 0x458: /* F410 */
1055 max_flash_size_in_kb
= 128;
1058 case 0x449: /* F74x/75x */
1059 max_flash_size_in_kb
= 1024;
1060 max_sector_size_in_kb
= 256;
1061 flash_size_reg
= 0x1FF0F442;
1062 stm32x_info
->has_extra_options
= true;
1063 stm32x_info
->has_boot_addr
= true;
1066 case 0x451: /* F76x/77x */
1067 max_flash_size_in_kb
= 2048;
1068 max_sector_size_in_kb
= 256;
1069 flash_size_reg
= 0x1FF0F442;
1070 stm32x_info
->has_extra_options
= true;
1071 stm32x_info
->has_boot_addr
= true;
1074 case 0x452: /* F72x/73x */
1075 max_flash_size_in_kb
= 512;
1076 flash_size_reg
= 0x1FF07A22; /* yes, 0x1FF*0*7A22, not 0x1FF*F*7A22 */
1077 stm32x_info
->has_extra_options
= true;
1078 stm32x_info
->has_boot_addr
= true;
1079 stm32x_info
->has_optcr2_pcrop
= true;
1082 case 0x463: /* F413x/423x */
1083 max_flash_size_in_kb
= 1536;
1084 stm32x_info
->has_extra_options
= true;
1085 stm32x_info
->protection_bits
= 15;
1086 num_prot_blocks
= 15;
1090 LOG_WARNING("Cannot identify target as a STM32 family.");
1094 /* get flash size from target. */
1095 retval
= target_read_u16(target
, flash_size_reg
, &flash_size_in_kb
);
1097 /* failed reading flash size or flash size invalid (early silicon),
1098 * default to max target family */
1099 if (retval
!= ERROR_OK
|| flash_size_in_kb
== 0xffff || flash_size_in_kb
== 0) {
1100 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
1101 max_flash_size_in_kb
);
1102 flash_size_in_kb
= max_flash_size_in_kb
;
1105 /* if the user sets the size manually then ignore the probed value
1106 * this allows us to work around devices that have a invalid flash size register value */
1107 if (stm32x_info
->user_bank_size
) {
1108 LOG_INFO("ignoring flash probed value, using configured bank size");
1109 flash_size_in_kb
= stm32x_info
->user_bank_size
/ 1024;
1112 LOG_INFO("flash size = %d kbytes", flash_size_in_kb
);
1114 /* did we assign flash size? */
1115 assert(flash_size_in_kb
!= 0xffff);
1117 /* F42x/43x/469/479 1024 kiByte devices have a dual bank option */
1118 if ((device_id
== 0x419) || (device_id
== 0x434)) {
1119 uint32_t optiondata
;
1120 retval
= target_read_u32(target
, STM32_FLASH_OPTCR
, &optiondata
);
1121 if (retval
!= ERROR_OK
) {
1122 LOG_DEBUG("unable to read option bytes");
1125 if ((flash_size_in_kb
> 1024) || (optiondata
& OPTCR_DB1M
)) {
1126 stm32x_info
->has_large_mem
= true;
1127 LOG_INFO("Dual Bank %d kiB STM32F42x/43x/469/479 found", flash_size_in_kb
);
1129 stm32x_info
->has_large_mem
= false;
1130 LOG_INFO("Single Bank %d kiB STM32F42x/43x/469/479 found", flash_size_in_kb
);
1134 /* F76x/77x devices have a dual bank option */
1135 if (device_id
== 0x451) {
1136 uint32_t optiondata
;
1137 retval
= target_read_u32(target
, STM32_FLASH_OPTCR
, &optiondata
);
1138 if (retval
!= ERROR_OK
) {
1139 LOG_DEBUG("unable to read option bytes");
1142 if (optiondata
& OPTCR_NDBANK
) {
1143 stm32x_info
->has_large_mem
= false;
1144 LOG_INFO("Single Bank %d kiB STM32F76x/77x found", flash_size_in_kb
);
1146 stm32x_info
->has_large_mem
= true;
1147 max_sector_size_in_kb
>>= 1; /* sector size divided by 2 in dual-bank mode */
1148 LOG_INFO("Dual Bank %d kiB STM32F76x/77x found", flash_size_in_kb
);
1152 /* calculate numbers of pages */
1153 int num_pages
= flash_size_in_kb
/ max_sector_size_in_kb
1154 + (stm32x_info
->has_large_mem
? 8 : 4);
1156 bank
->base
= base_address
;
1157 bank
->num_sectors
= num_pages
;
1158 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_pages
);
1159 for (i
= 0; i
< num_pages
; i
++) {
1160 bank
->sectors
[i
].is_erased
= -1;
1161 bank
->sectors
[i
].is_protected
= 0;
1164 LOG_DEBUG("allocated %d sectors", num_pages
);
1166 /* F76x/77x in dual bank mode */
1167 if ((device_id
== 0x451) && stm32x_info
->has_large_mem
)
1168 num_prot_blocks
= num_pages
>> 1;
1170 if (num_prot_blocks
) {
1171 bank
->prot_blocks
= malloc(sizeof(struct flash_sector
) * num_prot_blocks
);
1172 for (i
= 0; i
< num_prot_blocks
; i
++)
1173 bank
->prot_blocks
[i
].is_protected
= 0;
1174 LOG_DEBUG("allocated %d prot blocks", num_prot_blocks
);
1177 if (stm32x_info
->has_large_mem
) {
1179 setup_bank(bank
, 0, flash_size_in_kb
>> 1, max_sector_size_in_kb
);
1180 setup_bank(bank
, num_pages
>> 1, flash_size_in_kb
>> 1,
1181 max_sector_size_in_kb
);
1183 /* F767x/F77x in dual mode, one protection bit refers to two adjacent sectors */
1184 if (device_id
== 0x451) {
1185 for (i
= 0; i
< num_prot_blocks
; i
++) {
1186 bank
->prot_blocks
[i
].offset
= bank
->sectors
[i
<< 1].offset
;
1187 bank
->prot_blocks
[i
].size
= bank
->sectors
[i
<< 1].size
1188 + bank
->sectors
[(i
<< 1) + 1].size
;
1193 setup_bank(bank
, 0, flash_size_in_kb
, max_sector_size_in_kb
);
1195 /* F413/F423, sectors 14 and 15 share one common protection bit */
1196 if (device_id
== 0x463) {
1197 for (i
= 0; i
< num_prot_blocks
; i
++) {
1198 bank
->prot_blocks
[i
].offset
= bank
->sectors
[i
].offset
;
1199 bank
->prot_blocks
[i
].size
= bank
->sectors
[i
].size
;
1201 bank
->prot_blocks
[num_prot_blocks
- 1].size
<<= 1;
1204 bank
->num_prot_blocks
= num_prot_blocks
;
1205 assert((bank
->size
>> 10) == flash_size_in_kb
);
1207 stm32x_info
->probed
= true;
1211 static int stm32x_auto_probe(struct flash_bank
*bank
)
1213 struct stm32x_flash_bank
*stm32x_info
= bank
->driver_priv
;
1214 if (stm32x_info
->probed
)
1216 return stm32x_probe(bank
);
1219 static int get_stm32x_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
1221 uint32_t dbgmcu_idcode
;
1223 /* read stm32 device id register */
1224 int retval
= stm32x_get_device_id(bank
, &dbgmcu_idcode
);
1225 if (retval
!= ERROR_OK
)
1228 uint16_t device_id
= dbgmcu_idcode
& 0xfff;
1229 uint16_t rev_id
= dbgmcu_idcode
>> 16;
1230 const char *device_str
;
1231 const char *rev_str
= NULL
;
1233 switch (device_id
) {
1235 device_str
= "STM32F2xx";
1275 device_str
= "STM32F4xx";
1301 device_str
= "STM32F446";
1315 device_str
= "STM32F4xx (Low Power)";
1337 device_str
= "STM32F7[4|5]x";
1351 device_str
= "STM32F7[6|7]x";
1364 device_str
= "STM32F7[2|3]x";
1374 device_str
= "STM32F4[1|2]3";
1384 snprintf(buf
, buf_size
, "Cannot identify target as a STM32F2/4/7\n");
1388 if (rev_str
!= NULL
)
1389 snprintf(buf
, buf_size
, "%s - Rev: %s", device_str
, rev_str
);
1391 snprintf(buf
, buf_size
, "%s - Rev: unknown (0x%04x)", device_str
, rev_id
);
1396 COMMAND_HANDLER(stm32x_handle_lock_command
)
1398 struct target
*target
= NULL
;
1399 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1402 return ERROR_COMMAND_SYNTAX_ERROR
;
1404 struct flash_bank
*bank
;
1405 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1406 if (ERROR_OK
!= retval
)
1409 stm32x_info
= bank
->driver_priv
;
1410 target
= bank
->target
;
1412 if (target
->state
!= TARGET_HALTED
) {
1413 LOG_INFO("Target not halted");
1414 /* return ERROR_TARGET_NOT_HALTED; */
1417 if (stm32x_read_options(bank
) != ERROR_OK
) {
1418 command_print(CMD_CTX
, "%s failed to read options", bank
->driver
->name
);
1422 /* set readout protection */
1423 stm32x_info
->option_bytes
.RDP
= 0;
1425 if (stm32x_write_options(bank
) != ERROR_OK
) {
1426 command_print(CMD_CTX
, "%s failed to lock device", bank
->driver
->name
);
1430 command_print(CMD_CTX
, "%s locked", bank
->driver
->name
);
1435 COMMAND_HANDLER(stm32x_handle_unlock_command
)
1437 struct target
*target
= NULL
;
1438 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1441 return ERROR_COMMAND_SYNTAX_ERROR
;
1443 struct flash_bank
*bank
;
1444 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1445 if (ERROR_OK
!= retval
)
1448 stm32x_info
= bank
->driver_priv
;
1449 target
= bank
->target
;
1451 if (target
->state
!= TARGET_HALTED
) {
1452 LOG_INFO("Target not halted");
1453 /* return ERROR_TARGET_NOT_HALTED; */
1456 if (stm32x_read_options(bank
) != ERROR_OK
) {
1457 command_print(CMD_CTX
, "%s failed to read options", bank
->driver
->name
);
1461 /* clear readout protection and complementary option bytes
1462 * this will also force a device unlock if set */
1463 stm32x_info
->option_bytes
.RDP
= 0xAA;
1464 if (stm32x_info
->has_optcr2_pcrop
) {
1465 stm32x_info
->option_bytes
.optcr2_pcrop
= OPTCR2_PCROP_RDP
| (~1U << bank
->num_sectors
);
1468 if (stm32x_write_options(bank
) != ERROR_OK
) {
1469 command_print(CMD_CTX
, "%s failed to unlock device", bank
->driver
->name
);
1473 command_print(CMD_CTX
, "%s unlocked.\n"
1474 "INFO: a reset or power cycle is required "
1475 "for the new settings to take effect.", bank
->driver
->name
);
1480 static int stm32x_mass_erase(struct flash_bank
*bank
)
1484 struct target
*target
= bank
->target
;
1485 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1487 if (target
->state
!= TARGET_HALTED
) {
1488 LOG_ERROR("Target not halted");
1489 return ERROR_TARGET_NOT_HALTED
;
1492 stm32x_info
= bank
->driver_priv
;
1494 retval
= stm32x_unlock_reg(target
);
1495 if (retval
!= ERROR_OK
)
1498 /* mass erase flash memory */
1499 if (stm32x_info
->has_large_mem
)
1500 flash_mer
= FLASH_MER
| FLASH_MER1
;
1502 flash_mer
= FLASH_MER
;
1504 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), flash_mer
);
1505 if (retval
!= ERROR_OK
)
1507 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
),
1508 flash_mer
| FLASH_STRT
);
1509 if (retval
!= ERROR_OK
)
1512 retval
= stm32x_wait_status_busy(bank
, FLASH_MASS_ERASE_TIMEOUT
);
1513 if (retval
!= ERROR_OK
)
1516 retval
= target_write_u32(target
, stm32x_get_flash_reg(bank
, STM32_FLASH_CR
), FLASH_LOCK
);
1517 if (retval
!= ERROR_OK
)
1523 COMMAND_HANDLER(stm32x_handle_mass_erase_command
)
1528 command_print(CMD_CTX
, "stm32x mass_erase <bank>");
1529 return ERROR_COMMAND_SYNTAX_ERROR
;
1532 struct flash_bank
*bank
;
1533 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1534 if (ERROR_OK
!= retval
)
1537 retval
= stm32x_mass_erase(bank
);
1538 if (retval
== ERROR_OK
) {
1539 /* set all sectors as erased */
1540 for (i
= 0; i
< bank
->num_sectors
; i
++)
1541 bank
->sectors
[i
].is_erased
= 1;
1543 command_print(CMD_CTX
, "stm32x mass erase complete");
1545 command_print(CMD_CTX
, "stm32x mass erase failed");
1551 COMMAND_HANDLER(stm32f2x_handle_options_read_command
)
1554 struct flash_bank
*bank
;
1555 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1557 if (CMD_ARGC
!= 1) {
1558 command_print(CMD_CTX
, "stm32f2x options_read <bank>");
1559 return ERROR_COMMAND_SYNTAX_ERROR
;
1562 retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1563 if (ERROR_OK
!= retval
)
1566 retval
= stm32x_read_options(bank
);
1567 if (ERROR_OK
!= retval
)
1570 stm32x_info
= bank
->driver_priv
;
1571 if (stm32x_info
->has_extra_options
) {
1572 if (stm32x_info
->has_boot_addr
) {
1573 uint32_t boot_addr
= stm32x_info
->option_bytes
.boot_addr
;
1575 command_print(CMD_CTX
, "stm32f2x user_options 0x%03X,"
1576 " boot_add0 0x%04X, boot_add1 0x%04X",
1577 stm32x_info
->option_bytes
.user_options
,
1578 boot_addr
& 0xffff, (boot_addr
& 0xffff0000) >> 16);
1579 if (stm32x_info
->has_optcr2_pcrop
) {
1580 command_print(CMD_CTX
, "stm32f2x optcr2_pcrop 0x%08X",
1581 stm32x_info
->option_bytes
.optcr2_pcrop
);
1584 command_print(CMD_CTX
, "stm32f2x user_options 0x%03X",
1585 stm32x_info
->option_bytes
.user_options
);
1588 command_print(CMD_CTX
, "stm32f2x user_options 0x%02X",
1589 stm32x_info
->option_bytes
.user_options
);
1596 COMMAND_HANDLER(stm32f2x_handle_options_write_command
)
1599 struct flash_bank
*bank
;
1600 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1601 uint16_t user_options
, boot_addr0
, boot_addr1
, options_mask
;
1604 command_print(CMD_CTX
, "stm32f2x options_write <bank> ...");
1605 return ERROR_COMMAND_SYNTAX_ERROR
;
1608 retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1609 if (ERROR_OK
!= retval
)
1612 retval
= stm32x_read_options(bank
);
1613 if (ERROR_OK
!= retval
)
1616 stm32x_info
= bank
->driver_priv
;
1617 if (stm32x_info
->has_boot_addr
) {
1618 if (CMD_ARGC
!= 4) {
1619 command_print(CMD_CTX
, "stm32f2x options_write <bank> <user_options>"
1620 " <boot_addr0> <boot_addr1>");
1621 return ERROR_COMMAND_SYNTAX_ERROR
;
1623 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[2], boot_addr0
);
1624 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[3], boot_addr1
);
1625 stm32x_info
->option_bytes
.boot_addr
= boot_addr0
| (((uint32_t) boot_addr1
) << 16);
1627 if (CMD_ARGC
!= 2) {
1628 command_print(CMD_CTX
, "stm32f2x options_write <bank> <user_options>");
1629 return ERROR_COMMAND_SYNTAX_ERROR
;
1633 COMMAND_PARSE_NUMBER(u16
, CMD_ARGV
[1], user_options
);
1634 options_mask
= !stm32x_info
->has_extra_options
? ~0xfc :
1635 ~(((0xf00 << (stm32x_info
->protection_bits
- 12)) | 0xff) & 0xffc);
1636 if (user_options
& options_mask
) {
1637 command_print(CMD_CTX
, "stm32f2x invalid user_options");
1638 return ERROR_COMMAND_ARGUMENT_INVALID
;
1641 stm32x_info
->option_bytes
.user_options
= user_options
;
1643 if (stm32x_write_options(bank
) != ERROR_OK
) {
1644 command_print(CMD_CTX
, "stm32f2x failed to write options");
1648 /* switching between single- and dual-bank modes requires re-probe */
1649 /* ... and reprogramming of whole flash */
1650 stm32x_info
->probed
= false;
1652 command_print(CMD_CTX
, "stm32f2x write options complete.\n"
1653 "INFO: a reset or power cycle is required "
1654 "for the new settings to take effect.");
1658 COMMAND_HANDLER(stm32f2x_handle_optcr2_write_command
)
1661 struct flash_bank
*bank
;
1662 struct stm32x_flash_bank
*stm32x_info
= NULL
;
1663 uint32_t optcr2_pcrop
;
1665 if (CMD_ARGC
!= 2) {
1666 command_print(CMD_CTX
, "stm32f2x optcr2_write <bank> <optcr2_value>");
1667 return ERROR_COMMAND_SYNTAX_ERROR
;
1670 retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1671 if (ERROR_OK
!= retval
)
1674 stm32x_info
= bank
->driver_priv
;
1675 if (!stm32x_info
->has_optcr2_pcrop
) {
1676 command_print(CMD_CTX
, "no optcr2 register");
1677 return ERROR_COMMAND_ARGUMENT_INVALID
;
1680 command_print(CMD_CTX
, "INFO: To disable PCROP, set PCROP_RDP"
1681 " with PCROPi bits STILL SET, then\nlock device and"
1682 " finally unlock it. Clears PCROP and mass erases flash.");
1684 retval
= stm32x_read_options(bank
);
1685 if (ERROR_OK
!= retval
)
1688 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], optcr2_pcrop
);
1689 stm32x_info
->option_bytes
.optcr2_pcrop
= optcr2_pcrop
;
1691 if (stm32x_write_options(bank
) != ERROR_OK
) {
1692 command_print(CMD_CTX
, "stm32f2x failed to write options");
1696 command_print(CMD_CTX
, "stm32f2x optcr2_write complete.");
1700 COMMAND_HANDLER(stm32x_handle_otp_command
)
1703 command_print(CMD_CTX
, "stm32x otp <bank> (enable|disable|show)");
1704 return ERROR_COMMAND_SYNTAX_ERROR
;
1707 struct flash_bank
*bank
;
1708 int retval
= CALL_COMMAND_HANDLER(flash_command_get_bank
, 0, &bank
);
1709 if (ERROR_OK
!= retval
)
1711 if (stm32x_is_otp(bank
)) {
1712 if (strcmp(CMD_ARGV
[1], "enable") == 0) {
1713 stm32x_otp_enable(bank
);
1714 } else if (strcmp(CMD_ARGV
[1], "disable") == 0) {
1715 stm32x_otp_disable(bank
);
1716 } else if (strcmp(CMD_ARGV
[1], "show") == 0) {
1717 command_print(CMD_CTX
,
1718 "OTP memory bank #%d is %s for write commands.",
1720 stm32x_is_otp_unlocked(bank
) ? "enabled" : "disabled");
1722 return ERROR_COMMAND_SYNTAX_ERROR
;
1725 command_print(CMD_CTX
, "Failed: not an OTP bank.");
1731 static const struct command_registration stm32x_exec_command_handlers
[] = {
1734 .handler
= stm32x_handle_lock_command
,
1735 .mode
= COMMAND_EXEC
,
1737 .help
= "Lock entire flash device.",
1741 .handler
= stm32x_handle_unlock_command
,
1742 .mode
= COMMAND_EXEC
,
1744 .help
= "Unlock entire protected flash device.",
1747 .name
= "mass_erase",
1748 .handler
= stm32x_handle_mass_erase_command
,
1749 .mode
= COMMAND_EXEC
,
1751 .help
= "Erase entire flash device.",
1754 .name
= "options_read",
1755 .handler
= stm32f2x_handle_options_read_command
,
1756 .mode
= COMMAND_EXEC
,
1758 .help
= "Read and display device option bytes.",
1761 .name
= "options_write",
1762 .handler
= stm32f2x_handle_options_write_command
,
1763 .mode
= COMMAND_EXEC
,
1764 .usage
= "bank_id user_options [ boot_add0 boot_add1 ]",
1765 .help
= "Write option bytes",
1768 .name
= "optcr2_write",
1769 .handler
= stm32f2x_handle_optcr2_write_command
,
1770 .mode
= COMMAND_EXEC
,
1771 .usage
= "bank_id optcr2",
1772 .help
= "Write optcr2 word",
1776 .handler
= stm32x_handle_otp_command
,
1777 .mode
= COMMAND_EXEC
,
1779 .help
= "OTP (One Time Programmable) memory write enable/disable.",
1781 COMMAND_REGISTRATION_DONE
1784 static const struct command_registration stm32x_command_handlers
[] = {
1787 .mode
= COMMAND_ANY
,
1788 .help
= "stm32f2x flash command group",
1790 .chain
= stm32x_exec_command_handlers
,
1792 COMMAND_REGISTRATION_DONE
1795 const struct flash_driver stm32f2x_flash
= {
1797 .commands
= stm32x_command_handlers
,
1798 .flash_bank_command
= stm32x_flash_bank_command
,
1799 .erase
= stm32x_erase
,
1800 .protect
= stm32x_protect
,
1801 .write
= stm32x_write
,
1802 .read
= default_flash_read
,
1803 .probe
= stm32x_probe
,
1804 .auto_probe
= stm32x_auto_probe
,
1805 .erase_check
= default_flash_blank_check
,
1806 .protect_check
= stm32x_protect_check
,
1807 .info
= get_stm32x_info
,
1808 .free_driver_priv
= default_flash_free_driver_priv
,
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