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[openocd.git] / src / flash / nor / stm32f2x.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2011 Øyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
15 * *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
20 * *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
24
25 #ifdef HAVE_CONFIG_H
26 #include "config.h"
27 #endif
28
29 #include "imp.h"
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
33
34 /* Regarding performance:
35 *
36 * Short story - it might be best to leave the performance at
37 * current levels.
38 *
39 * You may see a jump in speed if you change to using
40 * 32bit words for the block programming.
41 *
42 * Its a shame you cannot use the double word as its
43 * even faster - but you require external VPP for that mode.
44 *
45 * Having said all that 16bit writes give us the widest vdd
46 * operating range, so may be worth adding a note to that effect.
47 *
48 */
49
50 /* Danger!!!! The STM32F1x and STM32F2x series actually have
51 * quite different flash controllers.
52 *
53 * What's more scary is that the names of the registers and their
54 * addresses are the same, but the actual bits and what they do are
55 * can be very different.
56 *
57 * To reduce testing complexity and dangers of regressions,
58 * a seperate file is used for stm32fx2x.
59 *
60 * Sector sizes in kiBytes:
61 * 1 MiByte part with 4 x 16, 1 x 64, 7 x 128.
62 * 1.5 MiByte part with 4 x 16, 1 x 64, 11 x 128.
63 * 2 MiByte part with 4 x 16, 1 x 64, 7 x 128, 4 x 16, 1 x 64, 7 x 128.
64 * 1 MiByte STM32F42x/43x part with DB1M Option set:
65 * 4 x 16, 1 x 64, 3 x 128, 4 x 16, 1 x 64, 3 x 128.
66 *
67 * STM32F7[2|3]
68 * 512 kiByte part with 4 x 16, 1 x 64, 3 x 128.
69 *
70 * STM32F7[4|5]
71 * 1 MiByte part with 4 x 32, 1 x 128, 3 x 256.
72 *
73 * STM32F7[6|7]
74 * 1 MiByte part in single bank mode with 4 x 32, 1 x 128, 3 x 256.
75 * 1 MiByte part in dual-bank mode two banks with 4 x 16, 1 x 64, 3 x 128 each.
76 * 2 MiByte part in single-bank mode with 4 x 32, 1 x 128, 7 x 256.
77 * 2 MiByte part in dual-bank mode two banks with 4 x 16, 1 x 64, 7 x 128 each.
78 *
79 * Protection size is sector size.
80 *
81 * Tested with STM3220F-EVAL board.
82 *
83 * STM32F4xx series for reference.
84 *
85 * RM0090
86 * http://www.st.com/web/en/resource/technical/document/reference_manual/DM00031020.pdf
87 *
88 * PM0059
89 * www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/
90 * PROGRAMMING_MANUAL/CD00233952.pdf
91 *
92 * STM32F7xx series for reference.
93 *
94 * RM0385
95 * http://www.st.com/web/en/resource/technical/document/reference_manual/DM00124865.pdf
96 *
97 * RM0410
98 * http://www.st.com/resource/en/reference_manual/dm00224583.pdf
99 *
100 * RM0430
101 * http://www.st.com/resource/en/reference_manual/dm00305666.pdf
102 *
103 * RM0431
104 * http://www.st.com/resource/en/reference_manual/dm00305990.pdf
105 *
106 * STM32F1x series - notice that this code was copy, pasted and knocked
107 * into a stm32f2x driver, so in case something has been converted or
108 * bugs haven't been fixed, here are the original manuals:
109 *
110 * RM0008 - Reference manual
111 *
112 * RM0042, the Flash programming manual for low-, medium- high-density and
113 * connectivity line STM32F10x devices
114 *
115 * PM0068, the Flash programming manual for XL-density STM32F10x devices.
116 *
117 */
118
119 /* Erase time can be as high as 1000ms, 10x this and it's toast... */
120 #define FLASH_ERASE_TIMEOUT 10000
121 #define FLASH_WRITE_TIMEOUT 5
122
123 /* Mass erase time can be as high as 32 s in x8 mode. */
124 #define FLASH_MASS_ERASE_TIMEOUT 33000
125
126 #define STM32_FLASH_BASE 0x40023c00
127 #define STM32_FLASH_ACR 0x40023c00
128 #define STM32_FLASH_KEYR 0x40023c04
129 #define STM32_FLASH_OPTKEYR 0x40023c08
130 #define STM32_FLASH_SR 0x40023c0C
131 #define STM32_FLASH_CR 0x40023c10
132 #define STM32_FLASH_OPTCR 0x40023c14
133 #define STM32_FLASH_OPTCR1 0x40023c18
134 #define STM32_FLASH_OPTCR2 0x40023c1c
135
136 /* FLASH_CR register bits */
137 #define FLASH_PG (1 << 0)
138 #define FLASH_SER (1 << 1)
139 #define FLASH_MER (1 << 2) /* MER/MER1 for f76x/77x */
140 #define FLASH_MER1 (1 << 15) /* MER2 for f76x/77x, confusing ... */
141 #define FLASH_STRT (1 << 16)
142 #define FLASH_PSIZE_8 (0 << 8)
143 #define FLASH_PSIZE_16 (1 << 8)
144 #define FLASH_PSIZE_32 (2 << 8)
145 #define FLASH_PSIZE_64 (3 << 8)
146 /* The sector number encoding is not straight binary for dual bank flash. */
147 #define FLASH_SNB(a) ((a) << 3)
148 #define FLASH_LOCK (1 << 31)
149
150 /* FLASH_SR register bits */
151 #define FLASH_BSY (1 << 16)
152 #define FLASH_PGSERR (1 << 7) /* Programming sequence error */
153 #define FLASH_PGPERR (1 << 6) /* Programming parallelism error */
154 #define FLASH_PGAERR (1 << 5) /* Programming alignment error */
155 #define FLASH_WRPERR (1 << 4) /* Write protection error */
156 #define FLASH_OPERR (1 << 1) /* Operation error */
157
158 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGPERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
159
160 /* STM32_FLASH_OPTCR register bits */
161 #define OPTCR_LOCK (1 << 0)
162 #define OPTCR_START (1 << 1)
163 #define OPTCR_NDBANK (1 << 29) /* not dual bank mode */
164 #define OPTCR_DB1M (1 << 30) /* 1 MiB devices dual flash bank option */
165 #define OPTCR_SPRMOD (1 << 31) /* switches PCROPi/nWPRi interpretation */
166
167 /* STM32_FLASH_OPTCR2 register bits */
168 #define OPTCR2_PCROP_RDP (1 << 31) /* erase PCROP zone when decreasing RDP */
169
170 /* register unlock keys */
171 #define KEY1 0x45670123
172 #define KEY2 0xCDEF89AB
173
174 /* option register unlock key */
175 #define OPTKEY1 0x08192A3B
176 #define OPTKEY2 0x4C5D6E7F
177
178 struct stm32x_options {
179 uint8_t RDP;
180 uint16_t user_options; /* bit 0-7 usual options, bit 8-11 extra options */
181 uint32_t protection;
182 uint32_t boot_addr;
183 uint32_t optcr2_pcrop;
184 };
185
186 struct stm32x_flash_bank {
187 struct stm32x_options option_bytes;
188 int probed;
189 bool has_large_mem; /* F42x/43x/469/479/7xx in dual bank mode */
190 bool has_extra_options; /* F42x/43x/469/479/7xx */
191 bool has_boot_addr; /* F7xx */
192 bool has_optcr2_pcrop; /* F72x/73x */
193 int protection_bits; /* F413/423 */
194 uint32_t user_bank_size;
195 };
196
197 /* flash bank stm32x <base> <size> 0 0 <target#>
198 */
199 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
200 {
201 struct stm32x_flash_bank *stm32x_info;
202
203 if (CMD_ARGC < 6)
204 return ERROR_COMMAND_SYNTAX_ERROR;
205
206 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
207 bank->driver_priv = stm32x_info;
208
209 stm32x_info->probed = 0;
210 stm32x_info->user_bank_size = bank->size;
211
212 return ERROR_OK;
213 }
214
215 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
216 {
217 return reg;
218 }
219
220 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
221 {
222 struct target *target = bank->target;
223 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
224 }
225
226 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
227 {
228 struct target *target = bank->target;
229 uint32_t status;
230 int retval = ERROR_OK;
231
232 /* wait for busy to clear */
233 for (;;) {
234 retval = stm32x_get_flash_status(bank, &status);
235 if (retval != ERROR_OK)
236 return retval;
237 LOG_DEBUG("status: 0x%" PRIx32 "", status);
238 if ((status & FLASH_BSY) == 0)
239 break;
240 if (timeout-- <= 0) {
241 LOG_ERROR("timed out waiting for flash");
242 return ERROR_FAIL;
243 }
244 alive_sleep(1);
245 }
246
247
248 if (status & FLASH_WRPERR) {
249 LOG_ERROR("stm32x device protected");
250 retval = ERROR_FAIL;
251 }
252
253 /* Clear but report errors */
254 if (status & FLASH_ERROR) {
255 if (retval == ERROR_OK)
256 retval = ERROR_FAIL;
257 /* If this operation fails, we ignore it and report the original
258 * retval
259 */
260 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
261 status & FLASH_ERROR);
262 }
263 return retval;
264 }
265
266 static int stm32x_unlock_reg(struct target *target)
267 {
268 uint32_t ctrl;
269
270 /* first check if not already unlocked
271 * otherwise writing on STM32_FLASH_KEYR will fail
272 */
273 int retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
274 if (retval != ERROR_OK)
275 return retval;
276
277 if ((ctrl & FLASH_LOCK) == 0)
278 return ERROR_OK;
279
280 /* unlock flash registers */
281 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
282 if (retval != ERROR_OK)
283 return retval;
284
285 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
286 if (retval != ERROR_OK)
287 return retval;
288
289 retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
290 if (retval != ERROR_OK)
291 return retval;
292
293 if (ctrl & FLASH_LOCK) {
294 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
295 return ERROR_TARGET_FAILURE;
296 }
297
298 return ERROR_OK;
299 }
300
301 static int stm32x_unlock_option_reg(struct target *target)
302 {
303 uint32_t ctrl;
304
305 int retval = target_read_u32(target, STM32_FLASH_OPTCR, &ctrl);
306 if (retval != ERROR_OK)
307 return retval;
308
309 if ((ctrl & OPTCR_LOCK) == 0)
310 return ERROR_OK;
311
312 /* unlock option registers */
313 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY1);
314 if (retval != ERROR_OK)
315 return retval;
316
317 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY2);
318 if (retval != ERROR_OK)
319 return retval;
320
321 retval = target_read_u32(target, STM32_FLASH_OPTCR, &ctrl);
322 if (retval != ERROR_OK)
323 return retval;
324
325 if (ctrl & OPTCR_LOCK) {
326 LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %" PRIx32, ctrl);
327 return ERROR_TARGET_FAILURE;
328 }
329
330 return ERROR_OK;
331 }
332
333 static int stm32x_read_options(struct flash_bank *bank)
334 {
335 uint32_t optiondata;
336 struct stm32x_flash_bank *stm32x_info = NULL;
337 struct target *target = bank->target;
338
339 stm32x_info = bank->driver_priv;
340
341 /* read current option bytes */
342 int retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
343 if (retval != ERROR_OK)
344 return retval;
345
346 /* caution: F2 implements 5 bits (WDG_SW only)
347 * whereas F7 6 bits (IWDG_SW and WWDG_SW) in user_options */
348 stm32x_info->option_bytes.user_options = optiondata & 0xfc;
349 stm32x_info->option_bytes.RDP = (optiondata >> 8) & 0xff;
350 stm32x_info->option_bytes.protection =
351 (optiondata >> 16) & (~(0xffff << stm32x_info->protection_bits) & 0xffff);
352
353 if (stm32x_info->has_extra_options) {
354 /* F42x/43x/469/479 and 7xx have up to 4 bits of extra options */
355 stm32x_info->option_bytes.user_options |= (optiondata >> 20) &
356 ((0xf00 << (stm32x_info->protection_bits - 12)) & 0xf00);
357 }
358
359 if (stm32x_info->has_large_mem || stm32x_info->has_boot_addr) {
360 retval = target_read_u32(target, STM32_FLASH_OPTCR1, &optiondata);
361 if (retval != ERROR_OK)
362 return retval;
363
364 /* FLASH_OPTCR1 has quite diffent meanings ... */
365 if (stm32x_info->has_boot_addr) {
366 /* for F7xx it contains boot0 and boot1 */
367 stm32x_info->option_bytes.boot_addr = optiondata;
368 } else {
369 /* for F42x/43x/469/479 it contains 12 additional protection bits */
370 stm32x_info->option_bytes.protection |= (optiondata >> 4) & 0x00fff000;
371 }
372 }
373
374 if (stm32x_info->has_optcr2_pcrop) {
375 retval = target_read_u32(target, STM32_FLASH_OPTCR2, &optiondata);
376 if (retval != ERROR_OK)
377 return retval;
378
379 stm32x_info->option_bytes.optcr2_pcrop = optiondata;
380 if (stm32x_info->has_optcr2_pcrop &&
381 (stm32x_info->option_bytes.optcr2_pcrop & ~OPTCR2_PCROP_RDP)) {
382 LOG_INFO("PCROP Engaged");
383 }
384 } else {
385 stm32x_info->option_bytes.optcr2_pcrop = 0x0;
386 }
387
388 if (stm32x_info->option_bytes.RDP != 0xAA)
389 LOG_INFO("Device Security Bit Set");
390
391 return ERROR_OK;
392 }
393
394 static int stm32x_write_options(struct flash_bank *bank)
395 {
396 struct stm32x_flash_bank *stm32x_info = NULL;
397 struct target *target = bank->target;
398 uint32_t optiondata, optiondata2;
399
400 stm32x_info = bank->driver_priv;
401
402 int retval = stm32x_unlock_option_reg(target);
403 if (retval != ERROR_OK)
404 return retval;
405
406 /* rebuild option data */
407 optiondata = stm32x_info->option_bytes.user_options & 0xfc;
408 optiondata |= stm32x_info->option_bytes.RDP << 8;
409 optiondata |= (stm32x_info->option_bytes.protection &
410 (~(0xffff << stm32x_info->protection_bits))) << 16;
411
412 if (stm32x_info->has_extra_options) {
413 /* F42x/43x/469/479 and 7xx have up to 4 bits of extra options */
414 optiondata |= (stm32x_info->option_bytes.user_options &
415 ((0xf00 << (stm32x_info->protection_bits - 12)) & 0xf00)) << 20;
416 }
417
418 if (stm32x_info->has_large_mem || stm32x_info->has_boot_addr) {
419 if (stm32x_info->has_boot_addr) {
420 /* F7xx uses FLASH_OPTCR1 for boot0 and boot1 ... */
421 optiondata2 = stm32x_info->option_bytes.boot_addr;
422 } else {
423 /* F42x/43x/469/479 uses FLASH_OPTCR1 for additional protection bits */
424 optiondata2 = (stm32x_info->option_bytes.protection & 0x00fff000) << 4;
425 }
426
427 retval = target_write_u32(target, STM32_FLASH_OPTCR1, optiondata2);
428 if (retval != ERROR_OK)
429 return retval;
430 }
431
432 /* program extra pcrop register */
433 if (stm32x_info->has_optcr2_pcrop) {
434 retval = target_write_u32(target, STM32_FLASH_OPTCR2,
435 stm32x_info->option_bytes.optcr2_pcrop);
436 if (retval != ERROR_OK)
437 return retval;
438 }
439
440 /* program options */
441 retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata);
442 if (retval != ERROR_OK)
443 return retval;
444
445 /* start programming cycle */
446 retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata | OPTCR_START);
447 if (retval != ERROR_OK)
448 return retval;
449
450 /* wait for completion, this might trigger a security erase and take a while */
451 retval = stm32x_wait_status_busy(bank, FLASH_MASS_ERASE_TIMEOUT);
452 if (retval != ERROR_OK)
453 return retval;
454
455 /* relock registers */
456 retval = target_write_u32(target, STM32_FLASH_OPTCR, optiondata | OPTCR_LOCK);
457 if (retval != ERROR_OK)
458 return retval;
459
460 return ERROR_OK;
461 }
462
463 static int stm32x_protect_check(struct flash_bank *bank)
464 {
465 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
466 struct flash_sector *prot_blocks;
467 int num_prot_blocks;
468
469 /* read write protection settings */
470 int retval = stm32x_read_options(bank);
471 if (retval != ERROR_OK) {
472 LOG_DEBUG("unable to read option bytes");
473 return retval;
474 }
475
476 if (bank->prot_blocks) {
477 num_prot_blocks = bank->num_prot_blocks;
478 prot_blocks = bank->prot_blocks;
479 } else {
480 num_prot_blocks = bank->num_sectors;
481 prot_blocks = bank->sectors;
482 }
483
484 for (int i = 0; i < num_prot_blocks; i++)
485 prot_blocks[i].is_protected =
486 ~(stm32x_info->option_bytes.protection >> i) & 1;
487
488 return ERROR_OK;
489 }
490
491 static int stm32x_erase(struct flash_bank *bank, int first, int last)
492 {
493 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
494 struct target *target = bank->target;
495 int i;
496
497 assert((0 <= first) && (first <= last) && (last < bank->num_sectors));
498
499 if (bank->target->state != TARGET_HALTED) {
500 LOG_ERROR("Target not halted");
501 return ERROR_TARGET_NOT_HALTED;
502 }
503
504 int retval;
505 retval = stm32x_unlock_reg(target);
506 if (retval != ERROR_OK)
507 return retval;
508
509 /*
510 Sector Erase
511 To erase a sector, follow the procedure below:
512 1. Check that no Flash memory operation is ongoing by checking the BSY bit in the
513 FLASH_SR register
514 2. Set the SER bit and select the sector
515 you wish to erase (SNB) in the FLASH_CR register
516 3. Set the STRT bit in the FLASH_CR register
517 4. Wait for the BSY bit to be cleared
518 */
519
520 for (i = first; i <= last; i++) {
521 int snb;
522 if (stm32x_info->has_large_mem && i >= 12)
523 snb = (i - 12) | 0x10;
524 else
525 snb = i;
526
527 retval = target_write_u32(target,
528 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_SER | FLASH_SNB(snb) | FLASH_STRT);
529 if (retval != ERROR_OK)
530 return retval;
531
532 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
533 if (retval != ERROR_OK)
534 return retval;
535
536 bank->sectors[i].is_erased = 1;
537 }
538
539 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
540 if (retval != ERROR_OK)
541 return retval;
542
543 return ERROR_OK;
544 }
545
546 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
547 {
548 struct target *target = bank->target;
549 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
550
551 if (target->state != TARGET_HALTED) {
552 LOG_ERROR("Target not halted");
553 return ERROR_TARGET_NOT_HALTED;
554 }
555
556 /* read protection settings */
557 int retval = stm32x_read_options(bank);
558 if (retval != ERROR_OK) {
559 LOG_DEBUG("unable to read option bytes");
560 return retval;
561 }
562
563 for (int i = first; i <= last; i++) {
564 if (set)
565 stm32x_info->option_bytes.protection &= ~(1 << i);
566 else
567 stm32x_info->option_bytes.protection |= (1 << i);
568 }
569
570 retval = stm32x_write_options(bank);
571 if (retval != ERROR_OK)
572 return retval;
573
574 return ERROR_OK;
575 }
576
577 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
578 uint32_t offset, uint32_t count)
579 {
580 struct target *target = bank->target;
581 uint32_t buffer_size = 16384;
582 struct working_area *write_algorithm;
583 struct working_area *source;
584 uint32_t address = bank->base + offset;
585 struct reg_param reg_params[5];
586 struct armv7m_algorithm armv7m_info;
587 int retval = ERROR_OK;
588
589 static const uint8_t stm32x_flash_write_code[] = {
590 #include "../../../contrib/loaders/flash/stm32/stm32f2x.inc"
591 };
592
593 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
594 &write_algorithm) != ERROR_OK) {
595 LOG_WARNING("no working area available, can't do block memory writes");
596 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
597 }
598
599 retval = target_write_buffer(target, write_algorithm->address,
600 sizeof(stm32x_flash_write_code),
601 stm32x_flash_write_code);
602 if (retval != ERROR_OK)
603 return retval;
604
605 /* memory buffer */
606 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
607 buffer_size /= 2;
608 if (buffer_size <= 256) {
609 /* we already allocated the writing code, but failed to get a
610 * buffer, free the algorithm */
611 target_free_working_area(target, write_algorithm);
612
613 LOG_WARNING("no large enough working area available, can't do block memory writes");
614 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
615 }
616 }
617
618 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
619 armv7m_info.core_mode = ARM_MODE_THREAD;
620
621 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
622 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT); /* buffer end */
623 init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT); /* target address */
624 init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT); /* count (halfword-16bit) */
625 init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT); /* flash base */
626
627 buf_set_u32(reg_params[0].value, 0, 32, source->address);
628 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
629 buf_set_u32(reg_params[2].value, 0, 32, address);
630 buf_set_u32(reg_params[3].value, 0, 32, count);
631 buf_set_u32(reg_params[4].value, 0, 32, STM32_FLASH_BASE);
632
633 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
634 0, NULL,
635 5, reg_params,
636 source->address, source->size,
637 write_algorithm->address, 0,
638 &armv7m_info);
639
640 if (retval == ERROR_FLASH_OPERATION_FAILED) {
641 LOG_ERROR("error executing stm32x flash write algorithm");
642
643 uint32_t error = buf_get_u32(reg_params[0].value, 0, 32) & FLASH_ERROR;
644
645 if (error & FLASH_WRPERR)
646 LOG_ERROR("flash memory write protected");
647
648 if (error != 0) {
649 LOG_ERROR("flash write failed = %08" PRIx32, error);
650 /* Clear but report errors */
651 target_write_u32(target, STM32_FLASH_SR, error);
652 retval = ERROR_FAIL;
653 }
654 }
655
656 target_free_working_area(target, source);
657 target_free_working_area(target, write_algorithm);
658
659 destroy_reg_param(&reg_params[0]);
660 destroy_reg_param(&reg_params[1]);
661 destroy_reg_param(&reg_params[2]);
662 destroy_reg_param(&reg_params[3]);
663 destroy_reg_param(&reg_params[4]);
664
665 return retval;
666 }
667
668 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
669 uint32_t offset, uint32_t count)
670 {
671 struct target *target = bank->target;
672 uint32_t words_remaining = (count / 2);
673 uint32_t bytes_remaining = (count & 0x00000001);
674 uint32_t address = bank->base + offset;
675 uint32_t bytes_written = 0;
676 int retval;
677
678 if (bank->target->state != TARGET_HALTED) {
679 LOG_ERROR("Target not halted");
680 return ERROR_TARGET_NOT_HALTED;
681 }
682
683 if (offset & 0x1) {
684 LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
685 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
686 }
687
688 retval = stm32x_unlock_reg(target);
689 if (retval != ERROR_OK)
690 return retval;
691
692 /* multiple half words (2-byte) to be programmed? */
693 if (words_remaining > 0) {
694 /* try using a block write */
695 retval = stm32x_write_block(bank, buffer, offset, words_remaining);
696 if (retval != ERROR_OK) {
697 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
698 /* if block write failed (no sufficient working area),
699 * we use normal (slow) single dword accesses */
700 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
701 }
702 } else {
703 buffer += words_remaining * 2;
704 address += words_remaining * 2;
705 words_remaining = 0;
706 }
707 }
708
709 if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
710 return retval;
711
712 /*
713 Standard programming
714 The Flash memory programming sequence is as follows:
715 1. Check that no main Flash memory operation is ongoing by checking the BSY bit in the
716 FLASH_SR register.
717 2. Set the PG bit in the FLASH_CR register
718 3. Perform the data write operation(s) to the desired memory address (inside main
719 memory block or OTP area):
720 – – Half-word access in case of x16 parallelism
721 – Word access in case of x32 parallelism
722 –
723 4.
724 Byte access in case of x8 parallelism
725 Double word access in case of x64 parallelism
726 Wait for the BSY bit to be cleared
727 */
728 while (words_remaining > 0) {
729 uint16_t value;
730 memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
731
732 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
733 FLASH_PG | FLASH_PSIZE_16);
734 if (retval != ERROR_OK)
735 return retval;
736
737 retval = target_write_u16(target, address, value);
738 if (retval != ERROR_OK)
739 return retval;
740
741 retval = stm32x_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
742 if (retval != ERROR_OK)
743 return retval;
744
745 bytes_written += 2;
746 words_remaining--;
747 address += 2;
748 }
749
750 if (bytes_remaining) {
751 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
752 FLASH_PG | FLASH_PSIZE_8);
753 if (retval != ERROR_OK)
754 return retval;
755 retval = target_write_u8(target, address, buffer[bytes_written]);
756 if (retval != ERROR_OK)
757 return retval;
758
759 retval = stm32x_wait_status_busy(bank, FLASH_WRITE_TIMEOUT);
760 if (retval != ERROR_OK)
761 return retval;
762 }
763
764 return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
765 }
766
767 static int setup_sector(struct flash_bank *bank, int start, int num, int size)
768 {
769
770 for (int i = start; i < (start + num) ; i++) {
771 assert(i < bank->num_sectors);
772 bank->sectors[i].offset = bank->size;
773 bank->sectors[i].size = size;
774 bank->size += bank->sectors[i].size;
775 LOG_DEBUG("sector %d: %dkBytes", i, size >> 10);
776 }
777
778 return start + num;
779 }
780
781 static void setup_bank(struct flash_bank *bank, int start,
782 uint16_t flash_size_in_kb, uint16_t max_sector_size_in_kb)
783 {
784 int remain;
785
786 start = setup_sector(bank, start, 4, (max_sector_size_in_kb / 8) * 1024);
787 start = setup_sector(bank, start, 1, (max_sector_size_in_kb / 2) * 1024);
788
789 /* remaining sectors all of size max_sector_size_in_kb */
790 remain = (flash_size_in_kb / max_sector_size_in_kb) - 1;
791 start = setup_sector(bank, start, remain, max_sector_size_in_kb * 1024);
792 }
793
794 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
795 {
796 /* this checks for a stm32f4x errata issue where a
797 * stm32f2x DBGMCU_IDCODE is incorrectly returned.
798 * If the issue is detected target is forced to stm32f4x Rev A.
799 * Only effects Rev A silicon */
800
801 struct target *target = bank->target;
802 uint32_t cpuid;
803
804 /* read stm32 device id register */
805 int retval = target_read_u32(target, 0xE0042000, device_id);
806 if (retval != ERROR_OK)
807 return retval;
808
809 if ((*device_id & 0xfff) == 0x411) {
810 /* read CPUID reg to check core type */
811 retval = target_read_u32(target, 0xE000ED00, &cpuid);
812 if (retval != ERROR_OK)
813 return retval;
814
815 /* check for cortex_m4 */
816 if (((cpuid >> 4) & 0xFFF) == 0xC24) {
817 *device_id &= ~((0xFFFF << 16) | 0xfff);
818 *device_id |= (0x1000 << 16) | 0x413;
819 LOG_INFO("stm32f4x errata detected - fixing incorrect MCU_IDCODE");
820 }
821 }
822 return retval;
823 }
824
825 static int stm32x_probe(struct flash_bank *bank)
826 {
827 struct target *target = bank->target;
828 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
829 int i, num_prot_blocks;
830 uint16_t flash_size_in_kb;
831 uint32_t flash_size_reg = 0x1FFF7A22;
832 uint16_t max_sector_size_in_kb = 128;
833 uint16_t max_flash_size_in_kb;
834 uint32_t device_id;
835 uint32_t base_address = 0x08000000;
836
837 stm32x_info->probed = 0;
838 stm32x_info->has_large_mem = false;
839 stm32x_info->has_boot_addr = false;
840 stm32x_info->has_extra_options = false;
841 stm32x_info->has_optcr2_pcrop = false;
842 stm32x_info->protection_bits = 12; /* max. number of nWRPi bits (in FLASH_OPTCR !!!) */
843 num_prot_blocks = 0;
844
845 if (bank->sectors) {
846 free(bank->sectors);
847 bank->num_sectors = 0;
848 bank->sectors = NULL;
849 }
850
851 if (bank->prot_blocks) {
852 free(bank->prot_blocks);
853 bank->num_prot_blocks = 0;
854 bank->prot_blocks = NULL;
855 }
856
857 /* read stm32 device id register */
858 int retval = stm32x_get_device_id(bank, &device_id);
859 if (retval != ERROR_OK)
860 return retval;
861 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
862 device_id &= 0xfff; /* only bits 0-11 are used further on */
863
864 /* set max flash size depending on family, id taken from AN2606 */
865 switch (device_id) {
866 case 0x411: /* F20x/21x */
867 case 0x413: /* F40x/41x */
868 max_flash_size_in_kb = 1024;
869 break;
870
871 case 0x419: /* F42x/43x */
872 case 0x434: /* F469/479 */
873 stm32x_info->has_extra_options = true;
874 max_flash_size_in_kb = 2048;
875 break;
876
877 case 0x423: /* F401xB/C */
878 max_flash_size_in_kb = 256;
879 break;
880
881 case 0x421: /* F446 */
882 case 0x431: /* F411 */
883 case 0x433: /* F401xD/E */
884 case 0x441: /* F412 */
885 max_flash_size_in_kb = 512;
886 break;
887
888 case 0x458: /* F410 */
889 max_flash_size_in_kb = 128;
890 break;
891
892 case 0x449: /* F74x/75x */
893 max_flash_size_in_kb = 1024;
894 max_sector_size_in_kb = 256;
895 flash_size_reg = 0x1FF0F442;
896 stm32x_info->has_extra_options = true;
897 stm32x_info->has_boot_addr = true;
898 break;
899
900 case 0x451: /* F76x/77x */
901 max_flash_size_in_kb = 2048;
902 max_sector_size_in_kb = 256;
903 flash_size_reg = 0x1FF0F442;
904 stm32x_info->has_extra_options = true;
905 stm32x_info->has_boot_addr = true;
906 break;
907
908 case 0x452: /* F72x/73x */
909 max_flash_size_in_kb = 512;
910 flash_size_reg = 0x1FF07A22; /* yes, 0x1FF*0*7A22, not 0x1FF*F*7A22 */
911 stm32x_info->has_extra_options = true;
912 stm32x_info->has_boot_addr = true;
913 stm32x_info->has_optcr2_pcrop = true;
914 break;
915
916 case 0x463: /* F413x/423x */
917 max_flash_size_in_kb = 1536;
918 stm32x_info->has_extra_options = true;
919 stm32x_info->protection_bits = 15;
920 num_prot_blocks = 15;
921 break;
922
923 default:
924 LOG_WARNING("Cannot identify target as a STM32 family.");
925 return ERROR_FAIL;
926 }
927
928 /* get flash size from target. */
929 retval = target_read_u16(target, flash_size_reg, &flash_size_in_kb);
930
931 /* failed reading flash size or flash size invalid (early silicon),
932 * default to max target family */
933 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
934 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
935 max_flash_size_in_kb);
936 flash_size_in_kb = max_flash_size_in_kb;
937 }
938
939 /* if the user sets the size manually then ignore the probed value
940 * this allows us to work around devices that have a invalid flash size register value */
941 if (stm32x_info->user_bank_size) {
942 LOG_INFO("ignoring flash probed value, using configured bank size");
943 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
944 }
945
946 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
947
948 /* did we assign flash size? */
949 assert(flash_size_in_kb != 0xffff);
950
951 /* F42x/43x/469/479 1024 kiByte devices have a dual bank option */
952 if ((device_id == 0x419) || (device_id == 0x434)) {
953 uint32_t optiondata;
954 retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
955 if (retval != ERROR_OK) {
956 LOG_DEBUG("unable to read option bytes");
957 return retval;
958 }
959 if ((flash_size_in_kb > 1024) || (optiondata & OPTCR_DB1M)) {
960 stm32x_info->has_large_mem = true;
961 LOG_INFO("Dual Bank %d kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
962 } else {
963 stm32x_info->has_large_mem = false;
964 LOG_INFO("Single Bank %d kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
965 }
966 }
967
968 /* F76x/77x devices have a dual bank option */
969 if (device_id == 0x451) {
970 uint32_t optiondata;
971 retval = target_read_u32(target, STM32_FLASH_OPTCR, &optiondata);
972 if (retval != ERROR_OK) {
973 LOG_DEBUG("unable to read option bytes");
974 return retval;
975 }
976 if (optiondata & OPTCR_NDBANK) {
977 stm32x_info->has_large_mem = false;
978 LOG_INFO("Single Bank %d kiB STM32F76x/77x found", flash_size_in_kb);
979 } else {
980 stm32x_info->has_large_mem = true;
981 max_sector_size_in_kb >>= 1; /* sector size divided by 2 in dual-bank mode */
982 LOG_INFO("Dual Bank %d kiB STM32F76x/77x found", flash_size_in_kb);
983 }
984 }
985
986 /* calculate numbers of pages */
987 int num_pages = flash_size_in_kb / max_sector_size_in_kb
988 + (stm32x_info->has_large_mem ? 8 : 4);
989
990 bank->base = base_address;
991 bank->num_sectors = num_pages;
992 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
993 for (i = 0; i < num_pages; i++) {
994 bank->sectors[i].is_erased = -1;
995 bank->sectors[i].is_protected = 0;
996 }
997 bank->size = 0;
998 LOG_DEBUG("allocated %d sectors", num_pages);
999
1000 /* F76x/77x in dual bank mode */
1001 if ((device_id == 0x451) && stm32x_info->has_large_mem)
1002 num_prot_blocks = num_pages >> 1;
1003
1004 if (num_prot_blocks) {
1005 bank->prot_blocks = malloc(sizeof(struct flash_sector) * num_prot_blocks);
1006 for (i = 0; i < num_prot_blocks; i++)
1007 bank->prot_blocks[i].is_protected = 0;
1008 LOG_DEBUG("allocated %d prot blocks", num_prot_blocks);
1009 }
1010
1011 if (stm32x_info->has_large_mem) {
1012 /* dual-bank */
1013 setup_bank(bank, 0, flash_size_in_kb >> 1, max_sector_size_in_kb);
1014 setup_bank(bank, num_pages >> 1, flash_size_in_kb >> 1,
1015 max_sector_size_in_kb);
1016
1017 /* F767x/F77x in dual mode, one protection bit refers to two adjacent sectors */
1018 if (device_id == 0x451) {
1019 for (i = 0; i < num_prot_blocks; i++) {
1020 bank->prot_blocks[i].offset = bank->sectors[i << 1].offset;
1021 bank->prot_blocks[i].size = bank->sectors[i << 1].size
1022 + bank->sectors[(i << 1) + 1].size;
1023 }
1024 }
1025 } else {
1026 /* single-bank */
1027 setup_bank(bank, 0, flash_size_in_kb, max_sector_size_in_kb);
1028
1029 /* F413/F423, sectors 14 and 15 share one common protection bit */
1030 if (device_id == 0x463) {
1031 for (i = 0; i < num_prot_blocks; i++) {
1032 bank->prot_blocks[i].offset = bank->sectors[i].offset;
1033 bank->prot_blocks[i].size = bank->sectors[i].size;
1034 }
1035 bank->prot_blocks[num_prot_blocks - 1].size <<= 1;
1036 }
1037 }
1038 bank->num_prot_blocks = num_prot_blocks;
1039 assert((bank->size >> 10) == flash_size_in_kb);
1040
1041 stm32x_info->probed = 1;
1042 return ERROR_OK;
1043 }
1044
1045 static int stm32x_auto_probe(struct flash_bank *bank)
1046 {
1047 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1048 if (stm32x_info->probed)
1049 return ERROR_OK;
1050 return stm32x_probe(bank);
1051 }
1052
1053 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1054 {
1055 uint32_t dbgmcu_idcode;
1056
1057 /* read stm32 device id register */
1058 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
1059 if (retval != ERROR_OK)
1060 return retval;
1061
1062 uint16_t device_id = dbgmcu_idcode & 0xfff;
1063 uint16_t rev_id = dbgmcu_idcode >> 16;
1064 const char *device_str;
1065 const char *rev_str = NULL;
1066
1067 switch (device_id) {
1068 case 0x411:
1069 device_str = "STM32F2xx";
1070
1071 switch (rev_id) {
1072 case 0x1000:
1073 rev_str = "A";
1074 break;
1075
1076 case 0x2000:
1077 rev_str = "B";
1078 break;
1079
1080 case 0x1001:
1081 rev_str = "Z";
1082 break;
1083
1084 case 0x2001:
1085 rev_str = "Y";
1086 break;
1087
1088 case 0x2003:
1089 rev_str = "X";
1090 break;
1091
1092 case 0x2007:
1093 rev_str = "1";
1094 break;
1095
1096 case 0x200F:
1097 rev_str = "V";
1098 break;
1099
1100 case 0x201F:
1101 rev_str = "2";
1102 break;
1103 }
1104 break;
1105
1106 case 0x413:
1107 case 0x419:
1108 case 0x434:
1109 device_str = "STM32F4xx";
1110
1111 switch (rev_id) {
1112 case 0x1000:
1113 rev_str = "A";
1114 break;
1115
1116 case 0x1001:
1117 rev_str = "Z";
1118 break;
1119
1120 case 0x1003:
1121 rev_str = "Y";
1122 break;
1123
1124 case 0x1007:
1125 rev_str = "1";
1126 break;
1127
1128 case 0x2001:
1129 rev_str = "3";
1130 break;
1131 }
1132 break;
1133
1134 case 0x421:
1135 device_str = "STM32F446";
1136
1137 switch (rev_id) {
1138 case 0x1000:
1139 rev_str = "A";
1140 break;
1141 }
1142 break;
1143
1144 case 0x423:
1145 case 0x431:
1146 case 0x433:
1147 case 0x458:
1148 case 0x441:
1149 device_str = "STM32F4xx (Low Power)";
1150
1151 switch (rev_id) {
1152 case 0x1000:
1153 rev_str = "A";
1154 break;
1155
1156 case 0x1001:
1157 rev_str = "Z";
1158 break;
1159
1160 case 0x2000:
1161 rev_str = "B";
1162 break;
1163
1164 case 0x3000:
1165 rev_str = "C";
1166 break;
1167 }
1168 break;
1169
1170 case 0x449:
1171 device_str = "STM32F7[4|5]x";
1172
1173 switch (rev_id) {
1174 case 0x1000:
1175 rev_str = "A";
1176 break;
1177
1178 case 0x1001:
1179 rev_str = "Z";
1180 break;
1181 }
1182 break;
1183
1184 case 0x451:
1185 device_str = "STM32F7[6|7]x";
1186
1187 switch (rev_id) {
1188 case 0x1000:
1189 rev_str = "A";
1190 break;
1191 }
1192 break;
1193
1194 case 0x452:
1195 device_str = "STM32F7[2|3]x";
1196
1197 switch (rev_id) {
1198 case 0x1000:
1199 rev_str = "A";
1200 break;
1201 }
1202 break;
1203
1204 case 0x463:
1205 device_str = "STM32F4[1|2]3";
1206
1207 switch (rev_id) {
1208 case 0x1000:
1209 rev_str = "A";
1210 break;
1211 }
1212 break;
1213
1214 default:
1215 snprintf(buf, buf_size, "Cannot identify target as a STM32F2/4/7\n");
1216 return ERROR_FAIL;
1217 }
1218
1219 if (rev_str != NULL)
1220 snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
1221 else
1222 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1223
1224 return ERROR_OK;
1225 }
1226
1227 COMMAND_HANDLER(stm32x_handle_lock_command)
1228 {
1229 struct target *target = NULL;
1230 struct stm32x_flash_bank *stm32x_info = NULL;
1231
1232 if (CMD_ARGC < 1)
1233 return ERROR_COMMAND_SYNTAX_ERROR;
1234
1235 struct flash_bank *bank;
1236 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1237 if (ERROR_OK != retval)
1238 return retval;
1239
1240 stm32x_info = bank->driver_priv;
1241 target = bank->target;
1242
1243 if (target->state != TARGET_HALTED) {
1244 LOG_INFO("Target not halted");
1245 /* return ERROR_TARGET_NOT_HALTED; */
1246 }
1247
1248 if (stm32x_read_options(bank) != ERROR_OK) {
1249 command_print(CMD_CTX, "%s failed to read options", bank->driver->name);
1250 return ERROR_OK;
1251 }
1252
1253 /* set readout protection */
1254 stm32x_info->option_bytes.RDP = 0;
1255
1256 if (stm32x_write_options(bank) != ERROR_OK) {
1257 command_print(CMD_CTX, "%s failed to lock device", bank->driver->name);
1258 return ERROR_OK;
1259 }
1260
1261 command_print(CMD_CTX, "%s locked", bank->driver->name);
1262
1263 return ERROR_OK;
1264 }
1265
1266 COMMAND_HANDLER(stm32x_handle_unlock_command)
1267 {
1268 struct target *target = NULL;
1269 struct stm32x_flash_bank *stm32x_info = NULL;
1270
1271 if (CMD_ARGC < 1)
1272 return ERROR_COMMAND_SYNTAX_ERROR;
1273
1274 struct flash_bank *bank;
1275 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1276 if (ERROR_OK != retval)
1277 return retval;
1278
1279 stm32x_info = bank->driver_priv;
1280 target = bank->target;
1281
1282 if (target->state != TARGET_HALTED) {
1283 LOG_INFO("Target not halted");
1284 /* return ERROR_TARGET_NOT_HALTED; */
1285 }
1286
1287 if (stm32x_read_options(bank) != ERROR_OK) {
1288 command_print(CMD_CTX, "%s failed to read options", bank->driver->name);
1289 return ERROR_OK;
1290 }
1291
1292 /* clear readout protection and complementary option bytes
1293 * this will also force a device unlock if set */
1294 stm32x_info->option_bytes.RDP = 0xAA;
1295 if (stm32x_info->has_optcr2_pcrop) {
1296 stm32x_info->option_bytes.optcr2_pcrop = OPTCR2_PCROP_RDP | (~1U << bank->num_sectors);
1297 }
1298
1299 if (stm32x_write_options(bank) != ERROR_OK) {
1300 command_print(CMD_CTX, "%s failed to unlock device", bank->driver->name);
1301 return ERROR_OK;
1302 }
1303
1304 command_print(CMD_CTX, "%s unlocked.\n"
1305 "INFO: a reset or power cycle is required "
1306 "for the new settings to take effect.", bank->driver->name);
1307
1308 return ERROR_OK;
1309 }
1310
1311 static int stm32x_mass_erase(struct flash_bank *bank)
1312 {
1313 int retval;
1314 uint32_t flash_mer;
1315 struct target *target = bank->target;
1316 struct stm32x_flash_bank *stm32x_info = NULL;
1317
1318 if (target->state != TARGET_HALTED) {
1319 LOG_ERROR("Target not halted");
1320 return ERROR_TARGET_NOT_HALTED;
1321 }
1322
1323 stm32x_info = bank->driver_priv;
1324
1325 retval = stm32x_unlock_reg(target);
1326 if (retval != ERROR_OK)
1327 return retval;
1328
1329 /* mass erase flash memory */
1330 if (stm32x_info->has_large_mem)
1331 flash_mer = FLASH_MER | FLASH_MER1;
1332 else
1333 flash_mer = FLASH_MER;
1334
1335 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), flash_mer);
1336 if (retval != ERROR_OK)
1337 return retval;
1338 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1339 flash_mer | FLASH_STRT);
1340 if (retval != ERROR_OK)
1341 return retval;
1342
1343 retval = stm32x_wait_status_busy(bank, FLASH_MASS_ERASE_TIMEOUT);
1344 if (retval != ERROR_OK)
1345 return retval;
1346
1347 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1348 if (retval != ERROR_OK)
1349 return retval;
1350
1351 return ERROR_OK;
1352 }
1353
1354 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1355 {
1356 int i;
1357
1358 if (CMD_ARGC < 1) {
1359 command_print(CMD_CTX, "stm32x mass_erase <bank>");
1360 return ERROR_COMMAND_SYNTAX_ERROR;
1361 }
1362
1363 struct flash_bank *bank;
1364 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1365 if (ERROR_OK != retval)
1366 return retval;
1367
1368 retval = stm32x_mass_erase(bank);
1369 if (retval == ERROR_OK) {
1370 /* set all sectors as erased */
1371 for (i = 0; i < bank->num_sectors; i++)
1372 bank->sectors[i].is_erased = 1;
1373
1374 command_print(CMD_CTX, "stm32x mass erase complete");
1375 } else {
1376 command_print(CMD_CTX, "stm32x mass erase failed");
1377 }
1378
1379 return retval;
1380 }
1381
1382 COMMAND_HANDLER(stm32f2x_handle_options_read_command)
1383 {
1384 int retval;
1385 struct flash_bank *bank;
1386 struct stm32x_flash_bank *stm32x_info = NULL;
1387
1388 if (CMD_ARGC != 1) {
1389 command_print(CMD_CTX, "stm32f2x options_read <bank>");
1390 return ERROR_COMMAND_SYNTAX_ERROR;
1391 }
1392
1393 retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1394 if (ERROR_OK != retval)
1395 return retval;
1396
1397 retval = stm32x_read_options(bank);
1398 if (ERROR_OK != retval)
1399 return retval;
1400
1401 stm32x_info = bank->driver_priv;
1402 if (stm32x_info->has_extra_options) {
1403 if (stm32x_info->has_boot_addr) {
1404 uint32_t boot_addr = stm32x_info->option_bytes.boot_addr;
1405
1406 command_print(CMD_CTX, "stm32f2x user_options 0x%03X,"
1407 " boot_add0 0x%04X, boot_add1 0x%04X",
1408 stm32x_info->option_bytes.user_options,
1409 boot_addr & 0xffff, (boot_addr & 0xffff0000) >> 16);
1410 if (stm32x_info->has_optcr2_pcrop) {
1411 command_print(CMD_CTX, "stm32f2x optcr2_pcrop 0x%08X",
1412 stm32x_info->option_bytes.optcr2_pcrop);
1413 }
1414 } else {
1415 command_print(CMD_CTX, "stm32f2x user_options 0x%03X",
1416 stm32x_info->option_bytes.user_options);
1417 }
1418 } else {
1419 command_print(CMD_CTX, "stm32f2x user_options 0x%02X",
1420 stm32x_info->option_bytes.user_options);
1421
1422 }
1423
1424 return retval;
1425 }
1426
1427 COMMAND_HANDLER(stm32f2x_handle_options_write_command)
1428 {
1429 int retval;
1430 struct flash_bank *bank;
1431 struct stm32x_flash_bank *stm32x_info = NULL;
1432 uint16_t user_options, boot_addr0, boot_addr1, options_mask;
1433
1434 if (CMD_ARGC < 1) {
1435 command_print(CMD_CTX, "stm32f2x options_write <bank> ...");
1436 return ERROR_COMMAND_SYNTAX_ERROR;
1437 }
1438
1439 retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1440 if (ERROR_OK != retval)
1441 return retval;
1442
1443 retval = stm32x_read_options(bank);
1444 if (ERROR_OK != retval)
1445 return retval;
1446
1447 stm32x_info = bank->driver_priv;
1448 if (stm32x_info->has_boot_addr) {
1449 if (CMD_ARGC != 4) {
1450 command_print(CMD_CTX, "stm32f2x options_write <bank> <user_options>"
1451 " <boot_addr0> <boot_addr1>");
1452 return ERROR_COMMAND_SYNTAX_ERROR;
1453 }
1454 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[2], boot_addr0);
1455 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[3], boot_addr1);
1456 stm32x_info->option_bytes.boot_addr = boot_addr0 | (((uint32_t) boot_addr1) << 16);
1457 } else {
1458 if (CMD_ARGC != 2) {
1459 command_print(CMD_CTX, "stm32f2x options_write <bank> <user_options>");
1460 return ERROR_COMMAND_SYNTAX_ERROR;
1461 }
1462 }
1463
1464 COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], user_options);
1465 options_mask = !stm32x_info->has_extra_options ? ~0xfc :
1466 ~(((0xf00 << (stm32x_info->protection_bits - 12)) | 0xff) & 0xffc);
1467 if (user_options & options_mask) {
1468 command_print(CMD_CTX, "stm32f2x invalid user_options");
1469 return ERROR_COMMAND_ARGUMENT_INVALID;
1470 }
1471
1472 stm32x_info->option_bytes.user_options = user_options;
1473
1474 if (stm32x_write_options(bank) != ERROR_OK) {
1475 command_print(CMD_CTX, "stm32f2x failed to write options");
1476 return ERROR_OK;
1477 }
1478
1479 /* switching between single- and dual-bank modes requires re-probe */
1480 /* ... and reprogramming of whole flash */
1481 stm32x_info->probed = 0;
1482
1483 command_print(CMD_CTX, "stm32f2x write options complete.\n"
1484 "INFO: a reset or power cycle is required "
1485 "for the new settings to take effect.");
1486 return retval;
1487 }
1488
1489 COMMAND_HANDLER(stm32f2x_handle_optcr2_write_command)
1490 {
1491 int retval;
1492 struct flash_bank *bank;
1493 struct stm32x_flash_bank *stm32x_info = NULL;
1494 uint32_t optcr2_pcrop;
1495
1496 if (CMD_ARGC != 2) {
1497 command_print(CMD_CTX, "stm32f2x optcr2_write <bank> <optcr2_value>");
1498 return ERROR_COMMAND_SYNTAX_ERROR;
1499 }
1500
1501 retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1502 if (ERROR_OK != retval)
1503 return retval;
1504
1505 stm32x_info = bank->driver_priv;
1506 if (!stm32x_info->has_optcr2_pcrop) {
1507 command_print(CMD_CTX, "no optcr2 register");
1508 return ERROR_COMMAND_ARGUMENT_INVALID;
1509 }
1510
1511 command_print(CMD_CTX, "INFO: To disable PCROP, set PCROP_RDP"
1512 " with PCROPi bits STILL SET, then\nlock device and"
1513 " finally unlock it. Clears PCROP and mass erases flash.");
1514
1515 retval = stm32x_read_options(bank);
1516 if (ERROR_OK != retval)
1517 return retval;
1518
1519 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], optcr2_pcrop);
1520 stm32x_info->option_bytes.optcr2_pcrop = optcr2_pcrop;
1521
1522 if (stm32x_write_options(bank) != ERROR_OK) {
1523 command_print(CMD_CTX, "stm32f2x failed to write options");
1524 return ERROR_OK;
1525 }
1526
1527 command_print(CMD_CTX, "stm32f2x optcr2_write complete.");
1528 return retval;
1529 }
1530
1531 static const struct command_registration stm32x_exec_command_handlers[] = {
1532 {
1533 .name = "lock",
1534 .handler = stm32x_handle_lock_command,
1535 .mode = COMMAND_EXEC,
1536 .usage = "bank_id",
1537 .help = "Lock entire flash device.",
1538 },
1539 {
1540 .name = "unlock",
1541 .handler = stm32x_handle_unlock_command,
1542 .mode = COMMAND_EXEC,
1543 .usage = "bank_id",
1544 .help = "Unlock entire protected flash device.",
1545 },
1546 {
1547 .name = "mass_erase",
1548 .handler = stm32x_handle_mass_erase_command,
1549 .mode = COMMAND_EXEC,
1550 .usage = "bank_id",
1551 .help = "Erase entire flash device.",
1552 },
1553 {
1554 .name = "options_read",
1555 .handler = stm32f2x_handle_options_read_command,
1556 .mode = COMMAND_EXEC,
1557 .usage = "bank_id",
1558 .help = "Read and display device option bytes.",
1559 },
1560 {
1561 .name = "options_write",
1562 .handler = stm32f2x_handle_options_write_command,
1563 .mode = COMMAND_EXEC,
1564 .usage = "bank_id user_options [ boot_add0 boot_add1 ]",
1565 .help = "Write option bytes",
1566 },
1567 {
1568 .name = "optcr2_write",
1569 .handler = stm32f2x_handle_optcr2_write_command,
1570 .mode = COMMAND_EXEC,
1571 .usage = "bank_id optcr2",
1572 .help = "Write optcr2 word",
1573 },
1574
1575 COMMAND_REGISTRATION_DONE
1576 };
1577
1578 static const struct command_registration stm32x_command_handlers[] = {
1579 {
1580 .name = "stm32f2x",
1581 .mode = COMMAND_ANY,
1582 .help = "stm32f2x flash command group",
1583 .usage = "",
1584 .chain = stm32x_exec_command_handlers,
1585 },
1586 COMMAND_REGISTRATION_DONE
1587 };
1588
1589 struct flash_driver stm32f2x_flash = {
1590 .name = "stm32f2x",
1591 .commands = stm32x_command_handlers,
1592 .flash_bank_command = stm32x_flash_bank_command,
1593 .erase = stm32x_erase,
1594 .protect = stm32x_protect,
1595 .write = stm32x_write,
1596 .read = default_flash_read,
1597 .probe = stm32x_probe,
1598 .auto_probe = stm32x_auto_probe,
1599 .erase_check = default_flash_blank_check,
1600 .protect_check = stm32x_protect_check,
1601 .info = get_stm32x_info,
1602 .free_driver_priv = default_flash_free_driver_priv,
1603 };
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